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https://github.com/holub/mame
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mips: enough to panic (nw)
With these changes, RISC/os now loads and panics in kmemalloc(). * mips1: added fpa imp/revision numbers * mips: hack around prom bootp broadcast bug * rambo: timer/counter interrupt * rambo: enough dma to make scsi work * rambo: simulate RISC/os video dma test/init behaviour
This commit is contained in:
Patrick Mackinlay
parent
82c91f7777
commit
f74ad668aa
@ -9,6 +9,18 @@
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class mips1core_device_base : public cpu_device
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{
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public:
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// floating point coprocessor revision numbers recognised by RISC/os 4.52 and IRIX
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enum fpu_rev_t : u32
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{
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MIPS_R2360 = 0x0100, // MIPS R2360 Floating Point Board
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MIPS_R2010 = 0x0200, // MIPS R2010 VLSI Floating Point Chip
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MIPS_R2010A = 0x0310, // MIPS R2010A VLSI Floating Point Chip
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MIPS_R3010 = 0x0320, // MIPS R3010 VLSI Floating Point Chip
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MIPS_R3010A = 0x0330, // MIPS R3010A VLSI Floating Point Chip
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MIPS_R3010Av4 = 0x0340, // MIPS R3010A VLSI Floating Point Chip
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MIPS_R6010 = 0x0400, // MIPS R6010 Floating Point Chip
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};
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// device configuration
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void set_endianness(endianness_t endianness) { m_endianness = endianness; }
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void set_fpurev(u32 revision) { m_hasfpu = true; m_fpurev = revision; }
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@ -39,6 +39,8 @@
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* http://www.umips.net/
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* http://www.geekdot.com/the-mips-rs2030/
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* http://www.jp.netbsd.org/ports/mipsco/models.html
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* http://www.prumpleffer.de/~miod/machineroom/machines/mips/magnum/index.html
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* https://web.archive.org/web/20140518203135/http://no-l.org/pages/riscos.html
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*
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* TODO (rx2030)
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* - remaining iop interface
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@ -178,6 +180,9 @@
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* 3 <- fpu
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* 4 <- fdc
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* 5 <- parity error
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*
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* Keyboard controller output port
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* 4: select 1M/4M SIMMs?
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*/
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#include "emu.h"
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@ -472,8 +477,8 @@ static void mips_scsi_devices(device_slot_interface &device)
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void rx2030_state::rx2030(machine_config &config)
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{
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R2000A(config, m_cpu, 33.333_MHz_XTAL / 2, 32768, 32768);
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m_cpu->set_fpurev(0x0315); // 0x0315 == R2010A v1.5
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m_cpu->in_brcond<0>().set([]() { return 1; }); // logerror("brcond0 sampled (%s)\n", machine().describe_context());
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m_cpu->set_fpurev(mips1_device_base::MIPS_R2010A);
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m_cpu->in_brcond<0>().set([]() { return 1; }); // writeback complete
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V50(config, m_iop, 20_MHz_XTAL / 2);
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m_iop->set_addrmap(AS_PROGRAM, &rx2030_state::iop_program_map);
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@ -728,14 +733,31 @@ void rx3230_state::rx3230_init()
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{
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// map the configured ram
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m_cpu->space(0).install_ram(0x00000000, m_ram->mask(), m_ram->pointer());
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/*
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* HACK: the prom bootp code broadcasts to the network address (i.e. the
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* host portion is "all zeroes"), instead of to the standard "all ones".
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* This makes it very difficult to receive the bootp request in a host OS,
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* so this patch changes the code to broadcast to the standard broadcast
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* address instead.
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*
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* 0xbfc1f1b0: addu r6,0,0
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* jal $bfc0be10 # set host portion from r6
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*
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* This patch changes the first instruction to one which loads r6 with
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* 0xffffffff, which is then or'd into the host part of the address, i.e.:
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*
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* addiu r6,0,-$1
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*/
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m_rom[0x1f1b0 >> 2] = 0x2406ffff;
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}
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void rx3230_state::rx3230(machine_config &config)
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{
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R3000A(config, m_cpu, 50_MHz_XTAL / 2, 32768, 32768);
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m_cpu->set_addrmap(AS_PROGRAM, &rx3230_state::rx3230_map);
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m_cpu->set_fpurev(0x0340); // 0x0340 == R3010A v4.0?
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m_cpu->in_brcond<0>().set([]() { return 1; }); // bus grant?
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m_cpu->set_fpurev(mips1_device_base::MIPS_R3010A);
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m_cpu->in_brcond<0>().set([]() { return 1; }); // writeback complete
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// 32 SIMM slots, 8-128MB memory, banks of 8 1MB or 4MB SIMMs
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RAM(config, m_ram);
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@ -748,6 +770,8 @@ void rx3230_state::rx3230(machine_config &config)
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m_rambo->parity_out().set_inputline(m_cpu, INPUT_LINE_IRQ5);
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//m_rambo->buzzer_out().set(m_buzzer, FUNC(speaker_sound_device::level_w));
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m_rambo->set_ram(m_ram);
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m_rambo->dma_r<0>().set("scsi:7:ncr53c94", FUNC(ncr53c94_device::dma_r));
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m_rambo->dma_w<0>().set("scsi:7:ncr53c94", FUNC(ncr53c94_device::dma_w));
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// scsi bus and devices
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NSCSI_BUS(config, m_scsibus, 0);
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@ -823,15 +847,15 @@ void rx3230_state::rx3230(machine_config &config)
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AT_KEYBOARD_CONTROLLER(config, m_kbdc, 12_MHz_XTAL); // TODO: confirm
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m_kbdc->kbd_clk().set(kbdc, FUNC(pc_kbdc_device::clock_write_from_mb));
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m_kbdc->kbd_data().set(kbdc, FUNC(pc_kbdc_device::data_write_from_mb));
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m_kbdc->kbd_irq().set(FUNC(rx3230_state::irq_w<INT_KBD>)).invert();
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m_kbdc->kbd_irq().set(FUNC(rx3230_state::irq_w<INT_KBD>));
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// buzzer
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SPEAKER(config, "mono").front_center();
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SPEAKER_SOUND(config, m_buzzer);
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m_buzzer->add_route(ALL_OUTPUTS, "mono", 0.50);
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// motherboard monochrome video (1152x900 @ 60Hz?)
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u32 const pixclock = 62'208'000;
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// motherboard monochrome video (1152x900 @ 72Hz)
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u32 const pixclock = 74'649'600;
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SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
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m_screen->set_raw(pixclock, 1152, 0, 1152, 900, 0, 900);
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@ -144,6 +144,7 @@ public:
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: driver_device(mconfig, type, tag)
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, m_cpu(*this, "cpu")
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, m_ram(*this, "ram")
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, m_rom(*this, "rx3230")
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, m_rambo(*this, "rambo")
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, m_scsibus(*this, "scsi")
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, m_scsi(*this, "scsi:7:ncr53c94")
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@ -188,6 +189,7 @@ private:
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// processors and memory
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required_device<r3000a_device> m_cpu;
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required_device<ram_device> m_ram;
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required_region_ptr<u32> m_rom;
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// i/o devices
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required_device<mips_rambo_device> m_rambo;
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@ -10,8 +10,6 @@
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*
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* TODO
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* - interrupts
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* - dma
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* - timer
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* - buzzer
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*/
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@ -33,6 +31,7 @@ mips_rambo_device::mips_rambo_device(const machine_config &mconfig, const char *
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, m_parity_out_cb(*this)
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, m_timer_out_cb(*this)
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, m_buzzer_out_cb(*this)
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, m_channel{{ 0,0,0,0,0,0, false, *this, *this }, { 0,0,0,0,0,0, false, *this, *this }}
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, m_irq_out_state(0)
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, m_buzzer_out_state(0)
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{
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@ -68,6 +67,13 @@ void mips_rambo_device::device_start()
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m_timer_out_cb.resolve_safe();
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m_buzzer_out_cb.resolve_safe();
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for (dma_t &ch : m_channel)
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{
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ch.read_cb.resolve_safe(0);
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ch.write_cb.resolve_safe();
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}
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m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mips_rambo_device::timer), this));
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m_buzzer_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mips_rambo_device::buzzer_toggle), this));
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}
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@ -81,7 +87,11 @@ void mips_rambo_device::device_reset()
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READ32_MEMBER(mips_rambo_device::tcount_r)
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{
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return attotime_to_clocks(machine().time() - m_tcount);
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u32 const data = attotime_to_clocks(machine().time() - m_tcount);
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LOGMASKED(LOG_REG, "tcount_r 0x%08x (%s)\n", data, machine().describe_context());
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return data;
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}
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WRITE32_MEMBER(mips_rambo_device::tcount_w)
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@ -94,6 +104,10 @@ WRITE32_MEMBER(mips_rambo_device::tcount_w)
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WRITE32_MEMBER(mips_rambo_device::tbreak_w)
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{
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LOGMASKED(LOG_REG, "tbreak_w 0x%08x (%s)\n", data, machine().describe_context());
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COMBINE_DATA(&m_tbreak);
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m_timer->adjust(clocks_to_attotime(m_tbreak) - (machine().time() - m_tcount));
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}
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WRITE32_MEMBER(mips_rambo_device::control_w)
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@ -130,6 +144,10 @@ template <unsigned Channel> WRITE32_MEMBER(mips_rambo_device::mode_w)
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{
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LOGMASKED(LOG_REG, "mode_w<%d> 0x%08x (%s)\n", Channel, data, machine().describe_context());
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if (data & MODE_CHANNEL_EN)
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m_channel[Channel].current_address = m_channel[Channel].load_address;
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mem_mask &= MODE_WRITE_MASK;
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COMBINE_DATA(&m_channel[Channel].mode);
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}
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@ -138,6 +156,14 @@ template <unsigned Channel> WRITE16_MEMBER(mips_rambo_device::block_count_w)
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LOGMASKED(LOG_REG, "block_count_w<%d> 0x%04x (%s)\n", Channel, data, machine().describe_context());
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COMBINE_DATA(&m_channel[Channel].block_count);
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COMBINE_DATA(&m_channel[Channel].reload_count);
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}
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TIMER_CALLBACK_MEMBER(mips_rambo_device::timer)
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{
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// FIXME: clear timer out line here, or on tcount/tbreak write?
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m_timer_out_cb(ASSERT_LINE);
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m_timer_out_cb(CLEAR_LINE);
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}
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TIMER_CALLBACK_MEMBER(mips_rambo_device::buzzer_toggle)
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@ -150,9 +176,19 @@ u32 mips_rambo_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap
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{
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// check if dma channel is configured
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u32 const blocks_required = (screen.visible_area().height() * screen.visible_area().width()) >> 9;
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if (!(m_channel[1].mode & MODE_CHANNEL_EN) || !(m_channel[1].mode & MODE_AUTO_RELOAD) || (m_channel[1].block_count != blocks_required))
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if (!(m_channel[1].mode & MODE_CHANNEL_EN) || (m_channel[1].reload_count != blocks_required))
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return 1;
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// screen is blanked unless auto reload is enabled
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if (!(m_channel[1].mode & MODE_AUTO_RELOAD))
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{
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m_channel[1].block_count = 0;
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return 0;
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}
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else
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m_channel[1].block_count = m_channel[1].reload_count;
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u32 address = m_channel[1].load_address;
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for (int y = screen.visible_area().min_y; y <= screen.visible_area().max_y; y++)
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for (int x = screen.visible_area().min_x; x <= screen.visible_area().max_x; x += 8)
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@ -173,3 +209,35 @@ u32 mips_rambo_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap
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return 0;
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}
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template WRITE_LINE_MEMBER(mips_rambo_device::drq_w<0>);
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template WRITE_LINE_MEMBER(mips_rambo_device::drq_w<1>);
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template <unsigned Channel> WRITE_LINE_MEMBER(mips_rambo_device::drq_w)
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{
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m_channel[Channel].drq_asserted = bool(state == ASSERT_LINE);
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while (m_channel[Channel].drq_asserted)
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{
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// check channel enabled
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if (!(m_channel[Channel].mode & MODE_CHANNEL_EN))
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break;
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// TODO: check data remaining
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// FIXME: 16 bit dma
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if (m_channel[Channel].mode & MODE_TO_MEMORY)
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{
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u8 const data = m_channel[Channel].read_cb();
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m_ram->write(BYTE4_XOR_BE(m_channel[Channel].current_address), data);
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}
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else
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{
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u8 const data = m_ram->read(BYTE4_XOR_BE(m_channel[Channel].current_address));
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m_channel[Channel].write_cb(data);
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}
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m_channel[Channel].current_address++;
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}
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}
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@ -21,9 +21,12 @@ public:
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auto buzzer_out() { return m_buzzer_out_cb.bind(); }
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template <typename T> void set_ram(T &&tag) { m_ram.set_tag(std::forward<T>(tag)); }
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template <unsigned Channel> auto dma_r() { return m_channel[Channel].read_cb.bind(); }
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template <unsigned Channel> auto dma_w() { return m_channel[Channel].write_cb.bind(); }
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// input lines
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template <unsigned Interrupt> DECLARE_WRITE_LINE_MEMBER(irq_w) {}
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template <unsigned Channel> DECLARE_WRITE_LINE_MEMBER(drq_w) {}
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template <unsigned Channel> DECLARE_WRITE_LINE_MEMBER(drq_w);
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void map(address_map &map);
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u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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@ -37,11 +40,27 @@ protected:
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template <unsigned Channel> DECLARE_READ32_MEMBER(diag_r) { return 0; }
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template <unsigned Channel> DECLARE_READ16_MEMBER(fifo_r) { return 0; }
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template <unsigned Channel> DECLARE_READ32_MEMBER(mode_r) { return m_channel[Channel].mode; }
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template <unsigned Channel> DECLARE_READ16_MEMBER(block_count_r) { return m_channel[Channel].block_count; }
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template <unsigned Channel> DECLARE_READ32_MEMBER(current_address_r) { return 0; }
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template <unsigned Channel> DECLARE_READ16_MEMBER(block_count_r)
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{
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if ((Channel == 0) || !(m_channel[Channel].mode & MODE_CHANNEL_EN))
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return m_channel[0].block_count;
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/*
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* HACK: The RISC/os boot sequence tests the dma channel 1 block count
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* when configuring the monochrome graphics option. This hack simulates
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* decrementing the block count for the video dma channel assuming a
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* transfer of 1152x900 1-bit pixels at 72 Hz. With a device clock of
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* 6.25 MHz, this is one block (64 bytes) approximately every 43 device
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* cycles.
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*/
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u64 const block_cycles = attotime_to_clocks(machine().time()) / 43;
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return m_channel[Channel].block_count - (block_cycles % (m_channel[Channel].block_count + 1));
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}
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template <unsigned Channel> DECLARE_READ32_MEMBER(current_address_r) { return m_channel[Channel].current_address; }
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DECLARE_READ32_MEMBER(tcount_r);
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DECLARE_READ32_MEMBER(tbreak_r) { return 0; }
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DECLARE_READ32_MEMBER(tbreak_r) { return m_tbreak; }
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DECLARE_READ32_MEMBER(error_r) { return 0; }
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DECLARE_READ32_MEMBER(control_r) { return 0; }
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@ -54,6 +73,7 @@ protected:
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DECLARE_WRITE32_MEMBER(tbreak_w);
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DECLARE_WRITE32_MEMBER(control_w);
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TIMER_CALLBACK_MEMBER(timer);
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TIMER_CALLBACK_MEMBER(buzzer_toggle);
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private:
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@ -73,6 +93,8 @@ private:
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MODE_DMA_ERROR = 0x00000200, // parity error during transfer
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MODE_DMA_INTR = 0x00000100, // channel interrupt pending
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MODE_COUNT_MASK = 0x000000ff, // halfword count bits
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MODE_WRITE_MASK = 0xff000000,
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};
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enum control_mask : u32
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@ -97,16 +119,25 @@ private:
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u32 diag;
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u32 mode;
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u16 block_count;
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u16 reload_count;
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u32 current_address;
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bool drq_asserted;
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// FIXME: 16 bit dma
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devcb_read8 read_cb;
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devcb_write8 write_cb;
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}
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m_channel[2];
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emu_timer *m_timer;
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emu_timer *m_buzzer_timer;
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int m_irq_out_state;
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int m_buzzer_out_state;
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attotime m_tcount;
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u32 m_tbreak;
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};
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DECLARE_DEVICE_TYPE(MIPS_RAMBO, mips_rambo_device)
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