From f79a9d16713b1996e49c9857e4081d0f5f6f8635 Mon Sep 17 00:00:00 2001 From: AJR Date: Sat, 10 Aug 2019 15:40:14 -0400 Subject: [PATCH] mc68hc11: CPU device modernization (nw) - Replace the old-style fake I/O space with callbacks - Add address spaces to handle remappable accesses to internal RAM and registers - Eliminate set_config in favor of separate device types for each model (not differentiated properly yet...) --- src/devices/bus/nscsi/cdd2000.cpp | 2 +- src/devices/cpu/mc68hc11/mc68hc11.cpp | 150 +++++++++++++++++--------- src/devices/cpu/mc68hc11/mc68hc11.h | 120 ++++++++++++++------- src/mame/drivers/30test.cpp | 15 +-- src/mame/drivers/alphasma.cpp | 15 +-- src/mame/drivers/ampscarp.cpp | 2 +- src/mame/drivers/hitpoker.cpp | 19 ++-- src/mame/drivers/ice_bozopail.cpp | 2 +- src/mame/drivers/skeetsht.cpp | 12 +-- src/mame/drivers/taitojc.cpp | 33 +++--- src/mame/includes/taitojc.h | 3 +- 11 files changed, 222 insertions(+), 151 deletions(-) diff --git a/src/devices/bus/nscsi/cdd2000.cpp b/src/devices/bus/nscsi/cdd2000.cpp index 36f6a7df82c..a4fb163f446 100644 --- a/src/devices/bus/nscsi/cdd2000.cpp +++ b/src/devices/bus/nscsi/cdd2000.cpp @@ -34,7 +34,7 @@ void cdd2000_device::mem_map(address_map &map) void cdd2000_device::device_add_mconfig(machine_config &config) { - MC68HC11(config, m_cdcpu, 8'000'000); // type and clock are total guesses + MC68HC11A1(config, m_cdcpu, 8'000'000); // type and clock are total guesses m_cdcpu->set_addrmap(AS_PROGRAM, &cdd2000_device::mem_map); NCR53CF94(config, "scsic", 25'000'000); // type and clock guessed diff --git a/src/devices/cpu/mc68hc11/mc68hc11.cpp b/src/devices/cpu/mc68hc11/mc68hc11.cpp index 902b3ca4a91..9de39725d1d 100644 --- a/src/devices/cpu/mc68hc11/mc68hc11.cpp +++ b/src/devices/cpu/mc68hc11/mc68hc11.cpp @@ -40,17 +40,62 @@ enum static const int div_tab[4] = { 1, 4, 8, 16 }; -DEFINE_DEVICE_TYPE(MC68HC11, mc68hc11_cpu_device, "mc68hc11", "Motorola MC68HC11") +DEFINE_DEVICE_TYPE(MC68HC11A1, mc68hc11a1_device, "mc68hc11a1", "Motorola MC68HC11A1") +DEFINE_DEVICE_TYPE(MC68HC11D0, mc68hc11d0_device, "mc68hc11d0", "Motorola MC68HC11D0") +DEFINE_DEVICE_TYPE(MC68HC11K1, mc68hc11k1_device, "mc68hc11k1", "Motorola MC68HC11K1") +DEFINE_DEVICE_TYPE(MC68HC11M0, mc68hc11m0_device, "mc68hc11m0", "Motorola MC68HC11M0") -mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : cpu_device(mconfig, MC68HC11, tag, owner, clock) - , m_program_config("program", ENDIANNESS_BIG, 8, 16, 0 ) - , m_io_config("io", ENDIANNESS_BIG, 8, 8, 0) +mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int reg_bits, uint16_t internal_ram_size, uint8_t init_value, address_map_constructor reg_map) + : cpu_device(mconfig, type, tag, owner, clock) + , m_program_config("program", ENDIANNESS_BIG, 8, 16, 0) + , m_data_config("data", ENDIANNESS_BIG, 8, internal_ram_size > 1024 ? 11 + : internal_ram_size > 512 ? 10 + : internal_ram_size > 256 ? 9 : 8, 0, address_map_constructor(FUNC(mc68hc11_cpu_device::ram_map), this)) + , m_io_config("I/O", ENDIANNESS_BIG, 8, reg_bits, 0, reg_map) + , m_port_input_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}} + , m_port_output_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}} + , m_analog_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}} + , m_spi2_data_input_cb(*this) + , m_spi2_data_output_cb(*this) + , m_reg_block_size(1 << reg_bits) + , m_internal_ram_size(internal_ram_size) + , m_init_value(init_value) +{ +} + +void mc68hc11_cpu_device::ram_map(address_map &map) +{ + map(0, m_internal_ram_size - 1).ram(); +} + +void mc68hc11_cpu_device::io_map(address_map &map) +{ /* defaults it to the HC11M0 version for now (I might strip this down on a later date) */ - , m_has_extended_io(1) - , m_internal_ram_size(1280) - , m_init_value(0x01) + map(0, m_reg_block_size - 1).rw(FUNC(mc68hc11_cpu_device::hc11_regs_r), FUNC(mc68hc11_cpu_device::hc11_regs_w)); +} + +mc68hc11a1_device::mc68hc11a1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : mc68hc11_cpu_device(mconfig, MC68HC11A1, tag, owner, clock, 6, 256, 0x01, + address_map_constructor(FUNC(mc68hc11a1_device::io_map), this)) // TODO: also has 512 bytes EEPROM +{ +} + +mc68hc11d0_device::mc68hc11d0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : mc68hc11_cpu_device(mconfig, MC68HC11D0, tag, owner, clock, 6, 192, 0x00, + address_map_constructor(FUNC(mc68hc11d0_device::io_map), this)) +{ +} + +mc68hc11k1_device::mc68hc11k1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : mc68hc11_cpu_device(mconfig, MC68HC11K1, tag, owner, clock, 7, 768, 0x00, + address_map_constructor(FUNC(mc68hc11k1_device::io_map), this)) // TODO: also has 640 bytes EEPROM +{ +} + +mc68hc11m0_device::mc68hc11m0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : mc68hc11_cpu_device(mconfig, MC68HC11M0, tag, owner, clock, 8, 1280, 0x00, + address_map_constructor(FUNC(mc68hc11m0_device::io_map), this)) { } @@ -58,10 +103,23 @@ device_memory_interface::space_config_vector mc68hc11_cpu_device::memory_space_c { return space_config_vector { std::make_pair(AS_PROGRAM, &m_program_config), - std::make_pair(AS_IO, &m_io_config) + std::make_pair(AS_DATA, &m_data_config), + std::make_pair(AS_IO, &m_io_config) }; } +void mc68hc11_cpu_device::device_resolve_objects() +{ + for (auto &cb : m_port_input_cb) + cb.resolve_safe(0xff); + for (auto &cb : m_port_output_cb) + cb.resolve_safe(); + for (auto &cb : m_analog_cb) + cb.resolve_safe(0); + m_spi2_data_input_cb.resolve_safe(0xff); + m_spi2_data_output_cb.resolve_safe(); +} + std::unique_ptr mc68hc11_cpu_device::create_disassembler() { return std::make_unique(); @@ -80,21 +138,21 @@ uint8_t mc68hc11_cpu_device::hc11_regs_r(uint32_t address) switch(reg) { case 0x00: /* PORTA */ - return m_io->read_byte(MC68HC11_IO_PORTA); + return m_port_input_cb[0](); case 0x01: /* DDRA */ return 0; case 0x02: /* PIOC */ return 0; case 0x03: /* PORTC */ - return m_io->read_byte(MC68HC11_IO_PORTC); + return m_port_input_cb[2](); case 0x04: /* PORTB */ - return m_io->read_byte(MC68HC11_IO_PORTB); + return m_port_input_cb[1](); case 0x08: /* PORTD */ - return m_io->read_byte(MC68HC11_IO_PORTD); + return m_port_input_cb[3](); case 0x09: /* DDRD */ return 0; case 0x0a: /* PORTE */ - return m_io->read_byte(MC68HC11_IO_PORTE); + return m_port_input_cb[4](); case 0x0e: /* TCNT */ return m_tcnt >> 8; case 0x0f: @@ -113,44 +171,44 @@ uint8_t mc68hc11_cpu_device::hc11_regs_r(uint32_t address) { if (m_adctl & 0x10) { - return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD0); + return m_analog_cb[m_adctl & 0x4](); } else { - return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); + return m_analog_cb[m_adctl & 0x7](); } } case 0x32: /* ADR2 */ { if (m_adctl & 0x10) { - return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD1); + return m_analog_cb[m_adctl & 0x4](); } else { - return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); + return m_analog_cb[m_adctl & 0x7](); } } case 0x33: /* ADR3 */ { if (m_adctl & 0x10) { - return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD2); + return m_analog_cb[m_adctl & 0x4](); } else { - return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); + return m_analog_cb[m_adctl & 0x7](); } } case 0x34: /* ADR4 */ { if (m_adctl & 0x10) { - return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD3); + return m_analog_cb[m_adctl & 0x4](); } else { - return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); + return m_analog_cb[m_adctl & 0x7](); } } case 0x38: /* OPT2 */ @@ -166,9 +224,9 @@ uint8_t mc68hc11_cpu_device::hc11_regs_r(uint32_t address) case 0x74: /* SCSR1 */ return 0x40; case 0x7c: /* PORTH */ - return m_io->read_byte(MC68HC11_IO_PORTH); + return m_port_input_cb[7](); case 0x7e: /* PORTG */ - return m_io->read_byte(MC68HC11_IO_PORTG); + return m_port_input_cb[6](); case 0x7f: /* DDRG */ return 0; @@ -177,13 +235,14 @@ uint8_t mc68hc11_cpu_device::hc11_regs_r(uint32_t address) case 0x89: /* SPSR2 */ return 0x80; case 0x8a: /* SPDR2 */ - return m_io->read_byte(MC68HC11_IO_SPI2_DATA); + return m_spi2_data_input_cb(); case 0x8b: /* OPT4 */ return 0; } - logerror("HC11: regs_r %02X\n", reg); + if (!machine().side_effects_disabled()) + logerror("HC11: regs_r %02X\n", reg); return 0; // Dummy } @@ -194,25 +253,25 @@ void mc68hc11_cpu_device::hc11_regs_w(uint32_t address, uint8_t value) switch(reg) { case 0x00: /* PORTA */ - m_io->write_byte(MC68HC11_IO_PORTA, value); + m_port_output_cb[0](value); return; case 0x01: /* DDRA */ //osd_printf_debug("HC11: ddra = %02X\n", value); return; case 0x03: /* PORTC */ - m_io->write_byte(MC68HC11_IO_PORTC, value); + m_port_output_cb[2](value); return; case 0x04: /* PORTC */ - m_io->write_byte(MC68HC11_IO_PORTB, value); + m_port_output_cb[1](value); return; case 0x08: /* PORTD */ - m_io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f? + m_port_output_cb[3](value); //mask & 0x3f? return; case 0x09: /* DDRD */ //osd_printf_debug("HC11: ddrd = %02X\n", value); return; case 0x0a: /* PORTE */ - m_io->write_byte(MC68HC11_IO_PORTE, value); + m_port_output_cb[4](value); return; case 0x0e: /* TCNT */ case 0x0f: @@ -251,9 +310,9 @@ void mc68hc11_cpu_device::hc11_regs_w(uint32_t address, uint8_t value) int reg_page = value & 0xf; int ram_page = (value >> 4) & 0xf; - if (reg_page == ram_page) { + if (reg_page == ram_page && m_init_value == 0x00) { m_reg_position = reg_page << 12; - m_ram_position = (ram_page << 12) + ((m_has_extended_io) ? 0x100 : 0x80); + m_ram_position = (ram_page << 12) + m_reg_block_size; } else { m_reg_position = reg_page << 12; m_ram_position = ram_page << 12; @@ -275,13 +334,13 @@ void mc68hc11_cpu_device::hc11_regs_w(uint32_t address, uint8_t value) case 0x77: /* SCDRL */ return; case 0x7c: /* PORTH */ - m_io->write_byte(MC68HC11_IO_PORTH, value); + m_port_output_cb[7](value); return; case 0x7d: /* DDRH */ //osd_printf_debug("HC11: ddrh = %02X at %04X\n", value, m_pc); return; case 0x7e: /* PORTG */ - m_io->write_byte(MC68HC11_IO_PORTG, value); + m_port_output_cb[6](value); return; case 0x7f: /* DDRG */ //osd_printf_debug("HC11: ddrg = %02X at %04X\n", value, m_pc); @@ -292,7 +351,7 @@ void mc68hc11_cpu_device::hc11_regs_w(uint32_t address, uint8_t value) case 0x89: /* SPSR2 */ return; case 0x8a: /* SPDR2 */ - m_io->write_byte(MC68HC11_IO_SPI2_DATA, value); + m_spi2_data_output_cb(value); return; case 0x8b: /* OPT4 */ @@ -320,27 +379,27 @@ uint16_t mc68hc11_cpu_device::FETCH16() uint8_t mc68hc11_cpu_device::READ8(uint32_t address) { - if(address >= m_reg_position && address < m_reg_position+(m_has_extended_io ? 0x100 : 0x40)) + if(address >= m_reg_position && (address - m_reg_position) < m_reg_block_size) { - return hc11_regs_r(address); + return m_io->read_byte(address-m_reg_position); } else if(address >= m_ram_position && address < m_ram_position+m_internal_ram_size) { - return m_internal_ram[address-m_ram_position]; + return m_data->read_byte(address-m_ram_position); } return m_program->read_byte(address); } void mc68hc11_cpu_device::WRITE8(uint32_t address, uint8_t value) { - if(address >= m_reg_position && address < m_reg_position+(m_has_extended_io ? 0x100 : 0x40)) + if(address >= m_reg_position && (address - m_reg_position) < m_reg_block_size) { - hc11_regs_w(address, value); + m_io->write_byte(address-m_reg_position, value); return; } else if(address >= m_ram_position && address < m_ram_position+m_internal_ram_size) { - m_internal_ram[address-m_ram_position] = value; + m_data->write_byte(address-m_ram_position, value); return; } m_program->write_byte(address, value); @@ -394,10 +453,9 @@ void mc68hc11_cpu_device::device_start() } } - m_internal_ram.resize(m_internal_ram_size); - m_program = &space(AS_PROGRAM); m_cache = m_program->cache<0, 0, ENDIANNESS_BIG>(); + m_data = &space(AS_DATA); m_io = &space(AS_IO); save_item(NAME(m_pc)); @@ -413,10 +471,6 @@ void mc68hc11_cpu_device::device_start() save_item(NAME(m_ram_position)); save_item(NAME(m_reg_position)); save_item(NAME(m_irq_state)); - save_item(NAME(m_has_extended_io)); - save_item(NAME(m_internal_ram_size)); - save_item(NAME(m_init_value)); - save_item(NAME(m_internal_ram)); save_item(NAME(m_wait_state)); save_item(NAME(m_stop_state)); save_item(NAME(m_tflg1)); diff --git a/src/devices/cpu/mc68hc11/mc68hc11.h b/src/devices/cpu/mc68hc11/mc68hc11.h index 5e1fc7171c8..b3ceb456873 100644 --- a/src/devices/cpu/mc68hc11/mc68hc11.h +++ b/src/devices/cpu/mc68hc11/mc68hc11.h @@ -6,51 +6,52 @@ #pragma once -#define MC68HC11_IO_PORTA 0x00 -#define MC68HC11_IO_PORTB 0x01 -#define MC68HC11_IO_PORTC 0x02 -#define MC68HC11_IO_PORTD 0x03 -#define MC68HC11_IO_PORTE 0x04 -#define MC68HC11_IO_PORTF 0x05 -#define MC68HC11_IO_PORTG 0x06 -#define MC68HC11_IO_PORTH 0x07 -#define MC68HC11_IO_SPI1_DATA 0x08 -#define MC68HC11_IO_SPI2_DATA 0x09 -#define MC68HC11_IO_AD0 0x10 -#define MC68HC11_IO_AD1 0x11 -#define MC68HC11_IO_AD2 0x12 -#define MC68HC11_IO_AD3 0x13 -#define MC68HC11_IO_AD4 0x14 -#define MC68HC11_IO_AD5 0x15 -#define MC68HC11_IO_AD6 0x16 -#define MC68HC11_IO_AD7 0x17 +enum { + MC68HC11_IRQ_LINE = 0, + MC68HC11_TOC1_LINE = 1 +}; -#define MC68HC11_IRQ_LINE 0 -#define MC68HC11_TOC1_LINE 1 - -DECLARE_DEVICE_TYPE(MC68HC11, mc68hc11_cpu_device) +DECLARE_DEVICE_TYPE(MC68HC11A1, mc68hc11a1_device) +DECLARE_DEVICE_TYPE(MC68HC11D0, mc68hc11d0_device) +DECLARE_DEVICE_TYPE(MC68HC11K1, mc68hc11k1_device) +DECLARE_DEVICE_TYPE(MC68HC11M0, mc68hc11m0_device) class mc68hc11_cpu_device : public cpu_device { public: - // construction/destruction - mc68hc11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - - void set_config(int has_extended_io, int internal_ram_size, int init_value) - { - set_has_extended_io(has_extended_io); - set_internal_ram_size(internal_ram_size); - set_init_value(init_value); - } - - // I/O enable flag - void set_has_extended_io(int has_extended_io) { m_has_extended_io = has_extended_io; } - void set_internal_ram_size(int internal_ram_size) { m_internal_ram_size = internal_ram_size; } - // default value for INIT register - void set_init_value(int init_value) { m_init_value = init_value; } + // port configuration + auto in_pa_callback() { return m_port_input_cb[0].bind(); } + auto in_pb_callback() { return m_port_input_cb[1].bind(); } + auto in_pc_callback() { return m_port_input_cb[2].bind(); } + auto in_pd_callback() { return m_port_input_cb[3].bind(); } + auto in_pe_callback() { return m_port_input_cb[4].bind(); } + auto in_pf_callback() { return m_port_input_cb[5].bind(); } + auto in_pg_callback() { return m_port_input_cb[6].bind(); } + auto in_ph_callback() { return m_port_input_cb[7].bind(); } + auto out_pa_callback() { return m_port_output_cb[0].bind(); } + auto out_pb_callback() { return m_port_output_cb[1].bind(); } + auto out_pc_callback() { return m_port_output_cb[2].bind(); } + auto out_pd_callback() { return m_port_output_cb[3].bind(); } + auto out_pe_callback() { return m_port_output_cb[4].bind(); } + auto out_pf_callback() { return m_port_output_cb[5].bind(); } + auto out_pg_callback() { return m_port_output_cb[6].bind(); } + auto out_ph_callback() { return m_port_output_cb[7].bind(); } + auto in_an0_callback() { return m_analog_cb[0].bind(); } + auto in_an1_callback() { return m_analog_cb[1].bind(); } + auto in_an2_callback() { return m_analog_cb[2].bind(); } + auto in_an3_callback() { return m_analog_cb[3].bind(); } + auto in_an4_callback() { return m_analog_cb[4].bind(); } + auto in_an5_callback() { return m_analog_cb[5].bind(); } + auto in_an6_callback() { return m_analog_cb[6].bind(); } + auto in_an7_callback() { return m_analog_cb[7].bind(); } + auto in_spi2_data_callback() { return m_spi2_data_input_cb.bind(); } + auto out_spi2_data_callback() { return m_spi2_data_output_cb.bind(); } protected: + mc68hc11_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int reg_bits, uint16_t internal_ram_size, uint8_t init_value, address_map_constructor reg_map); + // device-level overrides + virtual void device_resolve_objects() override; virtual void device_start() override; virtual void device_reset() override; @@ -70,8 +71,11 @@ protected: // device_disasm_interface overrides virtual std::unique_ptr create_disassembler() override; + void io_map(address_map &map); + private: address_space_config m_program_config; + address_space_config m_data_config; address_space_config m_io_config; union { @@ -100,16 +104,21 @@ private: uint8_t m_irq_state[2]; memory_access_cache<0, 0, ENDIANNESS_BIG> *m_cache; address_space *m_program; + address_space *m_data; address_space *m_io; + devcb_read8 m_port_input_cb[8]; + devcb_write8 m_port_output_cb[8]; + devcb_read8 m_analog_cb[8]; + devcb_read8 m_spi2_data_input_cb; + devcb_write8 m_spi2_data_output_cb; int m_icount; int m_ram_position; int m_reg_position; - std::vector m_internal_ram; - int m_has_extended_io; // extended I/O enable flag - int m_internal_ram_size; - int m_init_value; + const uint16_t m_reg_block_size; // size of internal I/O space + const uint16_t m_internal_ram_size; + const uint8_t m_init_value; // default value for INIT register uint8_t m_wait_state; uint8_t m_stop_state; @@ -137,6 +146,7 @@ private: ophandler hc11_optable_page3[256]; ophandler hc11_optable_page4[256]; + void ram_map(address_map &map); uint8_t hc11_regs_r(uint32_t address); void hc11_regs_w(uint32_t address, uint8_t value); uint8_t FETCH(); @@ -465,4 +475,32 @@ private: void check_irq_lines(); }; +class mc68hc11a1_device : public mc68hc11_cpu_device +{ +public: + // construction/destruction + mc68hc11a1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class mc68hc11d0_device : public mc68hc11_cpu_device +{ +public: + // construction/destruction + mc68hc11d0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class mc68hc11k1_device : public mc68hc11_cpu_device +{ +public: + // construction/destruction + mc68hc11k1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + +class mc68hc11m0_device : public mc68hc11_cpu_device +{ +public: + // construction/destruction + mc68hc11m0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; + #endif // MAME_CPU_MC68HC11_MC68HC11_H diff --git a/src/mame/drivers/30test.cpp b/src/mame/drivers/30test.cpp index a707ed17e12..4eadd5f8635 100644 --- a/src/mame/drivers/30test.cpp +++ b/src/mame/drivers/30test.cpp @@ -86,7 +86,6 @@ private: DECLARE_READ8_MEMBER(hc11_okibank_r); DECLARE_WRITE8_MEMBER(hc11_okibank_w); - void namco_30test_io(address_map &map); void namco_30test_map(address_map &map); }; @@ -174,13 +173,6 @@ void namco_30test_state::namco_30test_map(address_map &map) map(0x8000, 0xffff).rom(); } -void namco_30test_state::namco_30test_io(address_map &map) -{ - map(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA).r(FUNC(namco_30test_state::namco_30test_mux_r)); -// AM_RANGE(MC68HC11_IO_PORTD,MC68HC11_IO_PORTD) AM_RAM - map(MC68HC11_IO_PORTE, MC68HC11_IO_PORTE).portr("SYSTEM"); -} - static INPUT_PORTS_START( 30test ) PORT_START("IN0") @@ -256,10 +248,11 @@ void namco_30test_state::machine_start() void namco_30test_state::_30test(machine_config &config) { /* basic machine hardware */ - MC68HC11(config, m_maincpu, MAIN_CLOCK/4); + MC68HC11K1(config, m_maincpu, MAIN_CLOCK/4); m_maincpu->set_addrmap(AS_PROGRAM, &namco_30test_state::namco_30test_map); - m_maincpu->set_addrmap(AS_IO, &namco_30test_state::namco_30test_io); - m_maincpu->set_config(0, 768, 0x00); + m_maincpu->in_pa_callback().set(FUNC(namco_30test_state::namco_30test_mux_r)); + //m_maincpu->in_pd_callback().set_ram(); + m_maincpu->in_pe_callback().set_ioport("SYSTEM"); /* no video hardware */ diff --git a/src/mame/drivers/alphasma.cpp b/src/mame/drivers/alphasma.cpp index afb54668e78..39b25e3369a 100644 --- a/src/mame/drivers/alphasma.cpp +++ b/src/mame/drivers/alphasma.cpp @@ -64,7 +64,6 @@ protected: DECLARE_WRITE8_MEMBER(port_d_w); void update_lcdc(bool lcdc0, bool lcdc1); - void alphasmart_io(address_map &map); void alphasmart_mem(address_map &map); uint8_t m_matrix[2]; @@ -184,12 +183,6 @@ void alphasmart_state::alphasmart_mem(address_map &map) map(0xc000, 0xc000).w(FUNC(alphasmart_state::kb_matrixl_w)); } -void alphasmart_state::alphasmart_io(address_map &map) -{ - map(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA).rw(FUNC(alphasmart_state::port_a_r), FUNC(alphasmart_state::port_a_w)); - map(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD).rw(FUNC(alphasmart_state::port_d_r), FUNC(alphasmart_state::port_d_w)); -} - READ8_MEMBER(asma2k_state::io_r) { if (offset == 0x2000) @@ -434,10 +427,12 @@ void alphasmart_state::machine_reset() void alphasmart_state::alphasmart(machine_config &config) { /* basic machine hardware */ - MC68HC11(config, m_maincpu, XTAL(8'000'000)/2); // MC68HC11D0, XTAL is 8 Mhz, unknown divider + MC68HC11D0(config, m_maincpu, XTAL(8'000'000)/2); // XTAL is 8 Mhz, unknown divider m_maincpu->set_addrmap(AS_PROGRAM, &alphasmart_state::alphasmart_mem); - m_maincpu->set_addrmap(AS_IO, &alphasmart_state::alphasmart_io); - m_maincpu->set_config(0, 192, 0x00); + m_maincpu->in_pa_callback().set(FUNC(alphasmart_state::port_a_r)); + m_maincpu->out_pa_callback().set(FUNC(alphasmart_state::port_a_w)); + m_maincpu->in_pd_callback().set(FUNC(alphasmart_state::port_d_r)); + m_maincpu->out_pd_callback().set(FUNC(alphasmart_state::port_d_w)); KS0066_F05(config, m_lcdc0, 0); m_lcdc0->set_lcd_size(2, 40); diff --git a/src/mame/drivers/ampscarp.cpp b/src/mame/drivers/ampscarp.cpp index f9ca05e3442..8da8d3c86c5 100644 --- a/src/mame/drivers/ampscarp.cpp +++ b/src/mame/drivers/ampscarp.cpp @@ -39,7 +39,7 @@ INPUT_PORTS_END void ampscarp_state::ampscarp(machine_config &config) { - MC68HC11(config, m_maincpu, 8'000'000); // type and clock unknown + MC68HC11A1(config, m_maincpu, 8'000'000); // type and clock unknown m_maincpu->set_addrmap(AS_PROGRAM, &scarp_state::mem_map); } diff --git a/src/mame/drivers/hitpoker.cpp b/src/mame/drivers/hitpoker.cpp index c2b96159b12..c768041c357 100644 --- a/src/mame/drivers/hitpoker.cpp +++ b/src/mame/drivers/hitpoker.cpp @@ -59,7 +59,6 @@ class hitpoker_state : public driver_device public: hitpoker_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag), - m_sys_regs(*this, "sys_regs"), m_maincpu(*this, "maincpu"), m_gfxdecode(*this, "gfxdecode"), m_palette(*this, "palette") { } @@ -69,7 +68,7 @@ public: void init_hitpoker(); private: - required_shared_ptr m_sys_regs; + uint8_t m_sys_regs; uint8_t m_pic_data; std::unique_ptr m_videoram; @@ -97,7 +96,6 @@ private: required_device m_maincpu; required_device m_gfxdecode; required_device m_palette; - void hitpoker_io(address_map &map); void hitpoker_map(address_map &map); }; @@ -243,7 +241,7 @@ READ8_MEMBER(hitpoker_state::hitpoker_pic_r) return (m_pic_data & 0x7f) | (m_pic_data & 0x40 ? 0x80 : 0x00); } - return m_sys_regs[offset]; + return m_sys_regs; } WRITE8_MEMBER(hitpoker_state::hitpoker_pic_w) @@ -251,7 +249,7 @@ WRITE8_MEMBER(hitpoker_state::hitpoker_pic_w) if(offset == 0) m_pic_data = (data & 0xff);// | (data & 0x40) ? 0x80 : 0x00; // logerror("%02x W\n",data); - m_sys_regs[offset] = data; + m_sys_regs = data; } #if 0 @@ -299,11 +297,6 @@ void hitpoker_state::hitpoker_map(address_map &map) map(0xe000, 0xefff).rw(FUNC(hitpoker_state::hitpoker_paletteram_r), FUNC(hitpoker_state::hitpoker_paletteram_w)); } -void hitpoker_state::hitpoker_io(address_map &map) -{ - map(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA).rw(FUNC(hitpoker_state::hitpoker_pic_r), FUNC(hitpoker_state::hitpoker_pic_w)).share("sys_regs"); -} - static INPUT_PORTS_START( hitpoker ) PORT_START("VBLANK") PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) @@ -464,10 +457,10 @@ GFXDECODE_END void hitpoker_state::hitpoker(machine_config &config) { - MC68HC11(config, m_maincpu, 1000000); + MC68HC11A1(config, m_maincpu, 1000000); m_maincpu->set_addrmap(AS_PROGRAM, &hitpoker_state::hitpoker_map); - m_maincpu->set_addrmap(AS_IO, &hitpoker_state::hitpoker_io); - m_maincpu->set_config(0, 0x100, 0x01); + m_maincpu->in_pa_callback().set(FUNC(hitpoker_state::hitpoker_pic_r)); + m_maincpu->out_pa_callback().set(FUNC(hitpoker_state::hitpoker_pic_w)); NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0); diff --git a/src/mame/drivers/ice_bozopail.cpp b/src/mame/drivers/ice_bozopail.cpp index 94eba8818c4..d9ba63da518 100644 --- a/src/mame/drivers/ice_bozopail.cpp +++ b/src/mame/drivers/ice_bozopail.cpp @@ -61,7 +61,7 @@ void ice_bozopail_state::machine_reset() void ice_bozopail_state::ice_bozo(machine_config &config) { /* basic machine hardware */ - MC68HC11(config, m_maincpu, 8000000); // unknown clock + MC68HC11A1(config, m_maincpu, 8000000); // unknown clock m_maincpu->set_addrmap(AS_PROGRAM, &ice_bozopail_state::ice_bozo_map); /* sound hardware */ diff --git a/src/mame/drivers/skeetsht.cpp b/src/mame/drivers/skeetsht.cpp index 5f7e7286e02..9b0c142c70f 100644 --- a/src/mame/drivers/skeetsht.cpp +++ b/src/mame/drivers/skeetsht.cpp @@ -63,7 +63,6 @@ private: required_device m_68hc11; required_device m_ay; required_device m_tms; - void hc11_io_map(address_map &map); void hc11_pgm_map(address_map &map); void tms_program_map(address_map &map); }; @@ -198,11 +197,6 @@ void skeetsht_state::hc11_pgm_map(address_map &map) map(0xb600, 0xbdff).ram(); //internal EEPROM } -void skeetsht_state::hc11_io_map(address_map &map) -{ - map(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA).rw(FUNC(skeetsht_state::hc11_porta_r), FUNC(skeetsht_state::hc11_porta_w)); -} - /************************************* * @@ -237,10 +231,10 @@ INPUT_PORTS_END void skeetsht_state::skeetsht(machine_config &config) { - MC68HC11(config, m_68hc11, 4000000); // ? + MC68HC11A1(config, m_68hc11, 4000000); // ? m_68hc11->set_addrmap(AS_PROGRAM, &skeetsht_state::hc11_pgm_map); - m_68hc11->set_addrmap(AS_IO, &skeetsht_state::hc11_io_map); - m_68hc11->set_config(0, 0x100, 0x01); // And 512 bytes EEPROM? (68HC11A1) + m_68hc11->in_pa_callback().set(FUNC(skeetsht_state::hc11_porta_r)); + m_68hc11->out_pa_callback().set(FUNC(skeetsht_state::hc11_porta_w)); TMS34010(config, m_tms, 48000000); m_tms->set_addrmap(AS_PROGRAM, &skeetsht_state::tms_program_map); diff --git a/src/mame/drivers/taitojc.cpp b/src/mame/drivers/taitojc.cpp index 4bf276c1757..14f7827dc5d 100644 --- a/src/mame/drivers/taitojc.cpp +++ b/src/mame/drivers/taitojc.cpp @@ -745,9 +745,10 @@ WRITE8_MEMBER(taitojc_state::hc11_output_w) m_mcu_output = data; } -READ8_MEMBER(taitojc_state::hc11_analog_r) +template +uint8_t taitojc_state::hc11_analog_r() { - return m_analog_ports[offset].read_safe(0); + return m_analog_ports[Ch].read_safe(0); } @@ -757,15 +758,6 @@ void taitojc_state::hc11_pgm_map(address_map &map) map(0x8000, 0xffff).rom(); } -void taitojc_state::hc11_io_map(address_map &map) -{ - map(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA).nopr(); // ? - map(MC68HC11_IO_PORTG, MC68HC11_IO_PORTG).rw(FUNC(taitojc_state::hc11_comm_r), FUNC(taitojc_state::hc11_comm_w)); - map(MC68HC11_IO_PORTH, MC68HC11_IO_PORTH).rw(FUNC(taitojc_state::hc11_output_r), FUNC(taitojc_state::hc11_output_w)); - map(MC68HC11_IO_SPI2_DATA, MC68HC11_IO_SPI2_DATA).rw(FUNC(taitojc_state::hc11_data_r), FUNC(taitojc_state::hc11_data_w)); - map(MC68HC11_IO_AD0, MC68HC11_IO_AD7).r(FUNC(taitojc_state::hc11_analog_r)); -} - @@ -1091,10 +1083,23 @@ void taitojc_state::taitojc(machine_config &config) m_maincpu->set_vblank_int("screen", FUNC(taitojc_state::taitojc_vblank)); m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &taitojc_state::cpu_space_map); - mc68hc11_cpu_device &sub(MC68HC11(config, "sub", XTAL(16'000'000)/2)); // 8MHz, MC68HC11M0 + mc68hc11_cpu_device &sub(MC68HC11M0(config, "sub", XTAL(16'000'000)/2)); // 8MHz, MC68HC11M0 sub.set_addrmap(AS_PROGRAM, &taitojc_state::hc11_pgm_map); - sub.set_addrmap(AS_IO, &taitojc_state::hc11_io_map); - sub.set_config(1, 1280, 0x00); + sub.in_pa_callback().set_constant(0); // ? + sub.in_pg_callback().set(FUNC(taitojc_state::hc11_comm_r)); + sub.out_pg_callback().set(FUNC(taitojc_state::hc11_comm_w)); + sub.in_ph_callback().set(FUNC(taitojc_state::hc11_output_r)); + sub.out_ph_callback().set(FUNC(taitojc_state::hc11_output_w)); + sub.in_spi2_data_callback().set(FUNC(taitojc_state::hc11_data_r)); + sub.out_spi2_data_callback().set(FUNC(taitojc_state::hc11_data_w)); + sub.in_an0_callback().set(FUNC(taitojc_state::hc11_analog_r<0>)); + sub.in_an1_callback().set(FUNC(taitojc_state::hc11_analog_r<1>)); + sub.in_an2_callback().set(FUNC(taitojc_state::hc11_analog_r<2>)); + sub.in_an3_callback().set(FUNC(taitojc_state::hc11_analog_r<3>)); + sub.in_an4_callback().set(FUNC(taitojc_state::hc11_analog_r<4>)); + sub.in_an5_callback().set(FUNC(taitojc_state::hc11_analog_r<5>)); + sub.in_an6_callback().set(FUNC(taitojc_state::hc11_analog_r<6>)); + sub.in_an7_callback().set(FUNC(taitojc_state::hc11_analog_r<7>)); TMS32051(config, m_dsp, XTAL(10'000'000)*4); // 40MHz, clock source = CY7C991 m_dsp->set_addrmap(AS_PROGRAM, &taitojc_state::tms_program_map); diff --git a/src/mame/includes/taitojc.h b/src/mame/includes/taitojc.h index 9d6dd1da67d..e77dc3eff5c 100644 --- a/src/mame/includes/taitojc.h +++ b/src/mame/includes/taitojc.h @@ -109,7 +109,7 @@ private: DECLARE_READ8_MEMBER(hc11_data_r); DECLARE_READ8_MEMBER(hc11_output_r); DECLARE_WRITE8_MEMBER(hc11_data_w); - DECLARE_READ8_MEMBER(hc11_analog_r); + template uint8_t hc11_analog_r(); DECLARE_READ16_MEMBER(dsp_shared_r); DECLARE_WRITE16_MEMBER(dsp_shared_w); @@ -149,7 +149,6 @@ private: void draw_object_bank(bitmap_ind16 &bitmap, const rectangle &cliprect, uint8_t bank_type, uint8_t pri); void dendego_map(address_map &map); - void hc11_io_map(address_map &map); void hc11_pgm_map(address_map &map); void taitojc_map(address_map &map); void tms_data_map(address_map &map);