mirror of
https://github.com/holub/mame
synced 2025-05-08 23:31:54 +03:00
cleanup (nw)
This commit is contained in:
Miodrag Milanovic
parent
53b1eb69ac
commit
f7c4d79714
@ -152,10 +152,6 @@ TIMER_DEVICE_CALLBACK_MEMBER(pcw16_state::pcw16_timer_callback)
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static ADDRESS_MAP_START(pcw16_map, AS_PROGRAM, 8, pcw16_state )
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AM_RANGE(0x0000, 0xffff) AM_READWRITE(pcw16_mem_r, pcw16_mem_w)
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// AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank5")
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// AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank6")
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// AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank7")
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// AM_RANGE(0xc000, 0xffff) AM_READ_BANK("bank4") AM_WRITE_BANK("bank8")
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ADDRESS_MAP_END
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@ -164,339 +160,6 @@ WRITE8_MEMBER(pcw16_state::pcw16_palette_w)
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m_colour_palette[offset & 0x0f] = data & 31;
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}
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/*
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static const char *const pcw16_write_handler_dram[4] =
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{
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"bank5",
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"bank6",
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"bank7",
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"bank8"
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};
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static const char *const pcw16_read_handler_dram[4] =
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{
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"bank1",
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"bank2",
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"bank3",
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"bank4"
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};
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// PCW16 Flash interface
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// PCW16 can have two 1mb flash chips
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// read flash0
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static int pcw16_flash0_bank_handler_r(running_machine &machine, int bank, int offset)
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{
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pcw16_state *state = machine.driver_data<pcw16_state>();
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intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash0");
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int flash_offset = (state->m_banks[bank]<<14) | offset;
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return flash->read(flash_offset);
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}
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// read flash1
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static int pcw16_flash1_bank_handler_r(running_machine &machine, int bank, int offset)
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{
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pcw16_state *state = machine.driver_data<pcw16_state>();
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intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash1");
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int flash_offset = ((state->m_banks[bank]&0x03f)<<14) | offset;
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return flash->read(flash_offset);
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}
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// flash 0
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static READ8_HANDLER(pcw16_flash0_bank_handler0_r)
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{
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return pcw16_flash0_bank_handler_r(space.machine(),0, offset);
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}
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static READ8_HANDLER(pcw16_flash0_bank_handler1_r)
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{
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return pcw16_flash0_bank_handler_r(space.machine(),1, offset);
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}
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static READ8_HANDLER(pcw16_flash0_bank_handler2_r)
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{
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return pcw16_flash0_bank_handler_r(space.machine(),2, offset);
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}
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static READ8_HANDLER(pcw16_flash0_bank_handler3_r)
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{
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return pcw16_flash0_bank_handler_r(space.machine(),3, offset);
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}
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// flash 1
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static READ8_HANDLER(pcw16_flash1_bank_handler0_r)
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{
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return pcw16_flash1_bank_handler_r(space.machine(),0, offset);
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}
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static READ8_HANDLER(pcw16_flash1_bank_handler1_r)
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{
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return pcw16_flash1_bank_handler_r(space.machine(),1, offset);
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}
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static READ8_HANDLER(pcw16_flash1_bank_handler2_r)
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{
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return pcw16_flash1_bank_handler_r(space.machine(),2, offset);
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}
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static READ8_HANDLER(pcw16_flash1_bank_handler3_r)
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{
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return pcw16_flash1_bank_handler_r(space.machine(),3, offset);
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}
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static const struct { read8_space_func func; const char *name; } pcw16_flash0_bank_handlers_r[4] =
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{
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{ FUNC(pcw16_flash0_bank_handler0_r) },
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{ FUNC(pcw16_flash0_bank_handler1_r) },
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{ FUNC(pcw16_flash0_bank_handler2_r) },
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{ FUNC(pcw16_flash0_bank_handler3_r) }
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};
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static const struct { read8_space_func func; const char *name; } pcw16_flash1_bank_handlers_r[4] =
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{
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{ FUNC(pcw16_flash1_bank_handler0_r) },
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{ FUNC(pcw16_flash1_bank_handler1_r) },
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{ FUNC(pcw16_flash1_bank_handler2_r) },
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{ FUNC(pcw16_flash1_bank_handler3_r) }
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};
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// write flash0
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static void pcw16_flash0_bank_handler_w(running_machine &machine, int bank, int offset, int data)
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{
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pcw16_state *state = machine.driver_data<pcw16_state>();
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intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash0");
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int flash_offset = (state->m_banks[bank]<<14) | offset;
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flash->write(flash_offset, data);
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}
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// read flash1
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static void pcw16_flash1_bank_handler_w(running_machine &machine, int bank, int offset, int data)
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{
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pcw16_state *state = machine.driver_data<pcw16_state>();
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intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash1");
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int flash_offset = ((state->m_banks[bank]&0x03f)<<14) | offset;
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flash->write(flash_offset,data);
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}
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// flash 0
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static WRITE8_HANDLER(pcw16_flash0_bank_handler0_w)
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{
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pcw16_flash0_bank_handler_w(space.machine(),0, offset, data);
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}
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static WRITE8_HANDLER(pcw16_flash0_bank_handler1_w)
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{
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pcw16_flash0_bank_handler_w(space.machine(),1, offset, data);
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}
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static WRITE8_HANDLER(pcw16_flash0_bank_handler2_w)
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{
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pcw16_flash0_bank_handler_w(space.machine(),2, offset, data);
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}
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static WRITE8_HANDLER(pcw16_flash0_bank_handler3_w)
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{
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pcw16_flash0_bank_handler_w(space.machine(),3, offset, data);
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}
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// flash 1
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static WRITE8_HANDLER(pcw16_flash1_bank_handler0_w)
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{
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pcw16_flash1_bank_handler_w(space.machine(),0, offset, data);
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}
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static WRITE8_HANDLER(pcw16_flash1_bank_handler1_w)
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{
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pcw16_flash1_bank_handler_w(space.machine(),1, offset, data);
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}
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static WRITE8_HANDLER(pcw16_flash1_bank_handler2_w)
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{
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pcw16_flash1_bank_handler_w(space.machine(),2, offset, data);
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}
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static WRITE8_HANDLER(pcw16_flash1_bank_handler3_w)
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{
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pcw16_flash1_bank_handler_w(space.machine(),3, offset, data);
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}
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static const struct { write8_space_func func; const char *name; } pcw16_flash0_bank_handlers_w[4] =
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{
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{ FUNC(pcw16_flash0_bank_handler0_w) },
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{ FUNC(pcw16_flash0_bank_handler1_w) },
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{ FUNC(pcw16_flash0_bank_handler2_w) },
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{ FUNC(pcw16_flash0_bank_handler3_w) }
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};
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static const struct { write8_space_func func; const char *name; } pcw16_flash1_bank_handlers_w[4] =
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{
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{ FUNC(pcw16_flash1_bank_handler0_w) },
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{ FUNC(pcw16_flash1_bank_handler1_w) },
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{ FUNC(pcw16_flash1_bank_handler2_w) },
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{ FUNC(pcw16_flash1_bank_handler3_w) }
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};
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enum PCW16_RAM_TYPE
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{
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// rom which is really first block of flash0
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PCW16_MEM_ROM,
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// flash 0
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PCW16_MEM_FLASH_1,
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// flash 1 i.e. unexpanded pcw16
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PCW16_MEM_FLASH_2,
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// dram
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PCW16_MEM_DRAM,
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// no mem. i.e. unexpanded pcw16
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PCW16_MEM_NONE
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};
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READ8_MEMBER(pcw16_state::pcw16_no_mem_r)
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{
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return 0x0ff;
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}
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static void pcw16_set_bank_handlers(running_machine &machine, int bank, PCW16_RAM_TYPE type)
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{
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address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
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pcw16_state *state = machine.driver_data<pcw16_state>();
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switch (type) {
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case PCW16_MEM_ROM:
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// rom
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space.install_read_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_read_handler_dram[bank]);
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space.nop_write((bank * 0x4000), (bank * 0x4000) + 0x3fff);
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break;
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case PCW16_MEM_FLASH_1:
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// sram
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space.install_legacy_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash0_bank_handlers_r[bank].func, pcw16_flash0_bank_handlers_r[bank].name);
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space.install_legacy_write_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash0_bank_handlers_w[bank].func, pcw16_flash0_bank_handlers_w[bank].name);
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break;
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case PCW16_MEM_FLASH_2:
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space.install_legacy_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash1_bank_handlers_r[bank].func, pcw16_flash1_bank_handlers_r[bank].name);
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space.install_legacy_write_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash1_bank_handlers_w[bank].func, pcw16_flash1_bank_handlers_w[bank].name);
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break;
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case PCW16_MEM_NONE:
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space.install_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, read8_delegate(FUNC(pcw16_state::pcw16_no_mem_r),state));
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space.nop_write((bank * 0x4000), (bank * 0x4000) + 0x3fff);
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break;
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default:
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case PCW16_MEM_DRAM:
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// dram
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space.install_read_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_read_handler_dram[bank]);
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space.install_write_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_write_handler_dram[bank]);
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break;
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}
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}
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static void pcw16_update_bank(running_machine &machine, int bank)
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{
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pcw16_state *state = machine.driver_data<pcw16_state>();
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unsigned char *mem_ptr = NULL; // machine.device<ram_device>(RAM_TAG)->pointer();
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int bank_id = 0;
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int bank_offs = 0;
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char bank1[10];
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char bank2[10];
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// get memory bank
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bank_id = state->m_banks[bank];
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if ((bank_id & 0x080)==0)
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{
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bank_offs = 0;
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if (bank_id<4)
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{
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//lower 4 banks are write protected. Use the rom
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//loaded
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mem_ptr = &state->memregion("maincpu")->base()[0x010000];
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}
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else
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{
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intelfsh8_device *flashdev;
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// nvram
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if ((bank_id & 0x040)==0)
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{
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flashdev = machine.device<intelfsh8_device>("flash0");
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}
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else
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{
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flashdev = machine.device<intelfsh8_device>("flash1");
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}
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mem_ptr = (unsigned char *)flashdev->space().get_read_ptr(0);
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}
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}
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else
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{
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bank_offs = 128;
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//dram
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mem_ptr = machine.device<ram_device>(RAM_TAG)->pointer();
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}
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mem_ptr = mem_ptr + ((bank_id - bank_offs)<<14);
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state->m_mem_ptr[bank] = (char*)mem_ptr;
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sprintf(bank1,"bank%d",(bank+1));
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sprintf(bank2,"bank%d",(bank+5));
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state->membank(bank1)->set_base(mem_ptr);
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state->membank(bank2)->set_base(mem_ptr);
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if ((bank_id & 0x080)==0)
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{
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// selections 0-3 within the first 64k are write protected
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if (bank_id<4)
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{
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// rom
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pcw16_set_bank_handlers(machine, bank, PCW16_MEM_ROM);
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}
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else
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{
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// selections 0-63 are for flash-rom 0, selections
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// 64-128 are for flash-rom 1
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if ((bank_id & 0x040)==0)
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{
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pcw16_set_bank_handlers(machine, bank, PCW16_MEM_FLASH_1);
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}
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else
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{
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pcw16_set_bank_handlers(machine, bank, PCW16_MEM_FLASH_2);
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}
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}
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}
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else
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{
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pcw16_set_bank_handlers(machine, bank, PCW16_MEM_DRAM);
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}
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}
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// update memory h/w
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static void pcw16_update_memory(running_machine &machine)
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{
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pcw16_update_bank(machine, 0);
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pcw16_update_bank(machine, 1);
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pcw16_update_bank(machine, 2);
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pcw16_update_bank(machine, 3);
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}
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*/
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UINT8 pcw16_state::read_bank_data(UINT8 type, UINT16 offset)
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{
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if(type & 0x80) // DRAM
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@ -621,8 +284,6 @@ WRITE8_MEMBER(pcw16_state::pcw16_bankhw_w)
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//logerror("bank w: %d block: %02x\n", offset, data);
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m_banks[offset] = data;
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//pcw16_update_memory(machine());
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}
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WRITE8_MEMBER(pcw16_state::pcw16_video_control_w)
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@ -1392,29 +1053,28 @@ static ADDRESS_MAP_START(pcw16_io, AS_IO, 8, pcw16_state )
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ADDRESS_MAP_END
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static void pcw16_reset(running_machine &machine)
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void pcw16_state::machine_reset()
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{
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pcw16_state *state = machine.driver_data<pcw16_state>();
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/* initialise defaults */
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state->m_fdc_int_code = 2;
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m_fdc_int_code = 2;
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/* clear terminal count */
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pc_fdc_set_tc_state(machine, 0);
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pc_fdc_set_tc_state(machine(), 0);
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/* select first rom page */
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state->m_banks[0] = 0;
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m_banks[0] = 0;
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// pcw16_update_memory(machine);
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/* temp rtc setup */
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state->m_rtc_seconds = 0;
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state->m_rtc_minutes = 0;
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state->m_rtc_hours = 0;
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state->m_rtc_days_max = 0;
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state->m_rtc_days = 1;
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state->m_rtc_months = 1;
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state->m_rtc_years = 0;
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state->m_rtc_control = 1;
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state->m_rtc_256ths_seconds = 0;
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m_rtc_seconds = 0;
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m_rtc_minutes = 0;
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m_rtc_hours = 0;
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m_rtc_days_max = 0;
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m_rtc_days = 1;
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m_rtc_months = 1;
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m_rtc_years = 0;
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m_rtc_control = 1;
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m_rtc_256ths_seconds = 0;
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state->pcw16_keyboard_init();
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pcw16_keyboard_init();
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}
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@ -1430,8 +1090,6 @@ void pcw16_state::machine_start()
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at_keyboard_init(machine(), AT_KEYBOARD_TYPE_AT);
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at_keyboard_set_scan_code_set(3);
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pcw16_reset(machine());
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beep_set_state(speaker,0);
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beep_set_frequency(speaker,3750);
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}
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@ -95,6 +95,7 @@ public:
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UINT8 read_bank_data(UINT8 type, UINT16 offset);
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void write_bank_data(UINT8 type, UINT16 offset, UINT8 data);
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virtual void machine_start();
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virtual void machine_reset();
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virtual void video_start();
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virtual void palette_init();
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UINT32 screen_update_pcw16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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