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Get Kurzweil K2000 skeleton driver to boot. (#9545)
This commit is contained in:
Peter Sobot
GitHub
parent
0467f7c836
commit
f7eec60e64
@ -5,28 +5,38 @@
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krz2000.cpp - Kurzweil K2000 series
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Skeleton driver by R. Belmont
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Additional improvements by Peter Sobot
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Hardware in brief:
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TMP68301 CPU @ 16 MHz
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TMP68301 CPU @ 16 MHz (with debug port on RXD2/TXD2)
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uPD72064 FDC
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85C30 SCSI
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M37450 on I/O board to handle panel/display/keyboard scanning
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85C30 SCSI (53C80 on schematic?)
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M37450 @ 10 MHz on I/O board to handle panel/display/keyboard scanning, LED control, LCD contrast, and the audio switching matrix
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(16K of ROM stored on U69, 384 bytes of RAM, 8 A/D inputs, 2 D/A outputs, 6 ports of I/O, and a 31.25Kbaud serial link to the maincpu)
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HD6303 on I/O board to manage reverb DSP program loading
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VLSI ASIC "Calvin" - Unknown purpose (speculation: handles maincpu and PCM ROM/RAM addressing and DRAM refresh?)
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VLSI ASIC "Calvin" - Handles maincpu and PCM ROM/RAM addressing, as well as resampling (and possibly DRAM refresh)
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(on later K2000 and all later K-series units this is replaced by a more advanced VLSI ASIC "Janis")
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2x VLSI ASIC "Hobbes" - Unknown purpose (speculation: 'reverb' DSP, interpolation, accumulation, and shifting and dithering down a wider accumulator to a 16 bit output sample?)
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(service manual says "sample fetching tasks")
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2x VLSI ASIC "Hobbes" - specialized DSP processors for sound synthesis (oscillators, filters, etc)
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(service manual says "wave form generation and DSP functions")
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(each Hobbes chip handles a subset of available voices, and seems independently programmable)
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Digitech DSP256 Multi Effects VLSI Chip (reverb, chorus, delay, etc)
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(EPROM seems avaialble on eBay, but the chip itself is quite custom)
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***************************************************************************/
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#include "emu.h"
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#include "cpu/m68000/m68000.h"
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#include "cpu/m6502/m3745x.h"
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#include "machine/tmp68301.h"
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#include "machine/bankdev.h"
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#include "machine/upd765.h"
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#include "machine/ncr5380.h"
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#include "bus/nscsi/cd.h"
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#include "bus/nscsi/hd.h"
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#include "bus/midi/midi.h"
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#include "video/t6963c.h"
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#include "imagedev/floppy.h"
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#include "screen.h"
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#include "emupal.h"
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#include "softlist.h"
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@ -38,8 +48,11 @@ public:
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k2000_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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// , m_scanner(*this, "scanner")
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, m_1m_bank(*this, "bank1m")
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, m_mainram(*this, "mainram")
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// , m_midi(*this, "midi")
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// , m_fdc(*this, "fdc")
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{ }
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void k2000(machine_config &config);
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@ -52,24 +65,105 @@ private:
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void bank_map_1m(address_map &map);
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required_device<cpu_device> m_maincpu;
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// required_device<cpu_device> m_scanner;
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required_device<address_map_bank_device> m_1m_bank;
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required_shared_ptr<uint16_t> m_mainram;
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// optional_device<midi_port_device> m_midi;
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// required_device<upd765a_device> m_fdc;
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void ctrl_w(uint16_t data);
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void swap_bit_ctrl_w(uint16_t data);
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uint16_t battery_voltage_and_keyscanner_version(offs_t offset);
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uint16_t calvin_read(offs_t offset);
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void calvin_write(offs_t offset, uint16_t data);
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uint16_t hobbes0_read(offs_t offset);
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void hobbes0_write(offs_t offset, uint16_t data);
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uint16_t hobbes1_read(offs_t offset);
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void hobbes1_write(offs_t offset, uint16_t data);
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void k2000_palette(palette_device &palette) const;
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TIMER_CALLBACK_MEMBER(boot_hack_timer);
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emu_timer *m_boot_hack_timer;
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};
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void k2000_state::ctrl_w(uint16_t data)
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/**
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* From the K2000/K2000R service manual:
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*
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* The 68301 processor's 16 megabits (sic) of address space are divided into 16 equal memory blocks,
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* numbered 0-15. The first time the K2000 is powered up, Block 0 processes data for the boot
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* EPROM and setup EPROM, while Block 1 processes data for the PSRAM. Many of the K2000's basic
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* functions utilize the PSRAM, which accesses the higher address space of Block 1 in the CPU.
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* This slows down the access time somewhat, since the address space of the CPU is accessed in
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* sequence, beginning with Block 0.
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*
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* To optimize the processing speed, the K2000 performs a one-time software operation when
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* powered up for the first time. The memory management unit (MMU) in the gate array logic chip
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* (GAL) located at U35 on the engine board executes a "swap bit" function which makes Block 0
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* of the CPU responsible for the PSRAM, and Block 1 responsible for the Boot EPROM and Setup
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* EPROM. Consequently the PSRAM functions are processed as early as possible.
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*
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* Note this "16 equal memory blocks" idea is really just the top hex digit of the address -
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* i.e.: 0x?FFFFF
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*/
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void k2000_state::swap_bit_ctrl_w(uint16_t data)
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{
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data &= 0xff;
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logerror("%02x to ctrl_w\n", data);
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// bit 4: 0=program ROM at 0, work RAM at 100000, 1=work RAM at 0, program ROM at 100000.
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logerror("%02x written to swap_bit_ctrl_w\n", data);
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// bit 4:
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// 0 = program ROM at 0x000000, work RAM at 0x100000
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// 1 = work RAM at 0x000000, program ROM at 0x100000
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m_1m_bank->set_bank((data >> 4) & 1);
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}
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uint16_t k2000_state::battery_voltage_and_keyscanner_version(offs_t offset)
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{
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logerror("reading battery voltage and keyscanner version at %02x\n", offset);
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uint8_t battery_voltage = 0x36;
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uint8_t keyscanner_version = 0x12;
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return (((uint16_t) battery_voltage) << 8) | ((uint16_t) keyscanner_version);
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}
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uint16_t k2000_state::calvin_read(offs_t offset)
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{
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logerror("Read from Calvin at %06x\n", offset);
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return 0;
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}
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void k2000_state::calvin_write(offs_t offset, uint16_t data)
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{
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logerror("Write to Calvin at %06x = %04x\n", offset, data);
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}
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uint16_t k2000_state::hobbes0_read(offs_t offset)
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{
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logerror("Read from Hobbes[0] at %06x\n", offset);
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return 0;
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}
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void k2000_state::hobbes0_write(offs_t offset, uint16_t data)
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{
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logerror("Write to Hobbes[0] at %06x = %04x\n", offset, data);
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}
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uint16_t k2000_state::hobbes1_read(offs_t offset)
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{
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logerror("Read from Hobbes[1] at %06x\n", offset);
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return 0;
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}
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void k2000_state::hobbes1_write(offs_t offset, uint16_t data)
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{
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logerror("Write to Hobbes[1] at %06x = %04x\n", offset, data);
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}
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void k2000_state::machine_start()
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{
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m_boot_hack_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(k2000_state::boot_hack_timer), this));
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m_boot_hack_timer->adjust(attotime::from_seconds(2), 0, attotime::never);
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}
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void k2000_state::machine_reset()
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@ -77,23 +171,161 @@ void k2000_state::machine_reset()
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m_1m_bank->set_bank(0);
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}
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TIMER_CALLBACK_MEMBER(k2000_state::boot_hack_timer)
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{
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logerror("Jumping to interrupt vector to continue boot sequence");
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m_maincpu->set_pc(m_1m_bank->read32(0x80));
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}
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void k2000_state::k2000_map(address_map &map)
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{
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// word writes to 000000 region - unknown
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// word writes to 000090 region - unknown
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// word writes to 000180 region - unknown
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// word writes to 000240 region - unknown
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// The engine ROMs are mapped onto 0x0 when ENGROMCSb is low, which is IO3 of GODOT (pin 18)
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// The setup ROMs are mapped onto 0x100000 when SUROMCSb is low, which is the IO2 output (pin 17) of GODOT
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// This implies that IO3 of GODOT is low iff CA{20,23} are also low, and IO2 of GODOT is low iff CA{20,23} = 0x01
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// Block 0, Block 1: ROM and RAM (depending on bank switch)
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map(0x000000, 0x1fffff).m(m_1m_bank, FUNC(address_map_bank_device::amap16));
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// Lots of writes to 0x372B68 -> 0x372C8C
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// Block 4: PRAM?
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// "The K2000 comes standard with 116KB, and with the PRAM upgrade, totals 760KB."
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// Another source says:
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// For the K2000 Series, the total memory allocated to all of these objects is
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// 120K expandable to 760K with the PRAM option. For the K2500 Series, it is 256k,
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// expandable to 1280k with the PRAM option. For the K2600 Series, it is 486k,
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// expandable to 1506k with the PRAM option.
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// These are pretty odd numbers - but it sounds like ~8KB of the RAM space is used
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// for OS functions, meaning the built-in RAM might only be 128KB in total.
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// The K2000 schematic shows 2x 1M "NVRAM" chips, one for the low byte, and one for
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// the high byte, which means we should (?) actually have 2 * 1024 * 1024 / 8 = 262,144 bytes?
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//
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// The boot routines seem to write to 0x400000 and compare the value saved there, so
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// this is probably the optional PRAM expansion.
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map(0x400000, 0x400000 + ((2 * 1024 * 1024) / 8) - 1).ram();
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// Init routine sets 0x4BAB44 -> 0x4BFFFA to 0x0000
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// Reads from 0x4BFFFC and 0x4BFFFE seem to happen on startup.
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// HOBBES0CSb = NAND(CS1', CA19) = high unless CS1 is high and CA19 is high
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// HOBBES1CSb = NAND(CS1', !CA19) = high unless CS1 is high and CA19 is low
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// 0xFFFC00 is the Address Decoder area that controls which part of memory causes CS1 to be "enabled" (low)
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// At runtime,
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// 0xFFFC00 = 0x50 =
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// 0xFFFC01 = 0x3F
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// 0xFFFC02 = 0x00
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// 0xFFFC03 = 0x30
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// For CS1:
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// 0xFFFC04 = 0x60 = 0b0110 0000 = Start address of the memory area for CS1 = A21 + A22
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// 0xFFFC05 = 0x3F = 0b0011 1111 = Size of memory area = M19 + M18 + M17 + M16 + M15-M9 + M8 = 1MB
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// 0xFFFC06 = 0x00
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// 0xFFFC07 = 0x30 = 0b0011 0000 = Area enabled, use external DTACK
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// By this logic, Hobbes chips are mapped to 0x100000, 0x200000, 0x400000, 0x600000
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// And their address mask is 0x000FFF00, which means the effective ranges are:
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// 0x100???00
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// Hobbes chip selection seems to look at CA19 and CS1
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// Internal sample ROM is switched on SBA20,SBA21, which corresponds to CA21,CA22 (one bit off)
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// meaning the internal address space for accessing the sample ROM is 0x200000 through 0x6fffff (?)
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// Blocks 2, 3, 4, 5, 6
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// map(0x200000, 0x2fffff).rom().region("pcm", 0); // Block 2: Sample ROM
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// map(0x300000, 0x3fffff).rom().region("pcm", 0x100000); // Block 3: Sample ROM
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// map(0x400000, 0x4fffff).rom().region("pcm", 0x200000); // Block 4: Sample ROM
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// Writes to 0x4FFD82, 0x4FFD88, 0x4FFE24
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// Hypothesis: Calvin (or Janis) is mapped at 0x500000
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// Writes to 0x500402, 0x500418, 0x50041A early in the boot process
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// Initialization then writes zeros in a descending ladder:
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// 0x500400, 0x500402
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// 0x5003FC, 0x5003FE, ...
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// down to 0x500004 (then 0x500006)
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// Calvin memory?
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map(0x500000, 0x5003FF).rw(FUNC(k2000_state::calvin_read), FUNC(k2000_state::calvin_write));
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// Calvin control registers?
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map(0x500400, 0x5004FF).rw(FUNC(k2000_state::calvin_read), FUNC(k2000_state::calvin_write));
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// Reads and writes to 0x580000
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// Hobbes (it seems) is connected in the 0x600000 range
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// The second Hobbes chip (?) seems connected at 0x680000
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// Initialization seems to:
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// - write to 0x600300, followed by 0x600xxx where xxx is in 0x400 through 0x5FF
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// - write to 0x6?0002, 0x6?0006, 0x6?0004, through 0x6?000F4
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// - write to 0x600004, 0x600014, 0x600024... through 0x6002F4
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// (with a repeating pattern of [0x02, 0x00, 0x26, 0x24, 0x4A, 0x48])
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// - write to 0x680004, 0x680014, 0x680024... through 0x6802F4
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// (with a repeating pattern of [0x80, 0x02, 0xA4, 0x26, 0xC6, 0x4A])
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// Each Hobbes chip seems to have two control registers, mapped at 0x600300/0x680300 and 0x600400/0x680400
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// Hobbes memory?
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map(0x600000, 0x6002FF).rw(FUNC(k2000_state::hobbes0_read), FUNC(k2000_state::hobbes0_write));
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// Hobbes control registers?
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map(0x600300, 0x6005FF).rw(FUNC(k2000_state::hobbes0_read), FUNC(k2000_state::hobbes0_write));
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// Hobbes memory?
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map(0x680000, 0x6802FF).rw(FUNC(k2000_state::hobbes1_read), FUNC(k2000_state::hobbes1_write));
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// Hobbes control registers?
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map(0x680300, 0x6805FF).rw(FUNC(k2000_state::hobbes1_read), FUNC(k2000_state::hobbes1_write));
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// SROM - Setup ROM?
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uint32 srom_base = 0x280000;
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map(srom_base, srom_base + 0x40000 - 1).rom().region("maincpu", 0x100000);
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// Calvin chip has a 20-bit address bus with A0 tied low and A12-15 tied high, giving it access to 0x?0??[0-E]
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// Later models' Janis chips use 24-bit address buses (or at least they're all connected in the schematic)
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// Hobbes has a 10-bit address bus with A0 tied low, giving access to 0x0 through 0x3FF
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// Block 7: LCD control and bank switching
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map(0x700000, 0x700003).rw("lcd", FUNC(lm24014h_device::read), FUNC(lm24014h_device::write)).umask16(0x00ff);
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map(0x7e0000, 0x7e0001).w(FUNC(k2000_state::ctrl_w));
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// Reads from 0x740000 (floppy?)
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// Writes to 0x760000
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// Writes to 0x7C0000
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// Single byte reads seem to happen at 0x740000, which seems to be FDCCTLCSb?
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// map(0x740000, 0x74000F).
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map(0x7e0000, 0x7e0001).w(FUNC(k2000_state::swap_bit_ctrl_w));
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// Some sort of hardware mapping - initial firmware boot expects a 4 at $78000B
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map(0x780000, 0x78FFFF).ram();
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// When (CPUASb + GODOT I6) and (GODOT I/O0 + IOCSb) are low,
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// Address bits 17, 18, 19 get demultiplexed onto:
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// 0, 0, 0 => LCDCSb
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// 0, 0, 1 => FDCCSb
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// 0, 1, 0 => FDCCTLCSb
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// 0, 1, 1 => FDCOUTCSb
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// 1, 0, 0 => SCSICSb
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// 1, 0, 1 => SCSIDMACSb
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// 1, 1, 0 => CPUEXPCSb
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// 1, 1, 1 => MCTLREGCSb (OR'ed with WRITELOb to provide input into the Memory Management Control Register)
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// map(0x800000, 0x8fffff); // Block 8: ???
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// map(0x900000, 0x9fffff); // Block 9: ???
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// map(0xa00000, 0xffffff); // Blocks 10, 11, 12, 13, 14: Orchestral ROM
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// map(0x1000000, 0x18fffff); // Blocks 15, 16, 17, 18, 19: Contemporary ROM
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}
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void k2000_state::bank_map_1m(address_map &map)
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{
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map(0x000000, 0x0fffff).rom().region("maincpu", 0);
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map(0x100000, 0x1fffff).ram().share("mainram");
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// The "stride" of this bank map is 0x200000, so this is the second "view" of the same data
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map(0x200000, 0x2fffff).ram().share("mainram");
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map(0x300000, 0x3fffff).rom().region("maincpu", 0);
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// Unsure if the battery voltage and keyscanner data is memory-mapped at these ranges (unlikely)
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// or if this data is written to some time during the boot process. If it's the latter,
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// this will have to change when loading different versions of the ROM (or someone has to figure
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// out where the battery voltage is actually read from).
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map(0x100000 + 0x1052, 0x100000 + 0x1053).r(FUNC(k2000_state::battery_voltage_and_keyscanner_version));
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map(0x200000 + 0x1052, 0x200000 + 0x1053).r(FUNC(k2000_state::battery_voltage_and_keyscanner_version));
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}
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void k2000_state::k2000(machine_config &config)
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@ -101,14 +333,47 @@ void k2000_state::k2000(machine_config &config)
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TMP68301(config, m_maincpu, XTAL(12'000'000));
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m_maincpu->set_addrmap(AS_PROGRAM, &k2000_state::k2000_map);
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// MIDI_PORT(config, m_midi, midiin_slot, "midiin");
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// TODO: Uncomment when the TMP68301 has serial/MIDI support, to wire up MIDI I/O and scanner.
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// MIDI_PORT(config, m_midi, midiout_slot, "midiout");
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// M37450(config, m_scanner, XTAL(10'000'000));
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// The "Scanner" sub-CPU is connected to main CPU via:
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// - MIDI_FM_ENG, going to P34/RxD, which comes from SERTxD, which is INTMIDITxD == TxD1
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// - 37450_TXD, coming from P35/TxD, which is NAND'd together with 6303_TXD
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// and inverted to provide SERRxD to the engine (maincpu), which goes to INTMIDIRxD
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// eventually ending up at RxD1
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// Essentially, the 68k's second built-in serial port runs at 31250Hz, which is MIDI baud rate,
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// which is how it talks to the scanner to tell it to operate the LEDs on the front of the case.
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// The external MIDI port(s) are connected directly to the 68K's first serial port, RxD0 and TxD0.
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// (RxD2 and TxD2 are hooked up to a "debug port" which the manual says requires additional
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// hardware - this is untested.)
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// The scanner's ROM comes from an NTE2764 (U69, 28-pin DIP) EPROM of which 16Kb are used.
|
||||
// (Note that on the K2500 and above, the scanner is an M37451M8-FP the ROM is 16KB, but stored on an M27256.)
|
||||
// The scanner ROM from the K2500 may be compatible with the K2000, and can be pulled from "U2"
|
||||
// on the K2500 Audio Scanner Board (Rev D)
|
||||
|
||||
ADDRESS_MAP_BANK(config, "bank1m").set_map(&k2000_state::bank_map_1m).set_options(ENDIANNESS_BIG, 16, 24, 0x200000);
|
||||
|
||||
// uPD765AC; clocked through SED9420C
|
||||
// UPD765A(config, m_fdc, 16_MHz_XTAL / 4, true, true);
|
||||
// m_fdc->intrq_wr_callback().set_inputline(m_maincpu, I6);
|
||||
// FLOPPY_CONNECTOR(config, "fdc:0", dss1_floppies, "35dd", floppy_image_device::default_floppy_formats).enable_sound(true);
|
||||
// FLOPPY_CONNECTOR(config, "fdc:1", dss1_floppies, nullptr, floppy_image_device::default_floppy_formats).enable_sound(true);
|
||||
|
||||
PALETTE(config, "palette", FUNC(k2000_state::k2000_palette), 2);
|
||||
|
||||
LM24014H(config, "lcd");
|
||||
|
||||
SPEAKER(config, "lspeaker").front_left();
|
||||
SPEAKER(config, "rspeaker").front_right();
|
||||
}
|
||||
|
||||
void k2000_state::k2000_palette(palette_device &palette) const
|
||||
{
|
||||
palette.set_pen_color(0, rgb_t(131, 136, 139));
|
||||
palette.set_pen_color(1, rgb_t( 92, 83, 88));
|
||||
}
|
||||
|
||||
|
||||
static INPUT_PORTS_START( k2000 )
|
||||
@ -199,7 +464,12 @@ ROM_START( k2000 )
|
||||
ROM_REGION(0x3000, "pals", 0)
|
||||
ROM_LOAD( "pseudo_v4d.u11.gal16v8b.jed", 0x000000, 0x000bd0, CRC(43561132) SHA1(a0c567c81022bc7fb83023d89556ccd5aa1ab36d) )
|
||||
ROM_LOAD( "sndram_v1.u50.gal16v8b.jed", 0x001000, 0x000bd0, CRC(cabc9335) SHA1(968fa5baa43c7589c901f09b12085437834aeb37) )
|
||||
// GODOT seems to take in the top 4 maincpu address lines (A20-A24) and multiplex/decode onto 11 (?) I/O lines
|
||||
// Effectively takes care of the "memory block" logic (MMU/bank switching) that the service manual describes
|
||||
ROM_LOAD( "godot_v5.u10.gal20v8a.jed", 0x002000, 0x00066f, CRC(c6517456) SHA1(b82530d46afdca5f6460e77ac11710cad55a6b89) )
|
||||
// There's an additional GAL20V8 for the MMU - exact logic unknown, but the MCTL[0-3] lines are used, which seem
|
||||
// like the "address space select" lines - so at least one or more of those address space areas map directly to SBA[22-25], which
|
||||
// seem to be the Sample Bank address lines.
|
||||
ROM_END
|
||||
|
||||
CONS( 1990, k2000, 0, 0, k2000, k2000, k2000_state, empty_init, "Kurzweil Music Systems", "K2000", MACHINE_NOT_WORKING|MACHINE_NO_SOUND )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user