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https://github.com/holub/mame
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3c505: added lle [Patrick Mackinlay, Neko May]
LLE implementation of 3Com 3c505. Untested due to unresolved driver issues, but should replace existing HLE when tested working. (nw)
This commit is contained in:
Patrick Mackinlay
parent
d0356891eb
commit
f7fa5c89e1
@ -299,6 +299,7 @@ constexpr unsigned threecom3c505_device::ETH_BUFFER_SIZE;
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// device type definition
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DEFINE_DEVICE_TYPE(ISA16_3C505, threecom3c505_device, "3c505", "3Com 3C505 Network Adaptor")
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DEFINE_DEVICE_TYPE(ISA16_3C505_LLE, isa16_3c505_device, "3c505_lle", "3Com EtherLink Plus")
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//-------------------------------------------------
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// threecom3c505_device - constructor
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@ -1686,3 +1687,652 @@ int threecom3c505_device::setfilter(device_t *device, int node_id)
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{
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return 0;
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}
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/*
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* The following device is a low-level reimplementation of the 3c505, which
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* should entirely replace the HLE one above when it's been tested and proven
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* working.
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*
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* TODO
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* - testing (unable to install Domain/OS on Apollo, and not yet able to get
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* 3c505.exe diagnostic program running on MS-DOS)
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* - data DMA functionality unimplemented
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* - externalize mac address
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* - 8 bit isa slot support
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* - revision 1.0 and 2.0 hardware/firmware variants
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* - 8023 loopback mode
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*/
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#undef LOG
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#undef VERBOSE
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#define LOG_GENERAL (1U << 0)
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#define LOG_REG (1U << 1)
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#define VERBOSE (0)
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#include "logmacro.h"
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ROM_START(3c505)
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ROM_REGION16_LE(0x04000, "system", 0)
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// TODO: probably a revision 3.0 firmware dump
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ROMX_LOAD("0729-12_a.3h", 0x00000, 0x02000, CRC(5415fccd) SHA1(6a42d7f3acdb3e0213e1037fee1864819ac33991), ROM_SKIP(1))
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ROMX_LOAD("0729-62_a.3f", 0x00001, 0x02000, CRC(4240bd9d) SHA1(015d2f7282def85681bcf1a7c5a7f501a16d5a6c), ROM_SKIP(1))
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ROM_REGION(0x02000, "host", 0)
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ROM_SYSTEM_BIOS(0, "unused", "Unused")
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ROM_SYSTEM_BIOS(1, "apollo", "Apollo")
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ROMX_LOAD("3000_3c505_010728-00.bin", 0x00000, 0x02000, CRC(69b77ec6) SHA1(7ac36cc6fc90b90ddfc56c45303b514cbe18ae58), ROM_BIOS(1))
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ROM_SYSTEM_BIOS(2, "netware", "3C505-NW EtherLink Plus NetWare Boot PROM")
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ROMX_LOAD("3c505-nw.bin", 0x00000, 0x02000, NO_DUMP, ROM_BIOS(2))
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ROM_END
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static INPUT_PORTS_START(3c505)
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PORT_START("IO_BASE")
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PORT_DIPNAME(0x3f0, 0x300, "I/O Base")
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PORT_DIPSETTING( 0x010, "010h")
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PORT_DIPSETTING( 0x020, "020h")
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PORT_DIPSETTING( 0x030, "030h")
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PORT_DIPSETTING( 0x040, "040h")
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PORT_DIPSETTING( 0x050, "050h")
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PORT_DIPSETTING( 0x060, "060h")
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PORT_DIPSETTING( 0x070, "070h")
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PORT_DIPSETTING( 0x080, "080h")
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PORT_DIPSETTING( 0x090, "090h")
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PORT_DIPSETTING( 0x0a0, "0a0h")
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PORT_DIPSETTING( 0x0b0, "0b0h")
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PORT_DIPSETTING( 0x0c0, "0c0h")
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PORT_DIPSETTING( 0x0d0, "0d0h")
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PORT_DIPSETTING( 0x0e0, "0e0h")
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PORT_DIPSETTING( 0x0f0, "0f0h")
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PORT_DIPSETTING( 0x100, "0100h")
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PORT_DIPSETTING( 0x110, "0110h")
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PORT_DIPSETTING( 0x120, "0120h")
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PORT_DIPSETTING( 0x130, "0130h")
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PORT_DIPSETTING( 0x140, "0140h")
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PORT_DIPSETTING( 0x150, "0150h")
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PORT_DIPSETTING( 0x160, "0160h")
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PORT_DIPSETTING( 0x170, "0170h")
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PORT_DIPSETTING( 0x180, "0180h")
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PORT_DIPSETTING( 0x190, "0190h")
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PORT_DIPSETTING( 0x1a0, "01a0h")
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PORT_DIPSETTING( 0x1b0, "01b0h")
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PORT_DIPSETTING( 0x1c0, "01c0h")
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PORT_DIPSETTING( 0x1d0, "01d0h")
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PORT_DIPSETTING( 0x1e0, "01e0h")
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PORT_DIPSETTING( 0x1f0, "01f0h")
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PORT_DIPSETTING( 0x200, "0200h")
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PORT_DIPSETTING( 0x210, "0210h")
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PORT_DIPSETTING( 0x220, "0220h")
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PORT_DIPSETTING( 0x230, "0230h")
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PORT_DIPSETTING( 0x240, "0240h")
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PORT_DIPSETTING( 0x250, "0250h")
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PORT_DIPSETTING( 0x260, "0260h")
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PORT_DIPSETTING( 0x270, "0270h")
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PORT_DIPSETTING( 0x280, "0280h")
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PORT_DIPSETTING( 0x290, "0290h")
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PORT_DIPSETTING( 0x2a0, "02a0h")
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PORT_DIPSETTING( 0x2b0, "02b0h")
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PORT_DIPSETTING( 0x2c0, "02c0h")
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PORT_DIPSETTING( 0x2d0, "02d0h")
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PORT_DIPSETTING( 0x2e0, "02e0h")
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PORT_DIPSETTING( 0x2f0, "02f0h")
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PORT_DIPSETTING( 0x300, "0300h")
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PORT_DIPSETTING( 0x310, "0310h")
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PORT_DIPSETTING( 0x320, "0320h")
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PORT_DIPSETTING( 0x330, "0330h")
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PORT_DIPSETTING( 0x340, "0340h")
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PORT_DIPSETTING( 0x350, "0350h")
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PORT_DIPSETTING( 0x360, "0360h")
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PORT_DIPSETTING( 0x370, "0370h")
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PORT_DIPSETTING( 0x380, "0380h")
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PORT_DIPSETTING( 0x390, "0390h")
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PORT_DIPSETTING( 0x3a0, "03a0h")
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PORT_DIPSETTING( 0x3b0, "03b0h")
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PORT_DIPSETTING( 0x3c0, "03c0h")
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PORT_DIPSETTING( 0x3d0, "03d0h")
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PORT_DIPSETTING( 0x3e0, "03e0h")
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PORT_DIPSETTING( 0x3f0, "03f0h")
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PORT_START("IRQ_DRQ")
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PORT_DIPNAME(0x0f, 0x0a, "IRQ")
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// 8 or 16 bit slots
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PORT_DIPSETTING( 0x03, "IRQ 3")
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PORT_DIPSETTING( 0x04, "IRQ 4")
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PORT_DIPSETTING( 0x05, "IRQ 5")
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PORT_DIPSETTING( 0x06, "IRQ 6")
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PORT_DIPSETTING( 0x07, "IRQ 7")
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PORT_DIPSETTING( 0x09, "IRQ 9")
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// 16 bit slots only
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PORT_DIPSETTING( 0x0a, "IRQ 10")
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PORT_DIPSETTING( 0x0b, "IRQ 11")
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PORT_DIPSETTING( 0x0c, "IRQ 12")
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PORT_DIPSETTING( 0x0e, "IRQ 14")
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PORT_DIPSETTING( 0x0f, "IRQ 15")
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// TODO: dma channel uses two jumpers for each channel: mode selection?
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PORT_DIPNAME(0x70, 0x60, "DRQ")
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PORT_DIPSETTING( 0x00, "none")
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// 8 or 16 bit slots
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PORT_DIPSETTING( 0x10, "DRQ 1")
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PORT_DIPSETTING( 0x30, "DRQ 3")
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// 16 bit slots only
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PORT_DIPSETTING( 0x50, "DRQ 5")
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PORT_DIPSETTING( 0x60, "DRQ 6")
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PORT_DIPSETTING( 0x70, "DRQ 7")
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// 8-position jumper block marked EN,13-19 corresponds to address line decode
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PORT_START("ROM_OPTS")
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PORT_DIPNAME(0x01, 0x01, "ROM Enable")
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PORT_DIPSETTING( 0x00, DEF_STR(Off))
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PORT_DIPSETTING( 0x01, DEF_STR(On))
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PORT_DIPNAME(0xfe, 0x00, "ROM Base")
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PORT_DIPSETTING( 0x00, "0000h")
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PORT_DIPSETTING( 0x02, "2000h")
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PORT_DIPSETTING( 0x04, "4000h")
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PORT_DIPSETTING( 0x06, "6000h")
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// TODO: additional addresses
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PORT_START("TEST")
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PORT_DIPNAME(0x01, 0x00, "TEST Mode")
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PORT_DIPSETTING( 0x00, DEF_STR(Off))
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PORT_DIPSETTING( 0x01, DEF_STR(On))
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INPUT_PORTS_END
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isa16_3c505_device::isa16_3c505_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: device_t(mconfig, ISA16_3C505_LLE, tag, owner, clock)
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, device_isa16_card_interface(mconfig, *this)
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, m_cpu(*this, "cpu")
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, m_net(*this, "net")
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, m_ram(*this, "ram")
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, m_led(*this, "led%u", 0U)
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, m_iobase(*this, "IO_BASE")
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, m_irqdrq(*this, "IRQ_DRQ")
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, m_romopts(*this, "ROM_OPTS")
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, m_test(*this, "TEST")
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, m_installed(false)
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{
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}
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const tiny_rom_entry *isa16_3c505_device::device_rom_region() const
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{
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return ROM_NAME(3c505);
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}
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void isa16_3c505_device::device_add_mconfig(machine_config &config)
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{
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I80186(config, m_cpu, 16_MHz_XTAL);
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m_cpu->set_addrmap(AS_PROGRAM, &isa16_3c505_device::map_main);
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m_cpu->set_addrmap(AS_IO, &isa16_3c505_device::map_io);
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I82586(config, m_net, 8_MHz_XTAL);
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m_net->set_addrmap(0, &isa16_3c505_device::map_main);
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m_net->out_irq_cb().set(m_cpu, FUNC(i80186_cpu_device::int1_w));
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// 1986 document indicates 128KiB is default, but 1988 document does not
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// include it as an option
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RAM(config, m_ram);
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m_ram->set_default_size("256KiB");
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m_ram->set_extra_options("128KiB,256KiB,384KiB,512KiB");
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}
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ioport_constructor isa16_3c505_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME(3c505);
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}
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void isa16_3c505_device::device_start()
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{
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set_isa_device();
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// install ram in both i80186 and i82586 address spaces
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if (!m_ram->started())
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throw device_missing_dependencies();
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m_cpu->space(0).install_ram(0x00000, m_ram->mask() & 0xfffff, m_ram->pointer());
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m_net->space(0).install_ram(0x00000, m_ram->mask() & 0xfffff, m_ram->pointer());
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m_led.resolve();
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save_item(NAME(m_acmdr));
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save_item(NAME(m_acr));
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save_item(NAME(m_asr));
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save_item(NAME(m_hcmdr));
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save_item(NAME(m_hcr));
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save_item(NAME(m_hsr));
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save_item(NAME(m_hdr));
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//save_item(NAME(m_data);
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save_item(NAME(m_cpu_irq_asserted));
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save_item(NAME(m_isa_irq_asserted));
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}
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void isa16_3c505_device::device_reset()
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{
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if (!m_installed)
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{
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u16 const base = m_iobase->read();
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m_isa->install16_device(base, base | 0xf,
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read16_delegate(FUNC(isa16_3c505_device::host_r), this),
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write16_delegate(FUNC(isa16_3c505_device::host_w), this));
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m_isa_irq = m_irqdrq->read() & 0xf;
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m_isa_drq = (m_irqdrq->read() >> 4) & 0x7;
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if (m_romopts->read() & 1)
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{
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offs_t const rom_base = (m_romopts->read() & 0xfe) << 12;
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m_isa->install_rom(this, rom_base, rom_base | 0x01fff, "host", "host");
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}
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m_installed = true;
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}
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m_cpu->reset();
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// adapter registers
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m_acmdr = 0;
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m_acr = 0;
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m_asr = ASR_ACRE | ASR_8_16;
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if (m_test->read())
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m_asr |= ASR_SWTC;
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// host registers
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m_hcmdr = 0;
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m_hcr = 0;
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m_hsr = HSR_HCRE;
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m_hdr = 0;
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m_data.clear();
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update_rdy(m_acr, m_hcr);
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m_cpu_irq_asserted = false;
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m_isa_irq_asserted = false;
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}
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void isa16_3c505_device::map_main(address_map &map)
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{
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// i82586 upper 4 address lines are ignored
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map.global_mask(0x0fffff);
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map(0xfc000, 0xfffff).rom().region("system", 0);
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}
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void isa16_3c505_device::map_io(address_map &map)
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{
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/*
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* A read or write to I/O location 00H will cause an active transition on
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* the CA input.
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*/
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map(0x0000, 0x0000).lrw8("ca",
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[this]()
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{
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m_net->ca(1);
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m_net->ca(0);
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return 0;
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},
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[this](u8 data)
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{
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m_net->ca(1);
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m_net->ca(0);
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});
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/*
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* A read or write to I/O location 80H will produce a CAS before RAS cycle
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* in all banks simultaneously.
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*/
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map(0x0080, 0x0081).noprw();
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map(0x0100, 0x0100).rw(FUNC(isa16_3c505_device::acmd_r), FUNC(isa16_3c505_device::acmd_w));
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map(0x0102, 0x0102).r(FUNC(isa16_3c505_device::acr_r));
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map(0x0103, 0x0103).rw(FUNC(isa16_3c505_device::asr_r), FUNC(isa16_3c505_device::acr_w));
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map(0x0104, 0x0105).rw(FUNC(isa16_3c505_device::adata_r), FUNC(isa16_3c505_device::adata_w));
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map(0x0180, 0x018f).lr16("mac",
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[](offs_t offset)
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{
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// TODO: hard-code to Apollo Computer Inc. dummy address for now
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static const u8 mac[] = { 0x08, 0x00, 0x1e, 0x12, 0x34, 0x56, 0xff, 0xff};
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return mac[offset];
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});
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}
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u8 isa16_3c505_device::acmd_r()
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{
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u8 const data = m_hcmdr;
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m_asr &= ~ASR_HCRF;
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m_hsr |= HSR_HCRE;
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if (m_cpu_irq_asserted)
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{
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m_cpu_irq_asserted = false;
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m_cpu->int0_w(0);
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}
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return data;
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}
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void isa16_3c505_device::acmd_w(u8 data)
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{
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LOGMASKED(LOG_REG, "acmd_w 0x%02x (%s)\n", data, machine().describe_context());
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m_asr &= ~ASR_ACRE;
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m_hsr |= HSR_ACRF;
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m_acmdr = data;
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if (m_hcr & HCR_CMDE)
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update_irq(1);
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}
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void isa16_3c505_device::acr_w(u8 data)
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{
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LOGMASKED(LOG_REG, "acr_w 0x%02x (%s)\n", data, machine().describe_context());
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// update adapter status flags
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if ((data ^ m_acr) & ACR_ASF)
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m_hsr = (m_hsr & ~HSR_ASF) | (data & ACR_ASF);
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if ((data ^ m_acr) & ACR_LED1)
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{
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LOGMASKED(LOG_REG, "led #1 %s\n", (data & ACR_LED1) ? "on" : "off");
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m_led[0] = !!(data & ACR_LED1);
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}
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if ((data ^ m_acr) & ACR_LED2)
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{
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LOGMASKED(LOG_REG, "led #2 %d\n", (data & ACR_LED2) ? "on" : "off");
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m_led[1] = !!(data & ACR_LED2);
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}
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if (!(m_acr & ACR_R586) && (data & ACR_R586))
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{
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LOGMASKED(LOG_REG, "i82586 reset\n");
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m_net->reset();
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}
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if ((data ^ m_acr) & ACR_FLSH)
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{
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if (data & ACR_FLSH)
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{
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LOGMASKED(LOG_REG, "adapter flushed data fifo (%d bytes)\n", m_data.queue_length());
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m_data.clear();
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}
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update_rdy(data, m_hcr);
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}
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// loopback is active low
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if ((m_acr & ACR_LPBK) && !(data & ACR_LPBK))
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{
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LOGMASKED(LOG_REG, "loopback enabled\n", m_data.queue_length());
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// TODO: enable loopback on 8023
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}
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||||
m_acr = data;
|
||||
}
|
||||
|
||||
u16 isa16_3c505_device::adata_r()
|
||||
{
|
||||
if (!(m_asr & ASR_DIR) && !m_data.empty())
|
||||
{
|
||||
u16 const data = m_data.dequeue();
|
||||
|
||||
update_rdy(m_acr, m_hcr);
|
||||
|
||||
return data;
|
||||
}
|
||||
else
|
||||
fatalerror("%s: adata_r read fifo while %s (%s)\n",
|
||||
tag(), m_data.empty() ? "empty" : "write-only", machine().describe_context().c_str());
|
||||
}
|
||||
|
||||
void isa16_3c505_device::adata_w(u16 data)
|
||||
{
|
||||
if ((m_asr & ASR_DIR) && !m_data.full())
|
||||
{
|
||||
m_data.enqueue(data);
|
||||
|
||||
update_rdy(m_acr, m_hcr);
|
||||
}
|
||||
else
|
||||
fatalerror("%s: adata_w write fifo while %s (%s)\n",
|
||||
tag(), m_data.full() ? "full" : "read-only", machine().describe_context().c_str());
|
||||
}
|
||||
|
||||
READ16_MEMBER(isa16_3c505_device::host_r)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
case 0: return hcmd_r();
|
||||
case 1: return m_hsr;
|
||||
case 2: return hdata_r();
|
||||
case 3: return m_hcr;
|
||||
}
|
||||
|
||||
logerror("host_r unknown register %d (%s)\n", offset, machine().describe_context());
|
||||
return space.unmap();
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(isa16_3c505_device::host_w)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
case 0:
|
||||
hcmd_w(data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
m_hdr = data & HDR_BRST;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
hdata_w(data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
hcr_w(data);
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("host_w unknown register %d data 0x%04x (%s)\n", offset, data, machine().describe_context());
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
u8 isa16_3c505_device::hcmd_r()
|
||||
{
|
||||
u8 const data = m_acmdr;
|
||||
|
||||
m_asr |= ASR_ACRE;
|
||||
m_hsr &= ~HSR_ACRF;
|
||||
|
||||
update_irq(0);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
void isa16_3c505_device::hcmd_w(u8 data)
|
||||
{
|
||||
LOGMASKED(LOG_REG, "hcmd_w 0x%02x (%s)\n", data, machine().describe_context());
|
||||
|
||||
m_asr |= ASR_HCRF;
|
||||
m_hsr &= ~HSR_HCRE;
|
||||
|
||||
m_hcmdr = data;
|
||||
|
||||
if (!m_cpu_irq_asserted)
|
||||
{
|
||||
m_cpu_irq_asserted = true;
|
||||
m_cpu->int0_w(1);
|
||||
}
|
||||
}
|
||||
|
||||
void isa16_3c505_device::hcr_w(u8 data)
|
||||
{
|
||||
LOGMASKED(LOG_REG, "hcr_w 0x%02x (%s)\n", data, machine().describe_context());
|
||||
|
||||
// update host status flags
|
||||
if ((data ^ m_hcr) & HCR_HSF)
|
||||
m_asr = (m_asr & ~ASR_HSF) | (data & HCR_HSF);
|
||||
|
||||
// update direction flag
|
||||
if ((data ^ m_hcr) & HCR_DIR)
|
||||
{
|
||||
if (data & HCR_DIR)
|
||||
{
|
||||
LOGMASKED(LOG_REG, "transfer from host to adapter\n");
|
||||
|
||||
// transfer from host to adapter
|
||||
m_hsr |= HSR_DIR;
|
||||
m_asr |= ASR_DIR;
|
||||
|
||||
update_rdy(m_acr, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOGMASKED(LOG_REG, "transfer from adapter to host\n");
|
||||
|
||||
// transfer from adapter to host
|
||||
m_hsr &= ~HSR_DIR;
|
||||
m_asr &= ~ASR_DIR;
|
||||
|
||||
update_rdy(m_acr, data);
|
||||
}
|
||||
}
|
||||
|
||||
if ((data ^ m_hcr) & HCR_FLSH)
|
||||
{
|
||||
if (data & HCR_FLSH)
|
||||
{
|
||||
LOGMASKED(LOG_REG, "host flushed data fifo (%d bytes)\n", m_data.queue_length());
|
||||
m_data.clear();
|
||||
}
|
||||
|
||||
update_rdy(m_acr, data);
|
||||
}
|
||||
|
||||
// attention condition
|
||||
if (!(m_hcr & HCR_ATTN) && (data & HCR_ATTN))
|
||||
{
|
||||
if (!(data & HCR_FLSH))
|
||||
{
|
||||
LOGMASKED(LOG_REG, "soft reset\n");
|
||||
|
||||
// soft reset
|
||||
m_cpu->set_input_line(INPUT_LINE_NMI, 1);
|
||||
m_cpu->set_input_line(INPUT_LINE_NMI, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOGMASKED(LOG_REG, "hard reset\n");
|
||||
|
||||
// hard reset
|
||||
reset();
|
||||
}
|
||||
}
|
||||
|
||||
m_hcr = data;
|
||||
}
|
||||
|
||||
u16 isa16_3c505_device::hdata_r()
|
||||
{
|
||||
if ((m_hsr & HSR_DIR) && !m_data.empty())
|
||||
{
|
||||
u16 const data = m_data.dequeue();
|
||||
|
||||
update_rdy(m_acr, m_hcr);
|
||||
|
||||
return data;
|
||||
}
|
||||
else
|
||||
fatalerror("%s: hdata_r read fifo while %s (%s)\n",
|
||||
tag(), m_data.empty() ? "empty" : "write-only", machine().describe_context().c_str());
|
||||
}
|
||||
|
||||
void isa16_3c505_device::hdata_w(u16 data)
|
||||
{
|
||||
if (!(m_hsr & HSR_DIR) && !m_data.full())
|
||||
{
|
||||
m_data.enqueue(data);
|
||||
|
||||
update_rdy(m_acr, m_hcr);
|
||||
}
|
||||
else
|
||||
fatalerror("%s: hdata_w write fifo while %s (%s)\n",
|
||||
tag(), m_data.full() ? "full" : "read-only", machine().describe_context().c_str());
|
||||
}
|
||||
|
||||
void isa16_3c505_device::update_rdy(u8 const acr, u8 const hcr)
|
||||
{
|
||||
if (!(acr & ACR_FLSH) && !(hcr & HCR_FLSH))
|
||||
{
|
||||
if (hcr & HCR_DIR)
|
||||
{
|
||||
// adapter to host
|
||||
if (m_data.empty())
|
||||
m_hsr &= ~HSR_HRDY;
|
||||
else
|
||||
m_hsr |= HSR_HRDY;
|
||||
|
||||
if (m_data.full())
|
||||
m_asr &= ~ASR_ARDY;
|
||||
else
|
||||
m_asr |= ASR_ARDY;
|
||||
}
|
||||
else
|
||||
{
|
||||
// host to adapter
|
||||
if (m_data.empty())
|
||||
m_asr &= ~ASR_ARDY;
|
||||
else
|
||||
m_asr |= ASR_ARDY;
|
||||
|
||||
if (m_data.full())
|
||||
m_hsr &= ~HSR_HRDY;
|
||||
else
|
||||
m_hsr |= HSR_HRDY;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
m_asr &= ~ASR_ARDY;
|
||||
m_hsr &= ~HSR_HRDY;
|
||||
}
|
||||
}
|
||||
|
||||
void isa16_3c505_device::update_irq(int state)
|
||||
{
|
||||
if (bool(state) != m_isa_irq_asserted)
|
||||
{
|
||||
LOG("isa irq %d\n", state);
|
||||
|
||||
switch (m_isa_irq)
|
||||
{
|
||||
case 3: m_isa->irq3_w(state); break;
|
||||
case 4: m_isa->irq4_w(state); break;
|
||||
case 5: m_isa->irq5_w(state); break;
|
||||
case 6: m_isa->irq6_w(state); break;
|
||||
case 7: m_isa->irq7_w(state); break;
|
||||
case 9: m_isa->irq2_w(state); break;
|
||||
case 10: m_isa->irq10_w(state); break;
|
||||
case 11: m_isa->irq11_w(state); break;
|
||||
case 12: m_isa->irq12_w(state); break;
|
||||
case 14: m_isa->irq14_w(state); break;
|
||||
case 15: m_isa->irq15_w(state); break;
|
||||
|
||||
default:
|
||||
fatalerror("%s: invalid isa irq %d\n", tag(), m_isa_irq);
|
||||
}
|
||||
|
||||
m_isa_irq_asserted = bool(state);
|
||||
}
|
||||
}
|
||||
|
||||
@ -13,6 +13,10 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "cpu/i86/i186.h"
|
||||
#include "machine/i82586.h"
|
||||
#include "machine/ram.h"
|
||||
|
||||
#include "bus/isa/isa.h"
|
||||
|
||||
// ======================> PCB data structure
|
||||
@ -276,7 +280,136 @@ private:
|
||||
int m_irq, m_drq;
|
||||
};
|
||||
|
||||
class isa16_3c505_device
|
||||
: public device_t
|
||||
, public device_isa16_card_interface
|
||||
{
|
||||
public:
|
||||
isa16_3c505_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
DECLARE_READ16_MEMBER(host_r);
|
||||
DECLARE_WRITE16_MEMBER(host_w);
|
||||
|
||||
protected:
|
||||
// device_t overrides
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
void map_main(address_map &map);
|
||||
void map_io(address_map &map);
|
||||
|
||||
enum acr_mask : u8
|
||||
{
|
||||
ACR_ASF1 = 0x01, // adapter status flag 1
|
||||
ACR_ASF2 = 0x02, // adapter status flag 2
|
||||
ACR_ASF3 = 0x04, // adapter status flag 3
|
||||
ACR_LED1 = 0x08, // led control 1
|
||||
ACR_LED2 = 0x10, // led control 2
|
||||
ACR_R586 = 0x20, // reset 82586
|
||||
ACR_FLSH = 0x40, // flush data register
|
||||
ACR_LPBK = 0x80, // loopback control
|
||||
|
||||
ACR_ASF = 0x07,
|
||||
};
|
||||
enum asr_mask : u8
|
||||
{
|
||||
ASR_HSF1 = 0x01, // host status flag 1
|
||||
ASR_HSF2 = 0x02, // host status flag 2
|
||||
ASR_SWTC = 0x04, // external switch
|
||||
ASR_8_16 = 0x08, // 8/16 bit
|
||||
ASR_DIR = 0x10, // direction flag
|
||||
ASR_HCRF = 0x20, // host command register full
|
||||
ASR_ACRE = 0x40, // adapter command register empty
|
||||
ASR_ARDY = 0x80, // data register ready
|
||||
|
||||
ASR_HSF = 0x03,
|
||||
};
|
||||
enum hcr_mask : u8
|
||||
{
|
||||
HCR_HSF1 = 0x01, // host status flag 1
|
||||
HCR_HSF2 = 0x02, // host status flag 2
|
||||
HCR_CMDE = 0x04, // command register interrupt enable
|
||||
HCR_TCEN = 0x08, // terminal count interrupt enable
|
||||
HCR_DIR = 0x10, // direction flag
|
||||
HCR_DMAE = 0x20, // dma enable
|
||||
HCR_FLSH = 0x40, // flush data register
|
||||
HCR_ATTN = 0x80, // attention
|
||||
|
||||
HCR_HSF = 0x03,
|
||||
};
|
||||
enum hsr_mask : u8
|
||||
{
|
||||
HSR_ASF1 = 0x01, // adapter status flag 1
|
||||
HSR_ASF2 = 0x02, // adapter status flag 2
|
||||
HSR_ASF3 = 0x04, // adapter status flag 3
|
||||
HSR_DONE = 0x08, // dma done
|
||||
HSR_DIR = 0x10, // direction
|
||||
HSR_ACRF = 0x20, // adapter command register full
|
||||
HSR_HCRE = 0x40, // host command register empty
|
||||
HSR_HRDY = 0x80, // data register ready
|
||||
|
||||
HSR_ASF = 0x07,
|
||||
};
|
||||
enum hdr_mask : u8
|
||||
{
|
||||
HDR_BRST = 0x01, // dma burst
|
||||
};
|
||||
|
||||
// adapter register helpers
|
||||
u8 acmd_r();
|
||||
u8 acr_r() { return m_acr; };
|
||||
u8 asr_r() { return m_asr; };
|
||||
u16 adata_r();
|
||||
void acmd_w(u8 data);
|
||||
void acr_w(u8 data);
|
||||
void adata_w(u16 data);
|
||||
|
||||
// host register helpers
|
||||
u8 hcmd_r();
|
||||
u16 hdata_r();
|
||||
void hcmd_w(u8 data);
|
||||
void hcr_w(u8 data);
|
||||
void hdata_w(u16 data);
|
||||
|
||||
void update_irq(int state);
|
||||
void update_rdy(u8 const acr, u8 const hcr);
|
||||
|
||||
private:
|
||||
required_device<i80186_cpu_device> m_cpu;
|
||||
required_device<i82586_device> m_net;
|
||||
required_device<ram_device> m_ram;
|
||||
|
||||
output_finder<2> m_led;
|
||||
|
||||
required_ioport m_iobase;
|
||||
required_ioport m_irqdrq;
|
||||
required_ioport m_romopts;
|
||||
required_ioport m_test;
|
||||
|
||||
u8 m_acmdr; // adapter command register
|
||||
u8 m_acr; // adapter control register
|
||||
u8 m_asr; // adapter status register
|
||||
|
||||
u8 m_hcmdr; // host command register
|
||||
u8 m_hcr; // host control register
|
||||
u8 m_hsr; // host status register
|
||||
u8 m_hdr; // host aux dma register
|
||||
|
||||
util::fifo<u16, 10> m_data;
|
||||
|
||||
unsigned m_isa_irq;
|
||||
unsigned m_isa_drq;
|
||||
|
||||
bool m_cpu_irq_asserted;
|
||||
bool m_isa_irq_asserted;
|
||||
bool m_installed;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(ISA16_3C505, threecom3c505_device)
|
||||
DECLARE_DEVICE_TYPE(ISA16_3C505_LLE, isa16_3c505_device)
|
||||
|
||||
#endif // MAME_BUS_ISA_3C505_H
|
||||
|
||||
@ -176,6 +176,7 @@ void pc_isa16_cards(device_slot_interface &device)
|
||||
device.option_add("gfxultrap", ISA16_SVGA_GFXULTRAPRO);
|
||||
device.option_add("tgui9680",ISA16_SVGA_TGUI9680);
|
||||
device.option_add("3c505", ISA16_3C505);
|
||||
device.option_add("3c505_lle", ISA16_3C505_LLE);
|
||||
device.option_add("mach64", ISA16_SVGA_MACH64);
|
||||
device.option_add("sb16_lle", ISA16_SB16);
|
||||
device.option_add("mcd", ISA16_MCD);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user