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https://github.com/holub/mame
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gigatron: Disassembly tweaks (nw)
- Fix disassembly of control instructions in non-direct addressing modes - Fix edge case for jump page calculation (at PC = $xxFF) - Use NOP shorthand for LD AC - Acknowledge delay slot for jump instructions
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@ -43,11 +43,12 @@ u32 gigatron_disassembler::opcode_alignment() const
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offs_t gigatron_disassembler::disassemble(std::ostream &stream, offs_t pc, const gigatron_disassembler::data_buffer &opcodes, const gigatron_disassembler::data_buffer ¶ms)
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{
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u16 inst = opcodes.r16(pc);
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u32 flags = 0;
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if (inst >= 0xe000)
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{
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// Jump instructions use special format
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util::stream_format(stream, "%-6s", s_jumps[(inst & 0x1c00) >> 10]);
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util::stream_format(stream, "%-5s", s_jumps[(inst & 0x1c00) >> 10]);
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if ((inst & 0x1c00) == 0)
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stream << "y,";
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@ -57,7 +58,7 @@ offs_t gigatron_disassembler::disassemble(std::ostream &stream, offs_t pc, const
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if ((inst & 0x1c00) == 0)
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util::stream_format(stream, "$%02x", inst & 0x00ff);
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else
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util::stream_format(stream, "$%04x", (pc & 0x3f00) | (inst & 0x00ff));
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util::stream_format(stream, "$%04x", ((pc + 1) & 0x3f00) | (inst & 0x00ff));
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break;
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case 0x0100:
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@ -72,65 +73,78 @@ offs_t gigatron_disassembler::disassemble(std::ostream &stream, offs_t pc, const
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stream << "in";
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break;
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}
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flags = STEP_OVER | step_over_extra(1);
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}
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else if ((inst & 0xe300) == 0xc100)
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{
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// This was originally an undefined store mode
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util::stream_format(stream, "%-6s$%02x", "ctrl", inst & 0x00ff);
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}
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else if ((inst & 0xf300) == 0x0200)
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stream << "nop";
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else
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{
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util::stream_format(stream, "%-6s", s_ops[(inst & 0xe000) >> 13]);
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// Bus data
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switch (inst & 0x0300)
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if ((inst & 0xe300) == 0xc100)
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{
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case 0x0000:
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util::stream_format(stream, "$%02x", inst & 0x00ff);
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if (inst >= 0xc000)
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stream << ",";
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break;
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// This was originally an undefined store mode
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util::stream_format(stream, "%-5s", "ctrl");
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}
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else
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{
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util::stream_format(stream, "%-5s", s_ops[(inst & 0xe000) >> 13]);
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case 0x0100:
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break;
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// Bus data
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switch (inst & 0x0300)
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{
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case 0x0000:
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util::stream_format(stream, "$%02x", inst & 0x00ff);
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if (inst >= 0xc000)
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stream << ",";
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break;
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case 0x0200:
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if (inst < 0xc000)
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stream << "ac"; // implicit for store instruction
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break;
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case 0x0100:
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break;
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case 0x0300:
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stream << "in";
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if (inst >= 0xc000)
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stream << ",";
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break;
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case 0x0200:
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if (inst < 0xc000)
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stream << "ac"; // implicit for store instruction
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break;
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case 0x0300:
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stream << "in";
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if (inst >= 0xc000)
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stream << ",";
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break;
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}
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}
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// RAM source or store destination
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if (inst >= 0xc000 || (inst & 0x0300) == 0x0100)
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{
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if ((inst & 0xe300) != 0xc100)
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stream << "[";
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switch (inst & 0x1c00)
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{
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case 0x0000: case 0x1000: case 0x1400: case 0x1800:
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util::stream_format(stream, "[$%02x]", inst & 0x00ff);
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util::stream_format(stream, "$%02x", inst & 0x00ff);
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break;
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case 0x0400:
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stream << "[x]";
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stream << "x";
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break;
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case 0x0800:
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util::stream_format(stream, "[y,$%02x]", inst & 0x00ff);
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util::stream_format(stream, "y,$%02x", inst & 0x00ff);
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break;
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case 0x0c00:
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stream << "[y,x]";
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stream << "y,x";
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break;
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case 0x1c00:
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stream << "[y,x++]";
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stream << "y,x++";
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break;
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}
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if ((inst & 0xe300) != 0xc100)
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stream << "]";
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}
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// Non-accumulator destinations
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@ -143,5 +157,5 @@ offs_t gigatron_disassembler::disassemble(std::ostream &stream, offs_t pc, const
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}
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}
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return 1;
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return 1 | flags | SUPPORTED;
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}
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