mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
small cleanup, made shougi2 a parent instead of clone of shougi
This commit is contained in:
hap
parent
01db6150c2
commit
f80a65b5a5
@ -62,33 +62,30 @@ CUSTOM: ALPHA 8201 (42 pin DIP)
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DIPSW : 6 position (x1)
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Positions 1, 5 & 6 not used
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4 3 2
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------------------------------
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OFF OFF OFF 1 minutes (time for the opponent to make his decision)
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OFF OFF ON 2
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OFF ON OFF 3
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OFF ON ON 4
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ON OFF OFF 5
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ON OFF ON 10
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ON ON OFF 20
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ON ON ON 30
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4 3 2
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------------------------------
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OFF OFF OFF 1 minutes (time for the opponent to make his decision)
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OFF OFF ON 2
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OFF ON OFF 3
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OFF ON ON 4
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ON OFF OFF 5
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ON OFF ON 10
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ON ON OFF 20
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ON ON ON 30
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ROMs : All type 2732
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PROM : Type MB7051
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**************************************************************************/
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#include "emu.h"
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#include "cpu/alph8201/alph8201.h"
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//#include "cpu/hmcs40/hmcs40.h"
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#include "cpu/z80/z80.h"
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#include "sound/ay8910.h"
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#include "video/resnet.h"
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class shougi_state : public driver_device
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{
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public:
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@ -97,7 +94,8 @@ public:
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m_maincpu(*this, "maincpu"),
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m_subcpu(*this, "sub"),
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m_mcu(*this, "mcu"),
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m_videoram(*this, "videoram") { }
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m_videoram(*this, "videoram")
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{ }
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_subcpu;
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@ -107,18 +105,8 @@ public:
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int m_nmi_enabled;
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int m_r;
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//UINT8 *m_cpu_sharedram;
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//UINT8 m_cpu_sharedram_control_val;
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DECLARE_WRITE8_MEMBER(cpu_sharedram_sub_w);
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DECLARE_WRITE8_MEMBER(cpu_sharedram_main_w);
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DECLARE_READ8_MEMBER(cpu_sharedram_r);
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DECLARE_WRITE8_MEMBER(cpu_shared_ctrl_sub_w);
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DECLARE_WRITE8_MEMBER(cpu_shared_ctrl_main_w);
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DECLARE_WRITE8_MEMBER(mcu_halt_off_w);
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DECLARE_WRITE8_MEMBER(mcu_halt_on_w);
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DECLARE_WRITE8_MEMBER(nmi_disable_and_clear_line_w);
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DECLARE_WRITE8_MEMBER(nmi_enable_w);
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DECLARE_WRITE8_MEMBER(control_w);
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DECLARE_READ8_MEMBER(dummy_r);
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DECLARE_PALETTE_INIT(shougi);
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@ -132,16 +120,25 @@ public:
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void shougi_state::machine_start()
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{
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m_nmi_enabled = 0;
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m_r = 0;
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save_item(NAME(m_nmi_enabled));
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save_item(NAME(m_r));
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}
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/***************************************************************************
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Video
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***************************************************************************/
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/***************************************************************************
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Convert the color PROMs into a more useable format.
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bit 0 -- 1000 ohm resistor--\
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bit 1 -- 470 ohm resistor --+--+--> RED
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bit 2 -- 220 ohm resistor --/ \---------------1000 ohm resistor---\
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@ -153,22 +150,19 @@ void shougi_state::machine_start()
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***************************************************************************/
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PALETTE_INIT_MEMBER(shougi_state, shougi)
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{
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const UINT8 *color_prom = memregion("proms")->base();
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int i;
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static const int resistances_b[2] = { 470, 220 };
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static const int resistances_rg[3] = { 1000, 470, 220 };
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double weights_r[3], weights_g[3], weights_b[2];
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compute_resistor_weights(0, 255, -1.0,
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compute_resistor_weights(0, 255, -1.0,
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3, resistances_rg, weights_r, 1000, 0,
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3, resistances_rg, weights_g, 1000, 0,
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2, resistances_b, weights_b, 1000, 0);
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for (i = 0;i < palette.entries();i++)
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for (int i = 0; i < palette.entries(); i++)
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{
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int bit0,bit1,bit2,r,g,b;
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@ -194,22 +188,16 @@ PALETTE_INIT_MEMBER(shougi_state, shougi)
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}
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UINT32 shougi_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
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{
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int offs;
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for (offs = 0;offs <0x4000; offs++)
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for (int offs = 0; offs < 0x4000; offs++)
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{
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int sx, sy, x, data1, data2, color, data;
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sx = offs >> 8; /*00..0x3f (64*4=256)*/
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sy = offs & 0xff; /*00..0xff*/
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//if (flipscreen[0]) sx = 31 - sx;
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//if (flipscreen[1]) sy = 31 - sy;
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data1 = m_videoram[offs]; /* color */
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data1 = m_videoram[offs]; /* color */
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data2 = m_videoram[0x4000 + offs]; /* pixel data */
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for (x=0; x<4; x++) /*4 pixels per byte (2 bitplanes in 2 nibbles: 1st=bits 7-4, 2nd=bits 3-0)*/
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@ -224,155 +212,127 @@ UINT32 shougi_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap,
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return 0;
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}
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#if 0
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//to do:
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// add separate sharedram/r/w() for both CPUs and use control value to verify access
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WRITE8_MEMBER(shougi_state::cpu_sharedram_sub_w)
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/***************************************************************************
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I/O
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***************************************************************************/
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// maincpu side
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WRITE8_MEMBER(shougi_state::control_w)
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{
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if (m_cpu_sharedram_control_val!=0) logerror("sub CPU access to shared RAM when access set for main cpu\n");
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m_cpu_sharedram[offset] = data;
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}
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// 4800-480f connected to the 74LS259, A3 is data line
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// so 4800-4807 write 0, and 4808-480f write 1
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data = offset >> 3 & 1;
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offset &= 7;
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WRITE8_MEMBER(shougi_state::cpu_sharedram_main_w)
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{
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if (m_cpu_sharedram_control_val!=1) logerror("main CPU access to shared RAM when access set for sub cpu\n");
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m_cpu_sharedram[offset] = data;
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}
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READ8_MEMBER(shougi_state::cpu_sharedram_r)
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{
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return m_cpu_sharedram[offset];
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}
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#endif
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WRITE8_MEMBER(shougi_state::cpu_shared_ctrl_sub_w)
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{
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//m_cpu_sharedram_control_val = 0;
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//logerror("cpu_sharedram_ctrl=SUB");
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}
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WRITE8_MEMBER(shougi_state::cpu_shared_ctrl_main_w)
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{
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//m_cpu_sharedram_control_val = 1;
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//logerror("cpu_sharedram_ctrl=MAIN");
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}
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WRITE8_MEMBER(shougi_state::mcu_halt_off_w)
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{
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/* logerror("mcu HALT OFF"); */
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m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
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}
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WRITE8_MEMBER(shougi_state::mcu_halt_on_w)
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{
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/* logerror("mcu HALT ON"); */
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m_mcu->set_input_line(INPUT_LINE_HALT,ASSERT_LINE);
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}
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WRITE8_MEMBER(shougi_state::nmi_disable_and_clear_line_w)
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{
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m_nmi_enabled = 0; /* disable NMIs */
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/* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */
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m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
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m_subcpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
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}
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WRITE8_MEMBER(shougi_state::nmi_enable_w)
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{
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m_nmi_enabled = 1; /* enable NMIs */
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}
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INTERRUPT_GEN_MEMBER(shougi_state::vblank_nmi)
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{
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if ( m_nmi_enabled == 1 )
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switch (offset)
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{
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/* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */
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m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
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m_subcpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
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case 0:
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// TODO
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// 0: sharedram = sub
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// 1: sharedram = main
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break;
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case 1:
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m_nmi_enabled = data;
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// NMI lines are tied together on both CPUs and connected to the LS74 /Q output
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if (!m_nmi_enabled)
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{
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m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
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m_subcpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
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}
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break;
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case 4:
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m_mcu->set_input_line(INPUT_LINE_HALT, data ? ASSERT_LINE : CLEAR_LINE);
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break;
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default:
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// 7: ?????? connected to +5v via resistor
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break;
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}
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}
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static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, shougi_state )
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AM_RANGE(0x0000, 0x3fff) AM_ROM
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AM_RANGE(0x4000, 0x43ff) AM_RAM /* 2114 x 2 (0x400 x 4bit each) */
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/* 4800-480f connected to the 74LS259, A3 is data line so 4800-4807 write 0, and 4808-480f write 1 */
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AM_RANGE(0x4800, 0x4800) AM_READ_PORT("DSW") AM_WRITE(cpu_shared_ctrl_sub_w)
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AM_RANGE(0x4801, 0x4801) AM_WRITE(nmi_disable_and_clear_line_w)
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AM_RANGE(0x4802, 0x4802) AM_NOP
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AM_RANGE(0x4803, 0x4803) AM_NOP
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AM_RANGE(0x4804, 0x4804) AM_WRITE(mcu_halt_off_w)
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AM_RANGE(0x4807, 0x4807) AM_WRITENOP //?????? connected to +5v via resistor
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AM_RANGE(0x4808, 0x4808) AM_WRITE(cpu_shared_ctrl_main_w)
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AM_RANGE(0x4809, 0x4809) AM_WRITE(nmi_enable_w)
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AM_RANGE(0x480a, 0x480a) AM_NOP
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AM_RANGE(0x480b, 0x480b) AM_NOP
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AM_RANGE(0x480c, 0x480c) AM_WRITE(mcu_halt_on_w)
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AM_RANGE(0x480f, 0x480f) AM_NOP
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AM_RANGE(0x4000, 0x43ff) AM_RAM /* 2114 x 2 (0x400 x 4bit each) */
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AM_RANGE(0x4800, 0x480f) AM_WRITE(control_w)
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AM_RANGE(0x4800, 0x4800) AM_READ_PORT("DSW")
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AM_RANGE(0x5000, 0x5000) AM_READ_PORT("P1")
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AM_RANGE(0x5800, 0x5800) AM_READ_PORT("P2") AM_WRITE(watchdog_reset_w) /* game won't boot if watchdog doesn't work */
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AM_RANGE(0x5800, 0x5800) AM_READ_PORT("P2") AM_WRITE(watchdog_reset_w) /* game won't boot if watchdog doesn't work */
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AM_RANGE(0x6000, 0x6000) AM_DEVWRITE("aysnd", ay8910_device, address_w)
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AM_RANGE(0x6800, 0x6800) AM_DEVWRITE("aysnd", ay8910_device, data_w)
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AM_RANGE(0x7000, 0x73ff) AM_RAM AM_SHARE("share1") /* 2114 x 2 (0x400 x 4bit each) */
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AM_RANGE(0x7800, 0x7bff) AM_RAM AM_SHARE("share2") /* 2114 x 2 (0x400 x 4bit each) */
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AM_RANGE(0x8000, 0xffff) AM_RAM AM_SHARE("videoram") /* 4116 x 16 (32K) */
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AM_RANGE(0x8000, 0xffff) AM_RAM AM_SHARE("videoram") /* 4116 x 16 (32K) */
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ADDRESS_MAP_END
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/* sub */
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// subcpu side
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READ8_MEMBER(shougi_state::dummy_r)
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{
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// ?
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m_r ^= 1;
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if(m_r)
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if (m_r)
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return 0xff;
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else
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return 0;
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}
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static ADDRESS_MAP_START( readport_sub, AS_IO, 8, shougi_state )
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ADDRESS_MAP_GLOBAL_MASK( 0x00ff )
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AM_RANGE(0x00, 0x00) AM_READ(dummy_r)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, shougi_state )
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AM_RANGE(0x0000, 0x5fff) AM_ROM
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AM_RANGE(0x6000, 0x63ff) AM_RAM AM_SHARE("share2") /* 2114 x 2 (0x400 x 4bit each) */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( readport_sub, AS_IO, 8, shougi_state )
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ADDRESS_MAP_GLOBAL_MASK(0x00ff)
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AM_RANGE(0x00, 0x00) AM_READ(dummy_r)
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ADDRESS_MAP_END
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// mcu side (fake!)
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static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, shougi_state )
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AM_RANGE(0x0000, 0x03ff) AM_RAM AM_SHARE("share1")
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ADDRESS_MAP_END
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/***************************************************************************
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Inputs
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***************************************************************************/
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static INPUT_PORTS_START( shougi )
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PORT_START("P1")
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PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START2 )
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PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START1 )
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(1)
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1)
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
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PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 )
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON1 )
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
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PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
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PORT_START("P2")
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PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
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PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2)
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
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PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
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PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
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// dip switch order is not sequential. Only 2,3,4, and 5 identified.
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// 1 and 6 missing, with three possible positions (the third available
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@ -413,23 +373,38 @@ INPUT_PORTS_END
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/***************************************************************************
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Machine Config
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***************************************************************************/
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INTERRUPT_GEN_MEMBER(shougi_state::vblank_nmi)
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{
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if (m_nmi_enabled)
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{
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m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
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m_subcpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
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}
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}
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static MACHINE_CONFIG_START( shougi, shougi_state )
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MCFG_CPU_ADD("maincpu", Z80,10000000/4)
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", Z80, XTAL_10MHz/4)
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MCFG_CPU_PROGRAM_MAP(main_map)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", shougi_state, vblank_nmi)
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MCFG_CPU_ADD("sub", Z80,10000000/4)
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MCFG_CPU_ADD("sub", Z80, XTAL_10MHz/4)
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MCFG_CPU_PROGRAM_MAP(sub_map)
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MCFG_CPU_IO_MAP(readport_sub)
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/* NMIs triggered in vblank_nmi() */
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/* MCU */
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MCFG_CPU_ADD("mcu", ALPHA8201, 10000000/4/8)
|
||||
MCFG_CPU_ADD("mcu", ALPHA8201, XTAL_10MHz/4/8)
|
||||
MCFG_CPU_PROGRAM_MAP(mcu_map)
|
||||
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(600))
|
||||
MCFG_WATCHDOG_VBLANK_INIT(16) // assuming it's the same as champbas
|
||||
MCFG_QUANTUM_PERFECT_CPU("maincpu")
|
||||
MCFG_WATCHDOG_VBLANK_INIT(16) // assuming it's the same as champbas
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
@ -446,12 +421,18 @@ static MACHINE_CONFIG_START( shougi, shougi_state )
|
||||
/* sound hardware */
|
||||
MCFG_SPEAKER_STANDARD_MONO("mono")
|
||||
|
||||
MCFG_SOUND_ADD("aysnd", AY8910, 10000000/8)
|
||||
MCFG_SOUND_ADD("aysnd", AY8910, XTAL_10MHz/8)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
|
||||
Game driver(s)
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
ROM_START( shougi )
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_LOAD( "1.3a", 0x0000, 0x1000, CRC(b601303f) SHA1(ed07fb09053e15be49f4cb66e8916d1bdff48336) )
|
||||
@ -459,7 +440,7 @@ ROM_START( shougi )
|
||||
ROM_LOAD( "2.3b", 0x2000, 0x1000, CRC(09cb831f) SHA1(5a83a22d9245f980fe6a495433e51437d1f95644) )
|
||||
ROM_LOAD( "4.3d", 0x3000, 0x1000, CRC(ad1a642a) SHA1(d12b10f94a568d1126384e14af4b53c5e5b1a0d0) )
|
||||
|
||||
ROM_REGION( 0x10000, "sub", 0 )
|
||||
ROM_REGION( 0x10000, "sub", ROMREGION_ERASE00 )
|
||||
ROM_LOAD( "5.3e", 0x0000, 0x1000, CRC(ff1f07d0) SHA1(ae5bab09916b6d4ad8d3568ea39501850bdc6991) )
|
||||
ROM_LOAD( "8.3j", 0x1000, 0x1000, CRC(6230c4c1) SHA1(0b2c81bb02c270ed3bb5b42c4bd4eb25023090cb) )
|
||||
ROM_LOAD( "6.3f", 0x2000, 0x1000, CRC(d5a91b16) SHA1(1d21295667c3eb186f9e7f867763f2f2697fd350) )
|
||||
@ -474,6 +455,7 @@ ROM_START( shougi )
|
||||
ROM_LOAD( "pr.2l", 0x0000, 0x0020, CRC(cd3559ff) SHA1(a1291b06a8a337943660b2ef62c94c49d58a6fb5) )
|
||||
ROM_END
|
||||
|
||||
|
||||
ROM_START( shougi2 )
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_LOAD( "1-2.3a", 0x0000, 0x1000, CRC(16d75306) SHA1(2d090396abd1fe2b31cb8450cc5d2fbde75e0230) )
|
||||
@ -497,6 +479,6 @@ ROM_START( shougi2 )
|
||||
ROM_END
|
||||
|
||||
|
||||
|
||||
GAME( 1982, shougi, 0, shougi, shougi, driver_device, 0, ROT0, "Alpha Denshi Co.", "Shougi", MACHINE_SUPPORTS_SAVE )
|
||||
GAME( 1982, shougi2, shougi, shougi, shougi2, driver_device, 0, ROT0, "Alpha Denshi Co.", "Shougi 2", MACHINE_SUPPORTS_SAVE )
|
||||
/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR, COMPANY, FULLNAME, FLAGS */
|
||||
GAME( 1982, shougi, 0, shougi, shougi, driver_device, 0, ROT0, "Alpha Denshi Co. (Tehkan license)", "Shougi", MACHINE_SUPPORTS_SAVE )
|
||||
GAME( 1982, shougi2, 0, shougi, shougi2, driver_device, 0, ROT0, "Alpha Denshi Co. (Tehkan license)", "Shougi Part II", MACHINE_SUPPORTS_SAVE )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user