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https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
Added PIT and BIM devices and IRQ handling (nw)
This commit is contained in:
Joakim Larsson Edstrom
parent
905af3fee7
commit
f82ad755ae
@ -66,26 +66,47 @@
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*
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* History of Force Computers
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*---------------------------
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* see fccpu30.cpp
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*
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* Misc links about Force Computes and this board:
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*------------------------------------------------
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* http://bitsavers.trailing-edge.com/pdf/forceComputers/
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* http://bitsavers.org/pdf/forceComputers/
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*
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* Description(s)
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* -------------
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* CPU-20 has the following feature set
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* CPU-20 has the following feature set:
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* - 68020 CPU with l6.7MHz Clock Frequency
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* - 68881 Floating Point Coprocessor with l6.7MHz Clock Frequency
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* - Static RAM 5l2Kbyte with 55ns access time
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* - 5l2Kbyte (max) of ROM/EPROM for the system
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* - 2 RS232 Multi Protocol Communication Interfaces (110-38400 Baud)
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* - Parallel Interface and Timer Chip provides local control and timer function
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* - VMXbus Primary Master Interface to p2 connector
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* - Local Interrupt handling via interrupt vectors
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* - Each VMEbus IRQ level can be enabled/disabled via software
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* - Address range for the short I/O address modifies (AM4)
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* - Address range for the standard address modifier
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* - Single level bus arbiter
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* - One level slave bus arbitration
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* - Power monitor
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* - RESET and SOFTWARE ABORT function switches
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* - Fully VMEbus, VMXbus and IEEE Pl~14 compatible
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*
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* Address Map
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* --------------------------------------------------------------------------
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* Range Decscription
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* --------------------------------------------------------------------------
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Basadressen av I / O-enheter:
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* 00000000-0xxFFFFF Shared DRAM D8-D32
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* 0yy00000-FAFFFFFF VME A32 D8-D32 yy=xx+1
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* FB000000-FBFEFFFF VME A24 D8-D32
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* FBFF0000-FBFFFFFF VME A16 D8-D32
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* FC000000-FCFEFFFF VME A24 D8-D16
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* FCFF0000-FCFFFFFF VME A16 D8-D16
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* .... TBC
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* FF800800 BIM
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* FF800C00 PIT
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* FF800000 MPCC
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* FF800A00 RTC
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* --------------------------------------------------------------------------
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*
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* PIT #1 hardware wiring
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@ -121,10 +142,8 @@
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*---------------------------------------------------------------------------
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* TODO:
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* - Find accurate documentation and adjust memory map
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* - Add layouts and system description(s)
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* - Add layout
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* - Write & add 68561 UART
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* - Write & add VME device
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* - Write & add 68153 BIM
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* - Add 68230 PIT
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* - Add variants of boards in the CPU-20 and CPU-21 family
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* - Add FGA, DUSCC devices and CPU-22 variants
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@ -137,19 +156,23 @@
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#include "bus/vme/vme_fcisio.h"
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#include "bus/vme/vme_fcscsi.h"
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#include "bus/rs232/rs232.h"
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#include "machine/68230pit.h"
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#include "machine/68153bim.h"
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#include "machine/clock.h"
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#define LOG_GENERAL 0x01
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#define LOG_SETUP 0x02
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#define LOG_PRINTF 0x04
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#define LOG_INT 0x08
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#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
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#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL | LOG_INT)
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#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0)
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#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0)
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#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__)
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#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
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#define LOGINT(...) LOGMASK(LOG_INT, __VA_ARGS__)
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#if VERBOSE & LOG_PRINTF
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#define logerror printf
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@ -167,20 +190,33 @@ public:
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cpu20_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device (mconfig, type, tag)
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, m_maincpu (*this, "maincpu")
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, m_pit (*this, "pit")
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, m_bim (*this, "bim")
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{
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}
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DECLARE_READ32_MEMBER (bootvect_r);
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DECLARE_WRITE32_MEMBER (bootvect_w);
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DECLARE_WRITE_LINE_MEMBER(bim_irq_callback);
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uint8_t bim_irq_state;
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int bim_irq_level;
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virtual void machine_start () override;
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virtual void machine_reset () override;
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private:
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required_device<m68000_base_device> m_maincpu;
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required_device<pit68230_device> m_pit;
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required_device<bim68153_device> m_bim;
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// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
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uint32_t *m_sysrom;
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uint32_t m_sysram[2];
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void update_irq_to_maincpu();
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};
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/*
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*/
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static ADDRESS_MAP_START (cpu20_mem, AS_PROGRAM, 32, cpu20_state)
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
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@ -188,6 +224,11 @@ static ADDRESS_MAP_START (cpu20_mem, AS_PROGRAM, 32, cpu20_state)
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AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* RAM installed in machine start */
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AM_RANGE (0xff040000, 0xff04ffff) AM_RAM /* RAM installed in machine start */
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AM_RANGE (0xff000000, 0xff00ffff) AM_ROM AM_REGION("roms", 0x0000)
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// AM_RANGE (0xff800000, 0xff80000f) AM_DEVREADWRITE8("mpcc", mpcc68561_device, read, write, 0x00ff00ff)
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// AM_RANGE (0xff800200, 0xff80020f) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xff00ff00)
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AM_RANGE (0xff800800, 0xff80080f) AM_DEVREADWRITE8("bim", bim68153_device, read, write, 0xff00ff00)
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// AM_RANGE (0xff800a00, 0xff800a0f) AM_DEVREADWRITE8("rtc", rtc_device, read, write, 0x00ff00ff)
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AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0xffffffff)
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ADDRESS_MAP_END
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/* Input ports */
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@ -241,25 +282,33 @@ WRITE32_MEMBER (cpu20_state::bootvect_w){
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m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
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}
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#if 0
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WRITE_LINE_MEMBER(cpu20_state::bim_irq_callback)
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{
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LOGINT("%s(%02x)\n", FUNCNAME, state);
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bim_irq_state = state;
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bim_irq_level = m_bim->get_irq_level();
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LOGINT(" - BIM irq level %02x\n", bim_irq_level);
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update_irq_to_maincpu();
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}
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void cpu20_state::update_irq_to_maincpu()
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{
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LOGINT(("%s()\n", FUNCNAME);
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LOGINT((" - fga_irq_level: %02x\n", fga_irq_level));
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LOGINT((" - fga_irq_state: %02x\n", fga_irq_state));
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switch (fga_irq_level & 0x07)
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LOGINT("%s()\n", FUNCNAME);
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LOGINT(" - bim_irq_level: %02x\n", bim_irq_level);
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LOGINT(" - bim_irq_state: %02x\n", bim_irq_state);
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switch (bim_irq_level & 0x07)
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{
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case 1: m_maincpu->set_input_line(M68K_IRQ_1, fga_irq_state); break;
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case 2: m_maincpu->set_input_line(M68K_IRQ_2, fga_irq_state); break;
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case 3: m_maincpu->set_input_line(M68K_IRQ_3, fga_irq_state); break;
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case 4: m_maincpu->set_input_line(M68K_IRQ_4, fga_irq_state); break;
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case 5: m_maincpu->set_input_line(M68K_IRQ_5, fga_irq_state); break;
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case 6: m_maincpu->set_input_line(M68K_IRQ_6, fga_irq_state); break;
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case 7: m_maincpu->set_input_line(M68K_IRQ_7, fga_irq_state); break;
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case 1: m_maincpu->set_input_line(M68K_IRQ_1, bim_irq_state); break;
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case 2: m_maincpu->set_input_line(M68K_IRQ_2, bim_irq_state); break;
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case 3: m_maincpu->set_input_line(M68K_IRQ_3, bim_irq_state); break;
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case 4: m_maincpu->set_input_line(M68K_IRQ_4, bim_irq_state); break;
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case 5: m_maincpu->set_input_line(M68K_IRQ_5, bim_irq_state); break;
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case 6: m_maincpu->set_input_line(M68K_IRQ_6, bim_irq_state); break;
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case 7: m_maincpu->set_input_line(M68K_IRQ_7, bim_irq_state); break;
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default: logerror("Programmatic error in %s, please report\n", FUNCNAME);
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}
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}
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#endif
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static SLOT_INTERFACE_START(fccpu20_vme_cards)
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SLOT_INTERFACE("fcisio", VME_FCISIO1)
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@ -273,9 +322,23 @@ static MACHINE_CONFIG_START (cpu20, cpu20_state)
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/* basic machine hardware */
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MCFG_CPU_ADD ("maincpu", M68020, XTAL_16MHz) /* Crytstal not verified */
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MCFG_CPU_PROGRAM_MAP (cpu20_mem)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("bim", bim68153_device, iack)
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MCFG_VME_DEVICE_ADD("vme")
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MCFG_VME_SLOT_ADD ("vme", "slot1", fccpu20_vme_cards, nullptr)
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/* PIT Parallel Interface and Timer device, assumed strapped for on board clock */
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MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_8_664MHz)
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MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("bim", bim68153_device, int2_w))
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// MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_8_664MHz)
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MCFG_MC68153_ADD("bim", XTAL_16MHz / 2)
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MCFG_BIM68153_OUT_INT_CB(WRITELINE(cpu20_state, bim_irq_callback))
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/*INT0 - Abort switch */
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/*INT1 - MPCC@8.064 MHz aswell */
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/*INT2 - PI/T timer */
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/*INT3 - SYSFAIL/IRQVMX/ACFAIL/MPCC2/3 */
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MACHINE_CONFIG_END
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/* ROM definitions */
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@ -292,7 +355,37 @@ ROM_END
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* System ROM information
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*
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* xxxxxxx bootprom version xxx is released mmm dd, yyyy, coprighted by FORCE Computers Gmbh
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*
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* BIM setup: (reordered for improved reading)
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* : 0 Reg vector <- 1f
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* : 1 Reg vector <- 1c
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* : 2 Reg vector <- 1d
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* : 3 Reg vector <- 1c
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* : 0 Reg control <- 57 - Lev:7 Auto Disable:0 Int Enable:1 Vector:0 Auto Clear:1 Flag:0
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* : 1 Reg control <- 54 - Lev:4 Auto Disable:0 Int Enable:1 Vector:0 Auto Clear:1 Flag:0
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* : 2 Reg control <- 55 - Lev:5 Auto Disable:0 Int Enable:1 Vector:0 Auto Clear:1 Flag:0
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* : 3 Reg control <- 54 - Lev:4 Auto Disable:0 Int Enable:1 Vector:0 Auto Clear:1 Flag:0
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*
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* PIT setup:
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* :pit Reg 0a -> 00
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* :pit Reg 00 <- 30 - PGCR - Mode 0, H34:enabled, H12:enabled, Sense assert H4:Lo, H3:Lo, H2:Lo, H1:Lo
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* :pit Reg 01 <- 08 - PSSR - PC4 pin activated, PC5 pin support no interrupts, H prio mode:0
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* :pit Reg 06 <- 84 - PACR
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* :pit Reg 02 <- 00 - PADDR: 00
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* :pit Reg 07 <- 84 - PBCR
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* :pit Reg 09 <- ff - PBDR
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* :pit Reg 03 <- ff - PBDDR: ff
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* :pit Reg 0c <- 07 - PCDR
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* :pit Reg 04 <- 87 - PCDDR: 87
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* :pit Reg 15 <- d8 - CPRL
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* :pit Reg 14 <- 09 - CPRM
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* :pit Reg 13 <- 00 - CPRH
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* :pit Reg 10 <- e1 - TCR - PC3 used as TOUT and PC7 used as I/O pin, Interrupts enabled
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- PC2 used as I/O pin,CLK and x32 prescaler are used
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- Timer reload the preload values when reaching 0 (zero)
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- Timer is enabled
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*/
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/* Driver */
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/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
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COMP (1986, fccpu20, 0, 0, cpu20, cpu20, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-20", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
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