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https://github.com/holub/mame
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M3745x: Preliminary support for the Mitsubishi M37450 microcontroller [R. Belmont]
This commit is contained in:
R. Belmont
parent
6172ebc94e
commit
f89b0d6d3c
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -559,6 +559,8 @@ src/emu/cpu/m6502/dm65ce02.lst svneol=native#text/plain
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src/emu/cpu/m6502/dm740.lst svneol=native#text/plain
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src/emu/cpu/m6502/dn2a03.lst svneol=native#text/plain
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src/emu/cpu/m6502/dr65c02.lst svneol=native#text/plain
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src/emu/cpu/m6502/m3745x.c svneol=native#text/plain
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src/emu/cpu/m6502/m3745x.h svneol=native#text/plain
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src/emu/cpu/m6502/m4510.c svneol=native#text/plain
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src/emu/cpu/m6502/m4510.h svneol=native#text/plain
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src/emu/cpu/m6502/m6502.c svneol=native#text/plain
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@ -1034,7 +1034,8 @@ CPUOBJS += $(CPUOBJ)/m6502/deco16.o \
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$(CPUOBJ)/m6502/m8502.o \
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$(CPUOBJ)/m6502/n2a03.o \
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$(CPUOBJ)/m6502/r65c02.o \
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$(CPUOBJ)/m6502/m740.o
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$(CPUOBJ)/m6502/m740.o \
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$(CPUOBJ)/m6502/m3745x.o \
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DASMOBJS +=
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endif
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@ -1116,6 +1117,9 @@ $(CPUOBJ)/m6502/m740.o: $(CPUSRC)/m6502/m740.c \
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$(CPUSRC)/m6502/m740.h \
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$(CPUSRC)/m6502/m6502.h
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$(CPUOBJ)/m6502/m3745x.o: $(CPUSRC)/m6502/m3745x.c \
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$(CPUSRC)/m6502/m3745x.h
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# rule to generate the C files
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$(CPUOBJ)/m6502/deco16.inc: $(CPUSRC)/m6502/m6502make.py $(CPUSRC)/m6502/odeco16.lst $(CPUSRC)/m6502/ddeco16.lst
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@echo Generating DECO16 source file...
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498
src/emu/cpu/m6502/m3745x.c
Normal file
498
src/emu/cpu/m6502/m3745x.c
Normal file
@ -0,0 +1,498 @@
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/*
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Mitsubishi M3745x 8-bit microcontroller family
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*/
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#include "emu.h"
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#include "m3745x.h"
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//**************************************************************************
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// MACROS / CONSTANTS
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//**************************************************************************
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// Interrupt control bits (interpolated from C68 program; need 7450 Group manual badly)
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#define IRQ1_INT1 (0x04)
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#define IRQ1_INT2 (0x08) // guess, not used in C68
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#define IRQ1_INT3 (0x10) // guess, not used in C68
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#define IRQ2_SERIALRX (0x08)
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#define IRQ2_SERIALTX (0x10)
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#define IRQ2_ADC (0x20)
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#define ADCTRL_CH_MASK (0x07) // AD ctrl reg. channel mask
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#define ADCTRL_COMPLETE (0x08) // AD ctrl "start"/"complete" bit
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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const device_type M37450 = &device_creator<m37450_device>;
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// m3745x_device - constructor
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//-------------------------------------------------
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m3745x_device::m3745x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal_map) :
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m740_device(mconfig, type, name, tag, owner, clock),
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m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0, internal_map),
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read_p3(*this),
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read_p4(*this),
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read_p5(*this),
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read_p6(*this),
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write_p3(*this),
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write_p4(*this),
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write_p5(*this),
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write_p6(*this),
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read_ad_0(*this),
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read_ad_1(*this),
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read_ad_2(*this),
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read_ad_3(*this),
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read_ad_4(*this),
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read_ad_5(*this),
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read_ad_6(*this),
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read_ad_7(*this)
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{
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}
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void m3745x_device::device_config_complete()
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{
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m_shortname = "m3745x";
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void m3745x_device::device_start()
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{
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read_p3.resolve_safe(0);
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read_p4.resolve_safe(0);
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read_p5.resolve_safe(0);
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read_p6.resolve_safe(0);
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write_p3.resolve_safe();
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write_p4.resolve_safe();
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write_p5.resolve_safe();
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write_p6.resolve_safe();
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read_ad_0.resolve_safe(0);
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read_ad_1.resolve_safe(0);
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read_ad_2.resolve_safe(0);
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read_ad_3.resolve_safe(0);
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read_ad_4.resolve_safe(0);
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read_ad_5.resolve_safe(0);
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read_ad_6.resolve_safe(0);
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read_ad_7.resolve_safe(0);
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for (int i = 0; i < NUM_TIMERS; i++)
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{
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m_timers[i] = timer_alloc(i, NULL);
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}
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m740_device::device_start();
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// all ports reset to input on startup
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memset(m_ddrs, 0, sizeof(m_ddrs));
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memset(m_ports, 0, sizeof(m_ports));
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m_intreq1 = m_intreq2 = m_intctrl1 = m_intctrl2 = 0;
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m_adctrl = 0;
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m_last_all_ints = 0;
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void m3745x_device::device_reset()
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{
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m740_device::device_reset();
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SP = 0x01ff; // we have the "traditional" stack in page 1, not 0 like some M740 derivatives
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for (int i = 0; i < NUM_TIMERS; i++)
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{
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m_timers[i]->adjust(attotime::never);
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}
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// all ports reset to input on startup
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memset(m_ddrs, 0, sizeof(m_ddrs));
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memset(m_ports, 0, sizeof(m_ports));
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m_intreq1 = m_intreq2 = m_intctrl1 = m_intctrl2 = 0;
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m_adctrl = 0;
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m_last_all_ints = 0;
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}
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void m3745x_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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switch (id)
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{
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case TIMER_ADC:
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m_timers[TIMER_ADC]->adjust(attotime::never);
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m_adctrl |= ADCTRL_COMPLETE;
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m_intreq2 |= IRQ2_ADC;
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recalc_irqs();
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break;
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default:
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printf("M3775x: unknown timer expire %d\n", id);
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break;
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}
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}
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void m3745x_device::execute_set_input(int inputnum, int state)
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{
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switch (inputnum)
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{
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case M3745X_INT1_LINE:
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if (state == ASSERT_LINE)
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{
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m_intreq1 |= IRQ1_INT1;
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}
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else
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{
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m_intreq1 &= ~IRQ1_INT1;
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}
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break;
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case M3745X_INT2_LINE:
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if (state == ASSERT_LINE)
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{
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m_intreq1 |= IRQ1_INT2;
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}
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else
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{
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m_intreq1 &= ~IRQ1_INT2;
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}
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break;
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case M3745X_INT3_LINE:
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if (state == ASSERT_LINE)
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{
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m_intreq1 |= IRQ1_INT3;
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}
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else
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{
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m_intreq1 &= ~IRQ1_INT3;
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}
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break;
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case M3745X_SET_OVERFLOW: // the base 740 class can handle this
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m740_device::execute_set_input(M740_SET_OVERFLOW, state);
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break;
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}
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recalc_irqs();
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}
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void m3745x_device::recalc_irqs()
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{
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UINT16 all_ints = 0;
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int static const irq_lines[16] =
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{
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-1, -1, -1, M740_INT11_LINE, M740_INT12_LINE, M740_INT13_LINE, -1, -1,
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-1, -1, M740_INT2_LINE, M740_INT3_LINE, M740_INT4_LINE, -1, -1, -1
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};
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all_ints = (m_intreq1 & m_intctrl1) << 8;
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all_ints |= (m_intreq2 & m_intctrl2);
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// printf("recalc_irqs: last_all_ints = %04x last_ints = %04x (req1 %02x ctrl1 %02x req2 %02x ctrl2 %02x)\n", all_ints, m_last_all_ints, m_intreq1, m_intctrl1, m_intreq2, m_intctrl2);
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// check all 16 IRQ bits for changes
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for (int i = 0; i < 16; i++)
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{
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// if bit is set now
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if (all_ints & (1 << i))
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{
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// and wasn't last time
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if (!(m_last_all_ints & (1 << i)))
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{
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// printf(" asserting irq %d (%d)\n", i, irq_lines[i]);
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if (irq_lines[i] != -1)
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{
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m740_device::execute_set_input(irq_lines[i], ASSERT_LINE);
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}
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}
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}
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else // bit is clear now
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{
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// ...and wasn't clear last time
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if (m_last_all_ints & (1 << i))
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{
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// printf(" clearing irq %d (%d)\n", i, irq_lines[i]);
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if (irq_lines[i] != -1)
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{
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m740_device::execute_set_input(irq_lines[i], CLEAR_LINE);
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}
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}
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}
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}
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m_last_all_ints = all_ints;
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}
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void m3745x_device::send_port(address_space &space, UINT8 offset, UINT8 data)
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{
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switch (offset)
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{
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case 0:
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write_p3(data);
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break;
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case 1:
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write_p4(data);
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break;
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case 2:
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write_p5(data);
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break;
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case 3:
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write_p6(data);
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break;
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}
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}
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UINT8 m3745x_device::read_port(UINT8 offset)
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{
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UINT8 incoming = 0;
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switch (offset)
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{
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case 0:
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incoming = read_p3();
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break;
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case 1:
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incoming = read_p4();
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break;
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case 2:
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incoming = read_p5();
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break;
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case 3:
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incoming = read_p6();
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break;
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}
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// apply data direction registers
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incoming &= (m_ddrs[offset] ^ 0xff);
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// OR in ddr-masked version of port writes
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incoming |= (m_ports[offset] & m_ddrs[offset]);
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return incoming;
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}
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READ8_MEMBER(m3745x_device::ports_r)
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{
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switch (offset)
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{
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case 0:
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return read_port(0);
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case 1:
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return m_ddrs[0];
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case 2:
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return read_port(1);
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case 4:
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return read_port(2);
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case 5:
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return m_ddrs[2];
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case 6:
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return read_port(3);
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case 7:
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return m_ddrs[3];
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}
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return 0xff;
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}
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WRITE8_MEMBER(m3745x_device::ports_w)
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{
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switch (offset)
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{
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case 0: // p3
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send_port(space, 0, data & m_ddrs[0]);
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m_ports[0] = data;
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break;
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case 1: // p3 ddr
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send_port(space, 0, m_ports[0] & data);
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m_ddrs[0] = data;
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break;
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case 2: // p4
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send_port(space, 1, data & m_ddrs[1]);
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m_ports[1] = data;
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break;
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case 4: // p5
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send_port(space, 2, data & m_ddrs[2]);
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m_ports[2] = data;
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break;
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case 5: // p5 ddr
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send_port(space, 2, m_ports[2] & data);
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m_ddrs[2] = data;
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break;
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case 6: // p6
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send_port(space, 3, data & m_ddrs[3]);
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m_ports[3] = data;
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break;
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case 7: // p6 ddr
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send_port(space, 3, m_ports[3] & data);
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m_ddrs[3] = data;
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break;
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}
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}
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READ8_MEMBER(m3745x_device::intregs_r)
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{
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switch (offset)
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{
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case 0:
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return m_intreq1;
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case 1:
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return m_intreq2;
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case 2:
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return m_intctrl1;
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case 3:
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return m_intctrl2;
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}
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// this should never happen
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assert(0);
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return 0;
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}
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WRITE8_MEMBER(m3745x_device::intregs_w)
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{
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switch (offset)
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{
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case 0:
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m_intreq1 = data;
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break;
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case 1:
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m_intreq2 = data;
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break;
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case 2:
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m_intctrl1 = data;
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break;
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case 3:
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m_intctrl2 = data;
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break;
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}
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recalc_irqs();
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}
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READ8_MEMBER(m3745x_device::adc_r)
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{
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UINT8 rv = 0;
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switch (offset)
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{
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case 0:
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m_intreq2 &= ~IRQ2_ADC;
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recalc_irqs();
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switch (m_adctrl & 7)
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{
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case 0:
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rv = read_ad_0();
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break;
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case 1:
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rv = read_ad_1();
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break;
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case 2:
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rv = read_ad_2();
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break;
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case 3:
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rv = read_ad_3();
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break;
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case 4:
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rv = read_ad_4();
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break;
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case 5:
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rv = read_ad_5();
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break;
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case 6:
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rv = read_ad_6();
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break;
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case 7:
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rv = read_ad_7();
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break;
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}
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return rv;
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case 1:
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return m_adctrl;
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}
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return 0;
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}
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WRITE8_MEMBER(m3745x_device::adc_w)
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{
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switch (offset)
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{
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case 0:
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printf("M3745x: Write %02x to ADC output?!\n", data);
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break;
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case 1:
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m_adctrl = data;
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// starting a conversion? this takes 50 cycles.
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if (!(m_adctrl & ADCTRL_COMPLETE))
|
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{
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double hz = (double)clock() / 50.0f;
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m_timers[TIMER_ADC]->adjust(attotime::from_hz(hz));
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}
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||||
break;
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||||
}
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}
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/* M37450 - baseline for this familiy */
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static ADDRESS_MAP_START( m37450_map, AS_PROGRAM, 8, m37450_device )
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AM_RANGE(0x0000, 0x00bf) AM_RAM
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AM_RANGE(0x00d6, 0x00dd) AM_READWRITE(ports_r, ports_w)
|
||||
AM_RANGE(0x00e2, 0x00e3) AM_READWRITE(adc_r, adc_w)
|
||||
AM_RANGE(0x00fc, 0x00ff) AM_READWRITE(intregs_r, intregs_w)
|
||||
AM_RANGE(0x0100, 0x01ff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
m37450_device::m37450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
|
||||
m3745x_device(mconfig, M37450, "Mitsubishi M37450", tag, owner, clock, ADDRESS_MAP_NAME(m37450_map))
|
||||
{
|
||||
}
|
||||
|
||||
m37450_device::m37450_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
|
||||
m3745x_device(mconfig, type, name, tag, owner, clock, ADDRESS_MAP_NAME(m37450_map))
|
||||
{
|
||||
}
|
||||
|
||||
156
src/emu/cpu/m6502/m3745x.h
Normal file
156
src/emu/cpu/m6502/m3745x.h
Normal file
@ -0,0 +1,156 @@
|
||||
#pragma once
|
||||
|
||||
#ifndef __M3745X_H__
|
||||
#define __M3745X_H__
|
||||
|
||||
#include "m740.h"
|
||||
|
||||
//**************************************************************************
|
||||
// INTERFACE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define MCFG_M3745X_ADC14_CALLBACKS(_ad0, _ad1, _ad2, _ad3) \
|
||||
downcast<m3745x_device *>(device)->set_ad14_callbacks(DEVCB2_##_ad0, DEVCB2_##_ad1, DEVCB2_##_ad2, DEVCB2_##_ad3);
|
||||
|
||||
#define MCFG_M3745X_ADC58_CALLBACKS(_ad0, _ad1, _ad2, _ad3) \
|
||||
downcast<m3745x_device *>(device)->set_ad58_callbacks(DEVCB2_##_ad0, DEVCB2_##_ad1, DEVCB2_##_ad2, DEVCB2_##_ad3);
|
||||
|
||||
#define MCFG_M3745X_PORT3_CALLBACKS(_read, _write) \
|
||||
downcast<m3745x_device *>(device)->set_p3_callbacks(DEVCB2_##_read, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_M3745X_PORT4_CALLBACKS(_read, _write) \
|
||||
downcast<m3745x_device *>(device)->set_p4_callbacks(DEVCB2_##_read, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_M3745X_PORT5_CALLBACKS(_read, _write) \
|
||||
downcast<m3745x_device *>(device)->set_p5_callbacks(DEVCB2_##_read, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_M3745X_PORT6_CALLBACKS(_read, _write) \
|
||||
downcast<m3745x_device *>(device)->set_p6_callbacks(DEVCB2_##_read, DEVCB2_##_write);
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> m3745x_device
|
||||
|
||||
class m3745x_device : public m740_device
|
||||
{
|
||||
friend class m37450_device;
|
||||
|
||||
enum
|
||||
{
|
||||
TIMER_1 = 0,
|
||||
TIMER_2,
|
||||
TIMER_3,
|
||||
|
||||
TIMER_ADC,
|
||||
|
||||
NUM_TIMERS
|
||||
};
|
||||
|
||||
public:
|
||||
enum
|
||||
{
|
||||
M3745X_INT1_LINE = INPUT_LINE_IRQ0,
|
||||
M3745X_INT2_LINE,
|
||||
M3745X_INT3_LINE,
|
||||
|
||||
M3745X_SET_OVERFLOW = M740_SET_OVERFLOW
|
||||
};
|
||||
|
||||
// construction/destruction
|
||||
m3745x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal_map);
|
||||
|
||||
const address_space_config m_program_config;
|
||||
|
||||
template<class _read, class _write> void set_p3_callbacks(_read rd, _write wr)
|
||||
{
|
||||
read_p3.set_callback(rd);
|
||||
write_p3.set_callback(wr);
|
||||
}
|
||||
|
||||
template<class _read, class _write> void set_p4_callbacks(_read rd, _write wr)
|
||||
{
|
||||
read_p4.set_callback(rd);
|
||||
write_p4.set_callback(wr);
|
||||
}
|
||||
|
||||
template<class _read, class _write> void set_p5_callbacks(_read rd, _write wr)
|
||||
{
|
||||
read_p5.set_callback(rd);
|
||||
write_p5.set_callback(wr);
|
||||
}
|
||||
|
||||
template<class _read, class _write> void set_p6_callbacks(_read rd, _write wr)
|
||||
{
|
||||
read_p6.set_callback(rd);
|
||||
write_p6.set_callback(wr);
|
||||
}
|
||||
|
||||
template<class _read, class _read2, class _read3, class _read4> void set_ad14_callbacks(_read rd, _read2 rd2, _read3 rd3, _read4 rd4)
|
||||
{
|
||||
read_ad_0.set_callback(rd);
|
||||
read_ad_1.set_callback(rd2);
|
||||
read_ad_2.set_callback(rd3);
|
||||
read_ad_3.set_callback(rd4);
|
||||
}
|
||||
|
||||
template<class _read, class _read2, class _read3, class _read4> void set_ad58_callbacks(_read rd, _read2 rd2, _read3 rd3, _read4 rd4)
|
||||
{
|
||||
read_ad_4.set_callback(rd);
|
||||
read_ad_5.set_callback(rd2);
|
||||
read_ad_6.set_callback(rd3);
|
||||
read_ad_7.set_callback(rd4);
|
||||
}
|
||||
|
||||
devcb2_read8 read_p3, read_p4, read_p5, read_p6;
|
||||
devcb2_write8 write_p3, write_p4, write_p5, write_p6;
|
||||
devcb2_read8 read_ad_0, read_ad_1, read_ad_2, read_ad_3;
|
||||
devcb2_read8 read_ad_4, read_ad_5, read_ad_6, read_ad_7;
|
||||
|
||||
DECLARE_READ8_MEMBER(ports_r);
|
||||
DECLARE_WRITE8_MEMBER(ports_w);
|
||||
DECLARE_READ8_MEMBER(adc_r);
|
||||
DECLARE_WRITE8_MEMBER(adc_w);
|
||||
DECLARE_READ8_MEMBER(intregs_r);
|
||||
DECLARE_WRITE8_MEMBER(intregs_w);
|
||||
|
||||
bool are_port_bits_output(UINT8 port, UINT8 mask) { return ((m_ddrs[port] & mask) == mask) ? true : false; }
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
virtual void device_config_complete();
|
||||
virtual void execute_set_input(int inputnum, int state);
|
||||
virtual const address_space_config *memory_space_config(address_spacenum spacenum) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
|
||||
|
||||
void send_port(address_space &space, UINT8 offset, UINT8 data);
|
||||
UINT8 read_port(UINT8 offset);
|
||||
|
||||
void recalc_irqs();
|
||||
|
||||
UINT8 m_ports[6], m_ddrs[6];
|
||||
UINT8 m_intreq1, m_intreq2, m_intctrl1, m_intctrl2;
|
||||
UINT8 m_adctrl;
|
||||
UINT16 m_last_all_ints;
|
||||
|
||||
private:
|
||||
emu_timer *m_timers[NUM_TIMERS];
|
||||
};
|
||||
|
||||
class m37450_device : public m3745x_device
|
||||
{
|
||||
public:
|
||||
m37450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
m37450_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
protected:
|
||||
|
||||
private:
|
||||
};
|
||||
|
||||
extern const device_type M37450;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user