Small comment fixes/addenda. (n/w)

src/mame/audio/dkong.c

@@ -1145,7 +1145,7 @@ Addresses found at @0x510, cpu2
  0: 14 16       ... checkpoint charlie
  1: 14 18       ... checkpoint bravo
  2: 14 1A       ... checkpoint alpha
- 3: 1C          You'll notice
+ 3: 1C          Use Caution (sounds kinda like 'You'll notice')
  4: 1E 1E       Complete attack mission
  5: 10 10 10    trouble, trouble, trouble
  6: 12 12       all pilots climb up

src/mess/drivers/sdk86.c

@@ -9,8 +9,7 @@
         22/06/2011 Working [Robbbert]
 
     TODO:
-    Add 8251A for serial
-    Add optional 2x 8255A
+    Add optional 2x 8255A port read/write logging
 
 
 
@@ -19,6 +18,7 @@ This is an evaluation kit for the 8086 cpu.
 There is no speaker or storage facility in the standard kit.
 
 Download the User Manual to get the operating procedures.
+The user manual is available from: http://www.bitsavers.org/pdf/intel/8086/9800698A_SDK-86_Users_Man_Apr79.pdf
 
 ToDo:
 - Artwork

src/mess/drivers/tispeak.c

@@ -18,9 +18,10 @@
 #include "tispeak.lh"
 
 // The master clock is a single stage RC oscillator into TMS5100 RCOSC:
-// C is 68pf, R is a 50kohm trimpot wich is set to 33.6kohm. CPUCLK is this/2, ROMCLK is this/4.
+// In an early 1979 Speak & Spell, C is 68pf, R is a 50kohm trimpot which is set to around 33.6kohm
+// (measured in-circuit). CPUCLK is this osc freq /2, ROMCLK is this osc freq /4.
 // The typical osc freq curve for TMS5100 is unknown. Let's assume it is set to the default frequency,
-// which is 640kHz according to the TMS5100 documentation.
+// which is 640kHz for 8KHz according to the TMS5100 documentation.
 
 #define MASTER_CLOCK (640000)