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Small comment fixes/addenda. (n/w)
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@ -1145,7 +1145,7 @@ Addresses found at @0x510, cpu2
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0: 14 16 ... checkpoint charlie
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0: 14 16 ... checkpoint charlie
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1: 14 18 ... checkpoint bravo
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1: 14 18 ... checkpoint bravo
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2: 14 1A ... checkpoint alpha
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2: 14 1A ... checkpoint alpha
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3: 1C You'll notice
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3: 1C Use Caution (sounds kinda like 'You'll notice')
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4: 1E 1E Complete attack mission
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4: 1E 1E Complete attack mission
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5: 10 10 10 trouble, trouble, trouble
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5: 10 10 10 trouble, trouble, trouble
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6: 12 12 all pilots climb up
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6: 12 12 all pilots climb up
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@ -9,8 +9,7 @@
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22/06/2011 Working [Robbbert]
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22/06/2011 Working [Robbbert]
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TODO:
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TODO:
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Add 8251A for serial
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Add optional 2x 8255A port read/write logging
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Add optional 2x 8255A
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@ -19,6 +18,7 @@ This is an evaluation kit for the 8086 cpu.
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There is no speaker or storage facility in the standard kit.
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There is no speaker or storage facility in the standard kit.
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Download the User Manual to get the operating procedures.
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Download the User Manual to get the operating procedures.
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The user manual is available from: http://www.bitsavers.org/pdf/intel/8086/9800698A_SDK-86_Users_Man_Apr79.pdf
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ToDo:
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ToDo:
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- Artwork
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- Artwork
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@ -18,9 +18,10 @@
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#include "tispeak.lh"
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#include "tispeak.lh"
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// The master clock is a single stage RC oscillator into TMS5100 RCOSC:
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// The master clock is a single stage RC oscillator into TMS5100 RCOSC:
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// C is 68pf, R is a 50kohm trimpot wich is set to 33.6kohm. CPUCLK is this/2, ROMCLK is this/4.
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// In an early 1979 Speak & Spell, C is 68pf, R is a 50kohm trimpot which is set to around 33.6kohm
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// (measured in-circuit). CPUCLK is this osc freq /2, ROMCLK is this osc freq /4.
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// The typical osc freq curve for TMS5100 is unknown. Let's assume it is set to the default frequency,
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// The typical osc freq curve for TMS5100 is unknown. Let's assume it is set to the default frequency,
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// which is 640kHz according to the TMS5100 documentation.
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// which is 640kHz for 8KHz according to the TMS5100 documentation.
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#define MASTER_CLOCK (640000)
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#define MASTER_CLOCK (640000)
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