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(MESS) cat.c: Implemented watchdog counter readback, more documentation [Lord Nightmare]
This commit is contained in:
Jonathan Gevaryahu
parent
4d411b439f
commit
f9372ec51c
@ -281,14 +281,11 @@ ToDo:
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data, though track 0 is just a disk "unique" identifier for the cat
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meaning 404480 usable bytes
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* (Once the floppy is working I'd declare the system working)
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- Beeper/speaker; this is connected to the DUART 'user output' pin OP3 and
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probably depends on an accurate implementation of the duart counters/timers
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- Centronics port
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- WIP: Centronics port (need to hook up prn_ack_ff and correctly invert centronics busy
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- RS232C port and Modem "port" connected to the DUART's two ports
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- DTMF generator chip (connected to DUART 'user output' pins OP4,5,6,7)
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- Correctly hook the duart interrupt to the 68k, including autovector using
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the vector register on the duart; this is currently hacked around.
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- Watchdog timer/powerfail at 0x85xxxx
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- WIP: Watchdog timer/powerfail at 0x85xxxx (watchdog NMI needs to actually
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fire if wdt goes above a certain number, possibly 3, 7 or F?)
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- Canon Cat released versions known: 1.74 US (dumped), 2.40 US (dumped both
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original compile, and Dwight's recompile from the released source code),
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2.42 (NEED DUMP)
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@ -308,6 +305,7 @@ ToDo:
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happens inside an asic) for the SVROMS (or the svram or the code roms, for
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that matter!)
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- Hook Battery Low input to a dipswitch.
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- Hook pfail to a dipswitch?
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- Hook the floppy control register readback up properly, things seem to get
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confused.
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@ -340,8 +338,8 @@ ToDo:
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#undef DEBUG_FLOPPY_DATA_R
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#undef DEBUG_FLOPPY_STATUS_R
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#define DEBUG_PRINTER_DATA_W 1
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#define DEBUG_PRINTER_CONTROL_W 1
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#undef DEBUG_PRINTER_DATA_W
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#undef DEBUG_PRINTER_CONTROL_W
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#undef DEBUG_MODEM_R
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#undef DEBUG_MODEM_W
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@ -457,6 +455,7 @@ public:
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DECLARE_WRITE16_MEMBER(cat_modem_w);
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DECLARE_READ16_MEMBER(cat_6ms_counter_r);
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DECLARE_WRITE16_MEMBER(cat_opr_w);
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DECLARE_READ16_MEMBER(cat_wdt_r);
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DECLARE_WRITE16_MEMBER(cat_tcb_w);
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DECLARE_READ16_MEMBER(cat_2e80_r);
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DECLARE_READ16_MEMBER(cat_0080_r);
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@ -488,16 +487,30 @@ public:
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DECLARE_WRITE_LINE_MEMBER(write_acia_clock);
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UINT8 m_duart_inp;
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/* gate array 2 has a 16-bit counter inside which counts at 10mhz and
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rolls over at FFFF->0000; on roll-over (or maybe at FFFF terminal count)
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it triggers the KTDBF output. It does this every 6.5535ms, which causes
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a 74LS74 d-latch at IC100 to switch the state of the DUART IP2 line;
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rolls over at FFFF->0000; on roll-over (or likely at FFFF terminal count)
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it triggers the KTOBF output. It does this every 6.5535ms, which causes
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a 74LS74 d-latch at IC100 to invert the state of the DUART IP2 line;
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this causes the DUART to fire an interrupt, which makes the 68000 read
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the keyboard.
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The watchdog counter and the 6ms counter are both incremented
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every time the KTOBF pulses.
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*/
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UINT8 m_duart_irq_state;
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UINT16 m_6ms_counter;
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UINT8 m_wdt_counter;
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UINT8 m_duart_ktobf_ff;
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/* the /ACK line from the centronics printer port goes through a similar
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flipflop to the ktobf line as well, so duart IP4 inverts on /ACK rising edge
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*/
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UINT8 m_duart_prn_ack_ff;
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/* Gate array 2 is in charge of serializing the video for display to the screen;
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Gate array 1 is in charge of vblank/hblank timing, and in charge of refreshing
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dram and indicating to GA2, using the /LDPS signal, what times the address it is
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writing to ram it is intending to be used by GA2 to read 16 bits of data to be
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shifted out to the screen. (it is obviously not active during hblank and vblank)
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GA2 then takes: ((output_bit XNOR video_invert) AND video enable), and serially
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bangs the result to the analog display circuitry.
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*/
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UINT8 m_video_enable;
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UINT8 m_video_invert;
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UINT16 m_pr_cont;
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@ -682,10 +695,12 @@ READ16_MEMBER( cat_state::cat_keyboard_r )
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case 0x80: retVal = m_y7->read() << 8; break;
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}
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}
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#if 0
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if ((m_pr_cont != 0x0800) && (m_pr_cont != 0x0900) && (m_pr_cont != 0x0a00))
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{
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fprintf(stderr,"Read from keyboard in %06X with unexpected pr_cont %04X\n", 0x80000a+(offset<<1), m_pr_cont);
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}
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#endif
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return retVal;
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}
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@ -749,41 +764,67 @@ WRITE16_MEMBER( cat_state::cat_modem_w )
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#endif
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}
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// 0x830000: 6ms counter (used for KTDBF)
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// 0x830000: 6ms counter (counts KTOBF pulses and does not reset; 16 bits wide)
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READ16_MEMBER( cat_state::cat_6ms_counter_r )
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{
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return m_6ms_counter;
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}
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/* 0x840001: 'opr' or 'ga2opr' Output Port Register
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* writing 0x1c (or probably anything with bit 3 set) here resets the watchdog
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* if the watchdog expires an NMI is sent to the cpu
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/* 0x840001: 'opr' or 'ga2opr' Output Port Register (within GA2)
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* writing anything with bit 3 set here resets the watchdog
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* if the watchdog expires /NMI (and maybe /RESET) are asserted to the cpu
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* watchdog counter (counts KTOBF pulses and is reset on any ga2opr write with bit 3 set; <9 bits wide)
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*/
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WRITE16_MEMBER( cat_state::cat_opr_w )
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{
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/*
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* 76543210 (FEDCBA98 are ignored)
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* |||||||\-- ?
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* ||||||\--- ?
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* |||||||\-- OFFHOOK pin (pin 3) output control (1 = puts phone off hook by energizing relay K2)
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* ||||||\--- PHONE pin (pin 4) output control (1 = connects phone and line together by energizing relay K1)
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* |||||\---- Video enable (1 = video on, 0 = video off/screen black)
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* ||||\----- Watchdog reset?
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* ||||\----- Watchdog reset (the watchdog is reset whenever this bit is written with a 1)
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* |||\------ Video invert (1 = black-on-white video; 0 = white-on-black)
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* ||\------- ?
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* |\-------- ?
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* \--------- ?
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* ||\------- (unused?)
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* |\-------- (unused?)
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* \--------- (unused?)
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*/
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#ifdef DEBUG_VIDEO_ENABLE_W
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fprintf(stderr, "Video enable reg write: offset %06X, data %04X\n", 0x840000+(offset<<1), data);
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#ifdef DEBUG_GA2OPR_W
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fprintf(stderr, "GA2 OPR (video ena/inv, watchdog, and phone relay) reg write: offset %06X, data %04X\n", 0x840000+(offset<<1), data);
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#endif
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if (data&0x08) m_wdt_counter = 0;
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m_video_enable = BIT( data, 2 );
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m_video_invert = 1-BIT( data, 4 );
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}
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// 0x850000: 'wdt' watchdog timer/video status
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// implement me!
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// 0x850000: 'wdt' "watchdog timer and power fail", read only?
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/* NOTE: BELOW IS A GUESS based on seeing what the register reads as,
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* the cat code barely touches this stuff at all, despite the fact
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* that the service manual states that PFAIL is supposed to be checked
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* before each write to SVRAM, the forth code does NOT actually do that!
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*
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* 76543210
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* ??????\\-- Watchdog count? (counts upward? if this reaches <some unknown number greater than 2> the watchdog fires? writing bit 3 set to opr above resets this)
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*
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* FEDCBA98
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* |||||||\-- PFAIL state (1 = 5v detector near svram says power ok for saving; 0 = 5v detector shows power fail or unstable, hence do not write to svram!)
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* ||||||\--- (always 0?)
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* |||||\---- (always 0?)
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* ||||\----- (always 0?)
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* |||\------ (always 0?)
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* ||\------- (always 0?)
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* |\-------- (always 0?)
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* \--------- (always 0?)
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*/
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READ16_MEMBER( cat_state::cat_wdt_r )
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{
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uint16 Retval = 0x0100; // set pfail to 1; should this be a dipswitch?
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return Retval | m_wdt_counter;
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}
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// 0x860000: 'tcb' test regitser
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// the power fail status reset bit also lives here somewhere?
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// 0x860000: 'tcb' "test control bits" test mode register; what the bits do is
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// unknown. 0x0000 is written here to disable test mode, and that is the extent
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// of the cat touching this register.
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// it is possible that writing ANYTHING here will set the PFAIL state from 0 to 1, assuming the guessed information about pfail above is correct.
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WRITE16_MEMBER( cat_state::cat_tcb_w )
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{
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#ifdef DEBUG_TEST_W
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@ -843,7 +884,7 @@ a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4
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1 0 0 x x 0 1 1 x x x x x x x x x x x x x x x * R {'timer'} Read: Fixed 16-bit counter from ga2. increments every 6.5535ms when another 16-bit counter clocked at 10mhz overflows
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1 0 0 x x 1 0 0 x x x x x x x x x x x x x x x * W {'opr'} Output Port (Video/Sync enable and watchdog reset?) register (screen enable on bit 3?) (reads as 0x2e80)
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1 0 0 x x 1 0 1 x x x x x x x x x x x x x x x * R {'wdt'} Watchdog timer reads as 0x0100 0x0101 or 0x0102, some sort of test register or video status register?
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1 0 0 x x 1 1 0 x x x x x x x x x x x x x x x * R?W {'tcb'} test control bits: powerfail status in bit <?> (reads as 0x0000)
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1 0 0 x x 1 1 0 x x x x x x x x x x x x x x x * R?W {'tcb'} test control bits (reads as 0x0000)
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1 0 0 x x 1 1 1 x x x x x x x x x x x x x x x * ? Unknown (reads as 0x2e80)
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1 0 1 x x x x x x x x x x x x x x x x x x x x x O OPEN BUS (reads as 0x2e80) [68k DTACK is asserted by gate array 1 when accessing this area, for testing?] On real IAI shadow rom board, at least 0x40000 of ram lives here.
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@ -871,7 +912,7 @@ static ADDRESS_MAP_START(cat_mem, AS_PROGRAM, 16, cat_state)
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AM_RANGE(0x820000, 0x82003f) AM_READWRITE(cat_modem_r,cat_modem_w) AM_MIRROR(0x18FFC0) // AMI S35213 Modem Chip, all access is on bit 7
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AM_RANGE(0x830000, 0x830001) AM_READ(cat_6ms_counter_r) AM_MIRROR(0x18FFFE) // 16bit 6ms counter clocked by output of another 16bit counter clocked at 10mhz
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AM_RANGE(0x840000, 0x840001) AM_READWRITE(cat_2e80_r,cat_opr_w) AM_MIRROR(0x18FFFE) // GA2 Output port register (video enable, invert, watchdog reset, phone relays)
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//AM_RANGE(0x850000, 0x850001) AM_READ(cat_wdt_r) AM_MIRROR(0x18FFFE) // watchdog and power fail state read
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AM_RANGE(0x850000, 0x850001) AM_READ(cat_wdt_r) AM_MIRROR(0x18FFFE) // watchdog and power fail state read
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AM_RANGE(0x860000, 0x860001) AM_READWRITE(cat_0000_r, cat_tcb_w) AM_MIRROR(0x18FFFE) // Test mode
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AM_RANGE(0x870000, 0x870001) AM_READ(cat_2e80_r) AM_MIRROR(0x18FFFE) // Open bus?
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AM_RANGE(0xA00000, 0xA00001) AM_READ(cat_2e80_r) AM_MIRROR(0x1FFFFE) // Open bus/dtack? The 0xA00000-0xA3ffff area is ram used for shadow rom storage on cat developer machines, which is either banked over top of, or jumped to instead of the normal rom
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@ -1005,11 +1046,11 @@ void cat_state::device_timer(emu_timer &timer, device_timer_id id, int param, vo
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TIMER_CALLBACK_MEMBER(cat_state::counter_6ms_callback)
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{
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// This is effectively also the KTDBF line 'clock' output to the d-latch before the duart
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// Hence, invert the d-latch on the duart's input ports.
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// n68681 now properly generates interrupts when this bit changes, the previous hack is no longer necessary.
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m_duart_inp ^= 0x04;
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m_duart->ip2_w((m_duart_inp>>2)&1);
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// This is effectively also the KTOBF (guessed: acronym for "Keyboard Timer Out Bit Flip")
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// line connected in such a way to invert the d-flipflop connected to the duart IP2
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m_duart_ktobf_ff ^= 1;
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m_duart->ip2_w(m_duart_ktobf_ff);
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m_wdt_counter++;
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m_6ms_counter++;
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}
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@ -1021,9 +1062,10 @@ IRQ_CALLBACK_MEMBER(cat_state::cat_int_ack)
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MACHINE_START_MEMBER(cat_state,cat)
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{
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m_duart_inp = 0;
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m_duart_irq_state = 0;
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m_duart_ktobf_ff = 0;
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m_duart_prn_ack_ff = 0;
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m_6ms_counter = 0;
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m_wdt_counter = 0;
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m_video_enable = 1;
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m_video_invert = 0;
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m_6ms_timer = timer_alloc(TIMER_COUNTER_6MS);
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@ -1033,9 +1075,10 @@ MACHINE_START_MEMBER(cat_state,cat)
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MACHINE_RESET_MEMBER(cat_state,cat)
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{
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m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(cat_state::cat_int_ack),this));
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m_duart_inp = 0;
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m_duart_irq_state = 0;
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m_duart_ktobf_ff = 0;
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m_duart_prn_ack_ff = 0;
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m_6ms_counter = 0;
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m_wdt_counter = 0;
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m_floppy_control = 0;
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m_6ms_timer->adjust(attotime::zero, 0, attotime::from_hz((XTAL_19_968MHz/2)/65536));
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}
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@ -1072,7 +1115,7 @@ UINT32 cat_state::screen_update_cat(screen_device &screen, bitmap_ind16 &bitmap,
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}
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/* The duart is the only thing actually connected to the cpu IRQ pin
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* The KTDBF output of the gate array 2 (itself the terminal count output
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* The KTOBF output of the gate array 2 (itself the terminal count output
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* of a 16-bit counter clocked at ~10mhz, hence 6.5536ms period) goes to a
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* d-latch and inputs on ip2 of the duart, causing the duart to fire an irq;
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* this is used by the cat to read the keyboard.
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@ -1084,7 +1127,6 @@ WRITE_LINE_MEMBER(cat_state::cat_duart_irq_handler)
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#ifdef DEBUG_DUART_IRQ_HANDLER
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fprintf(stderr, "Duart IRQ handler called: state: %02X, vector: %06X\n", state, irqvector);
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#endif
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m_duart_irq_state = state;
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m_maincpu->set_input_line_and_vector(M68K_IRQ_1, state, irqvector);
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}
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@ -1098,7 +1140,7 @@ WRITE_LINE_MEMBER(cat_state::cat_duart_txa)
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/* mc68681 DUART Input pins:
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* IP0: CTS [using the DUART builtin hardware-CTS feature?]
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* IP1: Centronics /ACK (pin 10) positive edge detect (IP1 changes state 0->1 or 1->0 on the rising edge of /ACK using a 74ls74a d-flipflop)
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* IP2: KTDBF (IP2 changes state 0->1 or 1->0 on the rising edge of KTDBF using a 74ls74a d-flipflop; KTDBF is a 6.5536ms-period squarewave generated by one of the gate arrays, I need to check with a scope to see whether it is a single spike/pulse every 6.5536ms or if from the gate array it inverts every 6.5536ms, documentation isn't 100% clear but I suspect the former) [uses the Delta IP2 state change detection feature to generate an interrupt; I'm not sure if IP2 is used as a counter clock source but given the beep frequency of the real unit I very much doubt it, 6.5536ms is too slow]
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* IP2: KTOBF (IP2 changes state 0->1 or 1->0 on the rising edge of KTOBF using a 74ls74a d-flipflop; KTOBF is a 6.5536ms-period squarewave generated by one of the gate arrays, I need to check with a scope to see whether it is a single spike/pulse every 6.5536ms or if from the gate array it inverts every 6.5536ms, documentation isn't 100% clear but I suspect the former) [uses the Delta IP2 state change detection feature to generate an interrupt; I'm not sure if IP2 is used as a counter clock source but given the beep frequency of the real unit I very much doubt it, 6.5536ms is too slow]
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* IP3: RG ("ring" input)
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* IP4: Centronics BUSY (pin 11), inverted
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* IP5: DSR
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