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pci: expansion rom management [O. Galibert]

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This commit is contained in:
Olivier Galibert 2014-12-09 19:28:07 +01:00
parent 0c42fdfc3d
commit f9715d5a31
4 changed files with 57 additions and 16 deletions
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60
src/emu/machine/pci.c
View File

@ -13,12 +13,13 @@ DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device)
AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00)
AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000)
AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000)
AM_RANGE(0x0c, 0x0f) AM_WRITENOP
AM_RANGE(0x10, 0x27) AM_READWRITE (address_base_r, address_base_w)
// Cardbus CIS pointer at 28
AM_RANGE(0x2c, 0x2f) AM_READ16 (subvendor_r, 0x0000ffff)
AM_RANGE(0x2c, 0x2f) AM_READ16 (subsystem_r, 0xffff0000)
AM_RANGE(0x2c, 0x2f) AM_WRITENOP
AM_RANGE(0x30, 0x33) AM_READWRITE (expansion_base_r, expansion_base_w)
AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff)
ADDRESS_MAP_END
@ -88,6 +89,10 @@ void pci_device::device_start()
bank_count = 0;
bank_reg_count = 0;
expansion_rom = 0;
expansion_rom_size = 0;
expansion_rom_base = 0;
}
void pci_device::device_reset()
@ -209,6 +214,24 @@ READ16_MEMBER(pci_device::subsystem_r)
return subsystem_id;
}
READ32_MEMBER(pci_device::expansion_base_r)
{
return expansion_rom_base;
}
WRITE32_MEMBER(pci_device::expansion_base_w)
{
COMBINE_DATA(&expansion_rom_base);
if(!expansion_rom_size)
expansion_rom_base = 0;
else {
// Trick to get an address resolution at expansion_rom_size with minimal granularity of 0x800, plus bit 1 set to keep the on/off information
expansion_rom_base &= 0xfffff801 & (1-expansion_rom_size);
}
remap_cb();
}
READ8_MEMBER(pci_device::capptr_r)
{
return 0x00;
@ -256,10 +279,20 @@ void pci_device::map_device(UINT64 memory_window_start, UINT64 memory_window_end
case 5: space->install_readwrite_handler(start, end, 0, 0, read32_delegate(FUNC(pci_device::unmapped5_r), this), write32_delegate(FUNC(pci_device::unmapped5_w), this)); break;
}
space->install_device_delegate(start, end, *this, bi.map);
logerror("%s: map %s at %0*x-%0*x\n", tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
}
map_extra(memory_window_start, memory_window_end, memory_offset, memory_space,
io_window_start, io_window_end, io_offset, io_space);
if(expansion_rom_base & 1) {
logerror("%s: map expansion rom at %08x-%08x\n", tag(), expansion_rom_base & ~1, (expansion_rom_base & ~1) + expansion_rom_size - 1);
UINT32 start = (expansion_rom_base & ~1) + memory_offset;
UINT32 end = start + expansion_rom_size - 1;
if(end > memory_window_end)
end = memory_window_end;
memory_space->install_rom(start, end, (void *)expansion_rom);
}
}
void pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
@ -305,6 +338,18 @@ void pci_device::add_map(UINT64 size, int flags, address_map_delegate &map)
logerror("Device %s (%s) has 0x%" I64FMT "x bytes of %s named %s\n", tag(), name(), size, flags & M_IO ? "io" : "memory", map.name());
}
void pci_device::add_rom(const UINT8 *rom, UINT32 size)
{
expansion_rom = rom;
expansion_rom_size = size;
logerror("Device %s (%s) has 0x%x bytes of expansion rom\n", tag(), name(), size);
}
void pci_device::add_rom_from_region()
{
add_rom(m_region->base(), m_region->bytes());
}
agp_device::agp_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
: pci_device(mconfig, type, name, tag, owner, clock, shortname, source)
{
@ -662,17 +707,6 @@ WRITE16_MEMBER(pci_bridge_device::iolimitu_w)
logerror("%s: iolimitu_w %04x\n", tag(), data);
}
READ32_MEMBER (pci_bridge_device::expansion_base_r)
{
logerror("%s: expansion_base_r\n", tag());
return 0xffffffff;
}
WRITE32_MEMBER(pci_bridge_device::expansion_base_w)
{
logerror("%s: expansion_base_w %08x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::interrupt_line_r)
{
logerror("%s: interrupt_line_r\n", tag());

10
src/emu/machine/pci.h
View File

@ -74,6 +74,8 @@ public:
DECLARE_WRITE32_MEMBER(address_base_w);
DECLARE_READ16_MEMBER(subvendor_r);
DECLARE_READ16_MEMBER(subsystem_r);
DECLARE_READ32_MEMBER (expansion_base_r);
DECLARE_WRITE32_MEMBER(expansion_base_w);
virtual DECLARE_READ8_MEMBER(capptr_r);
protected:
@ -104,6 +106,9 @@ protected:
UINT32 pclass;
UINT8 revision;
UINT16 command, command_mask, status;
const UINT8 *expansion_rom;
UINT32 expansion_rom_size;
UINT32 expansion_rom_base;
virtual void device_start();
virtual void device_reset();
@ -116,6 +121,9 @@ protected:
address_map_delegate delegate(map, name, static_cast<T *>(this));
add_map(size, flags, delegate);
}
void add_rom(const UINT8 *data, UINT32 size);
void add_rom_from_region();
};
class agp_device : public pci_device {
@ -173,8 +181,6 @@ public:
DECLARE_WRITE16_MEMBER(iobaseu_w);
DECLARE_READ16_MEMBER (iolimitu_r);
DECLARE_WRITE16_MEMBER(iolimitu_w);
DECLARE_READ32_MEMBER (expansion_base_r);
DECLARE_WRITE32_MEMBER(expansion_base_w);
DECLARE_READ8_MEMBER (interrupt_line_r);
DECLARE_WRITE8_MEMBER (interrupt_line_w);
DECLARE_READ8_MEMBER (interrupt_pin_r);

1
src/emu/video/gf6800gt.c
View File

@ -22,6 +22,7 @@ void geforce_6800gt_device::device_start()
add_map( 16*1024*1024, M_MEM, FUNC(geforce_6800gt_device::map1));
add_map(256*1024*1024, M_MEM, FUNC(geforce_6800gt_device::map2));
add_map( 16*1024*1024, M_MEM, FUNC(geforce_6800gt_device::map3));
add_rom_from_region();
}
void geforce_6800gt_device::device_reset()

2
src/mame/drivers/lindbergh.c
View File

@ -384,7 +384,7 @@ MACHINE_CONFIG_END
ROM_REGION(0x400000, ":pci:1e.0:03.0", 0) /* Baseboard MPC firmware */ \
ROM_LOAD("fpr-24370b.ic6", 0x000000, 0x400000, CRC(c3b021a4) SHA1(1b6938a50fe0e4ae813864649eb103838c399ac0)) \
\
ROM_REGION32_LE(0x10000, ":pci:01.0:00.0", 0) /* Geforce bios extension (custom or standard?) */ \
ROM_REGION32_LE(0x10000, ":pci:01.0:00.0", 0) /* Geforce bios extension (custom for the card) */ \
ROM_LOAD("vid_bios.u504", 0x00000, 0x10000, CRC(f78d14d7) SHA1(f129787e487984edd23bf344f2e9500c85052275)) \
ROM_START(lindbios)