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Converted Namco IO chips 56xx, 58xx and 59xx to be devices and converted gaplus.c, mappy.c and toypop.c to use the new code

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This commit is contained in:
Fabio Priuli 2009-12-26 23:56:44 +00:00
parent 933132291e
commit f98d17e45b
6 changed files with 807 additions and 524 deletions
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225
src/mame/drivers/gaplus.c
View File

@ -157,78 +157,6 @@ TODO:
#include "includes/gaplus.h" #include "includes/gaplus.h"
/***************************************************************************
Custom I/O initialization
***************************************************************************/
static READ8_HANDLER( in0_l ) { return input_port_read(space->machine, "IN0"); } // P1 joystick
static READ8_HANDLER( in0_h ) { return input_port_read(space->machine, "IN0") >> 4; } // P2 joystick
static READ8_HANDLER( in1_l ) { return input_port_read(space->machine, "IN1"); } // fire and start buttons
static READ8_HANDLER( in1_h ) { return input_port_read(space->machine, "IN1") >> 4; } // coins
static READ8_HANDLER( dipA_l ) { return input_port_read(space->machine, "DSW0"); } // dips A
static READ8_HANDLER( dipA_h ) { return input_port_read(space->machine, "DSW0") >> 4; } // dips A
static READ8_HANDLER( dipB_l ) { return input_port_read(space->machine, "DSW1"); } // dips B
static READ8_HANDLER( dipB_h ) { return input_port_read(space->machine, "DSW1") >> 4; } // dips B
static WRITE8_HANDLER( out_lamps0 )
{
set_led_status(space->machine, 0,data & 1);
set_led_status(space->machine, 1,data & 2);
coin_lockout_global_w(space->machine, data & 4);
coin_counter_w(space->machine, 0,~data & 8);
}
static WRITE8_HANDLER( out_lamps1 )
{
coin_counter_w(space->machine, 1,~data & 1);
}
/* chip #0: player inputs, buttons, coins */
static const struct namcoio_interface intf0 =
{
{ in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
{ NULL, NULL } /* port write handlers */
};
static const struct namcoio_interface intf0_lamps =
{
{ in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
{ out_lamps0, out_lamps1 } /* port write handlers */
};
/* chip #1: dip switches */
static const struct namcoio_interface intf1 =
{
{ dipA_h, dipB_l, dipB_h, dipA_l }, /* port read handlers */
{ NULL, NULL } /* port write handlers */
};
/* TODO: chip #2: test/cocktail, optional buttons */
static void unpack_gfx(running_machine *machine);
static DRIVER_INIT( 56_58 )
{
unpack_gfx(machine);
namcoio_init(machine, 0, NAMCOIO_56XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_58XX, &intf1, NULL);
}
static DRIVER_INIT( 56_58l )
{
unpack_gfx(machine);
namcoio_init(machine, 0, NAMCOIO_56XX, &intf0_lamps, NULL);
namcoio_init(machine, 1, NAMCOIO_58XX, &intf1, NULL);
}
static DRIVER_INIT( 58_56 )
{
unpack_gfx(machine);
namcoio_init(machine, 0, NAMCOIO_58XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1, NULL);
}
/***************************************************************************/
static READ8_HANDLER( gaplus_spriteram_r ) static READ8_HANDLER( gaplus_spriteram_r )
{ {
return gaplus_spriteram[offset]; return gaplus_spriteram[offset];
@ -280,17 +208,21 @@ static WRITE8_HANDLER( gaplus_irq_2_ctrl_w )
static WRITE8_HANDLER( gaplus_sreset_w ) static WRITE8_HANDLER( gaplus_sreset_w )
{ {
int bit = !BIT(offset, 11); int bit = !BIT(offset, 11);
cputag_set_input_line(space->machine, "sub", INPUT_LINE_RESET, bit ? CLEAR_LINE : ASSERT_LINE); cputag_set_input_line(space->machine, "sub", INPUT_LINE_RESET, bit ? CLEAR_LINE : ASSERT_LINE);
cputag_set_input_line(space->machine, "sub2", INPUT_LINE_RESET, bit ? CLEAR_LINE : ASSERT_LINE); cputag_set_input_line(space->machine, "sub2", INPUT_LINE_RESET, bit ? CLEAR_LINE : ASSERT_LINE);
mappy_sound_enable(devtag_get_device(space->machine, "namco"), bit); mappy_sound_enable(devtag_get_device(space->machine, "namco"), bit);
} }
static WRITE8_HANDLER( gaplus_freset_w ) static WRITE8_HANDLER( gaplus_freset_w )
{ {
const device_config *io58xx = devtag_get_device(space->machine, "58xx");
const device_config *io56xx = devtag_get_device(space->machine, "56xx");
int bit = !BIT(offset, 11); int bit = !BIT(offset, 11);
logerror("%04x: freset %d\n",cpu_get_pc(space->cpu), bit); logerror("%04x: freset %d\n",cpu_get_pc(space->cpu), bit);
namcoio_set_reset_line(0, bit ? CLEAR_LINE : ASSERT_LINE);
namcoio_set_reset_line(1, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(io58xx, bit ? CLEAR_LINE : ASSERT_LINE);
namcoio_set_reset_line(io56xx, bit ? CLEAR_LINE : ASSERT_LINE);
} }
static MACHINE_RESET( gaplus ) static MACHINE_RESET( gaplus )
@ -300,13 +232,36 @@ static MACHINE_RESET( gaplus )
cputag_set_input_line(machine, "sub", 0, CLEAR_LINE); cputag_set_input_line(machine, "sub", 0, CLEAR_LINE);
} }
static TIMER_CALLBACK( namcoio_run )
{
const device_config *io58xx = devtag_get_device(machine, "58xx");
const device_config *io56xx = devtag_get_device(machine, "56xx");
switch (param)
{
case 0:
namco_customio_58xx_run(io58xx);
break;
case 1:
namco_customio_56xx_run(io56xx);
break;
}
}
static INTERRUPT_GEN( gaplus_interrupt_1 ) static INTERRUPT_GEN( gaplus_interrupt_1 )
{ {
const device_config *io58xx = devtag_get_device(device->machine, "58xx");
const device_config *io56xx = devtag_get_device(device->machine, "56xx");
irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT! irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT!
// so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE); // so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
namcoio_set_irq_line(device->machine, 0, PULSE_LINE); if (!namcoio_read_reset_line(io58xx)) /* give the cpu a tiny bit of time to write the command before processing it */
namcoio_set_irq_line(device->machine, 1, PULSE_LINE); timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 0, namcoio_run);
if (!namcoio_read_reset_line(io56xx)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 1, namcoio_run);
} }
@ -315,8 +270,25 @@ static ADDRESS_MAP_START( cpu1_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0800, 0x1fff) AM_READWRITE(gaplus_spriteram_r, gaplus_spriteram_w) AM_BASE(&gaplus_spriteram) /* shared RAM with CPU #2 (includes sprite RAM) */ AM_RANGE(0x0800, 0x1fff) AM_READWRITE(gaplus_spriteram_r, gaplus_spriteram_w) AM_BASE(&gaplus_spriteram) /* shared RAM with CPU #2 (includes sprite RAM) */
AM_RANGE(0x6000, 0x63ff) AM_READ(gaplus_snd_sharedram_r) /* shared RAM with CPU #3 */ AM_RANGE(0x6000, 0x63ff) AM_READ(gaplus_snd_sharedram_r) /* shared RAM with CPU #3 */
AM_RANGE(0x6000, 0x63ff) AM_DEVWRITE("namco", gaplus_snd_sharedram_w) /* shared RAM with CPU #3 */ AM_RANGE(0x6000, 0x63ff) AM_DEVWRITE("namco", gaplus_snd_sharedram_w) /* shared RAM with CPU #3 */
AM_RANGE(0x6800, 0x680f) AM_DEVREADWRITE("56xx", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x6810, 0x681f) AM_DEVREADWRITE("58xx", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x6820, 0x682f) AM_READWRITE(gaplus_customio_3_r, gaplus_customio_3_w) AM_BASE(&gaplus_customio_3) /* custom I/O chip #3 interface */
AM_RANGE(0x7000, 0x7fff) AM_WRITE(gaplus_irq_1_ctrl_w) /* main CPU irq control */
AM_RANGE(0x7800, 0x7fff) AM_READ(watchdog_reset_r) /* watchdog */
AM_RANGE(0x8000, 0x8fff) AM_WRITE(gaplus_sreset_w) /* reset CPU #2 & #3, enable sound */
AM_RANGE(0x9000, 0x9fff) AM_WRITE(gaplus_freset_w) /* reset I/O chips */
AM_RANGE(0xa000, 0xa7ff) AM_WRITE(gaplus_starfield_control_w) /* starfield control */
AM_RANGE(0xa000, 0xffff) AM_ROM /* ROM */
ADDRESS_MAP_END
static ADDRESS_MAP_START( gaplusa_cpu1_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x07ff) AM_READWRITE(gaplus_videoram_r, gaplus_videoram_w) AM_BASE(&gaplus_videoram) /* tilemap RAM (shared with CPU #2) */
AM_RANGE(0x0800, 0x1fff) AM_READWRITE(gaplus_spriteram_r, gaplus_spriteram_w) AM_BASE(&gaplus_spriteram) /* shared RAM with CPU #2 (includes sprite RAM) */
AM_RANGE(0x6000, 0x63ff) AM_READ(gaplus_snd_sharedram_r) /* shared RAM with CPU #3 */
AM_RANGE(0x6000, 0x63ff) AM_DEVWRITE("namco", gaplus_snd_sharedram_w) /* shared RAM with CPU #3 */
AM_RANGE(0x6800, 0x680f) AM_DEVREADWRITE("58xx", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x6810, 0x681f) AM_DEVREADWRITE("56xx", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x6820, 0x682f) AM_READWRITE(gaplus_customio_3_r, gaplus_customio_3_w) AM_BASE(&gaplus_customio_3) /* custom I/O chip #3 interface */ AM_RANGE(0x6820, 0x682f) AM_READWRITE(gaplus_customio_3_r, gaplus_customio_3_w) AM_BASE(&gaplus_customio_3) /* custom I/O chip #3 interface */
AM_RANGE(0x6800, 0x6bff) AM_READWRITE(namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x7000, 0x7fff) AM_WRITE(gaplus_irq_1_ctrl_w) /* main CPU irq control */ AM_RANGE(0x7000, 0x7fff) AM_WRITE(gaplus_irq_1_ctrl_w) /* main CPU irq control */
AM_RANGE(0x7800, 0x7fff) AM_READ(watchdog_reset_r) /* watchdog */ AM_RANGE(0x7800, 0x7fff) AM_READ(watchdog_reset_r) /* watchdog */
AM_RANGE(0x8000, 0x8fff) AM_WRITE(gaplus_sreset_w) /* reset CPU #2 & #3, enable sound */ AM_RANGE(0x8000, 0x8fff) AM_WRITE(gaplus_sreset_w) /* reset CPU #2 & #3, enable sound */
@ -516,6 +488,60 @@ static const samples_interface gaplus_samples_interface =
/***************************************************************************
Custom I/O initialization
***************************************************************************/
static READ8_DEVICE_HANDLER( in0_l ) { return input_port_read(device->machine, "IN0"); } // P1 joystick
static READ8_DEVICE_HANDLER( in0_h ) { return input_port_read(device->machine, "IN0") >> 4; } // P2 joystick
static READ8_DEVICE_HANDLER( in1_l ) { return input_port_read(device->machine, "IN1"); } // fire and start buttons
static READ8_DEVICE_HANDLER( in1_h ) { return input_port_read(device->machine, "IN1") >> 4; } // coins
static READ8_DEVICE_HANDLER( dipA_l ) { return input_port_read(device->machine, "DSW0"); } // dips A
static READ8_DEVICE_HANDLER( dipA_h ) { return input_port_read(device->machine, "DSW0") >> 4; } // dips A
static READ8_DEVICE_HANDLER( dipB_l ) { return input_port_read(device->machine, "DSW1"); } // dips B
static READ8_DEVICE_HANDLER( dipB_h ) { return input_port_read(device->machine, "DSW1") >> 4; } // dips B
static WRITE8_DEVICE_HANDLER( out_lamps0 )
{
set_led_status(device->machine, 0, data & 1);
set_led_status(device->machine, 1, data & 2);
coin_lockout_global_w(device->machine, data & 4);
coin_counter_w(device->machine, 0, ~data & 8);
}
static WRITE8_DEVICE_HANDLER( out_lamps1 )
{
coin_counter_w(device->machine, 1, ~data & 1);
}
/* chip #0: player inputs, buttons, coins */
static const namcoio_interface intf0 =
{
{ DEVCB_HANDLER(in1_h), DEVCB_HANDLER(in0_l), DEVCB_HANDLER(in0_h), DEVCB_HANDLER(in1_l) }, /* port read handlers */
{ DEVCB_NULL, DEVCB_NULL }, /* port write handlers */
NULL /* device */
};
static const namcoio_interface intf0_lamps =
{
{ DEVCB_HANDLER(in1_h), DEVCB_HANDLER(in0_l), DEVCB_HANDLER(in0_h), DEVCB_HANDLER(in1_l) }, /* port read handlers */
{ DEVCB_HANDLER(out_lamps0), DEVCB_HANDLER(out_lamps1) }, /* port write handlers */
NULL /* device */
};
/* chip #1: dip switches */
static const namcoio_interface intf1 =
{
{ DEVCB_HANDLER(dipA_h), DEVCB_HANDLER(dipB_l), DEVCB_HANDLER(dipB_h), DEVCB_HANDLER(dipA_l) }, /* port read handlers */
{ DEVCB_NULL, DEVCB_NULL }, /* port write handlers */
NULL /* device */
};
/* TODO: chip #2: test/cocktail, optional buttons */
static MACHINE_DRIVER_START( gaplus ) static MACHINE_DRIVER_START( gaplus )
/* basic machine hardware */ /* basic machine hardware */
@ -534,6 +560,9 @@ static MACHINE_DRIVER_START( gaplus )
MDRV_QUANTUM_TIME(HZ(6000)) /* a high value to ensure proper synchronization of the CPUs */ MDRV_QUANTUM_TIME(HZ(6000)) /* a high value to ensure proper synchronization of the CPUs */
MDRV_MACHINE_RESET(gaplus) MDRV_MACHINE_RESET(gaplus)
MDRV_NAMCO56XX_ADD("56xx", intf0_lamps)
MDRV_NAMCO58XX_ADD("58xx", intf1)
/* video hardware */ /* video hardware */
MDRV_SCREEN_ADD("screen", RASTER) MDRV_SCREEN_ADD("screen", RASTER)
MDRV_SCREEN_REFRESH_RATE(60.606060) MDRV_SCREEN_REFRESH_RATE(60.606060)
@ -562,6 +591,30 @@ static MACHINE_DRIVER_START( gaplus )
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
MACHINE_DRIVER_END MACHINE_DRIVER_END
static MACHINE_DRIVER_START( gaplusa )
/* basic machine hardware */
MDRV_IMPORT_FROM(gaplus)
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_PROGRAM_MAP(gaplusa_cpu1_map)
MDRV_DEVICE_REMOVE("56xx")
MDRV_DEVICE_REMOVE("58xx")
MDRV_NAMCO56XX_ADD("56xx", intf1)
MDRV_NAMCO58XX_ADD("58xx", intf0)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( gapluso )
/* basic machine hardware */
MDRV_IMPORT_FROM(gaplus)
MDRV_DEVICE_REMOVE("56xx")
MDRV_DEVICE_REMOVE("58xx")
MDRV_NAMCO58XX_ADD("56xx", intf0)
MDRV_NAMCO56XX_ADD("58xx", intf1)
MACHINE_DRIVER_END
ROM_START( gaplus ) ROM_START( gaplus )
@ -802,7 +855,7 @@ ROM_START( galaga3m )
ROM_END ROM_END
static void unpack_gfx(running_machine *machine) static DRIVER_INIT( gaplus )
{ {
UINT8 *rom; UINT8 *rom;
int i; int i;
@ -817,9 +870,9 @@ static void unpack_gfx(running_machine *machine)
} }
GAME( 1984, gaplus, 0, gaplus, gaplus, 56_58l, ROT90, "Namco", "Gaplus (rev. D)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) GAME( 1984, gaplus, 0, gaplus, gaplus, gaplus, ROT90, "Namco", "Gaplus (rev. D)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAME( 1984, galaga3, gaplus, gaplus, gaplus, 56_58l, ROT90, "Namco", "Galaga 3 (rev. C)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) GAME( 1984, galaga3, gaplus, gaplus, gaplus, gaplus, ROT90, "Namco", "Galaga 3 (rev. C)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAME( 1984, gapluso, gaplus, gaplus, gapluso, 56_58, ROT90, "Namco", "Gaplus (rev. B)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) GAME( 1984, gapluso, gaplus, gapluso, gapluso, gaplus, ROT90, "Namco", "Gaplus (rev. B)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAME( 1984, gaplusa, gaplus, gaplus, gapluso, 58_56, ROT90, "Namco", "Gaplus (alternate hardware)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) GAME( 1984, gaplusa, gaplus, gaplusa, gapluso, gaplus, ROT90, "Namco", "Gaplus (alternate hardware)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAME( 1984, galaga3a, gaplus, gaplus, galaga3a, 56_58l, ROT90, "Namco", "Galaga 3 (set 2)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) GAME( 1984, galaga3a, gaplus, gaplus, galaga3a, gaplus, ROT90, "Namco", "Galaga 3 (set 2)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAME( 1984, galaga3m, gaplus, gaplus, galaga3m, 56_58l, ROT90, "Namco", "Galaga 3 (set 3)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) GAME( 1984, galaga3m, gaplus, gaplus, galaga3m, gaplus, ROT90, "Namco", "Galaga 3 (set 3)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )

438
src/mame/drivers/mappy.c
View File

@ -553,10 +553,6 @@ TODO:
#include "machine/namcoio.h" #include "machine/namcoio.h"
#include "includes/mappy.h" #include "includes/mappy.h"
/************************************* /*************************************
* *
* Constants * Constants
@ -578,108 +574,6 @@ TODO:
/***************************************************************************
Custom I/O initialization
***************************************************************************/
static READ8_HANDLER( in0_l ) { return input_port_read(space->machine, "IN0"); } // P1 joystick
static READ8_HANDLER( in0_h ) { return input_port_read(space->machine, "IN0") >> 4; } // P2 joystick
static READ8_HANDLER( in1_l ) { return input_port_read(space->machine, "IN1"); } // fire and start buttons
static READ8_HANDLER( in1_h ) { return input_port_read(space->machine, "IN1") >> 4; } // coins
static READ8_HANDLER( in2 ) { return input_port_read(space->machine, "DSW0"); } // test, cocktail, optional buttons
static READ8_HANDLER( dipA_l ) { return input_port_read(space->machine, "DSW1"); } // dips A
static READ8_HANDLER( dipA_h ) { return input_port_read(space->machine, "DSW1") >> 4; } // dips A
static READ8_HANDLER( dipB_mux ) // dips B
{
mappy_state *state = (mappy_state *)space->machine->driver_data;
return input_port_read(space->machine, "DSW2") >> (4*state->mux);
}
static READ8_HANDLER( dipB_muxi ) // dips B
{
mappy_state *state = (mappy_state *)space->machine->driver_data;
// bits are interleaved in Phozon
return BITSWAP8(input_port_read(space->machine, "DSW2"),6,4,2,0,7,5,3,1) >> (4*state->mux);
}
static WRITE8_HANDLER( out_mux )
{
mappy_state *state = (mappy_state *)space->machine->driver_data;
state->mux = data & 1;
}
static WRITE8_HANDLER( out_lamps )
{
set_led_status(space->machine, 0,data & 1);
set_led_status(space->machine, 1,data & 2);
coin_lockout_global_w(space->machine, data & 4);
coin_counter_w(space->machine, 0,~data & 8);
}
/* chip #0: player inputs, buttons, coins */
static const struct namcoio_interface intf0 =
{
{ in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
{ NULL, NULL } /* port write handlers */
};
static const struct namcoio_interface intf0_lamps =
{
{ in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
{ out_lamps, NULL } /* port write handlers */
};
/* chip #1: dip switches, test/cocktail, optional buttons */
static const struct namcoio_interface intf1 =
{
{ dipB_mux, dipA_l, dipA_h, in2 }, /* port read handlers */
{ out_mux, NULL } /* port write handlers */
};
static const struct namcoio_interface intf1_interleave =
{
{ dipB_muxi, dipA_l, dipA_h, in2 }, /* port read handlers */
{ out_mux, NULL } /* port write handlers */
};
static DRIVER_INIT( 56_56 )
{
namcoio_init(machine, 0, NAMCOIO_56XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1, NULL);
}
static DRIVER_INIT( 58_56i )
{
namcoio_init(machine, 0, NAMCOIO_58XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1_interleave, NULL);
}
static DRIVER_INIT( 56out_56 )
{
namcoio_init(machine, 0, NAMCOIO_56XX, &intf0_lamps, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1, NULL);
}
static DRIVER_INIT( 56out_59 )
{
namcoio_init(machine, 0, NAMCOIO_56XX, &intf0_lamps, NULL);
namcoio_init(machine, 1, NAMCOIO_59XX, &intf1, NULL);
}
static DRIVER_INIT( 58_58 )
{
namcoio_init(machine, 0, NAMCOIO_58XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_58XX, &intf1, NULL);
}
static DRIVER_INIT( 58_56 )
{
namcoio_init(machine, 0, NAMCOIO_58XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1, NULL);
}
/***************************************************************************/ /***************************************************************************/
@ -693,6 +587,8 @@ static WRITE8_DEVICE_HANDLER( mappy_snd_sharedram_w )
static WRITE8_HANDLER( superpac_latch_w ) static WRITE8_HANDLER( superpac_latch_w )
{ {
const device_config *namcoio_1 = devtag_get_device(space->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(space->machine, "namcoio_2");
int bit = offset & 1; int bit = offset & 1;
switch (offset & 0x0e) switch (offset & 0x0e)
@ -717,8 +613,8 @@ static WRITE8_HANDLER( superpac_latch_w )
break; break;
case 0x08: /* 4 RESET */ case 0x08: /* 4 RESET */
namcoio_set_reset_line(0, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(namcoio_1, bit ? CLEAR_LINE : ASSERT_LINE);
namcoio_set_reset_line(1, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(namcoio_2, bit ? CLEAR_LINE : ASSERT_LINE);
break; break;
case 0x0a: /* SUB RESET */ case 0x0a: /* SUB RESET */
@ -735,6 +631,8 @@ static WRITE8_HANDLER( superpac_latch_w )
static WRITE8_HANDLER( phozon_latch_w ) static WRITE8_HANDLER( phozon_latch_w )
{ {
const device_config *namcoio_1 = devtag_get_device(space->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(space->machine, "namcoio_2");
int bit = offset & 1; int bit = offset & 1;
switch (offset & 0x0e) switch (offset & 0x0e)
@ -762,8 +660,8 @@ static WRITE8_HANDLER( phozon_latch_w )
break; break;
case 0x08: case 0x08:
namcoio_set_reset_line(0, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(namcoio_1, bit ? CLEAR_LINE : ASSERT_LINE);
namcoio_set_reset_line(1, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(namcoio_2, bit ? CLEAR_LINE : ASSERT_LINE);
break; break;
case 0x0a: case 0x0a:
@ -781,6 +679,8 @@ static WRITE8_HANDLER( phozon_latch_w )
static WRITE8_HANDLER( mappy_latch_w ) static WRITE8_HANDLER( mappy_latch_w )
{ {
const device_config *namcoio_1 = devtag_get_device(space->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(space->machine, "namcoio_2");
int bit = offset & 1; int bit = offset & 1;
switch (offset & 0x0e) switch (offset & 0x0e)
@ -806,8 +706,8 @@ static WRITE8_HANDLER( mappy_latch_w )
break; break;
case 0x08: /* 4 RESET */ case 0x08: /* 4 RESET */
namcoio_set_reset_line(0, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(namcoio_1, bit ? CLEAR_LINE : ASSERT_LINE);
namcoio_set_reset_line(1, bit ? CLEAR_LINE : ASSERT_LINE); namcoio_set_reset_line(namcoio_2, bit ? CLEAR_LINE : ASSERT_LINE);
break; break;
case 0x0a: /* SUB RESET */ case 0x0a: /* SUB RESET */
@ -829,7 +729,7 @@ static MACHINE_RESET( superpac )
int i; int i;
/* Reset all latches */ /* Reset all latches */
for (i = 0;i < 0x10;i += 2) for (i = 0; i < 0x10; i += 2)
superpac_latch_w(space,i,0); superpac_latch_w(space,i,0);
} }
@ -839,8 +739,8 @@ static MACHINE_RESET( phozon )
int i; int i;
/* Reset all latches */ /* Reset all latches */
for (i = 0;i < 0x10;i += 2) for (i = 0; i < 0x10; i += 2)
phozon_latch_w(space,i,0); phozon_latch_w(space, i, 0);
} }
static MACHINE_RESET( mappy ) static MACHINE_RESET( mappy )
@ -849,27 +749,144 @@ static MACHINE_RESET( mappy )
int i; int i;
/* Reset all latches */ /* Reset all latches */
for (i = 0;i < 0x10;i += 2) for (i = 0; i < 0x10; i += 2)
mappy_latch_w(space,i,0); mappy_latch_w(space, i, 0);
}
/* different games need different interrupt generators & timers because they use different Namco I/O devices */
static TIMER_CALLBACK( superpac_io_run )
{
const device_config *io56xx_1 = devtag_get_device(machine, "namcoio_1");
const device_config *io56xx_2 = devtag_get_device(machine, "namcoio_2");
switch (param)
{
case 0:
namco_customio_56xx_run(io56xx_1);
break;
case 1:
namco_customio_56xx_run(io56xx_2);
break;
}
}
static INTERRUPT_GEN( superpac_interrupt_1 )
{
const device_config *namcoio_1 = devtag_get_device(device->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(device->machine, "namcoio_2");
irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT!
// so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
if (!namcoio_read_reset_line(namcoio_1)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 0, superpac_io_run);
if (!namcoio_read_reset_line(namcoio_2)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 1, superpac_io_run);
}
static TIMER_CALLBACK( pacnpal_io_run )
{
const device_config *io56xx = devtag_get_device(machine, "namcoio_1");
const device_config *io59xx = devtag_get_device(machine, "namcoio_2");
switch (param)
{
case 0:
namco_customio_56xx_run(io56xx);
break;
case 1:
namco_customio_59xx_run(io59xx);
break;
}
}
static INTERRUPT_GEN( pacnpal_interrupt_1 )
{
const device_config *namcoio_1 = devtag_get_device(device->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(device->machine, "namcoio_2");
irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT!
// so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
if (!namcoio_read_reset_line(namcoio_1)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 0, pacnpal_io_run);
if (!namcoio_read_reset_line(namcoio_2)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 1, pacnpal_io_run);
}
static TIMER_CALLBACK( phozon_io_run )
{
const device_config *io58xx = devtag_get_device(machine, "namcoio_1");
const device_config *io56xx = devtag_get_device(machine, "namcoio_2");
switch (param)
{
case 0:
namco_customio_58xx_run(io58xx);
break;
case 1:
namco_customio_56xx_run(io56xx);
break;
}
}
static INTERRUPT_GEN( phozon_interrupt_1 )
{
const device_config *namcoio_1 = devtag_get_device(device->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(device->machine, "namcoio_2");
irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT!
// so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
if (!namcoio_read_reset_line(namcoio_1)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 0, phozon_io_run);
if (!namcoio_read_reset_line(namcoio_2)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 1, phozon_io_run);
}
static TIMER_CALLBACK( mappy_io_run )
{
const device_config *io58xx_1 = devtag_get_device(machine, "namcoio_1");
const device_config *io58xx_2 = devtag_get_device(machine, "namcoio_2");
switch (param)
{
case 0:
namco_customio_58xx_run(io58xx_1);
break;
case 1:
namco_customio_58xx_run(io58xx_2);
break;
}
} }
static INTERRUPT_GEN( mappy_interrupt_1 ) static INTERRUPT_GEN( mappy_interrupt_1 )
{ {
const device_config *namcoio_1 = devtag_get_device(device->machine, "namcoio_1");
const device_config *namcoio_2 = devtag_get_device(device->machine, "namcoio_2");
irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT! irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT!
// so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE); // so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
namcoio_set_irq_line(device->machine, 0, PULSE_LINE); if (!namcoio_read_reset_line(namcoio_1)) /* give the cpu a tiny bit of time to write the command before processing it */
namcoio_set_irq_line(device->machine, 1, PULSE_LINE); timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 0, mappy_io_run);
if (!namcoio_read_reset_line(namcoio_2)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 1, mappy_io_run);
} }
static ADDRESS_MAP_START( superpac_cpu1_map, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( superpac_cpu1_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x07ff) AM_RAM_WRITE(superpac_videoram_w) AM_BASE_MEMBER(mappy_state,videoram) /* video RAM */ AM_RANGE(0x0000, 0x07ff) AM_RAM_WRITE(superpac_videoram_w) AM_BASE_MEMBER(mappy_state,videoram) /* video RAM */
AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(mappy_state,spriteram) /* work RAM with embedded sprite RAM */ AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(mappy_state,spriteram) /* work RAM with embedded sprite RAM */
AM_RANGE(0x2000, 0x2000) AM_READWRITE(superpac_flipscreen_r, superpac_flipscreen_w) AM_RANGE(0x2000, 0x2000) AM_READWRITE(superpac_flipscreen_r, superpac_flipscreen_w)
AM_RANGE(0x4000, 0x43ff) AM_RAM_DEVWRITE("namco", mappy_snd_sharedram_w) AM_SHARE("share1") /* shared RAM with the sound CPU */ AM_RANGE(0x4000, 0x43ff) AM_RAM_DEVWRITE("namco", mappy_snd_sharedram_w) AM_SHARE("share1") /* shared RAM with the sound CPU */
AM_RANGE(0x4800, 0x4bff) AM_READWRITE(namcoio_r, namcoio_w) /* custom I/O chips interface */ AM_RANGE(0x4800, 0x480f) AM_DEVREADWRITE("namcoio_1", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x4810, 0x481f) AM_DEVREADWRITE("namcoio_2", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x5000, 0x500f) AM_WRITE(superpac_latch_w) /* various control bits */ AM_RANGE(0x5000, 0x500f) AM_WRITE(superpac_latch_w) /* various control bits */
AM_RANGE(0x8000, 0x8000) AM_WRITE(watchdog_reset_w) AM_RANGE(0x8000, 0x8000) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xa000, 0xffff) AM_ROM AM_RANGE(0xa000, 0xffff) AM_ROM
@ -879,7 +896,8 @@ static ADDRESS_MAP_START( phozon_cpu1_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x07ff) AM_RAM_WRITE(superpac_videoram_w) AM_SHARE("share2") AM_BASE_MEMBER(mappy_state,videoram) /* video RAM */ AM_RANGE(0x0000, 0x07ff) AM_RAM_WRITE(superpac_videoram_w) AM_SHARE("share2") AM_BASE_MEMBER(mappy_state,videoram) /* video RAM */
AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(mappy_state,spriteram) AM_SHARE("share3") /* shared RAM with CPU #2/sprite RAM*/ AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(mappy_state,spriteram) AM_SHARE("share3") /* shared RAM with CPU #2/sprite RAM*/
AM_RANGE(0x4000, 0x43ff) AM_RAM_DEVWRITE("namco", mappy_snd_sharedram_w) AM_SHARE("share1") /* shared RAM with the sound CPU */ AM_RANGE(0x4000, 0x43ff) AM_RAM_DEVWRITE("namco", mappy_snd_sharedram_w) AM_SHARE("share1") /* shared RAM with the sound CPU */
AM_RANGE(0x4800, 0x4bff) AM_READWRITE(namcoio_r, namcoio_w) /* custom I/O chips interface */ AM_RANGE(0x4800, 0x480f) AM_DEVREADWRITE("namcoio_1", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x4810, 0x481f) AM_DEVREADWRITE("namcoio_2", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x5000, 0x500f) AM_WRITE(phozon_latch_w) /* various control bits */ AM_RANGE(0x5000, 0x500f) AM_WRITE(phozon_latch_w) /* various control bits */
AM_RANGE(0x7000, 0x7000) AM_WRITE(watchdog_reset_w) /* watchdog reset */ AM_RANGE(0x7000, 0x7000) AM_WRITE(watchdog_reset_w) /* watchdog reset */
AM_RANGE(0x8000, 0xffff) AM_ROM /* ROM */ AM_RANGE(0x8000, 0xffff) AM_ROM /* ROM */
@ -890,7 +908,8 @@ static ADDRESS_MAP_START( mappy_cpu1_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x1000, 0x27ff) AM_RAM AM_BASE_MEMBER(mappy_state,spriteram) /* work RAM with embedded sprite RAM */ AM_RANGE(0x1000, 0x27ff) AM_RAM AM_BASE_MEMBER(mappy_state,spriteram) /* work RAM with embedded sprite RAM */
AM_RANGE(0x3800, 0x3fff) AM_WRITE(mappy_scroll_w) /* scroll */ AM_RANGE(0x3800, 0x3fff) AM_WRITE(mappy_scroll_w) /* scroll */
AM_RANGE(0x4000, 0x43ff) AM_RAM_DEVWRITE("namco", mappy_snd_sharedram_w) AM_SHARE("share1") /* shared RAM with the sound CPU */ AM_RANGE(0x4000, 0x43ff) AM_RAM_DEVWRITE("namco", mappy_snd_sharedram_w) AM_SHARE("share1") /* shared RAM with the sound CPU */
AM_RANGE(0x4800, 0x4bff) AM_READWRITE(namcoio_r, namcoio_w) /* custom I/O chips interface */ AM_RANGE(0x4800, 0x480f) AM_DEVREADWRITE("namcoio_1", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x4810, 0x481f) AM_DEVREADWRITE("namcoio_2", namcoio_r, namcoio_w) /* custom I/O chips interface */
AM_RANGE(0x5000, 0x500f) AM_WRITE(mappy_latch_w) /* various control bits */ AM_RANGE(0x5000, 0x500f) AM_WRITE(mappy_latch_w) /* various control bits */
AM_RANGE(0x8000, 0x8000) AM_WRITE(watchdog_reset_w) /* watchdog reset */ AM_RANGE(0x8000, 0x8000) AM_WRITE(watchdog_reset_w) /* watchdog reset */
AM_RANGE(0x8000, 0xffff) AM_ROM /* ROM code (only a000-ffff in Mappy) */ AM_RANGE(0x8000, 0xffff) AM_ROM /* ROM code (only a000-ffff in Mappy) */
@ -1503,6 +1522,12 @@ GFXDECODE_END
/***************************************************************************
Sound interface
***************************************************************************/
static const namco_interface namco_config = static const namco_interface namco_config =
{ {
8, /* number of voices */ 8, /* number of voices */
@ -1510,6 +1535,80 @@ static const namco_interface namco_config =
}; };
/***************************************************************************
Custom I/O initialization
***************************************************************************/
static READ8_DEVICE_HANDLER( in0_l ) { return input_port_read(device->machine, "IN0"); } // P1 joystick
static READ8_DEVICE_HANDLER( in0_h ) { return input_port_read(device->machine, "IN0") >> 4; } // P2 joystick
static READ8_DEVICE_HANDLER( in1_l ) { return input_port_read(device->machine, "IN1"); } // fire and start buttons
static READ8_DEVICE_HANDLER( in1_h ) { return input_port_read(device->machine, "IN1") >> 4; } // coins
static READ8_DEVICE_HANDLER( in2 ) { return input_port_read(device->machine, "DSW0"); } // test, cocktail, optional buttons
static READ8_DEVICE_HANDLER( dipA_l ) { return input_port_read(device->machine, "DSW1"); } // dips A
static READ8_DEVICE_HANDLER( dipA_h ) { return input_port_read(device->machine, "DSW1") >> 4; } // dips A
static READ8_DEVICE_HANDLER( dipB_mux ) // dips B
{
mappy_state *state = (mappy_state *)device->machine->driver_data;
return input_port_read(device->machine, "DSW2") >> (4*state->mux);
}
static READ8_DEVICE_HANDLER( dipB_muxi ) // dips B
{
mappy_state *state = (mappy_state *)device->machine->driver_data;
// bits are interleaved in Phozon
return BITSWAP8(input_port_read(device->machine, "DSW2"),6,4,2,0,7,5,3,1) >> (4*state->mux);
}
static WRITE8_DEVICE_HANDLER( out_mux )
{
mappy_state *state = (mappy_state *)device->machine->driver_data;
state->mux = data & 1;
}
static WRITE8_DEVICE_HANDLER( out_lamps )
{
set_led_status(device->machine, 0, data & 1);
set_led_status(device->machine, 1, data & 2);
coin_lockout_global_w(device->machine, data & 4);
coin_counter_w(device->machine, 0, ~data & 8);
}
/* chip #0: player inputs, buttons, coins */
static const namcoio_interface intf0 =
{
{ DEVCB_HANDLER(in1_h), DEVCB_HANDLER(in0_l), DEVCB_HANDLER(in0_h), DEVCB_HANDLER(in1_l) }, /* port read handlers */
{ DEVCB_NULL, DEVCB_NULL }, /* port write handlers */
NULL
};
static const namcoio_interface intf0_lamps =
{
{ DEVCB_HANDLER(in1_h), DEVCB_HANDLER(in0_l), DEVCB_HANDLER(in0_h), DEVCB_HANDLER(in1_l) }, /* port read handlers */
{ DEVCB_HANDLER(out_lamps), DEVCB_NULL }, /* port write handlers */
NULL
};
/* chip #1: dip switches, test/cocktail, optional buttons */
static const namcoio_interface intf1 =
{
{ DEVCB_HANDLER(dipB_mux), DEVCB_HANDLER(dipA_l), DEVCB_HANDLER(dipA_h), DEVCB_HANDLER(in2) }, /* port read handlers */
{ DEVCB_HANDLER(out_mux), DEVCB_NULL }, /* port write handlers */
NULL
};
static const namcoio_interface intf1_interleave =
{
{ DEVCB_HANDLER(dipB_muxi), DEVCB_HANDLER(dipA_l), DEVCB_HANDLER(dipA_h), DEVCB_HANDLER(in2) }, /* port read handlers */
{ DEVCB_HANDLER(out_mux), DEVCB_NULL }, /* port write handlers */
NULL
};
static MACHINE_DRIVER_START( superpac ) static MACHINE_DRIVER_START( superpac )
@ -1518,7 +1617,7 @@ static MACHINE_DRIVER_START( superpac )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", M6809, PIXEL_CLOCK/4) /* 1.536 MHz */ MDRV_CPU_ADD("maincpu", M6809, PIXEL_CLOCK/4) /* 1.536 MHz */
MDRV_CPU_PROGRAM_MAP(superpac_cpu1_map) MDRV_CPU_PROGRAM_MAP(superpac_cpu1_map)
MDRV_CPU_VBLANK_INT("screen", mappy_interrupt_1) // also update the custom I/O chips MDRV_CPU_VBLANK_INT("screen", superpac_interrupt_1) // also update the custom I/O chips
MDRV_CPU_ADD("sub", M6809, PIXEL_CLOCK/4) /* 1.536 MHz */ MDRV_CPU_ADD("sub", M6809, PIXEL_CLOCK/4) /* 1.536 MHz */
MDRV_CPU_PROGRAM_MAP(superpac_cpu2_map) MDRV_CPU_PROGRAM_MAP(superpac_cpu2_map)
@ -1529,6 +1628,9 @@ static MACHINE_DRIVER_START( superpac )
/* synchronization of the CPUs */ /* synchronization of the CPUs */
MDRV_MACHINE_RESET(superpac) MDRV_MACHINE_RESET(superpac)
MDRV_NAMCO56XX_ADD("namcoio_1", intf0)
MDRV_NAMCO56XX_ADD("namcoio_2", intf1)
/* video hardware */ /* video hardware */
MDRV_GFXDECODE(superpac) MDRV_GFXDECODE(superpac)
MDRV_PALETTE_LENGTH(64*4+64*4) MDRV_PALETTE_LENGTH(64*4+64*4)
@ -1549,10 +1651,31 @@ static MACHINE_DRIVER_START( superpac )
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
MACHINE_DRIVER_END MACHINE_DRIVER_END
static MACHINE_DRIVER_START( pacnpal )
/* basic machine hardware */
MDRV_IMPORT_FROM( superpac )
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_VBLANK_INT("screen", pacnpal_interrupt_1) // also update the custom I/O chips
MDRV_DEVICE_REMOVE("namcoio_1")
MDRV_DEVICE_REMOVE("namcoio_2")
MDRV_NAMCO56XX_ADD("namcoio_1", intf0_lamps)
MDRV_NAMCO59XX_ADD("namcoio_2", intf1)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( grobda ) static MACHINE_DRIVER_START( grobda )
/* basic machine hardware */ /* basic machine hardware */
MDRV_IMPORT_FROM( superpac ) MDRV_IMPORT_FROM( superpac )
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_VBLANK_INT("screen", phozon_interrupt_1) // also update the custom I/O chips
MDRV_DEVICE_REMOVE("namcoio_1")
MDRV_DEVICE_REMOVE("namcoio_2")
MDRV_NAMCO58XX_ADD("namcoio_1", intf0)
MDRV_NAMCO56XX_ADD("namcoio_2", intf1)
/* sound hardware */ /* sound hardware */
MDRV_SOUND_ADD("dac", DAC, 0) MDRV_SOUND_ADD("dac", DAC, 0)
@ -1567,7 +1690,7 @@ static MACHINE_DRIVER_START( phozon )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", M6809, PIXEL_CLOCK/4) /* MAIN CPU */ MDRV_CPU_ADD("maincpu", M6809, PIXEL_CLOCK/4) /* MAIN CPU */
MDRV_CPU_PROGRAM_MAP(phozon_cpu1_map) MDRV_CPU_PROGRAM_MAP(phozon_cpu1_map)
MDRV_CPU_VBLANK_INT("screen", mappy_interrupt_1) // also update the custom I/O chips MDRV_CPU_VBLANK_INT("screen", phozon_interrupt_1) // also update the custom I/O chips
MDRV_CPU_ADD("sub", M6809, PIXEL_CLOCK/4) /* SOUND CPU */ MDRV_CPU_ADD("sub", M6809, PIXEL_CLOCK/4) /* SOUND CPU */
MDRV_CPU_PROGRAM_MAP(phozon_cpu2_map) MDRV_CPU_PROGRAM_MAP(phozon_cpu2_map)
@ -1582,6 +1705,9 @@ static MACHINE_DRIVER_START( phozon )
/* synchronization of the CPUs */ /* synchronization of the CPUs */
MDRV_MACHINE_RESET(phozon) MDRV_MACHINE_RESET(phozon)
MDRV_NAMCO58XX_ADD("namcoio_1", intf0)
MDRV_NAMCO56XX_ADD("namcoio_2", intf1_interleave)
/* video hardware */ /* video hardware */
MDRV_GFXDECODE(phozon) MDRV_GFXDECODE(phozon)
MDRV_PALETTE_LENGTH(64*4+64*4) MDRV_PALETTE_LENGTH(64*4+64*4)
@ -1621,6 +1747,9 @@ static MACHINE_DRIVER_START( mappy )
/* synchronization of the CPUs */ /* synchronization of the CPUs */
MDRV_MACHINE_RESET(mappy) MDRV_MACHINE_RESET(mappy)
MDRV_NAMCO58XX_ADD("namcoio_1", intf0)
MDRV_NAMCO58XX_ADD("namcoio_2", intf1)
/* video hardware */ /* video hardware */
MDRV_GFXDECODE(mappy) MDRV_GFXDECODE(mappy)
MDRV_PALETTE_LENGTH(64*4+16*16) MDRV_PALETTE_LENGTH(64*4+16*16)
@ -1645,19 +1774,47 @@ static MACHINE_DRIVER_START( digdug2 )
/* basic machine hardware */ /* basic machine hardware */
MDRV_IMPORT_FROM( mappy ) MDRV_IMPORT_FROM( mappy )
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_VBLANK_INT("screen", phozon_interrupt_1) // also update the custom I/O chips
MDRV_WATCHDOG_VBLANK_INIT(0) MDRV_WATCHDOG_VBLANK_INIT(0)
MDRV_DEVICE_REMOVE("namcoio_1")
MDRV_DEVICE_REMOVE("namcoio_2")
MDRV_NAMCO58XX_ADD("namcoio_1", intf0)
MDRV_NAMCO56XX_ADD("namcoio_2", intf1)
MACHINE_DRIVER_END MACHINE_DRIVER_END
static MACHINE_DRIVER_START( todruaga ) static MACHINE_DRIVER_START( todruaga )
/* basic machine hardware */ /* basic machine hardware */
MDRV_IMPORT_FROM( mappy ) MDRV_IMPORT_FROM( mappy )
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_VBLANK_INT("screen", phozon_interrupt_1) // also update the custom I/O chips
MDRV_DEVICE_REMOVE("namcoio_1")
MDRV_DEVICE_REMOVE("namcoio_2")
MDRV_NAMCO58XX_ADD("namcoio_1", intf0)
MDRV_NAMCO56XX_ADD("namcoio_2", intf1)
/* video hardware */ /* video hardware */
MDRV_GFXDECODE(todruaga) MDRV_GFXDECODE(todruaga)
MDRV_PALETTE_LENGTH(64*4+64*16) MDRV_PALETTE_LENGTH(64*4+64*16)
MACHINE_DRIVER_END MACHINE_DRIVER_END
static MACHINE_DRIVER_START( motos )
/* basic machine hardware */
MDRV_IMPORT_FROM( mappy )
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_VBLANK_INT("screen", superpac_interrupt_1) // also update the custom I/O chips
MDRV_DEVICE_REMOVE("namcoio_1")
MDRV_DEVICE_REMOVE("namcoio_2")
MDRV_NAMCO56XX_ADD("namcoio_1", intf0_lamps)
MDRV_NAMCO56XX_ADD("namcoio_2", intf1)
MACHINE_DRIVER_END
ROM_START( superpac ) ROM_START( superpac )
@ -2101,39 +2258,36 @@ static DRIVER_INIT( grobda )
However, removing the 15XX from the board causes sound to disappear completely, so However, removing the 15XX from the board causes sound to disappear completely, so
the DAC might be built-in after all. the DAC might be built-in after all.
*/ */
const device_config *dac = devtag_get_device(machine, "dac"); const device_config *dac = devtag_get_device(machine, "dac");
memory_install_write8_device_handler(cputag_get_address_space(machine, "sub", ADDRESS_SPACE_PROGRAM), dac, 0x0002, 0x0002, 0, 0, grobda_DAC_w ); memory_install_write8_device_handler(cputag_get_address_space(machine, "sub", ADDRESS_SPACE_PROGRAM), dac, 0x0002, 0x0002, 0, 0, grobda_DAC_w );
DRIVER_INIT_CALL(58_56);
} }
static DRIVER_INIT( digdug2 ) static DRIVER_INIT( digdug2 )
{ {
/* appears to not use the watchdog */ /* appears to not use the watchdog */
memory_nop_write(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0x8000, 0, 0); memory_nop_write(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0x8000, 0, 0);
DRIVER_INIT_CALL(58_56);
} }
/* 2x6809, static tilemap, 2bpp sprites (Super Pacman type) */ /* 2x6809, static tilemap, 2bpp sprites (Super Pacman type) */
GAME( 1982, superpac, 0, superpac, superpac, 56_56, ROT90, "Namco", "Super Pac-Man", GAME_SUPPORTS_SAVE ) GAME( 1982, superpac, 0, superpac, superpac, 0, ROT90, "Namco", "Super Pac-Man", GAME_SUPPORTS_SAVE )
GAME( 1982, superpacm,superpac, superpac, superpac, 56_56, ROT90, "[Namco] (Bally Midway license)", "Super Pac-Man (Midway)", GAME_SUPPORTS_SAVE ) GAME( 1982, superpacm,superpac, superpac, superpac, 0, ROT90, "[Namco] (Bally Midway license)", "Super Pac-Man (Midway)", GAME_SUPPORTS_SAVE )
GAME( 1983, pacnpal, 0, superpac, pacnpal, 56out_59, ROT90, "Namco", "Pac & Pal", GAME_SUPPORTS_SAVE ) GAME( 1983, pacnpal, 0, pacnpal, pacnpal, 0, ROT90, "Namco", "Pac & Pal", GAME_SUPPORTS_SAVE )
GAME( 1983, pacnpal2, pacnpal, superpac, pacnpal, 56out_59, ROT90, "Namco", "Pac & Pal (older)", GAME_SUPPORTS_SAVE ) GAME( 1983, pacnpal2, pacnpal, pacnpal, pacnpal, 0, ROT90, "Namco", "Pac & Pal (older)", GAME_SUPPORTS_SAVE )
GAME( 1983, pacnchmp, pacnpal, superpac, pacnpal, 56out_59, ROT90, "Namco", "Pac-Man & Chomp Chomp", GAME_SUPPORTS_SAVE ) GAME( 1983, pacnchmp, pacnpal, pacnpal, pacnpal, 0, ROT90, "Namco", "Pac-Man & Chomp Chomp", GAME_SUPPORTS_SAVE )
GAME( 1984, grobda, 0, grobda, grobda, grobda, ROT90, "Namco", "Grobda (New Ver.)", GAME_SUPPORTS_SAVE ) GAME( 1984, grobda, 0, grobda, grobda, grobda, ROT90, "Namco", "Grobda (New Ver.)", GAME_SUPPORTS_SAVE )
GAME( 1984, grobda2, grobda, grobda, grobda, grobda, ROT90, "Namco", "Grobda (Old Ver. set 1)", GAME_SUPPORTS_SAVE ) GAME( 1984, grobda2, grobda, grobda, grobda, grobda, ROT90, "Namco", "Grobda (Old Ver. set 1)", GAME_SUPPORTS_SAVE )
GAME( 1984, grobda3, grobda, grobda, grobda, grobda, ROT90, "Namco", "Grobda (Old Ver. set 2)", GAME_SUPPORTS_SAVE ) GAME( 1984, grobda3, grobda, grobda, grobda, grobda, ROT90, "Namco", "Grobda (Old Ver. set 2)", GAME_SUPPORTS_SAVE )
/* 3x6809, static tilemap, 2bpp sprites (Gaplus type) */ /* 3x6809, static tilemap, 2bpp sprites (Gaplus type) */
GAME( 1983, phozon, 0, phozon, phozon, 58_56i, ROT90, "Namco", "Phozon (Japan)", GAME_SUPPORTS_SAVE ) GAME( 1983, phozon, 0, phozon, phozon, 0, ROT90, "Namco", "Phozon (Japan)", GAME_SUPPORTS_SAVE )
/* 2x6809, scroling tilemap, 4bpp sprites (Super Pacman type) */ /* 2x6809, scroling tilemap, 4bpp sprites (Super Pacman type) */
GAME( 1983, mappy, 0, mappy, mappy, 58_58, ROT90, "Namco", "Mappy (US)", GAME_SUPPORTS_SAVE ) GAME( 1983, mappy, 0, mappy, mappy, 0, ROT90, "Namco", "Mappy (US)", GAME_SUPPORTS_SAVE )
GAME( 1983, mappyj, mappy, mappy, mappy, 58_58, ROT90, "Namco", "Mappy (Japan)", GAME_SUPPORTS_SAVE ) GAME( 1983, mappyj, mappy, mappy, mappy, 0, ROT90, "Namco", "Mappy (Japan)", GAME_SUPPORTS_SAVE )
GAME( 1984, todruaga, 0, todruaga, todruaga, 58_56, ROT90, "Namco", "Tower of Druaga (New Ver.)", GAME_SUPPORTS_SAVE ) GAME( 1984, todruaga, 0, todruaga, todruaga, 0, ROT90, "Namco", "Tower of Druaga (New Ver.)", GAME_SUPPORTS_SAVE )
GAME( 1984, todruagao,todruaga, todruaga, todruaga, 58_56, ROT90, "Namco", "Tower of Druaga (Old Ver.)", GAME_SUPPORTS_SAVE ) GAME( 1984, todruagao,todruaga, todruaga, todruaga, 0, ROT90, "Namco", "Tower of Druaga (Old Ver.)", GAME_SUPPORTS_SAVE )
GAME( 1984, todruagas,todruaga, todruaga, todruaga, 58_56, ROT90, "Namco", "Tower of Druaga (Manufactured by Sidam)", GAME_SUPPORTS_SAVE ) GAME( 1984, todruagas,todruaga, todruaga, todruaga, 0, ROT90, "Namco", "Tower of Druaga (Manufactured by Sidam)", GAME_SUPPORTS_SAVE )
GAME( 1985, digdug2, 0, digdug2, digdug2, digdug2, ROT90, "Namco", "Dig Dug II (New Ver.)", GAME_SUPPORTS_SAVE ) GAME( 1985, digdug2, 0, digdug2, digdug2, digdug2, ROT90, "Namco", "Dig Dug II (New Ver.)", GAME_SUPPORTS_SAVE )
GAME( 1985, digdug2o, digdug2, digdug2, digdug2, digdug2, ROT90, "Namco", "Dig Dug II (Old Ver.)", GAME_SUPPORTS_SAVE ) GAME( 1985, digdug2o, digdug2, digdug2, digdug2, digdug2, ROT90, "Namco", "Dig Dug II (Old Ver.)", GAME_SUPPORTS_SAVE )
GAME( 1985, motos, 0, mappy, motos, 56out_56, ROT90, "Namco", "Motos", GAME_SUPPORTS_SAVE ) GAME( 1985, motos, 0, motos, motos, 0, ROT90, "Namco", "Motos", GAME_SUPPORTS_SAVE )

194
src/mame/drivers/toypop.c
View File

@ -37,81 +37,6 @@ TODO:
#include "includes/toypop.h" #include "includes/toypop.h"
/***************************************************************************
Custom I/O initialization
***************************************************************************/
static READ8_HANDLER( in0_l ) { return input_port_read(space->machine, "INPUT_RIGHT"); } // P1 joystick
static READ8_HANDLER( in0_h ) { return input_port_read(space->machine, "INPUT_RIGHT") >> 4; } // P2 joystick
static READ8_HANDLER( in1_l ) { return input_port_read(space->machine, "SYSTEM"); } // fire and start buttons
static READ8_HANDLER( in1_h ) { return input_port_read(space->machine, "SYSTEM") >> 4; } // coins
static READ8_HANDLER( dipA_l ) { return input_port_read(space->machine, "DSW1"); } // dips A
static READ8_HANDLER( dipA_h ) { return input_port_read(space->machine, "DSW1") >> 4; } // dips A
static READ8_HANDLER( dipB_l ) { return input_port_read(space->machine, "DSW2"); } // dips B
static READ8_HANDLER( dipB_h ) { return input_port_read(space->machine, "DSW2") >> 4; } // dips B
static READ8_HANDLER( in2_l ) { return input_port_read(space->machine, "INPUT_LEFT"); } // P1 joystick left in liblrabl
static READ8_HANDLER( in2_h ) { return input_port_read(space->machine, "INPUT_LEFT") >> 4; } // P2 joystick left in liblrabl
static READ8_HANDLER( in3 ) { return input_port_read(space->machine, "SERVICE"); } // test, cocktail, optional buttons
static WRITE8_HANDLER( out_coin0 )
{
coin_lockout_global_w(space->machine, data & 4);
coin_counter_w(space->machine, 0,~data & 8);
}
static WRITE8_HANDLER( out_coin1 )
{
coin_counter_w(space->machine, 1,~data & 1);
}
static WRITE8_HANDLER( flip )
{
flip_screen_set(space->machine, data & 1);
}
/* chip #0: player inputs, buttons, coins */
static const struct namcoio_interface intf0_coin =
{
{ in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
{ out_coin0, out_coin1 } /* port write handlers */
};
static const struct namcoio_interface intf0 =
{
{ in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
{ NULL, NULL } /* port write handlers */
};
/* chip #1: dip switches */
static const struct namcoio_interface intf1 =
{
{ dipA_h, dipB_l, dipB_h, dipA_l }, /* port read handlers */
{ flip, NULL } /* port write handlers */
};
/* chip #2: test/cocktail, optional buttons */
static const struct namcoio_interface intf2 =
{
{ NULL, in2_l, in2_h, in3 }, /* port read handlers */
{ NULL, NULL } /* port write handlers */
};
static DRIVER_INIT( 58c_56_56 )
{
namcoio_init(machine, 0, NAMCOIO_58XX, &intf0_coin, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1, NULL);
namcoio_init(machine, 2, NAMCOIO_56XX, &intf2, NULL);
}
static DRIVER_INIT( 58_56_56 )
{
namcoio_init(machine, 0, NAMCOIO_58XX, &intf0, NULL);
namcoio_init(machine, 1, NAMCOIO_56XX, &intf1, NULL);
namcoio_init(machine, 2, NAMCOIO_56XX, &intf2, NULL);
}
/***************************************************************************/
static READ8_DEVICE_HANDLER( toypop_sound_sharedram_r ) static READ8_DEVICE_HANDLER( toypop_sound_sharedram_r )
{ {
return namco_soundregs[offset]; return namco_soundregs[offset];
@ -168,14 +93,44 @@ static WRITE8_HANDLER( toypop_sound_interrupt_disable_w )
cpu_interrupt_enable(cputag_get_cpu(space->machine, "audiocpu"), 0); cpu_interrupt_enable(cputag_get_cpu(space->machine, "audiocpu"), 0);
} }
static TIMER_CALLBACK( namcoio_run )
{
const device_config *io58xx = devtag_get_device(machine, "58xx");
const device_config *io56xx_1 = devtag_get_device(machine, "56xx_1");
const device_config *io56xx_2 = devtag_get_device(machine, "56xx_2");
switch (param)
{
case 0:
namco_customio_58xx_run(io58xx);
break;
case 1:
namco_customio_56xx_run(io56xx_1);
break;
case 2:
namco_customio_56xx_run(io56xx_2);
break;
}
}
static INTERRUPT_GEN( toypop_main_interrupt ) static INTERRUPT_GEN( toypop_main_interrupt )
{ {
const device_config *namcoio_0 = devtag_get_device(device->machine, "58xx");
const device_config *namcoio_1 = devtag_get_device(device->machine, "56xx_1");
const device_config *namcoio_2 = devtag_get_device(device->machine, "56xx_2");
irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT! irq0_line_assert(device); // this also checks if irq is enabled - IMPORTANT!
// so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE); // so don't replace with cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
namcoio_set_irq_line(device->machine, 0, PULSE_LINE); if (!namcoio_read_reset_line(namcoio_0)) /* give the cpu a tiny bit of time to write the command before processing it */
namcoio_set_irq_line(device->machine, 1, PULSE_LINE); timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 0, namcoio_run);
namcoio_set_irq_line(device->machine, 2, PULSE_LINE);
if (!namcoio_read_reset_line(namcoio_1)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 1, namcoio_run);
if (!namcoio_read_reset_line(namcoio_2)) /* give the cpu a tiny bit of time to write the command before processing it */
timer_set(device->machine, ATTOTIME_IN_USEC(50), NULL, 2, namcoio_run);
} }
static WRITE8_HANDLER( toypop_sound_clear_w ) static WRITE8_HANDLER( toypop_sound_clear_w )
@ -247,7 +202,9 @@ static ADDRESS_MAP_START( liblrabl_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(toypop_state,spriteram) /* general RAM, area 1 */ AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(toypop_state,spriteram) /* general RAM, area 1 */
AM_RANGE(0x2800, 0x2fff) AM_RAM AM_BASE_MEMBER(toypop_state,m68000_sharedram) /* shared RAM with the 68000 CPU */ AM_RANGE(0x2800, 0x2fff) AM_RAM AM_BASE_MEMBER(toypop_state,m68000_sharedram) /* shared RAM with the 68000 CPU */
AM_RANGE(0x6000, 0x63ff) AM_DEVREADWRITE("namco", toypop_sound_sharedram_r, toypop_sound_sharedram_w) /* shared RAM with sound CPU */ AM_RANGE(0x6000, 0x63ff) AM_DEVREADWRITE("namco", toypop_sound_sharedram_r, toypop_sound_sharedram_w) /* shared RAM with sound CPU */
AM_RANGE(0x6800, 0x683f) AM_READWRITE(namcoio_r, namcoio_w) /* custom I/O */ AM_RANGE(0x6800, 0x680f) AM_DEVREADWRITE("58xx", namcoio_r, namcoio_w) /* custom I/O */
AM_RANGE(0x6810, 0x681f) AM_DEVREADWRITE("56xx_1", namcoio_r, namcoio_w) /* custom I/O */
AM_RANGE(0x6820, 0x682f) AM_DEVREADWRITE("56xx_2", namcoio_r, namcoio_w) /* custom I/O */
AM_RANGE(0x7000, 0x7000) AM_WRITE(toypop_main_interrupt_enable_w) /* enable interrupt */ AM_RANGE(0x7000, 0x7000) AM_WRITE(toypop_main_interrupt_enable_w) /* enable interrupt */
AM_RANGE(0x7800, 0x7800) AM_READWRITE(watchdog_reset_r, toypop_main_interrupt_disable_w) /* disable interrupt */ AM_RANGE(0x7800, 0x7800) AM_READWRITE(watchdog_reset_r, toypop_main_interrupt_disable_w) /* disable interrupt */
AM_RANGE(0x8000, 0x8000) AM_WRITE(toypop_m68000_clear_w) /* reset 68000 */ AM_RANGE(0x8000, 0x8000) AM_WRITE(toypop_m68000_clear_w) /* reset 68000 */
@ -262,7 +219,9 @@ static ADDRESS_MAP_START( toypop_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x07ff) AM_RAM_WRITE(toypop_videoram_w) AM_BASE_MEMBER(toypop_state,videoram) /* video RAM */ AM_RANGE(0x0000, 0x07ff) AM_RAM_WRITE(toypop_videoram_w) AM_BASE_MEMBER(toypop_state,videoram) /* video RAM */
AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(toypop_state,spriteram) /* general RAM, area 1 */ AM_RANGE(0x0800, 0x1fff) AM_RAM AM_BASE_MEMBER(toypop_state,spriteram) /* general RAM, area 1 */
AM_RANGE(0x2800, 0x2fff) AM_RAM AM_BASE_MEMBER(toypop_state,m68000_sharedram) /* shared RAM with the 68000 CPU */ AM_RANGE(0x2800, 0x2fff) AM_RAM AM_BASE_MEMBER(toypop_state,m68000_sharedram) /* shared RAM with the 68000 CPU */
AM_RANGE(0x6000, 0x603f) AM_READWRITE(namcoio_r, namcoio_w) /* custom I/O */ AM_RANGE(0x6000, 0x600f) AM_DEVREADWRITE("58xx", namcoio_r, namcoio_w) /* custom I/O */
AM_RANGE(0x6010, 0x601f) AM_DEVREADWRITE("56xx_1", namcoio_r, namcoio_w) /* custom I/O */
AM_RANGE(0x6020, 0x602f) AM_DEVREADWRITE("56xx_2", namcoio_r, namcoio_w) /* custom I/O */
AM_RANGE(0x6800, 0x6bff) AM_DEVREADWRITE("namco", toypop_sound_sharedram_r, toypop_sound_sharedram_w) /* shared RAM with sound CPU */ AM_RANGE(0x6800, 0x6bff) AM_DEVREADWRITE("namco", toypop_sound_sharedram_r, toypop_sound_sharedram_w) /* shared RAM with sound CPU */
AM_RANGE(0x7000, 0x7000) AM_READWRITE(toypop_main_interrupt_enable_r, toypop_main_interrupt_disable_w) /* disable interrupt */ AM_RANGE(0x7000, 0x7000) AM_READWRITE(toypop_main_interrupt_enable_r, toypop_main_interrupt_disable_w) /* disable interrupt */
AM_RANGE(0x8000, 0x8000) AM_WRITE(toypop_m68000_clear_w) /* reset 68000 */ AM_RANGE(0x8000, 0x8000) AM_WRITE(toypop_m68000_clear_w) /* reset 68000 */
@ -527,6 +486,70 @@ static const namco_interface namco_config =
}; };
/***************************************************************************
Custom I/O initialization
***************************************************************************/
static READ8_DEVICE_HANDLER( in0_l ) { return input_port_read(device->machine, "INPUT_RIGHT"); } // P1 joystick
static READ8_DEVICE_HANDLER( in0_h ) { return input_port_read(device->machine, "INPUT_RIGHT") >> 4; } // P2 joystick
static READ8_DEVICE_HANDLER( in1_l ) { return input_port_read(device->machine, "SYSTEM"); } // fire and start buttons
static READ8_DEVICE_HANDLER( in1_h ) { return input_port_read(device->machine, "SYSTEM") >> 4; } // coins
static READ8_DEVICE_HANDLER( dipA_l ) { return input_port_read(device->machine, "DSW1"); } // dips A
static READ8_DEVICE_HANDLER( dipA_h ) { return input_port_read(device->machine, "DSW1") >> 4; } // dips A
static READ8_DEVICE_HANDLER( dipB_l ) { return input_port_read(device->machine, "DSW2"); } // dips B
static READ8_DEVICE_HANDLER( dipB_h ) { return input_port_read(device->machine, "DSW2") >> 4; } // dips B
static READ8_DEVICE_HANDLER( in2_l ) { return input_port_read(device->machine, "INPUT_LEFT"); } // P1 joystick left in liblrabl
static READ8_DEVICE_HANDLER( in2_h ) { return input_port_read(device->machine, "INPUT_LEFT") >> 4; } // P2 joystick left in liblrabl
static READ8_DEVICE_HANDLER( in3 ) { return input_port_read(device->machine, "SERVICE"); } // test, cocktail, optional buttons
static WRITE8_DEVICE_HANDLER( out_coin0 )
{
coin_lockout_global_w(device->machine, data & 4);
coin_counter_w(device->machine, 0, ~data & 8);
}
static WRITE8_DEVICE_HANDLER( out_coin1 )
{
coin_counter_w(device->machine, 1, ~data & 1);
}
static WRITE8_DEVICE_HANDLER( flip )
{
flip_screen_set(device->machine, data & 1);
}
/* chip #0: player inputs, buttons, coins */
static const namcoio_interface intf0_coin =
{
{ DEVCB_HANDLER(in1_h), DEVCB_HANDLER(in0_l), DEVCB_HANDLER(in0_h), DEVCB_HANDLER(in1_l) }, /* port read handlers */
{ DEVCB_HANDLER(out_coin0), DEVCB_HANDLER(out_coin1) }, /* port write handlers */
NULL /* device */
};
static const namcoio_interface intf0 =
{
{ DEVCB_HANDLER(in1_h), DEVCB_HANDLER(in0_l), DEVCB_HANDLER(in0_h), DEVCB_HANDLER(in1_l) }, /* port read handlers */
{ DEVCB_NULL, DEVCB_NULL }, /* port write handlers */
NULL /* device */
};
/* chip #1: dip switches */
static const namcoio_interface intf1 =
{
{ DEVCB_HANDLER(dipA_h), DEVCB_HANDLER(dipB_l), DEVCB_HANDLER(dipB_h), DEVCB_HANDLER(dipA_l) }, /* port read handlers */
{ DEVCB_HANDLER(flip), DEVCB_NULL }, /* port write handlers */
NULL /* device */
};
/* chip #2: test/cocktail, optional buttons */
static const namcoio_interface intf2 =
{
{ DEVCB_NULL, DEVCB_HANDLER(in2_l), DEVCB_HANDLER(in2_h), DEVCB_HANDLER(in3) }, /* port read handlers */
{ DEVCB_NULL, DEVCB_NULL }, /* port write handlers */
NULL /* device */
};
static MACHINE_DRIVER_START( liblrabl ) static MACHINE_DRIVER_START( liblrabl )
@ -549,6 +572,10 @@ static MACHINE_DRIVER_START( liblrabl )
/* synchronization of the CPUs */ /* synchronization of the CPUs */
MDRV_MACHINE_RESET(toypop) MDRV_MACHINE_RESET(toypop)
MDRV_NAMCO58XX_ADD("58xx", intf0)
MDRV_NAMCO56XX_ADD("56xx_1", intf1)
MDRV_NAMCO56XX_ADD("56xx_2", intf2)
/* video hardware */ /* video hardware */
MDRV_SCREEN_ADD("screen", RASTER) MDRV_SCREEN_ADD("screen", RASTER)
MDRV_SCREEN_REFRESH_RATE(60.606060) MDRV_SCREEN_REFRESH_RATE(60.606060)
@ -578,6 +605,9 @@ static MACHINE_DRIVER_START( toypop )
MDRV_IMPORT_FROM(liblrabl) MDRV_IMPORT_FROM(liblrabl)
MDRV_CPU_MODIFY("maincpu") MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_PROGRAM_MAP(toypop_map) MDRV_CPU_PROGRAM_MAP(toypop_map)
MDRV_DEVICE_REMOVE("58xx")
MDRV_NAMCO58XX_ADD("58xx", intf0_coin)
MACHINE_DRIVER_END MACHINE_DRIVER_END
@ -650,5 +680,5 @@ ROM_END
GAME( 1983, liblrabl, 0, liblrabl, liblrabl, 58_56_56, ROT0, "Namco", "Libble Rabble", 0 ) GAME( 1983, liblrabl, 0, liblrabl, liblrabl, 0, ROT0, "Namco", "Libble Rabble", 0 )
GAME( 1986, toypop, 0, toypop, toypop, 58c_56_56, ROT0, "Namco", "Toypop", 0 ) GAME( 1986, toypop, 0, toypop, toypop, 0, ROT0, "Namco", "Toypop", 0 )

4
src/mame/machine/gaplus.c
View File

@ -8,7 +8,6 @@
***************************************************************************/ ***************************************************************************/
#include "driver.h" #include "driver.h"
#include "machine/namcoio.h"
#include "sound/samples.h" #include "sound/samples.h"
#include "includes/gaplus.h" #include "includes/gaplus.h"
@ -25,7 +24,8 @@ WRITE8_HANDLER( gaplus_customio_3_w )
const device_config *samples = devtag_get_device(space->machine, "samples"); const device_config *samples = devtag_get_device(space->machine, "samples");
if ((offset == 0x09) && (data >= 0x0f)) if ((offset == 0x09) && (data >= 0x0f))
sample_start(samples,0,0,0); sample_start(samples,0,0,0);
gaplus_customio_3[offset] = data;
gaplus_customio_3[offset] = data;
} }

399
src/mame/machine/namcoio.c
View File

@ -110,85 +110,97 @@ TODO:
#include "driver.h" #include "driver.h"
#include "machine/namcoio.h" #include "machine/namcoio.h"
#include "machine/namco50.h"
#include "machine/namco51.h"
#include "machine/namco53.h"
#include "audio/namco52.h"
#include "audio/namco54.h"
#define VERBOSE 0 #define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0) #define LOG(x) do { if (VERBOSE) logerror x; } while (0)
struct namcoio
typedef struct _namcoio_state namcoio_state;
struct _namcoio_state
{ {
INT32 type; UINT8 ram[16];
devcb_resolved_read8 in[4];
devcb_resolved_write8 out[2];
int reset;
INT32 lastcoins, lastbuttons;
INT32 credits;
INT32 coins[2];
INT32 coins_per_cred[2];
INT32 creds_per_coin[2];
INT32 in_count;
const device_config *device; const device_config *device;
read8_space_func in[4];
write8_space_func out[2];
INT32 reset;
INT32 lastcoins,lastbuttons;
INT32 credits;
INT32 coins[2];
INT32 coins_per_cred[2];
INT32 creds_per_coin[2];
INT32 in_count;
}; };
static struct namcoio io[MAX_NAMCOIO]; /*****************************************************************************
INLINE FUNCTIONS
*****************************************************************************/
static READ8_HANDLER( nop_r ) { return 0x0f; } INLINE namcoio_state *get_safe_token( const device_config *device )
static WRITE8_HANDLER( nop_w ) { }
#define READ_PORT(m,n) (io[chip].in[n](m,0) & 0x0f)
#define WRITE_PORT(m,n,d) io[chip].out[n](m,0,(d) & 0x0f)
/***************************************************************************/
static UINT8 namcoio_ram[MAX_NAMCOIO * 16];
#define IORAM_READ(offset) (namcoio_ram[chip * 0x10 + (offset)] & 0x0f)
#define IORAM_WRITE(offset,data) {namcoio_ram[chip * 0x10 + (offset)] = (data) & 0x0f;}
static void handle_coins(running_machine *machine,int chip,int swap)
{ {
int val,toggled; assert(device != NULL);
assert(device->token != NULL);
assert(device->type == NAMCO56XX || device->type == NAMCO58XX || device->type == NAMCO59XX);
return (namcoio_state *)device->token;
}
INLINE const namcoio_interface *get_interface( const device_config *device )
{
assert(device != NULL);
assert(device->type == NAMCO56XX || device->type == NAMCO58XX || device->type == NAMCO59XX);
return (const namcoio_interface *) device->static_config;
}
/*****************************************************************************
DEVICE HANDLERS
*****************************************************************************/
#define READ_PORT(n) (devcb_call_read8(&namcoio->in[n], 0) & 0x0f)
#define WRITE_PORT(n,d) (devcb_call_write8(&namcoio->out[n], 0, (d) & 0x0f))
#define IORAM_READ(offset) (namcoio->ram[offset] & 0x0f)
#define IORAM_WRITE(offset,data) {namcoio->ram[offset] = (data) & 0x0f;}
static void handle_coins( const device_config *device, int swap )
{
namcoio_state *namcoio = get_safe_token(device);
int val, toggled;
int credit_add = 0; int credit_add = 0;
int credit_sub = 0; int credit_sub = 0;
int button; int button;
const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
//popmessage("%x %x %x %x %x %x %x %x",IORAM_READ(8),IORAM_READ(9),IORAM_READ(10),IORAM_READ(11),IORAM_READ(12),IORAM_READ(13),IORAM_READ(14),IORAM_READ(15)); //popmessage("%x %x %x %x %x %x %x %x",IORAM_READ(8),IORAM_READ(9),IORAM_READ(10),IORAM_READ(11),IORAM_READ(12),IORAM_READ(13),IORAM_READ(14),IORAM_READ(15));
val = ~READ_PORT(space,0); // pins 38-41 val = ~READ_PORT(0); // pins 38-41
toggled = val ^ io[chip].lastcoins; toggled = val ^ namcoio->lastcoins;
io[chip].lastcoins = val; namcoio->lastcoins = val;
/* check coin insertion */ /* check coin insertion */
if (val & toggled & 0x01) if (val & toggled & 0x01)
{ {
io[chip].coins[0]++; namcoio->coins[0]++;
if (io[chip].coins[0] >= (io[chip].coins_per_cred[0] & 7)) if (namcoio->coins[0] >= (namcoio->coins_per_cred[0] & 7))
{ {
credit_add = io[chip].creds_per_coin[0] - (io[chip].coins_per_cred[0] >> 3); credit_add = namcoio->creds_per_coin[0] - (namcoio->coins_per_cred[0] >> 3);
io[chip].coins[0] -= io[chip].coins_per_cred[0] & 7; namcoio->coins[0] -= namcoio->coins_per_cred[0] & 7;
} }
else if (io[chip].coins_per_cred[0] & 8) else if (namcoio->coins_per_cred[0] & 8)
credit_add = 1; credit_add = 1;
} }
if (val & toggled & 0x02) if (val & toggled & 0x02)
{ {
io[chip].coins[1]++; namcoio->coins[1]++;
if (io[chip].coins[1] >= (io[chip].coins_per_cred[1] & 7)) if (namcoio->coins[1] >= (namcoio->coins_per_cred[1] & 7))
{ {
credit_add = io[chip].creds_per_coin[1] - (io[chip].coins_per_cred[1] >> 3); credit_add = namcoio->creds_per_coin[1] - (namcoio->coins_per_cred[1] >> 3);
io[chip].coins[1] -= io[chip].coins_per_cred[1] & 7; namcoio->coins[1] -= namcoio->coins_per_cred[1] & 7;
} }
else if (io[chip].coins_per_cred[1] & 8) else if (namcoio->coins_per_cred[1] & 8)
credit_add = 1; credit_add = 1;
} }
if (val & toggled & 0x08) if (val & toggled & 0x08)
@ -196,9 +208,9 @@ static void handle_coins(running_machine *machine,int chip,int swap)
credit_add = 1; credit_add = 1;
} }
val = ~READ_PORT(space,3); // pins 30-33 val = ~READ_PORT(3); // pins 30-33
toggled = val ^ io[chip].lastbuttons; toggled = val ^ namcoio->lastbuttons;
io[chip].lastbuttons = val; namcoio->lastbuttons = val;
/* check start buttons, only if the game allows */ /* check start buttons, only if the game allows */
if (IORAM_READ(9) == 0) if (IORAM_READ(9) == 0)
@ -206,35 +218,34 @@ static void handle_coins(running_machine *machine,int chip,int swap)
{ {
if (val & toggled & 0x04) if (val & toggled & 0x04)
{ {
if (io[chip].credits >= 1) credit_sub = 1; if (namcoio->credits >= 1) credit_sub = 1;
} }
else if (val & toggled & 0x08) else if (val & toggled & 0x08)
{ {
if (io[chip].credits >= 2) credit_sub = 2; if (namcoio->credits >= 2) credit_sub = 2;
} }
} }
io[chip].credits += credit_add - credit_sub; namcoio->credits += credit_add - credit_sub;
IORAM_WRITE(0 ^ swap, io[chip].credits / 10); // BCD credits IORAM_WRITE(0 ^ swap, namcoio->credits / 10); // BCD credits
IORAM_WRITE(1 ^ swap, io[chip].credits % 10); // BCD credits IORAM_WRITE(1 ^ swap, namcoio->credits % 10); // BCD credits
IORAM_WRITE(2 ^ swap, credit_add); // credit increment (coin inputs) IORAM_WRITE(2 ^ swap, credit_add); // credit increment (coin inputs)
IORAM_WRITE(3 ^ swap, credit_sub); // credit decrement (start buttons) IORAM_WRITE(3 ^ swap, credit_sub); // credit decrement (start buttons)
IORAM_WRITE(4, ~READ_PORT(space,1)); // pins 22-25 IORAM_WRITE(4, ~READ_PORT(1)); // pins 22-25
button = ((val & 0x05) << 1) | (val & toggled & 0x05); button = ((val & 0x05) << 1) | (val & toggled & 0x05);
IORAM_WRITE(5, button); // pins 30 & 32 normal and impulse IORAM_WRITE(5, button); // pins 30 & 32 normal and impulse
IORAM_WRITE(6, ~READ_PORT(space,2)); // pins 26-29 IORAM_WRITE(6, ~READ_PORT(2)); // pins 26-29
button = (val & 0x0a) | ((val & toggled & 0x0a) >> 1); button = (val & 0x0a) | ((val & toggled & 0x0a) >> 1);
IORAM_WRITE(7, button); // pins 31 & 33 normal and impulse IORAM_WRITE(7, button); // pins 31 & 33 normal and impulse
} }
void namco_customio_56xx_run( const device_config *device )
static void namco_customio_56XX_run(running_machine *machine, int chip)
{ {
const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM); namcoio_state *namcoio = get_safe_token(device);
LOG(("execute 56XX %d mode %d\n",chip,IORAM_READ(8))); LOG(("execute 56XX mode %d\n", IORAM_READ(8)));
switch (IORAM_READ(8)) switch (IORAM_READ(8))
{ {
@ -242,22 +253,22 @@ static void namco_customio_56XX_run(running_machine *machine, int chip)
break; break;
case 1: // read switch inputs case 1: // read switch inputs
IORAM_WRITE(0, ~READ_PORT(space,0)); // pins 38-41 IORAM_WRITE(0, ~READ_PORT(0)); // pins 38-41
IORAM_WRITE(1, ~READ_PORT(space,1)); // pins 22-25 IORAM_WRITE(1, ~READ_PORT(1)); // pins 22-25
IORAM_WRITE(2, ~READ_PORT(space,2)); // pins 26-29 IORAM_WRITE(2, ~READ_PORT(2)); // pins 26-29
IORAM_WRITE(3, ~READ_PORT(space,3)); // pins 30-33 IORAM_WRITE(3, ~READ_PORT(3)); // pins 30-33
//popmessage("%x %x %x %x %x %x %x %x",IORAM_READ(8),IORAM_READ(9),IORAM_READ(10),IORAM_READ(11),IORAM_READ(12),IORAM_READ(13),IORAM_READ(14),IORAM_READ(15)); //popmessage("%x %x %x %x %x %x %x %x",IORAM_READ(8),IORAM_READ(9),IORAM_READ(10),IORAM_READ(11),IORAM_READ(12),IORAM_READ(13),IORAM_READ(14),IORAM_READ(15));
WRITE_PORT(space,0,IORAM_READ(9)); // output to pins 13-16 (motos, pacnpal, gaplus) WRITE_PORT(0, IORAM_READ(9)); // output to pins 13-16 (motos, pacnpal, gaplus)
WRITE_PORT(space,1,IORAM_READ(10)); // output to pins 17-20 (gaplus) WRITE_PORT(1, IORAM_READ(10)); // output to pins 17-20 (gaplus)
break; break;
case 2: // initialize coinage settings case 2: // initialize coinage settings
io[chip].coins_per_cred[0] = IORAM_READ(9); namcoio->coins_per_cred[0] = IORAM_READ(9);
io[chip].creds_per_coin[0] = IORAM_READ(10); namcoio->creds_per_coin[0] = IORAM_READ(10);
io[chip].coins_per_cred[1] = IORAM_READ(11); namcoio->coins_per_cred[1] = IORAM_READ(11);
io[chip].creds_per_coin[1] = IORAM_READ(12); namcoio->creds_per_coin[1] = IORAM_READ(12);
// IORAM_READ(13) = 1; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A) // IORAM_READ(13) = 1; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A)
// IORAM_READ(14) = 1; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A) // IORAM_READ(14) = 1; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A)
// IORAM_READ(15) = 0; meaning unknown // IORAM_READ(15) = 0; meaning unknown
@ -265,58 +276,58 @@ static void namco_customio_56XX_run(running_machine *machine, int chip)
case 4: // druaga, digdug chip #1: read dip switches and inputs case 4: // druaga, digdug chip #1: read dip switches and inputs
// superpac chip #0: process coin and start inputs, read switch inputs // superpac chip #0: process coin and start inputs, read switch inputs
handle_coins(machine,chip,0); handle_coins(device, 0);
break; break;
case 7: // bootup check (liblrabl only) case 7: // bootup check (liblrabl only)
{ {
// liblrabl chip #1: 9-15 = f 1 2 3 4 0 0, expects 2 = e // liblrabl chip #1: 9-15 = f 1 2 3 4 0 0, expects 2 = e
// liblrabl chip #2: 9-15 = 0 1 4 5 5 0 0, expects 7 = 6 // liblrabl chip #2: 9-15 = 0 1 4 5 5 0 0, expects 7 = 6
IORAM_WRITE(2,0xe); IORAM_WRITE(2, 0xe);
IORAM_WRITE(7,0x6); IORAM_WRITE(7, 0x6);
} }
break; break;
case 8: // bootup check case 8: // bootup check
{ {
int i,sum; int i, sum;
// superpac: 9-15 = f f f f f f f, expects 0-1 = 6 9. 0x69 = f+f+f+f+f+f+f. // superpac: 9-15 = f f f f f f f, expects 0-1 = 6 9. 0x69 = f+f+f+f+f+f+f.
// motos: 9-15 = f f f f f f f, expects 0-1 = 6 9. 0x69 = f+f+f+f+f+f+f. // motos: 9-15 = f f f f f f f, expects 0-1 = 6 9. 0x69 = f+f+f+f+f+f+f.
// phozon: 9-15 = 1 2 3 4 5 6 7, expects 0-1 = 1 c. 0x1c = 1+2+3+4+5+6+7 // phozon: 9-15 = 1 2 3 4 5 6 7, expects 0-1 = 1 c. 0x1c = 1+2+3+4+5+6+7
sum = 0; sum = 0;
for (i = 9;i < 16;i++) for (i = 9; i < 16; i++)
sum += IORAM_READ(i); sum += IORAM_READ(i);
IORAM_WRITE(0,sum >> 4); IORAM_WRITE(0, sum >> 4);
IORAM_WRITE(1,sum & 0xf); IORAM_WRITE(1, sum & 0xf);
} }
break; break;
case 9: // read dip switches and inputs case 9: // read dip switches and inputs
WRITE_PORT(space,0,0); // set pin 13 = 0 WRITE_PORT(0, 0); // set pin 13 = 0
IORAM_WRITE(0, ~READ_PORT(space,0)); // pins 38-41, pin 13 = 0 IORAM_WRITE(0, ~READ_PORT(0)); // pins 38-41, pin 13 = 0
IORAM_WRITE(2, ~READ_PORT(space,1)); // pins 22-25, pin 13 = 0 IORAM_WRITE(2, ~READ_PORT(1)); // pins 22-25, pin 13 = 0
IORAM_WRITE(4, ~READ_PORT(space,2)); // pins 26-29, pin 13 = 0 IORAM_WRITE(4, ~READ_PORT(2)); // pins 26-29, pin 13 = 0
IORAM_WRITE(6, ~READ_PORT(space,3)); // pins 30-33, pin 13 = 0 IORAM_WRITE(6, ~READ_PORT(3)); // pins 30-33, pin 13 = 0
WRITE_PORT(space,0,1); // set pin 13 = 1 WRITE_PORT(0, 1); // set pin 13 = 1
IORAM_WRITE(1, ~READ_PORT(space,0)); // pins 38-41, pin 13 = 1 IORAM_WRITE(1, ~READ_PORT(0)); // pins 38-41, pin 13 = 1
IORAM_WRITE(3, ~READ_PORT(space,1)); // pins 22-25, pin 13 = 1 IORAM_WRITE(3, ~READ_PORT(1)); // pins 22-25, pin 13 = 1
IORAM_WRITE(5, ~READ_PORT(space,2)); // pins 26-29, pin 13 = 1 IORAM_WRITE(5, ~READ_PORT(2)); // pins 26-29, pin 13 = 1
IORAM_WRITE(7, ~READ_PORT(space,3)); // pins 30-33, pin 13 = 1 IORAM_WRITE(7, ~READ_PORT(3)); // pins 30-33, pin 13 = 1
break; break;
default: default:
logerror("Namco I/O %d: unknown I/O mode %d\n",chip,IORAM_READ(8)); logerror("Namco I/O unknown I/O mode %d\n", IORAM_READ(8));
} }
} }
static void namco_customio_59XX_run(running_machine *machine, int chip) void namco_customio_59xx_run( const device_config *device )
{ {
const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM); namcoio_state *namcoio = get_safe_token(device);
LOG(("execute 59XX %d mode %d\n",chip,IORAM_READ(8))); LOG(("execute 59XX mode %d\n", IORAM_READ(8)));
switch (IORAM_READ(8)) switch (IORAM_READ(8))
{ {
@ -324,24 +335,24 @@ static void namco_customio_59XX_run(running_machine *machine, int chip)
break; break;
case 3: // pacnpal chip #1: read dip switches and inputs case 3: // pacnpal chip #1: read dip switches and inputs
IORAM_WRITE(4, ~READ_PORT(space,0)); // pins 38-41, pin 13 = 0 ? IORAM_WRITE(4, ~READ_PORT(0)); // pins 38-41, pin 13 = 0 ?
IORAM_WRITE(5, ~READ_PORT(space,2)); // pins 26-29 ? IORAM_WRITE(5, ~READ_PORT(2)); // pins 26-29 ?
IORAM_WRITE(6, ~READ_PORT(space,1)); // pins 22-25 ? IORAM_WRITE(6, ~READ_PORT(1)); // pins 22-25 ?
IORAM_WRITE(7, ~READ_PORT(space,3)); // pins 30-33 IORAM_WRITE(7, ~READ_PORT(3)); // pins 30-33
break; break;
default: default:
logerror("Namco I/O %d: unknown I/O mode %d\n",chip,IORAM_READ(8)); logerror("Namco I/O: unknown I/O mode %d\n", IORAM_READ(8));
} }
} }
static void namco_customio_58XX_run(running_machine *machine, int chip) void namco_customio_58xx_run( const device_config *device )
{ {
const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM); namcoio_state *namcoio = get_safe_token(device);
LOG(("execute 58XX %d mode %d\n",chip,IORAM_READ(8))); LOG(("execute 58XX mode %d\n", IORAM_READ(8)));
switch (IORAM_READ(8)) switch (IORAM_READ(8))
{ {
@ -349,42 +360,42 @@ static void namco_customio_58XX_run(running_machine *machine, int chip)
break; break;
case 1: // read switch inputs case 1: // read switch inputs
IORAM_WRITE(4, ~READ_PORT(space,0)); // pins 38-41 IORAM_WRITE(4, ~READ_PORT(0)); // pins 38-41
IORAM_WRITE(5, ~READ_PORT(space,1)); // pins 22-25 IORAM_WRITE(5, ~READ_PORT(1)); // pins 22-25
IORAM_WRITE(6, ~READ_PORT(space,2)); // pins 26-29 IORAM_WRITE(6, ~READ_PORT(2)); // pins 26-29
IORAM_WRITE(7, ~READ_PORT(space,3)); // pins 30-33 IORAM_WRITE(7, ~READ_PORT(3)); // pins 30-33
//popmessage("%x %x %x %x %x %x %x %x",IORAM_READ(8),IORAM_READ(9),IORAM_READ(10),IORAM_READ(11),IORAM_READ(12),IORAM_READ(13),IORAM_READ(14),IORAM_READ(15)); //popmessage("%x %x %x %x %x %x %x %x",IORAM_READ(8),IORAM_READ(9),IORAM_READ(10),IORAM_READ(11),IORAM_READ(12),IORAM_READ(13),IORAM_READ(14),IORAM_READ(15));
WRITE_PORT(space,0,IORAM_READ(9)); // output to pins 13-16 (toypop) WRITE_PORT(0, IORAM_READ(9)); // output to pins 13-16 (toypop)
WRITE_PORT(space,1,IORAM_READ(10)); // output to pins 17-20 (toypop) WRITE_PORT(1, IORAM_READ(10)); // output to pins 17-20 (toypop)
break; break;
case 2: // initialize coinage settings case 2: // initialize coinage settings
io[chip].coins_per_cred[0] = IORAM_READ(9); namcoio->coins_per_cred[0] = IORAM_READ(9);
io[chip].creds_per_coin[0] = IORAM_READ(10); namcoio->creds_per_coin[0] = IORAM_READ(10);
io[chip].coins_per_cred[1] = IORAM_READ(11); namcoio->coins_per_cred[1] = IORAM_READ(11);
io[chip].creds_per_coin[1] = IORAM_READ(12); namcoio->creds_per_coin[1] = IORAM_READ(12);
// IORAM_READ(13) = 1; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A) // IORAM_READ(13) = 1; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A)
// IORAM_READ(14) = 0; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A) // IORAM_READ(14) = 0; meaning unknown - possibly a 3rd coin input? (there's a IPT_UNUSED bit in port A)
// IORAM_READ(15) = 0; meaning unknown // IORAM_READ(15) = 0; meaning unknown
break; break;
case 3: // process coin and start inputs, read switch inputs case 3: // process coin and start inputs, read switch inputs
handle_coins(machine,chip,2); handle_coins(device, 2);
break; break;
case 4: // read dip switches and inputs case 4: // read dip switches and inputs
WRITE_PORT(space,0,0); // set pin 13 = 0 WRITE_PORT(0, 0); // set pin 13 = 0
IORAM_WRITE(0, ~READ_PORT(space,0)); // pins 38-41, pin 13 = 0 IORAM_WRITE(0, ~READ_PORT(0)); // pins 38-41, pin 13 = 0
IORAM_WRITE(2, ~READ_PORT(space,1)); // pins 22-25, pin 13 = 0 IORAM_WRITE(2, ~READ_PORT(1)); // pins 22-25, pin 13 = 0
IORAM_WRITE(4, ~READ_PORT(space,2)); // pins 26-29, pin 13 = 0 IORAM_WRITE(4, ~READ_PORT(2)); // pins 26-29, pin 13 = 0
IORAM_WRITE(6, ~READ_PORT(space,3)); // pins 30-33, pin 13 = 0 IORAM_WRITE(6, ~READ_PORT(3)); // pins 30-33, pin 13 = 0
WRITE_PORT(space,0,1); // set pin 13 = 1 WRITE_PORT(0, 1); // set pin 13 = 1
IORAM_WRITE(1, ~READ_PORT(space,0)); // pins 38-41, pin 13 = 1 IORAM_WRITE(1, ~READ_PORT(0)); // pins 38-41, pin 13 = 1
IORAM_WRITE(3, ~READ_PORT(space,1)); // pins 22-25, pin 13 = 1 IORAM_WRITE(3, ~READ_PORT(1)); // pins 22-25, pin 13 = 1
IORAM_WRITE(5, ~READ_PORT(space,2)); // pins 26-29, pin 13 = 1 IORAM_WRITE(5, ~READ_PORT(2)); // pins 26-29, pin 13 = 1
IORAM_WRITE(7, ~READ_PORT(space,3)); // pins 30-33, pin 13 = 1 IORAM_WRITE(7, ~READ_PORT(3)); // pins 30-33, pin 13 = 1
break; break;
case 5: // bootup check case 5: // bootup check
@ -402,17 +413,17 @@ static void namco_customio_58XX_run(running_machine *machine, int chip)
to give Gaplus the F it expects. to give Gaplus the F it expects.
*/ */
{ {
int i,n,rng,seed; int i, n, rng, seed;
#define NEXT(n) ((((n) & 1) ? (n) ^ 0x90 : (n)) >> 1) #define NEXT(n) ((((n) & 1) ? (n) ^ 0x90 : (n)) >> 1)
/* initialize the LFSR depending on the first two arguments */ /* initialize the LFSR depending on the first two arguments */
n = (IORAM_READ(9) * 16 + IORAM_READ(10)) & 0x7f; n = (IORAM_READ(9) * 16 + IORAM_READ(10)) & 0x7f;
seed = 0x22; seed = 0x22;
for (i = 0;i < n;i++) for (i = 0; i < n; i++)
seed = NEXT(seed); seed = NEXT(seed);
/* calculate the answer */ /* calculate the answer */
for (i = 1;i < 8;i++) for (i = 1; i < 8; i++)
{ {
n = 0; n = 0;
rng = seed; rng = seed;
@ -431,109 +442,113 @@ static void namco_customio_58XX_run(running_machine *machine, int chip)
rng = NEXT(rng); rng = NEXT(rng);
if (rng & 1) { n ^= ~IORAM_READ(12); } if (rng & 1) { n ^= ~IORAM_READ(12); }
IORAM_WRITE(i,~n); IORAM_WRITE(i, ~n);
} }
IORAM_WRITE(0,0x0); IORAM_WRITE(0, 0x0);
/* kludge for gaplus */ /* kludge for gaplus */
if (IORAM_READ(9) == 0xf) IORAM_WRITE(0,0xf); if (IORAM_READ(9) == 0xf) IORAM_WRITE(0, 0xf);
} }
break; break;
default: default:
logerror("Namco I/O %d: unknown I/O mode %d\n",chip,IORAM_READ(8)); logerror("Namco I/O: unknown I/O mode %d\n", IORAM_READ(8));
} }
} }
READ8_HANDLER( namcoio_r ) READ8_DEVICE_HANDLER( namcoio_r )
{ {
// RAM is 4-bit wide; Pac & Pal requires the | 0xf0 otherwise Easter egg doesn't work // RAM is 4-bit wide; Pac & Pal requires the | 0xf0 otherwise Easter egg doesn't work
namcoio_state *namcoio = get_safe_token(device);
offset &= 0x3f; offset &= 0x3f;
LOG(("%04x: I/O read %d: mode %d, offset %d = %02x\n", cpu_get_pc(space->cpu), offset / 16, namcoio_ram[(offset & 0x30) + 8], offset & 0x0f, namcoio_ram[offset]&0x0f)); // LOG(("%04x: I/O read: mode %d, offset %d = %02x\n", cpu_get_pc(space->cpu), offset / 16, namcoio_ram[(offset & 0x30) + 8], offset & 0x0f, namcoio_ram[offset]&0x0f));
return 0xf0 | namcoio_ram[offset]; return 0xf0 | namcoio->ram[offset];
} }
WRITE8_HANDLER( namcoio_w ) WRITE8_DEVICE_HANDLER( namcoio_w )
{ {
namcoio_state *namcoio = get_safe_token(device);
offset &= 0x3f; offset &= 0x3f;
data &= 0x0f; // RAM is 4-bit wide data &= 0x0f; // RAM is 4-bit wide
LOG(("%04x: I/O write %d: offset %d = %02x\n", cpu_get_pc(space->cpu), offset / 16, offset & 0x0f, data)); // LOG(("%04x: I/O write %d: offset %d = %02x\n", cpu_get_pc(space->cpu), offset / 16, offset & 0x0f, data));
namcoio_ram[offset] = data; namcoio->ram[offset] = data;
} }
void namcoio_set_reset_line(int chipnum, int state) WRITE_LINE_DEVICE_HANDLER( namcoio_set_reset_line )
{ {
io[chipnum].reset = (state == ASSERT_LINE) ? 1 : 0; namcoio_state *namcoio = get_safe_token(device);
namcoio->reset = (state == ASSERT_LINE) ? 1 : 0;
if (state != CLEAR_LINE) if (state != CLEAR_LINE)
{ {
/* reset internal registers */ /* reset internal registers */
io[chipnum].credits = 0; namcoio->credits = 0;
io[chipnum].coins[0] = 0; namcoio->coins[0] = 0;
io[chipnum].coins_per_cred[0] = 1; namcoio->coins_per_cred[0] = 1;
io[chipnum].creds_per_coin[0] = 1; namcoio->creds_per_coin[0] = 1;
io[chipnum].coins[1] = 0; namcoio->coins[1] = 0;
io[chipnum].coins_per_cred[1] = 1; namcoio->coins_per_cred[1] = 1;
io[chipnum].creds_per_coin[1] = 1; namcoio->creds_per_coin[1] = 1;
io[chipnum].in_count = 0; namcoio->in_count = 0;
} }
} }
static TIMER_CALLBACK( namcoio_run ) READ_LINE_DEVICE_HANDLER( namcoio_read_reset_line )
{ {
switch (io[param].type) namcoio_state *namcoio = get_safe_token(device);
{ return namcoio->reset;
case NAMCOIO_56XX:
namco_customio_56XX_run(machine, param);
break;
case NAMCOIO_58XX:
namco_customio_58XX_run(machine, param);
break;
case NAMCOIO_59XX:
namco_customio_59XX_run(machine, param);
break;
}
} }
void namcoio_set_irq_line(running_machine *machine, int chipnum, int state)
/*****************************************************************************
DEVICE INTERFACE
*****************************************************************************/
static DEVICE_START( namcoio )
{ {
if (chipnum < MAX_NAMCOIO && state != CLEAR_LINE && !io[chipnum].reset) namcoio_state *namcoio = get_safe_token(device);
{ const namcoio_interface *intf = get_interface(device);
/* give the cpu a tiny bit of time to write the command before processing it */
timer_set(machine, ATTOTIME_IN_USEC(50), NULL, chipnum, namcoio_run); namcoio->device = intf->device;
}
devcb_resolve_read8(&namcoio->in[0], &intf->in[0], device);
devcb_resolve_read8(&namcoio->in[1], &intf->in[1], device);
devcb_resolve_read8(&namcoio->in[2], &intf->in[2], device);
devcb_resolve_read8(&namcoio->in[3], &intf->in[3], device);
devcb_resolve_write8(&namcoio->out[0], &intf->out[0], device);
devcb_resolve_write8(&namcoio->out[1], &intf->out[1], device);
state_save_register_device_item_array(device, 0, namcoio->ram);
state_save_register_device_item(device, 0, namcoio->reset);
state_save_register_device_item(device, 0, namcoio->lastcoins);
state_save_register_device_item(device, 0, namcoio->lastbuttons);
state_save_register_device_item(device, 0, namcoio->credits);
state_save_register_device_item_array(device, 0, namcoio->coins);
state_save_register_device_item_array(device, 0, namcoio->coins_per_cred);
state_save_register_device_item_array(device, 0, namcoio->creds_per_coin);
state_save_register_device_item(device, 0, namcoio->in_count);
} }
static void namcoio_state_save(running_machine *machine, int chipnum) static DEVICE_RESET( namcoio )
{ {
state_save_register_item_pointer(machine, "namcoio", NULL, chipnum, ((UINT8 *) (&namcoio_ram[chipnum * 16])), 16); namcoio_state *namcoio = get_safe_token(device);
state_save_register_item(machine, "namcoio", NULL, chipnum, io[chipnum].reset); int i;
state_save_register_item(machine, "namcoio", NULL, chipnum, io[chipnum].lastcoins);
state_save_register_item(machine, "namcoio", NULL, chipnum, io[chipnum].lastbuttons); for (i = 0; i < 16; i++)
state_save_register_item(machine, "namcoio", NULL, chipnum, io[chipnum].credits); namcoio->ram[i] = 0;
state_save_register_item_array(machine, "namcoio", NULL, chipnum, io[chipnum].coins);
state_save_register_item_array(machine, "namcoio", NULL, chipnum, io[chipnum].coins_per_cred); namcoio_set_reset_line(device, PULSE_LINE);
state_save_register_item_array(machine, "namcoio", NULL, chipnum, io[chipnum].creds_per_coin);
state_save_register_item(machine, "namcoio", NULL, chipnum, io[chipnum].in_count);
} }
void namcoio_init(running_machine *machine, int chipnum, int type, const struct namcoio_interface *intf, const char *device) static const char DEVTEMPLATE_SOURCE[] = __FILE__;
{
if (chipnum < MAX_NAMCOIO) #define DEVTEMPLATE_ID(p,s) p##namcoio##s
{ #define DEVTEMPLATE_FEATURES DT_HAS_START | DT_HAS_RESET
io[chipnum].type = type; #define DEVTEMPLATE_NAME "Namco 56xx, 58xx & 59xx"
io[chipnum].device = device ? devtag_get_device(machine, device) : NULL; #define DEVTEMPLATE_FAMILY "Namco I/O"
io[chipnum].in[0] = (intf && intf->in[0]) ? intf->in[0] : nop_r; #include "devtempl.h"
io[chipnum].in[1] = (intf && intf->in[1]) ? intf->in[1] : nop_r;
io[chipnum].in[2] = (intf && intf->in[2]) ? intf->in[2] : nop_r;
io[chipnum].in[3] = (intf && intf->in[3]) ? intf->in[3] : nop_r;
io[chipnum].out[0] = (intf && intf->out[0]) ? intf->out[0] : nop_w;
io[chipnum].out[1] = (intf && intf->out[1]) ? intf->out[1] : nop_w;
namcoio_state_save(machine, chipnum);
namcoio_set_reset_line(chipnum,PULSE_LINE);
}
}

71
src/mame/machine/namcoio.h
View File

@ -1,32 +1,63 @@
#ifndef NAMCOIO_H #ifndef __NAMCOIO_H__
#define NAMCOIO_H #define __NAMCOIO_H__
#include "devintrf.h" #include "devcb.h"
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
enum typedef struct _namcoio_interface namcoio_interface;
struct _namcoio_interface
{ {
NAMCOIO_56XX, devcb_read8 in[4];
NAMCOIO_58XX, devcb_write8 out[2];
NAMCOIO_59XX,
NAMCOIO_62XX const device_config *device;
}; };
#define MAX_NAMCOIO 8 /***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
DEVICE_GET_INFO( namcoio );
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define NAMCO56XX DEVICE_GET_INFO_NAME( namcoio )
#define NAMCO58XX DEVICE_GET_INFO_NAME( namcoio )
#define NAMCO59XX DEVICE_GET_INFO_NAME( namcoio )
#define MDRV_NAMCO56XX_ADD(_tag, _interface) \
MDRV_DEVICE_ADD(_tag, NAMCO56XX, 0) \
MDRV_DEVICE_CONFIG(_interface)
#define MDRV_NAMCO58XX_ADD(_tag, _interface) \
MDRV_DEVICE_ADD(_tag, NAMCO58XX, 0) \
MDRV_DEVICE_CONFIG(_interface)
#define MDRV_NAMCO59XX_ADD(_tag, _interface) \
MDRV_DEVICE_ADD(_tag, NAMCO59XX, 0) \
MDRV_DEVICE_CONFIG(_interface)
struct namcoio_interface /***************************************************************************
{ DEVICE I/O FUNCTIONS
read8_space_func in[4]; /* read handlers for ports A-D */ ***************************************************************************/
write8_space_func out[2]; /* write handlers for ports A-B */
}; READ8_DEVICE_HANDLER( namcoio_r );
WRITE8_DEVICE_HANDLER( namcoio_w );
WRITE_LINE_DEVICE_HANDLER( namcoio_set_reset_line );
READ_LINE_DEVICE_HANDLER( namcoio_read_reset_line );
READ8_HANDLER( namcoio_r ); /* these must be used in the single drivers, inside a timer */
WRITE8_HANDLER( namcoio_w ); void namco_customio_56xx_run(const device_config *device);
void namcoio_init(running_machine *machine, int chipnum, int type, const struct namcoio_interface *intf, const char *device); void namco_customio_58xx_run(const device_config *device);
void namcoio_set_reset_line(int chipnum, int state); void namco_customio_59xx_run(const device_config *device);
void namcoio_set_irq_line(running_machine *machine, int chipnum, int state);
#endif #endif /* __NAMCOIO_H__ */