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https://github.com/holub/mame
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(MESS) VK100: Correctly hooked up vsync interrupt to crtc instead of video subsystem; Figured out the low two bits of SYSTAT_A from tracing and hooked both up, and updated the SYSTAT_A documentation comments. Additional documentation comments for the SMC COM5016T baud rate divider. Made the DU/DVM/DIR/WOPS 8*4bit register file an actual 4-entry array, to simplify address decoding later. [Lord Nightmare]
This commit is contained in:
Jonathan Gevaryahu
parent
5dabd67b34
commit
f9903caa1a
@ -4,13 +4,14 @@
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12/05/2009 Skeleton driver.
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28/07/2009 added Guru-readme(TM)
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08/01/2012 Fleshed out driver.
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Todo:
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* fix vector generator hardware enough to pass the startup self test
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the tests are described on page 6-5 thru 6-8 of the tech reference
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* hook up the direction and sync prom to the sync counter
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* figure out the correct meaning of systat b register - needed for communications selftest
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* hook up smc_5016t baud generator to i8251 rx and tx clocks - begun
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* hook up smc com5016t baud generator to i8251 rx and tx clocks - begun
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Tony DiCenzo, now the director of standards and architecture at Oracle, was on the team that developed the VK100
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see http://startup.nmnaturalhistory.org/visitorstories/view.php?ii=79
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@ -154,6 +155,7 @@ public:
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UINT8* m_trans;
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UINT8* m_pattern;
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UINT8* m_dir;
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UINT8 m_vsync; // vsync pin of crtc
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UINT16 m_vgX;
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UINT16 m_vgY;
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UINT16 m_vgERR; // error register can cause carries which need to be caught
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@ -163,10 +165,11 @@ public:
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UINT8 m_vgPMUL; // reload value for PMUL_Count
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UINT8 m_vgPMUL_Count;
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UINT8 m_vgDownCount; // down counter = number of pixels, loaded from vgDU on execute
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UINT8 m_vgDU;
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UINT8 m_vgDVM;
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UINT8 m_vgDIR;
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UINT8 m_vgWOPS;
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#define VG_DU m_regfile[0]
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#define VG_DVM m_regfile[1]
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#define VG_DIR m_regfile[2]
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#define VG_WOPS m_regfile[3]
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UINT8 m_regfile[4];
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UINT8 m_VG_MODE; // 2 bits, latched on EXEC
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UINT8 m_vgGO; // activated on next SYNC pulse after EXEC
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UINT8 m_ACTS;
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@ -243,7 +246,7 @@ static void vram_write(running_machine &machine, UINT8 data)
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block |= data<<(nybbleNum*4); // write the new part
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// NOTE: this next part may have to be made conditional on VG_MODE
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// check if the attribute nybble is supposed to be modified, and if so do so
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if (state->m_vgWOPS&0x08) block = (block&0x0FFF)|(((UINT16)state->m_vgWOPS&0xF0)<<8);
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if (state->VG_WOPS&0x08) block = (block&0x0FFF)|(((UINT16)state->VG_WOPS&0xF0)<<8);
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state->m_vram[(EA<<1)+1] = block&0xFF; // write block back to vram
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state->m_vram[(EA<<1)] = (block&0xFF00)>>8; // ''
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}
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@ -253,7 +256,7 @@ static TIMER_CALLBACK( execute_vg )
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vk100_state *state = machine.driver_data<vk100_state>();
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UINT8 thisNyb = vram_read(machine); // read in the nybble
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// pattern rom addressing is a complex mess. see the pattern rom def later in this file.
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UINT8 newNyb = state->m_pattern[((state->m_vgPAT&state->m_vgPAT_Mask)?0x200:0)|((state->m_vgWOPS&7)<<6)|((state->m_vgX&3)<<4)|thisNyb]; // calculate new nybble based on pattern rom
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UINT8 newNyb = state->m_pattern[((state->m_vgPAT&state->m_vgPAT_Mask)?0x200:0)|((state->VG_WOPS&7)<<6)|((state->m_vgX&3)<<4)|thisNyb]; // calculate new nybble based on pattern rom
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// finally write the block back to ram depending on the VG_MODE (sort of a hack until we get the vector and synd and dir roms all hooked up)
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switch (state->m_VG_MODE)
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{
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@ -305,7 +308,7 @@ static TIMER_CALLBACK( execute_vg )
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*/
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//UINT8 direction_rom = state->m_dir[];
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// HACK: we need the proper direction rom dump for this!
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switch(state->m_vgDIR&0x7)
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switch(state->VG_DIR&0x7)
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{
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case 0:
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state->m_vgX++;
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@ -423,27 +426,27 @@ WRITE8_MEMBER(vk100_state::vgPMUL)
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/* port 0x60: "DU" load vg vector major register */
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WRITE8_MEMBER(vk100_state::vgDU)
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{
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m_vgDU = data;
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VG_DU = data;
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#ifdef VG60_VERBOSE
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logerror("VG: 0x60: DU Reg loaded with %02X\n", m_vgDU);
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logerror("VG: 0x60: DU Reg loaded with %02X\n", VG_DU);
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#endif
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}
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/* port 0x61: "DVM" load vg vector minor register */
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WRITE8_MEMBER(vk100_state::vgDVM)
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{
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m_vgDVM = data;
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VG_DVM = data;
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#ifdef VG60_VERBOSE
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logerror("VG: 0x61: DVM Reg loaded with %02X\n", m_vgDVM);
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logerror("VG: 0x61: DVM Reg loaded with %02X\n", VG_DVM);
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#endif
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}
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/* port 0x62: "DIR" load vg Direction register */
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WRITE8_MEMBER(vk100_state::vgDIR)
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{
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m_vgDIR = data;
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VG_DIR = data;
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#ifdef VG60_VERBOSE
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logerror("VG: 0x62: DIR Reg loaded with %02X\n", m_vgDIR);
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logerror("VG: 0x62: DIR Reg loaded with %02X\n", VG_DIR);
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#endif
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}
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@ -455,10 +458,10 @@ WRITE8_MEMBER(vk100_state::vgDIR)
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*/
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WRITE8_MEMBER(vk100_state::vgWOPS)
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{
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m_vgWOPS = data;
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VG_WOPS = data;
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#ifdef VG60_VERBOSE
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static const char *const functions[] = { "Overlay", "Replace", "Complement", "Erase" };
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logerror("VG: 0x64: WOPS Reg loaded with %02X: KGRB %d%d%d%d, AttrChange %d, Function %s, Negate %d\n", data, (m_vgWOPS>>7)&1, (m_vgWOPS>>6)&1, (m_vgWOPS>>5)&1, (m_vgWOPS>>4)&1, (m_vgWOPS>>3)&1, functions[(m_vgWOPS>>1)&3], m_vgWOPS&1);
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logerror("VG: 0x64: WOPS Reg loaded with %02X: KGRB %d%d%d%d, AttrChange %d, Function %s, Negate %d\n", data, (VG_WOPS>>7)&1, (VG_WOPS>>6)&1, (VG_WOPS>>5)&1, (VG_WOPS>>4)&1, (VG_WOPS>>3)&1, functions[(VG_WOPS>>1)&3], VG_WOPS&1);
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#endif
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}
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@ -475,7 +478,7 @@ WRITE8_MEMBER(vk100_state::vgEX)
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#endif
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m_vgPMUL_Count = m_vgPMUL; // load PMUL_Count
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m_vgPAT_Mask = 0x80;
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m_vgDownCount = m_vgDU; // set down counter to length of major vector
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m_vgDownCount = VG_DU; // set down counter to length of major vector
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m_VG_MODE = offset&3;
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m_vgGO = 1;
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machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
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@ -501,9 +504,32 @@ WRITE8_MEMBER(vk100_state::KBDW)
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#endif
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}
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/* port 0x6C: "BAUD" controls the smc5016t dual baud generator which
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/* port 0x6C: "BAUD" controls the smc com5016t dual baud generator which
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* controls the divisors for the rx and tx clocks on the 8251 from the
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* 5.0688Mhz cpu xtal :
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5.0688Mhz cpu xtal.
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It has 5v,12v on pins 2 and 9, pin 10 is NC.
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* A later part that replaced this on the market is SMC COM8116(T)/8136(T), which
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was a 5v-only part (pin 9 and 10 are NC, 10 is a clock out on the 8136.
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* Note that even on the SMC COM5016T version, SMC would allow the user
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to mask their own dividers on custom ordered chips if desired.
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* The COM8116(T)/8136(T) came it at least 4 mask rom types meant for different
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input clocks:
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-000 or no mark for 5.0688Mhz (which exactly matches the table below)
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-003 is for 6.01835MHz
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-005 is for 4.915200Mhz
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-006 is for 5.0688Mhz but omits the 2000 baud entry, instead has 200,
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and output frequencies are 2x as fast (meant for a 32X clock uart)
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-013 is for 2.76480MHz
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-013A is for 5.52960MHz
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(several other unknown refclock masks appear on partscalper sites)
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GI also made a clone of the 8116 5v chip called the AY-5-8116(T)/8136(T)
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which had at least two masks: -000/no mark and -005, matching speeds above
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WD made the WD1943 which is similarly 5v compatible, with -00, -05, -06 masks
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The COM8046(T) has 5 bits for selection instead of 4, but still expects
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a 5.0688MHz reference clock, and the second half of the table matches the
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values below; the first half of the table is the values below /2, rounded
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down (for uarts which need a clock rate of 32x baud instead of 16x).
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WD's BR1941 is also functionally compatible but uses 5v,12v,-5v on pins 2,9,10
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* The baud divisor lookup table has 16 entries, but only entries 2,5,6,7,A,C,E,F are documented/used in the vk100 tech manual
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* The others are based on page 13 of http://www.hartetechnologies.com/manuals/Tarbell/Tarbell%20Z80%20CPU%20Board%20Model%203033.pdf
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* D C B A Divisor Expected Baud
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@ -537,19 +563,18 @@ WRITE8_MEMBER(vk100_state::BAUD)
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}
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/* port 0x40-0x47: "SYSTAT A"; various status bits, poorly documented in the tech manual
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* /GO BIT3 BIT2 BIT1 BIT0 Dip ? ?
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* Switch
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* d7 d6 d5 d4 d3 d2 d1 d0
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* bit3, 2, 1, 0 are the last 4 bits read by the vector generator from VRAM
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* note: if the vector generator is not running, reading SYSTAT A will
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* supposedly FORCE the vector generator to read one nybble from the
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* current x,y! (how does this work schematicwise??? it may just read
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* the last nybble read by the constantly running sync counter, in
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* which case the hack here sort of works as well)
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* this appears to be the only way the vram can be READ by the cpu
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d2 is where the dipswitch values are read from, based on the offset
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d1 is unknown
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d0 is unknown
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* /GO BIT3 BIT2 BIT1 BIT0 Dip RST7.5 GND
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* Switch VSYNC
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* d7 d6 d5 d4 d3 d2 d1 d0
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bit3, 2, 1, 0 are the 4 bits output from the VRAM 12->4 multiplexer
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which are also inputs to the pattern rom; they are constantly updated
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by the sync rom and related circuitry.
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This is the only way the vram can be read by the cpu.
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d7 is from the /Q output of the GO latch
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d6,5,4,3 are from the 74ls298 at ic4 (right edge of pcb)
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d2 is where the dipswitch values are read from, based on the offset
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d1 is connected to 8085 rst7.5 (pin 7) and crtc pin 40 (VSYNC) [verified via tracing]
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d0 is tied to GND [verified via tracing]
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31D reads and checks d7 in a loop
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205 reads, xors with 0x55 (from reg D), ANDS result with 0x78 and branches if it is not zero (checking for bit pattern 1010?)
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@ -562,7 +587,7 @@ READ8_MEMBER(vk100_state::SYSTAT_A)
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#ifdef SYSTAT_A_VERBOSE
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if (cpu_get_pc(m_maincpu) != 0x31D) logerror("0x%04X: SYSTAT_A Read!\n", cpu_get_pc(m_maincpu));
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#endif
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return ((m_vgGO?0:1)<<7)|(vram_read(machine())<<3)|(((ioport("SWITCHES")->read()>>dipswitchLUT[offset])&1)?0x4:0)|0x3;
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return ((m_vgGO?0:1)<<7)|(vram_read(machine())<<3)|(((ioport("SWITCHES")->read()>>dipswitchLUT[offset])&1)?0x4:0)|(m_vsync?0x2:0);
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}
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/* port 0x48: "SYSTAT B"; NOT documented in the tech manual at all.
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@ -853,6 +878,7 @@ static MACHINE_RESET( vk100 )
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output_set_value("hardcopy_led", 1);
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output_set_value("l1_led", 1);
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output_set_value("l2_led", 1);
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state->m_vsync = 0;
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state->m_vgX = 0;
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state->m_vgY = 0;
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state->m_vgERR = 0;
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@ -862,10 +888,10 @@ static MACHINE_RESET( vk100 )
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state->m_vgPMUL = 0;
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state->m_vgPMUL_Count = 0;
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state->m_vgDownCount = 0;
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state->m_vgDU = 0;
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state->m_vgDVM = 0;
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state->m_vgDIR = 0;
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state->m_vgWOPS = 0;
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state->VG_DU = 0;
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state->VG_DVM = 0;
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state->VG_DIR = 0;
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state->VG_WOPS = 0;
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state->m_VG_MODE = 0;
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state->m_vgGO = 0;
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state->m_ACTS = 1;
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@ -873,11 +899,11 @@ static MACHINE_RESET( vk100 )
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state->m_TXDivisor = 6336;
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}
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static INTERRUPT_GEN( vk100_vertical_interrupt )
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static WRITE_LINE_DEVICE_HANDLER(crtc_vsync)
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{
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vk100_state *state = device->machine().driver_data<vk100_state>();
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device_set_input_line(state->m_maincpu, I8085_RST75_LINE, ASSERT_LINE);
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device_set_input_line(state->m_maincpu, I8085_RST75_LINE, CLEAR_LINE);
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vk100_state *m_state = device->machine().driver_data<vk100_state>();
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device_set_input_line(m_state->m_maincpu, I8085_RST75_LINE, state? ASSERT_LINE : CLEAR_LINE);
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m_state->m_vsync = state;
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}
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static WRITE_LINE_DEVICE_HANDLER(i8251_rxrdy_int)
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@ -958,7 +984,7 @@ static const mc6845_interface mc6845_intf =
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_LINE(crtc_vsync),
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NULL
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};
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@ -982,7 +1008,6 @@ static MACHINE_CONFIG_START( vk100, vk100_state )
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MCFG_CPU_ADD("maincpu", I8085A, XTAL_5_0688MHz)
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MCFG_CPU_PROGRAM_MAP(vk100_mem)
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MCFG_CPU_IO_MAP(vk100_io)
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MCFG_CPU_VBLANK_INT("screen", vk100_vertical_interrupt)
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MCFG_MACHINE_RESET(vk100)
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