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https://github.com/holub/mame
synced 2025-07-03 00:56:03 +03:00
Removed a no longer needed hack. (nw)
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404e0abb30
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@ -9047,23 +9047,15 @@ static void CALT(upd7810_state *cpustate)
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PAIR w;
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PAIR w;
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w.d = 0;
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w.d = 0;
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switch (cpustate->config.type) {
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case TYPE_7810_GAMEMASTER:
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logerror ("!!!!!!!%.4x calt %.2x game master table position not known\n",PPC, OP);
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break;
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default:
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w.w.l = 0x80 + 2 * (OP & 0x1f);
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w.w.l = 0x80 + 2 * (OP & 0x1f);
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}
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if (cpustate->config.type!=TYPE_7810_GAMEMASTER) {
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SP--;
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SP--;
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WM( SPD, PCH );
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WM( SPD, PCH );
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SP--;
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SP--;
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WM( SPD, PCL );
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WM( SPD, PCL );
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PCL=RM(w.w.l);
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PCL=RM(w.w.l);
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PCH=RM(w.w.l+1);
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PCH=RM(w.w.l+1);
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}
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}
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}
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/* a0: 1010 0000 */
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/* a0: 1010 0000 */
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@ -886,28 +886,14 @@ static void upd7810_take_irq(upd7810_state *cpustate)
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/* check the interrupts in priority sequence */
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/* check the interrupts in priority sequence */
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if ((IRR & INTFT0) && 0 == (MKL & 0x02))
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if ((IRR & INTFT0) && 0 == (MKL & 0x02))
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{
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{
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switch (cpustate->config.type)
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vector = 0x0008;
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2a;
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break;
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default:
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vector = 0x0008;
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}
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if (!((IRR & INTFT1) && 0 == (MKL & 0x04)))
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if (!((IRR & INTFT1) && 0 == (MKL & 0x04)))
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IRR&=~INTFT0;
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IRR&=~INTFT0;
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}
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}
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else
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else
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if ((IRR & INTFT1) && 0 == (MKL & 0x04))
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if ((IRR & INTFT1) && 0 == (MKL & 0x04))
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{
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{
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switch (cpustate->config.type)
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vector = 0x0008;
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2a;
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break;
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default:
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vector = 0x0008;
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}
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IRR&=~INTFT1;
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IRR&=~INTFT1;
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}
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}
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else
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else
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@ -928,28 +914,14 @@ static void upd7810_take_irq(upd7810_state *cpustate)
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else
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else
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if ((IRR & INTFE0) && 0 == (MKL & 0x20))
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if ((IRR & INTFE0) && 0 == (MKL & 0x20))
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{
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{
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switch (cpustate->config.type)
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vector = 0x0018;
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2d;
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break;
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default:
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vector = 0x0018;
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}
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if (!((IRR & INTFE1) && 0 == (MKL & 0x40)))
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if (!((IRR & INTFE1) && 0 == (MKL & 0x40)))
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IRR&=~INTFE0;
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IRR&=~INTFE0;
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}
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}
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else
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else
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if ((IRR & INTFE1) && 0 == (MKL & 0x40))
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if ((IRR & INTFE1) && 0 == (MKL & 0x40))
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{
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{
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switch (cpustate->config.type)
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vector = 0x0018;
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{
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case TYPE_7810_GAMEMASTER:
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vector = 0xff2d;
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break;
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default:
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vector = 0x0018;
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}
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IRR&=~INTFE1;
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IRR&=~INTFE1;
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}
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}
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else
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else
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@ -1801,19 +1773,8 @@ static CPU_RESET( upd7810 )
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TMM = 0xff;
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TMM = 0xff;
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MA = 0xff;
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MA = 0xff;
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MB = 0xff;
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MB = 0xff;
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switch (cpustate->config.type)
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MC = 0xff;
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{
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case TYPE_7810_GAMEMASTER:
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// needed for lcd screen/ram selection; might be internal in cpu and therefor not needed; 0x10 written in some games
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MC = 0xff&~0x7;
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WP( cpustate, UPD7810_PORTC, 1 ); //hyper space
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PCD=0x8000;
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break;
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default:
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MC = 0xff;
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}
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MF = 0xff;
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MF = 0xff;
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// gamemaster falling block "and"s to enable interrupts
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MKL = 0xff;
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MKL = 0xff;
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MKH = 0xff; //?
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MKH = 0xff; //?
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cpustate->handle_timers = upd7810_timers;
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cpustate->handle_timers = upd7810_timers;
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@ -17,7 +17,6 @@ enum UPD7810_TYPE
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TYPE_78C05,
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TYPE_78C05,
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TYPE_78C06,
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TYPE_78C06,
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TYPE_7810,
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TYPE_7810,
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TYPE_7810_GAMEMASTER, // a few modifications until internal rom dumped
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TYPE_7807
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TYPE_7807
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// TYPE_78C10, // stop instruction added
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// TYPE_78C10, // stop instruction added
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// TYPE_78IV,
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// TYPE_78IV,
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