mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
Merge branch 'master' of https://github.com/mamedev/mame
This commit is contained in:
RobertoFresca
commit
f9b063306e
@ -17955,14 +17955,14 @@ Info from Atariage and Atarimania
|
||||
</part>
|
||||
</software>
|
||||
|
||||
<!-- This was released by the author, also available via Atariage, are both versions the same? needs DPC+ emulation -->
|
||||
<!-- This was released by the author, also available via Atariage, are both versions the same? needs HARMONY/MELODY emulation -->
|
||||
<software name="stayfr2" supported="no">
|
||||
<description>Stay Frosty 2 (NTSC)</description>
|
||||
<year>2013</year>
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="NTSC" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_dpcplus" />
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="SF2_20131217_RC8_NTSC.bin" size="0x8000" crc="4eb739ab" sha1="5eceaf8e90bd9a002f4935f082df7b25716dceb0" offset="0" />
|
||||
</dataarea>
|
||||
@ -17975,7 +17975,7 @@ Info from Atariage and Atarimania
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="NTSC" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_dpcplus" />
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="SF2_demo_NTSC.bin" size="0x8000" crc="fd850bd6" sha1="bd8166da7777c66e6bb3ab0c77563193d8289f5f" offset="0" />
|
||||
</dataarea>
|
||||
@ -17989,7 +17989,7 @@ Info from Atariage and Atarimania
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="PAL" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_dpcplus" />
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="SF2_20131217_RC8_PAL.bin" size="0x8000" crc="7b495dc3" sha1="1625ef74b0a48c2968fad832ab8e2edc8187a53f" offset="0" />
|
||||
</dataarea>
|
||||
@ -18002,13 +18002,80 @@ Info from Atariage and Atarimania
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="PAL" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_dpcplus" />
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="SF2_demo_PAL.bin" size="0x8000" crc="b47582f3" sha1="73625429e73f1b354e0cbe6a360d79590032de2b" offset="0" />
|
||||
</dataarea>
|
||||
</part>
|
||||
</software>
|
||||
|
||||
<software name="spcrocks" supported="no">
|
||||
<description>Space Rocks (RC7, NTSC)</description>
|
||||
<year>2012</year>
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="NTSC" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="spacerocks20121129_NTSC.bin" size="0x8000" crc="c5d8eb83" sha1="bf3af5c76bb4dded5cb9c9b232c369250ad20ac4" offset="0" />
|
||||
</dataarea>
|
||||
</part>
|
||||
</software>
|
||||
|
||||
<software name="spcrockse" cloneof="spcrocks" supported="no">
|
||||
<description>Space Rocks (RC7, PAL)</description>
|
||||
<year>2012</year>
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="PAL" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="spacerocks20121129_PAL.bin" size="0x8000" crc="133cb923" sha1="0511a35ee435227fbb5665e8488590eb993256f7" offset="0" />
|
||||
</dataarea>
|
||||
</part>
|
||||
</software>
|
||||
|
||||
<software name="frantic" supported="no">
|
||||
<description>Frantic (20140305, NTSC)</description>
|
||||
<year>2014</year>
|
||||
<publisher>Spiceware</publisher>
|
||||
<sharedfeat name="compatibility" value="NTSC" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="frantic20140305.bin" size="0x8000" crc="04d0f558" sha1="ee2a004a50861c5fdfbdabfa5ed4bf825333ec43" offset="0" />
|
||||
</dataarea>
|
||||
</part>
|
||||
</software>
|
||||
|
||||
<software name="harmbios" supported="no"> <!-- I think these are the bios roms if you're using it as a multi-game cart? -->
|
||||
<description>Harmony Bios Updater</description>
|
||||
<year>2014</year>
|
||||
<publisher>Harmony</publisher>
|
||||
<sharedfeat name="compatibility" value="NTSC" />
|
||||
<part name="cart" interface="a2600_cart">
|
||||
<feature name="slot" value="a26_harmony" />
|
||||
<dataarea name="rom" size="0x8000">
|
||||
<rom name="bios_updater_NTSC.cu" size="0x8000" crc="03153eb2" sha1="cd9ee1d820737b3887ebe5fc6fe96a2a043ab009" offset="0" />
|
||||
</dataarea>
|
||||
<dataarea name="bios" size="0x21400">
|
||||
<rom name="hbios_106_NTSC_official_beta.bin" size="0x21400" crc="1e1d237b" sha1="8fd74e0119bce43a89bcc4998b750bc6884971da" offset="0" />
|
||||
<rom name="hbios_106_NTSC_beta_2.bin" size="0x21400" crc="807b86bd" sha1="633960295c30e7430b3ce58f6244495f4b708e9d" offset="0" />
|
||||
<rom name="hbios_106_NTSC.bin" size="0x21400" crc="48664301" sha1="aaa5e839f307734306c2a9ccbe38482579c70391" offset="0" />
|
||||
|
||||
<rom name="hbios_105_NTSC.bin" size="0x19400" crc="c0b8aae9" sha1="68b10153695da505756eb7dc7cc4a7e93fe68860" offset="0" />
|
||||
<rom name="hbios_105_PAL50.bin" size="0x19400" crc="fb942c80" sha1="81bba9d9c245d23cc4b9503180ebe2d67bf1e117" offset="0" />
|
||||
<rom name="hbios_105_PAL60.bin" size="0x19400" crc="b59ebe6d" sha1="873830286c66935fd23e3ea7c192e6573e056cbd" offset="0" />
|
||||
|
||||
<rom name="eeloader_104e_NTSC.bin" size="0x36f8" crc="ad04a8d9" sha1="c83d724299875cd5ea8d6be05db12d688ce8eff1" offset="0" />
|
||||
<rom name="eeloader_104e_PAL50.bin" size="0x36f8" crc="4868ba51" sha1="e6a65523824ecf4f2a5145e2c5118cfb4bee059d" offset="0" />
|
||||
<rom name="eeloader_104e_PAL60.bin" size="0x36f8" crc="58845532" sha1="255b5c9f4f2f7322c20d2619126cd150a1b8f71c" offset="0" />
|
||||
|
||||
</dataarea>
|
||||
|
||||
</part>
|
||||
</software>
|
||||
|
||||
</softwarelist>
|
||||
|
||||
|
||||
|
||||
@ -1161,8 +1161,8 @@ if (BUSES["VCS"]~=null) then
|
||||
MAME_DIR .. "src/devices/bus/vcs/compumat.h",
|
||||
MAME_DIR .. "src/devices/bus/vcs/dpc.c",
|
||||
MAME_DIR .. "src/devices/bus/vcs/dpc.h",
|
||||
MAME_DIR .. "src/devices/bus/vcs/dpcplus.c",
|
||||
MAME_DIR .. "src/devices/bus/vcs/dpcplus.h",
|
||||
MAME_DIR .. "src/devices/bus/vcs/harmony_melody.c",
|
||||
MAME_DIR .. "src/devices/bus/vcs/harmony_melody.h",
|
||||
MAME_DIR .. "src/devices/bus/vcs/scharger.c",
|
||||
MAME_DIR .. "src/devices/bus/vcs/scharger.h",
|
||||
}
|
||||
|
||||
@ -132,6 +132,8 @@ if (CPUS["ARM7"]~=null) then
|
||||
MAME_DIR .. "src/devices/cpu/arm7/arm7.h",
|
||||
MAME_DIR .. "src/devices/cpu/arm7/arm7thmb.c",
|
||||
MAME_DIR .. "src/devices/cpu/arm7/arm7ops.c",
|
||||
MAME_DIR .. "src/devices/cpu/arm7/lpc210x.c",
|
||||
MAME_DIR .. "src/devices/cpu/arm7/lpc210x.h",
|
||||
}
|
||||
end
|
||||
|
||||
@ -1134,6 +1136,7 @@ end
|
||||
--@src/devices/cpu/m6502/r65c02.h,CPUS["M6502"] = true
|
||||
--@src/devices/cpu/m6502/m65sc02.h,CPUS["M6502"] = true
|
||||
--@src/devices/cpu/m6502/m6504.h,CPUS["M6502"] = true
|
||||
--@src/devices/cpu/m6502/m6507.h,CPUS["M6502"] = true
|
||||
--@src/devices/cpu/m6502/m6509.h,CPUS["M6502"] = true
|
||||
--@src/devices/cpu/m6502/m6510.h,CPUS["M6502"] = true
|
||||
--@src/devices/cpu/m6502/m6510t.h,CPUS["M6502"] = true
|
||||
@ -1162,6 +1165,8 @@ if (CPUS["M6502"]~=null) then
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m65sc02.h",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6504.c",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6504.h",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6507.c",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6507.h",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6509.c",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6509.h",
|
||||
MAME_DIR .. "src/devices/cpu/m6502/m6510.c",
|
||||
|
||||
@ -1,98 +0,0 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:
|
||||
/***************************************************************************
|
||||
|
||||
Atari 2600 cart with DPC+
|
||||
|
||||
the DPC+ adds an ARM CPU amongst other things (display improvements, etc.)
|
||||
|
||||
map (according to a blogpost on atariage):
|
||||
NOTE: All banks are accessible via $F000
|
||||
|
||||
* ARM RAM mapped at $40000000 in this area
|
||||
$0000-$0BFF: DPC+ driver (not accessible by 2600 itself)
|
||||
$0C00-$1BFF: Bank 0
|
||||
$1C00-$2BFF: Bank 1
|
||||
$2C00-$3BFF: Bank 2
|
||||
$3C00-$4BFF: Bank 3
|
||||
$4C00-$5BFF: Bank 4
|
||||
$5C00-$6BFF: Bank 5
|
||||
* ARM RAM mapped at $40000C00 in this area
|
||||
$6C00-$7BFF: Display Data (indirect access)
|
||||
* ARM RAM mapped at $40001C00 in this area
|
||||
$7C00-$7FFF: Frequency Data (not accessible by 2600 itself)
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
#include "emu.h"
|
||||
#include "dpcplus.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// cart device
|
||||
|
||||
const device_type A26_ROM_DPCPLUS = &device_creator<a26_rom_dpcplus_device>;
|
||||
|
||||
|
||||
a26_rom_dpcplus_device::a26_rom_dpcplus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: a26_rom_f8_device(mconfig, A26_ROM_DPCPLUS, "Atari 2600 ROM Cart DPC+", tag, owner, clock, "a2600_dpcplus", __FILE__)
|
||||
{
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// mapper specific start/reset
|
||||
//-------------------------------------------------
|
||||
|
||||
void a26_rom_dpcplus_device::device_start()
|
||||
{
|
||||
save_item(NAME(m_base_bank));
|
||||
}
|
||||
|
||||
void a26_rom_dpcplus_device::device_reset()
|
||||
{
|
||||
m_base_bank = 0;
|
||||
}
|
||||
|
||||
READ32_MEMBER(a26_rom_dpcplus_device::armrom_r)
|
||||
{
|
||||
UINT32 ret = (a26_rom_f8_device::read_rom(space, offset * 4 + 3) << 24) |
|
||||
(a26_rom_f8_device::read_rom(space, offset * 4 + 2) << 16) |
|
||||
(a26_rom_f8_device::read_rom(space, offset * 4 + 1) << 8) |
|
||||
(a26_rom_f8_device::read_rom(space, offset * 4 + 0) << 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(a26_rom_dpcplus_device::armrom_w)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( dpcplus_arm7_map, AS_PROGRAM, 32, a26_rom_dpcplus_device )
|
||||
// todo: implement all this correctly
|
||||
AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w)// flash, 32k
|
||||
AM_RANGE(0x40000000, 0x40001fff) AM_RAM // sram, 8k
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( a26_dpcplus )
|
||||
MCFG_CPU_ADD("arm", ARM7, 70000000) // correct type?
|
||||
MCFG_CPU_PROGRAM_MAP(dpcplus_arm7_map)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
machine_config_constructor a26_rom_dpcplus_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( a26_dpcplus );
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(a26_rom_dpcplus_device::read_rom)
|
||||
{
|
||||
return a26_rom_f8_device::read_rom(space, offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(a26_rom_dpcplus_device::write_bank)
|
||||
{
|
||||
a26_rom_f8_device::write_bank(space, offset, data);
|
||||
}
|
||||
@ -1,38 +0,0 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:
|
||||
#ifndef __VCS_DPCPLUS_H
|
||||
#define __VCS_DPCPLUS_H
|
||||
|
||||
#include "rom.h"
|
||||
#include "cpu/arm7/arm7.h"
|
||||
|
||||
|
||||
// ======================> a26_rom_dpcplus_device
|
||||
|
||||
class a26_rom_dpcplus_device : public a26_rom_f8_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
a26_rom_dpcplus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual void device_reset();
|
||||
|
||||
// reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(read_rom);
|
||||
virtual DECLARE_WRITE8_MEMBER(write_bank);
|
||||
|
||||
DECLARE_READ32_MEMBER(armrom_r);
|
||||
DECLARE_WRITE32_MEMBER(armrom_w);
|
||||
|
||||
|
||||
protected:
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type A26_ROM_DPCPLUS;
|
||||
|
||||
#endif
|
||||
146
src/devices/bus/vcs/harmony_melody.c
Normal file
146
src/devices/bus/vcs/harmony_melody.c
Normal file
@ -0,0 +1,146 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:David Haywood
|
||||
/***************************************************************************
|
||||
|
||||
Harmony / Melody cart for the A2600
|
||||
|
||||
The Harmony cart is a 'modern' A2600 cartridge, used for homebrew etc. It has
|
||||
an SD slot and can be connected to a PC, roms can be transfered to it with
|
||||
software on the PC side. It uses an ARM7TDMI-S LPC2103 @ 70 Mhz to emulate
|
||||
the mapper behavior of other cartridges. It has an SD card slot for storing
|
||||
game data.
|
||||
|
||||
The Melody version of the cartridge has been used for several recent A2600
|
||||
commercial releases as well as some reproductions due to it's ability to be
|
||||
programmed as any other cartridge type. This lacks the SD slot?
|
||||
|
||||
The 'DPC+' games by SpiceWare run on a Harmony / Melody cart, DPC+ seems to
|
||||
be a virtual 'software mapper' programmed on the ARM rather than a real mapper.
|
||||
|
||||
|
||||
There is also a 'Harmony Encore' cartridge which adds support for some of the
|
||||
games the original couldn't handle due to them having larger ROMs and more
|
||||
complex banking schemes (Stella's Stocking etc.)
|
||||
|
||||
some Harmony cart details can be found at
|
||||
http://atariage.com/forums/topic/156500-latest-harmony-cart-software/
|
||||
|
||||
|
||||
DPC+ notes
|
||||
----------
|
||||
|
||||
Some info on the Harmony / Melody when configured as DPC+ hardware can be found on Darrell Spice Jr's guides:
|
||||
http://atariage.com/forums/blog/148/entry-11811-dpcarm-part-6-dpc-cartridge-layout/
|
||||
http://atariage.com/forums/blog/148/entry-11883-dpcarm-part-7-6507arm-exchange-of-information/
|
||||
http://atariage.com/forums/blog/148/entry-11903-dpcarm-part-8-multiple-functions/
|
||||
http://atariage.com/forums/blog/148/entry-11935-dpcarm-part-9-functional-menu/
|
||||
http://atariage.com/forums/blog/148/entry-11964-dpcarm-part-10-score-timer-display/
|
||||
http://atariage.com/forums/blog/148/entry-11988-dpcarm-part-12-gamepad-support/
|
||||
|
||||
map:
|
||||
Bankswitching uses addresses $FFF6-$FFFB
|
||||
|
||||
* ARM RAM mapped at $40000000 in this area
|
||||
$0000-$0BFF: HARMONY/MELODY driver (not accessible by 2600 itself) (copied to $40000000 - $40000bff on startup by ARM)
|
||||
$0C00-$1BFF: Bank 0 (each bank can map to 0x1000 - 0x1fff in 6507 space, like other carts)
|
||||
$1C00-$2BFF: Bank 1
|
||||
$2C00-$3BFF: Bank 2
|
||||
$3C00-$4BFF: Bank 3
|
||||
$4C00-$5BFF: Bank 4
|
||||
$5C00-$6BFF: Bank 5 (default bank is bank 5)
|
||||
$6C00-$7BFF: Display Data (indirect access) (copied to $40000C00 - $40001bff on startup by ARM)
|
||||
$7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) (copied to $40001C00 - $40001fff on startup by ARM)
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
#include "emu.h"
|
||||
#include "harmony_melody.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// cart device
|
||||
|
||||
const device_type A26_ROM_HARMONY = &device_creator<a26_rom_harmony_device>;
|
||||
|
||||
|
||||
a26_rom_harmony_device::a26_rom_harmony_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: a26_rom_f8_device(mconfig, A26_ROM_HARMONY, "Atari 2600 ROM Cart HARMONY/MELODY", tag, owner, clock, "a2600_harmony", __FILE__),
|
||||
m_cpu(*this, "arm")
|
||||
{
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// mapper specific start/reset
|
||||
//-------------------------------------------------
|
||||
|
||||
void a26_rom_harmony_device::device_start()
|
||||
{
|
||||
save_item(NAME(m_base_bank));
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( harmony_arm7_map, AS_PROGRAM, 32, a26_rom_harmony_device )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( a26_harmony )
|
||||
MCFG_CPU_ADD("arm", LPC2103, 70000000)
|
||||
MCFG_CPU_PROGRAM_MAP(harmony_arm7_map)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
machine_config_constructor a26_rom_harmony_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( a26_harmony );
|
||||
}
|
||||
|
||||
// actually if the ARM code is doing this and providing every opcode to the main CPU based
|
||||
// on bus activity then we shouldn't be doing and of this here (if the ROM is actually
|
||||
// the internal Flash rom of the ARM CPU then the A2600 CPU won't be able to see it directly
|
||||
// at all?)
|
||||
//
|
||||
// instead we need the ARM monitoring the bus at all times and supplying the code on
|
||||
// demand transparent to the main CPU? is this theory correct?
|
||||
|
||||
void a26_rom_harmony_device::device_reset()
|
||||
{
|
||||
m_base_bank = 5;
|
||||
|
||||
memcpy(m_cpu->m_flash, m_rom, 0x8000);
|
||||
m_cpu->reset();
|
||||
}
|
||||
|
||||
READ8_MEMBER(a26_rom_harmony_device::read8_r)
|
||||
{
|
||||
return m_rom[offset + (m_base_bank * 0x1000)];
|
||||
}
|
||||
|
||||
|
||||
void a26_rom_harmony_device::check_bankswitch(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
case 0x0FF6: m_base_bank = 0; break;
|
||||
case 0x0FF7: m_base_bank = 1; break;
|
||||
case 0x0FF8: m_base_bank = 2; break;
|
||||
case 0x0FF9: m_base_bank = 3; break;
|
||||
case 0x0FFa: m_base_bank = 4; break;
|
||||
case 0x0FFb: m_base_bank = 5; break;
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(a26_rom_harmony_device::read_rom)
|
||||
{
|
||||
UINT8 retvalue = read8_r(space, offset + 0xc00); // banks start at 0xc00
|
||||
|
||||
check_bankswitch(offset);
|
||||
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(a26_rom_harmony_device::write_bank)
|
||||
{
|
||||
check_bankswitch(offset);
|
||||
// a26_rom_f8_device::write_bank(space, offset, data);
|
||||
}
|
||||
42
src/devices/bus/vcs/harmony_melody.h
Normal file
42
src/devices/bus/vcs/harmony_melody.h
Normal file
@ -0,0 +1,42 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:David Haywood
|
||||
#ifndef __VCS_HARMONY_H
|
||||
#define __VCS_HARMONY_H
|
||||
|
||||
#include "rom.h"
|
||||
#include "cpu/arm7/lpc210x.h"
|
||||
|
||||
|
||||
// ======================> a26_rom_harmony_device
|
||||
|
||||
class a26_rom_harmony_device : public a26_rom_f8_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
a26_rom_harmony_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual void device_reset();
|
||||
|
||||
// reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(read_rom);
|
||||
virtual DECLARE_WRITE8_MEMBER(write_bank);
|
||||
|
||||
|
||||
DECLARE_READ8_MEMBER(read8_r);
|
||||
|
||||
void check_bankswitch(offs_t offset);
|
||||
|
||||
protected:
|
||||
|
||||
private:
|
||||
required_device<lpc210x_device> m_cpu;
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type A26_ROM_HARMONY;
|
||||
|
||||
#endif
|
||||
@ -157,7 +157,7 @@ static const vcs_slot slot_list[] =
|
||||
{ A26_8IN1, "a26_8in1" },
|
||||
{ A26_32IN1, "a26_32in1" },
|
||||
{ A26_X07, "a26_x07" },
|
||||
{ A26_DPCPLUS, "a26_dpcplus" },
|
||||
{ A26_HARMONY, "a26_harmony" },
|
||||
};
|
||||
|
||||
static int vcs_get_pcb_id(const char *slot)
|
||||
|
||||
@ -36,7 +36,7 @@ enum
|
||||
A26_SS,
|
||||
A26_CM,
|
||||
A26_X07,
|
||||
A26_DPCPLUS,
|
||||
A26_HARMONY,
|
||||
};
|
||||
|
||||
|
||||
|
||||
285
src/devices/cpu/arm7/lpc210x.c
Normal file
285
src/devices/cpu/arm7/lpc210x.c
Normal file
@ -0,0 +1,285 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:David Haywood
|
||||
/***************************************************************************
|
||||
|
||||
NXP (Phillips) LPC2103 series
|
||||
covering LPC2101, LPC2102, LPC2103*
|
||||
|
||||
*currently only LPC2103
|
||||
|
||||
these are based on an ARM7TDMI-S CPU
|
||||
internal flash and integrated peripherals
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "lpc210x.h"
|
||||
|
||||
const device_type LPC2103 = &device_creator<lpc210x_device>;
|
||||
|
||||
static ADDRESS_MAP_START( lpc2103_map, AS_PROGRAM, 32, lpc210x_device )
|
||||
AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(flash_r, flash_w) // 32kb internal FLASH rom
|
||||
|
||||
AM_RANGE(0x3FFFC000, 0x3FFFC01f) AM_READWRITE( fio_r, fio_w ) // GPIO
|
||||
|
||||
|
||||
AM_RANGE(0x40000000, 0x40001fff) AM_RAM // 8kb internal SROM (writes should actually latch - see docs)
|
||||
|
||||
AM_RANGE(0xE0004000, 0xE000407f) AM_READWRITE( timer0_r, timer0_w)
|
||||
|
||||
AM_RANGE(0xE0008000, 0xE000807f) AM_READWRITE( timer1_r, timer1_w)
|
||||
|
||||
AM_RANGE(0xE002C000, 0xE002C007) AM_READWRITE( pin_r, pin_w )
|
||||
|
||||
AM_RANGE(0xE01FC000, 0xE01FC007) AM_READWRITE( mam_r, mam_w )
|
||||
AM_RANGE(0xE01FC080, 0xE01FC08f) AM_READWRITE( pll_r, pll_w ) // phase locked loop
|
||||
AM_RANGE(0xE01FC100, 0xE01FC103) AM_READWRITE( apbdiv_r, apbdiv_w )
|
||||
AM_RANGE(0xE01FC1a0, 0xE01FC1a3) AM_READWRITE( scs_r, scs_w )
|
||||
|
||||
AM_RANGE(0xFFFFF000, 0xFFFFF2ff) AM_READWRITE( vic_r, vic_w ) // interrupt controller
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
lpc210x_device::lpc210x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: arm7_cpu_device(mconfig, LPC2103, "LPC2103", tag, owner, clock, "lpc2103", __FILE__, 4, eARM_ARCHFLAGS_T, ENDIANNESS_LITTLE),
|
||||
m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0, ADDRESS_MAP_NAME(lpc2103_map))
|
||||
{
|
||||
}
|
||||
|
||||
READ32_MEMBER(lpc210x_device::arm_E01FC088_r)
|
||||
{
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
READ32_MEMBER(lpc210x_device::flash_r)
|
||||
{
|
||||
UINT32 ret = (m_flash[offset * 4 + 3] << 24) |
|
||||
(m_flash[offset * 4 + 2] << 16) |
|
||||
(m_flash[offset * 4 + 1] << 8) |
|
||||
(m_flash[offset * 4 + 0] << 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(lpc210x_device::flash_w)
|
||||
{
|
||||
//
|
||||
}
|
||||
|
||||
|
||||
const address_space_config *lpc210x_device::memory_space_config(address_spacenum spacenum) const
|
||||
{
|
||||
switch(spacenum)
|
||||
{
|
||||
case AS_PROGRAM: return &m_program_config;
|
||||
default: return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_start - device-specific startup
|
||||
//-------------------------------------------------
|
||||
|
||||
void lpc210x_device::device_start()
|
||||
{
|
||||
arm7_cpu_device::device_start();
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_reset - device-specific reset
|
||||
//-------------------------------------------------
|
||||
|
||||
void lpc210x_device::device_reset()
|
||||
{
|
||||
arm7_cpu_device::device_reset();
|
||||
|
||||
m_TxPR[0] = 0;
|
||||
m_TxPR[1] = 0;
|
||||
}
|
||||
|
||||
/* VIC (Vectored Interrupt Controller) */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::vic_r )
|
||||
{
|
||||
switch (offset*4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled read from VIC offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
|
||||
}
|
||||
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::vic_w )
|
||||
{
|
||||
switch (offset * 4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled write VIC offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* PIN Select block */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::pin_r )
|
||||
{
|
||||
switch (offset*4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled read from PINSEL offset %08x mem_mask %08x\n",space.device().safe_pc(), offset * 4, mem_mask);
|
||||
}
|
||||
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::pin_w )
|
||||
{
|
||||
switch (offset * 4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled write PINSEL offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* MAM block (memory conttroller) */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::mam_r )
|
||||
{
|
||||
switch (offset*4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled read from MAM offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
|
||||
}
|
||||
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::mam_w )
|
||||
{
|
||||
switch (offset * 4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled write MAM offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* FIO block */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::fio_r )
|
||||
{
|
||||
switch (offset*4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled read from FIO offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
|
||||
}
|
||||
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::fio_w )
|
||||
{
|
||||
switch (offset * 4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled write FIO offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* APB Divider */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::apbdiv_r )
|
||||
{
|
||||
logerror("%08x unhandled read from APBDIV offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::apbdiv_w )
|
||||
{
|
||||
logerror("%08x unhandled write APBDIV offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask);
|
||||
}
|
||||
|
||||
/* Syscon misc registers */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::scs_r )
|
||||
{
|
||||
logerror("%08x unhandled read from SCS offset %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, mem_mask);
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::scs_w )
|
||||
{
|
||||
logerror("%08x unhandled write SCS offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask);
|
||||
}
|
||||
|
||||
/* PLL Phase Locked Loop */
|
||||
|
||||
READ32_MEMBER( lpc210x_device::pll_r )
|
||||
{
|
||||
switch (offset*4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled read from PLL offset %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, mem_mask);
|
||||
}
|
||||
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER( lpc210x_device::pll_w )
|
||||
{
|
||||
switch (offset * 4)
|
||||
{
|
||||
default:
|
||||
logerror("%08x unhandled write PLL offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Timers */
|
||||
|
||||
UINT32 lpc210x_device::read_timer(address_space &space, int timer, int offset, UINT32 mem_mask)
|
||||
{
|
||||
switch (offset*4)
|
||||
{
|
||||
case 0x0c:
|
||||
return m_TxPR[timer];
|
||||
|
||||
default:
|
||||
logerror("%08x unhandled read from timer %d offset %02x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, mem_mask);
|
||||
}
|
||||
|
||||
return 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
void lpc210x_device::write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask)
|
||||
{
|
||||
switch (offset * 4)
|
||||
{
|
||||
case 0x0c:
|
||||
COMBINE_DATA(&m_TxPR[timer]);
|
||||
logerror("%08x Timer %d Prescale Register set to %08x\n", space.device().safe_pc(),timer, m_TxPR[timer]);
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("%08x unhandled write timer %d offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( lpc210x )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
machine_config_constructor lpc210x_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( lpc210x );
|
||||
}
|
||||
104
src/devices/cpu/arm7/lpc210x.h
Normal file
104
src/devices/cpu/arm7/lpc210x.h
Normal file
@ -0,0 +1,104 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:David Haywood
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __LPC2103__
|
||||
#define __LPC2103__
|
||||
|
||||
#include "emu.h"
|
||||
#include "arm7.h"
|
||||
#include "arm7core.h"
|
||||
|
||||
/***************************************************************************
|
||||
DEVICE CONFIGURATION MACROS
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
TYPE DEFINITIONS
|
||||
***************************************************************************/
|
||||
|
||||
class lpc210x_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
lpc210x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
|
||||
|
||||
// static configuration helpers
|
||||
|
||||
// todo, use an appropriate flash type instead
|
||||
UINT8 m_flash[0x8000];
|
||||
|
||||
|
||||
DECLARE_READ32_MEMBER(arm_E01FC088_r);
|
||||
DECLARE_READ32_MEMBER(flash_r);
|
||||
DECLARE_WRITE32_MEMBER(flash_w);
|
||||
|
||||
// timer 0 / 1
|
||||
DECLARE_READ32_MEMBER(timer0_r) { return read_timer(space, 0, offset, mem_mask); }
|
||||
DECLARE_WRITE32_MEMBER(timer0_w) { write_timer(space, 0, offset, data, mem_mask); }
|
||||
|
||||
DECLARE_READ32_MEMBER(timer1_r) { return read_timer(space, 1, offset, mem_mask); }
|
||||
DECLARE_WRITE32_MEMBER(timer1_w) { write_timer(space, 1, offset, data, mem_mask); }
|
||||
|
||||
void write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask);
|
||||
UINT32 read_timer(address_space &space, int timer, int offset, UINT32 mem_mask);
|
||||
|
||||
UINT32 m_TxPR[2];
|
||||
|
||||
// VIC
|
||||
DECLARE_READ32_MEMBER(vic_r);
|
||||
DECLARE_WRITE32_MEMBER(vic_w);
|
||||
|
||||
// PIN select block
|
||||
DECLARE_READ32_MEMBER(pin_r);
|
||||
DECLARE_WRITE32_MEMBER(pin_w);
|
||||
|
||||
//PLL Phase Locked Loop
|
||||
DECLARE_READ32_MEMBER(pll_r);
|
||||
DECLARE_WRITE32_MEMBER(pll_w);
|
||||
|
||||
//MAM memory controller
|
||||
DECLARE_READ32_MEMBER(mam_r);
|
||||
DECLARE_WRITE32_MEMBER(mam_w);
|
||||
|
||||
//APB divider
|
||||
DECLARE_READ32_MEMBER(apbdiv_r);
|
||||
DECLARE_WRITE32_MEMBER(apbdiv_w);
|
||||
|
||||
//syscon misc
|
||||
DECLARE_READ32_MEMBER(scs_r);
|
||||
DECLARE_WRITE32_MEMBER(scs_w);
|
||||
|
||||
// fio
|
||||
DECLARE_READ32_MEMBER(fio_r);
|
||||
DECLARE_WRITE32_MEMBER(fio_w);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
private:
|
||||
address_space_config m_program_config;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type LPC2103;
|
||||
|
||||
|
||||
#endif /// __LPC2103__
|
||||
61
src/devices/cpu/m6502/m6507.c
Normal file
61
src/devices/cpu/m6502/m6507.c
Normal file
@ -0,0 +1,61 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
/***************************************************************************
|
||||
|
||||
m6507.c
|
||||
|
||||
Mostek 6502, NMOS variant with reduced address bus
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "m6507.h"
|
||||
|
||||
const device_type M6507 = &device_creator<m6507_device>;
|
||||
|
||||
m6507_device::m6507_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
|
||||
m6502_device(mconfig, M6507, "M6507", tag, owner, clock, "m6507", __FILE__)
|
||||
{
|
||||
program_config.m_addrbus_width = 13;
|
||||
sprogram_config.m_addrbus_width = 13;
|
||||
}
|
||||
|
||||
void m6507_device::device_start()
|
||||
{
|
||||
if(direct_disabled)
|
||||
mintf = new mi_6507_nd;
|
||||
else
|
||||
mintf = new mi_6507_normal;
|
||||
|
||||
init();
|
||||
}
|
||||
|
||||
UINT8 m6507_device::mi_6507_normal::read(UINT16 adr)
|
||||
{
|
||||
return program->read_byte(adr & 0x1fff);
|
||||
}
|
||||
|
||||
UINT8 m6507_device::mi_6507_normal::read_sync(UINT16 adr)
|
||||
{
|
||||
return sdirect->read_byte(adr & 0x1fff);
|
||||
}
|
||||
|
||||
UINT8 m6507_device::mi_6507_normal::read_arg(UINT16 adr)
|
||||
{
|
||||
return direct->read_byte(adr & 0x1fff);
|
||||
}
|
||||
|
||||
void m6507_device::mi_6507_normal::write(UINT16 adr, UINT8 val)
|
||||
{
|
||||
program->write_byte(adr & 0x1fff, val);
|
||||
}
|
||||
|
||||
UINT8 m6507_device::mi_6507_nd::read_sync(UINT16 adr)
|
||||
{
|
||||
return sprogram->read_byte(adr & 0x1fff);
|
||||
}
|
||||
|
||||
UINT8 m6507_device::mi_6507_nd::read_arg(UINT16 adr)
|
||||
{
|
||||
return program->read_byte(adr & 0x1fff);
|
||||
}
|
||||
49
src/devices/cpu/m6502/m6507.h
Normal file
49
src/devices/cpu/m6502/m6507.h
Normal file
@ -0,0 +1,49 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
/***************************************************************************
|
||||
|
||||
m6507.h
|
||||
|
||||
Mostek 6502, NMOS variant with reduced address bus
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __M6507_H__
|
||||
#define __M6507_H__
|
||||
|
||||
#include "m6502.h"
|
||||
|
||||
class m6507_device : public m6502_device {
|
||||
public:
|
||||
m6507_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
protected:
|
||||
class mi_6507_normal : public memory_interface {
|
||||
public:
|
||||
virtual ~mi_6507_normal() {}
|
||||
virtual UINT8 read(UINT16 adr);
|
||||
virtual UINT8 read_sync(UINT16 adr);
|
||||
virtual UINT8 read_arg(UINT16 adr);
|
||||
virtual void write(UINT16 adr, UINT8 val);
|
||||
};
|
||||
|
||||
class mi_6507_nd : public mi_6507_normal {
|
||||
public:
|
||||
virtual ~mi_6507_nd() {}
|
||||
virtual UINT8 read_sync(UINT16 adr);
|
||||
virtual UINT8 read_arg(UINT16 adr);
|
||||
};
|
||||
|
||||
virtual void device_start();
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
M6507_IRQ_LINE = m6502_device::IRQ_LINE,
|
||||
M6507_NMI_LINE = m6502_device::NMI_LINE,
|
||||
M6507_SET_OVERFLOW = m6502_device::V_LINE
|
||||
};
|
||||
|
||||
extern const device_type M6507;
|
||||
|
||||
#endif
|
||||
@ -3120,6 +3120,7 @@ leds2011u // 1988 (c) 1988 (US)
|
||||
|
||||
// Capcom CPS1 games
|
||||
forgottn // 7/1988 (c) 1988 (World)
|
||||
forgottna // 7/1988 (c) 1988 (World)
|
||||
forgottnu // 7/1988 (c) 1988 (USA)
|
||||
forgottnu1 // 7/1988 (c) 1988 (USA)
|
||||
forgottnua // 7/1988 (c) 1988 (USA)
|
||||
@ -11399,6 +11400,7 @@ pepp0045 // (c) 1987 IGT - International Game Technology
|
||||
pepp0045a // (c) 1987 IGT - International Game Technology
|
||||
pepp0045b // (c) 1987 IGT - International Game Technology
|
||||
pepp0045c // (c) 1987 IGT - International Game Technology
|
||||
pepp0045d // (c) 1987 IGT - International Game Technology
|
||||
pepp0046 // (c) 1987 IGT - International Game Technology
|
||||
pepp0046a // (c) 1987 IGT - International Game Technology
|
||||
pepp0046b // (c) 1987 IGT - International Game Technology
|
||||
|
||||
@ -12,13 +12,13 @@ TODO:
|
||||
|
||||
#include "emu.h"
|
||||
#include "machine/mos6530n.h"
|
||||
#include "cpu/m6502/m6502.h"
|
||||
#include "cpu/m6502/m6507.h"
|
||||
#include "sound/tiaintf.h"
|
||||
#include "video/tia.h"
|
||||
#include "bus/vcs/vcs_slot.h"
|
||||
#include "bus/vcs/rom.h"
|
||||
#include "bus/vcs/dpc.h"
|
||||
#include "bus/vcs/dpcplus.h"
|
||||
#include "bus/vcs/harmony_melody.h"
|
||||
#include "bus/vcs/scharger.h"
|
||||
#include "bus/vcs/compumat.h"
|
||||
#include "bus/vcs_ctrl/ctrl.h"
|
||||
@ -70,7 +70,7 @@ protected:
|
||||
required_device<tia_video_device> m_tia;
|
||||
|
||||
unsigned long detect_2600controllers();
|
||||
required_device<m6502_device> m_maincpu;
|
||||
required_device<m6507_device> m_maincpu;
|
||||
required_device<screen_device> m_screen;
|
||||
required_ioport m_swb;
|
||||
required_device<mos6532_t> m_riot;
|
||||
@ -85,8 +85,7 @@ protected:
|
||||
static const UINT16 supported_screen_heights[4] = { 262, 312, 328, 342 };
|
||||
|
||||
|
||||
static ADDRESS_MAP_START(a2600_mem, AS_PROGRAM, 8, a2600_state )
|
||||
ADDRESS_MAP_GLOBAL_MASK(0x1fff)
|
||||
static ADDRESS_MAP_START(a2600_mem, AS_PROGRAM, 8, a2600_state ) // 6507 has 13-bit address space, 0x0000 - 0x1fff
|
||||
AM_RANGE(0x0000, 0x007f) AM_MIRROR(0x0f00) AM_DEVREADWRITE("tia_video", tia_video_device, read, write)
|
||||
AM_RANGE(0x0080, 0x00ff) AM_MIRROR(0x0d00) AM_RAM AM_SHARE("riot_ram")
|
||||
AM_RANGE(0x0280, 0x029f) AM_MIRROR(0x0d00) AM_DEVICE("riot", mos6532_t, io_map)
|
||||
@ -391,7 +390,7 @@ MACHINE_START_MEMBER(a2600_state,a2600)
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x1000, 0x1fff, read8_delegate(FUNC(vcs_cart_slot_device::read_rom),(vcs_cart_slot_device*)m_cart), write8_delegate(FUNC(vcs_cart_slot_device::write_bank),(vcs_cart_slot_device*)m_cart));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x0000, 0x0fff, read8_delegate(FUNC(a2600_state::cart_over_all_r), this), write8_delegate(FUNC(a2600_state::cart_over_all_w), this));
|
||||
break;
|
||||
case A26_DPCPLUS:
|
||||
case A26_HARMONY:
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x1000, 0x1fff, read8_delegate(FUNC(vcs_cart_slot_device::read_rom),(vcs_cart_slot_device*)m_cart), write8_delegate(FUNC(vcs_cart_slot_device::write_bank),(vcs_cart_slot_device*)m_cart));
|
||||
break;
|
||||
}
|
||||
@ -528,7 +527,7 @@ static SLOT_INTERFACE_START(a2600_cart)
|
||||
SLOT_INTERFACE_INTERNAL("a26_8in1", A26_ROM_8IN1)
|
||||
SLOT_INTERFACE_INTERNAL("a26_32in1", A26_ROM_32IN1)
|
||||
SLOT_INTERFACE_INTERNAL("a26_x07", A26_ROM_X07)
|
||||
SLOT_INTERFACE_INTERNAL("a26_dpcplus", A26_ROM_DPCPLUS)
|
||||
SLOT_INTERFACE_INTERNAL("a26_harmony", A26_ROM_HARMONY)
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT(a2600_cartslot)
|
||||
@ -541,7 +540,7 @@ MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( a2600, a2600_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M6502, MASTER_CLOCK_NTSC / 3) /* actually M6507 */
|
||||
MCFG_CPU_ADD("maincpu", M6507, MASTER_CLOCK_NTSC / 3)
|
||||
MCFG_M6502_DISABLE_DIRECT()
|
||||
MCFG_CPU_PROGRAM_MAP(a2600_mem)
|
||||
|
||||
@ -581,7 +580,7 @@ MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( a2600p, a2600_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M6502, MASTER_CLOCK_PAL / 3) /* actually M6507 */
|
||||
MCFG_CPU_ADD("maincpu", M6507, MASTER_CLOCK_PAL / 3)
|
||||
MCFG_CPU_PROGRAM_MAP(a2600_mem)
|
||||
MCFG_M6502_DISABLE_DIRECT()
|
||||
|
||||
|
||||
@ -3284,12 +3284,10 @@ MACHINE_CONFIG_END
|
||||
|
||||
/* B-Board 88621B-2 */
|
||||
/*
|
||||
These ROMs read from a dead and very unique top board. All EPROMs are type 27C1000, except LW_00.13C which is a 27C512.
|
||||
There are 5 surface mounted ROMs each on it's own small 88621B-sub satellite board, type HN62404FP-18 package is QFP44.
|
||||
There are 4 surface mounted ROMs each on it's own small 88621B-sub satellite board, type HN62404FP-18 package is QFP44.
|
||||
The ROMs on the satellite boards are named and located as follows:
|
||||
|
||||
LW-02 @ 6B
|
||||
LW-05 @ 6D
|
||||
LW-08 @ 9B
|
||||
LW-06 @ 9D
|
||||
LW-07 @ 10G
|
||||
@ -3301,6 +3299,82 @@ MACHINE_CONFIG_END
|
||||
*/
|
||||
/* Note that ROMs are labeled left to right, top to bottom, instead of top to bottom, left to right as usual. */
|
||||
ROM_START( forgottn )
|
||||
ROM_REGION( CODE_SIZE, "maincpu", 0 )
|
||||
ROM_LOAD16_BYTE( "lw40.12f", 0x00000, 0x20000, CRC(73e920b7) SHA1(2df12fc1a66f488d06b0927db909da81466d7d07) ) /* Higher program numbers indicates a later revision */
|
||||
ROM_LOAD16_BYTE( "lw41.12h", 0x00001, 0x20000, CRC(58210b9e) SHA1(416cb56a81e74fce6f86c2b2519ba620457b785a) ) /* 1 byte difference: 0x66D4 == 0x0C versus 0x04 in lw15.12h below */
|
||||
ROM_LOAD16_BYTE( "lw42.13f", 0x40000, 0x20000, CRC(bea45994) SHA1(c419f65c5e0c11ae7508ec54412bf6b62fac4f72) )
|
||||
ROM_LOAD16_BYTE( "lw43.13h", 0x40001, 0x20000, CRC(539b2339) SHA1(8a9e452ef8ed05e0b956d36990266657d3077470) )
|
||||
ROM_LOAD16_WORD_SWAP( "lw-07.10g", 0x80000, 0x80000, CRC(fd252a26) SHA1(5cfb097984912a5167a8c7ec4c2e119b642f9970) ) // == lw-07.13e
|
||||
|
||||
ROM_REGION( 0x400000, "gfx", 0 )
|
||||
ROMX_LOAD( "lw_2.2b", 0x000000, 0x20000, CRC(4bd75fee) SHA1(c27bfba951a0dc4f493937ceca335c50a1afeddf) , ROM_SKIP(7) ) // == lw-01.9d
|
||||
ROMX_LOAD( "lw_1.2a", 0x000001, 0x20000, CRC(65f41485) SHA1(fb05dffc87ee2f2b1b6646d54b13671f8eee0429) , ROM_SKIP(7) ) // == lw-01.9d
|
||||
ROMX_LOAD( "lw-08.9b", 0x000002, 0x80000, CRC(25a8e43c) SHA1(d57cee1fc508db2677e84882fb814e4d9ad20543) , ROM_GROUPWORD | ROM_SKIP(6) ) // == lw-08.9f
|
||||
ROMX_LOAD( "lw_18.5e", 0x000004, 0x20000, CRC(b4b6241b) SHA1(92b6b530e18ce27ba8739ebba0d8096b1551026c) , ROM_SKIP(7) )
|
||||
ROMX_LOAD( "lw_17.5c", 0x000005, 0x20000, CRC(c5eea115) SHA1(22fe692eaf9dd00a56a76f46c19fb76bb5e5f0d6) , ROM_SKIP(7) )
|
||||
ROMX_LOAD( "lw_30.8h", 0x000006, 0x20000, CRC(b385954e) SHA1(d33adb5842e7b85d304836bd92a7a96be4ff3694) , ROM_SKIP(7) ) // == lw-12.9g
|
||||
ROMX_LOAD( "lw_29.8f", 0x000007, 0x20000, CRC(7bda1ac6) SHA1(5b8bd05f52798f98ae16efa2ff61c06e28a4e3a0) , ROM_SKIP(7) ) // == lw-12.9g
|
||||
ROMX_LOAD( "lw_4.3b", 0x100000, 0x20000, CRC(50cf757f) SHA1(c70d7d34ac2d6671d40dd372e241ccb60bf3bf2b) , ROM_SKIP(7) ) // == lw-01.9d
|
||||
ROMX_LOAD( "lw_3.3a", 0x100001, 0x20000, CRC(c03ef278) SHA1(ad33b01bd8194025a2ecf7755894d6d638da457a) , ROM_SKIP(7) ) // == lw-01.9d
|
||||
ROMX_LOAD( "lw_20.7e", 0x100004, 0x20000, CRC(df1a3665) SHA1(7ba9c0edc64d4f9a8563533ce723a0a748352a15) , ROM_SKIP(7) )
|
||||
ROMX_LOAD( "lw_19.7c", 0x100005, 0x20000, CRC(15af8440) SHA1(5afd0e833593f1a78487af489fe4384ab68f52b1) , ROM_SKIP(7) )
|
||||
ROMX_LOAD( "lw_32.9h", 0x100006, 0x20000, CRC(30967a15) SHA1(6f6c6ca2f40aa9beec63ed64f0571bebc7c1aa50) , ROM_SKIP(7) ) // == lw-12.9g
|
||||
ROMX_LOAD( "lw_31.9f", 0x100007, 0x20000, CRC(c49d37fb) SHA1(ce400261a0f8d5a9b95d3823f8f52de87b8007f1) , ROM_SKIP(7) ) // == lw-12.9g
|
||||
ROMX_LOAD( "lw-02.6b", 0x200000, 0x80000, CRC(43e6c5c8) SHA1(d3e6c971de0477ec4e178adc82508208dd8b397f) , ROM_GROUPWORD | ROM_SKIP(6) ) // == lw-02.12d
|
||||
ROMX_LOAD( "lw_14.10b", 0x200002, 0x20000, CRC(82862cce) SHA1(727ca4ee55e076185b071a49afc87533fde9ec27) , ROM_SKIP(7) ) // == lw-09.12f
|
||||
ROMX_LOAD( "lw_13.10a", 0x200003, 0x20000, CRC(b81c0e96) SHA1(09f4235786b8ff92a57112669c0385b64477eb01) , ROM_SKIP(7) ) // == lw-09.12f
|
||||
ROMX_LOAD( "lw-06.9d", 0x200004, 0x80000, CRC(5b9edffc) SHA1(6fd8f4a3ab070733b52365ab1945bf86acb2bf62) , ROM_GROUPWORD | ROM_SKIP(6) ) // == lw-06.12e
|
||||
ROMX_LOAD( "lw_26.10e", 0x200006, 0x20000, CRC(57bcd032) SHA1(6db0f96fb909ed02fe4b7ee25fe662ea23f884d2) , ROM_SKIP(7) ) // == lw-13.12g
|
||||
ROMX_LOAD( "lw_25.10c", 0x200007, 0x20000, CRC(bac91554) SHA1(52f5de144193e0f78b9824cc8fd6f934dc19bab0) , ROM_SKIP(7) ) // == lw-13.12g
|
||||
ROMX_LOAD( "lw_16.11b", 0x300002, 0x20000, CRC(40b26554) SHA1(b4b27573d6c329bc2bc4c64fd857475bf2a10877) , ROM_SKIP(7) ) // == lw-09.12f
|
||||
ROMX_LOAD( "lw_15.11a", 0x300003, 0x20000, CRC(1b7d2e07) SHA1(0edf4d4b314fd9c29e7915d5d1adef6f9617f921) , ROM_SKIP(7) ) // == lw-09.12f
|
||||
ROMX_LOAD( "lw_28.11e", 0x300006, 0x20000, CRC(a805ad30) SHA1(baded4ab5fe4e87d53233b5df88edc693c292fc4) , ROM_SKIP(7) ) // == lw-13.12g
|
||||
ROMX_LOAD( "lw_27.11c", 0x300007, 0x20000, CRC(103c1bd2) SHA1(fc7ce74e108c30554139e55651c5348b11e9e3bd) , ROM_SKIP(7) ) // == lw-13.12g
|
||||
|
||||
ROM_REGION( 0x8000, "stars", 0 )
|
||||
ROM_COPY( "gfx", 0x200000, 0x000000, 0x8000 )
|
||||
|
||||
ROM_REGION( 0x18000, "audiocpu", 0 )
|
||||
ROM_LOAD( "lw_37.13c", 0x00000, 0x08000, CRC(59df2a63) SHA1(dfe1fffc7a17179a80a2ae623e93b30a7d6df20d) ) // == lw_00b.13c
|
||||
ROM_CONTINUE( 0x10000, 0x08000 )
|
||||
|
||||
ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
|
||||
ROM_LOAD( "lw-03u.12e", 0x00000, 0x20000, CRC(807d051f) SHA1(720e4733787b9b11f4d1cdce0892b69475802844) ) // == lw-03u.14c
|
||||
ROM_LOAD( "lw-04u.13e", 0x20000, 0x20000, CRC(e6cd098e) SHA1(667f6e5736f76a1c4c450c4e2035574ea89d7910) ) // == lw-04u.13c
|
||||
|
||||
ROM_REGION( 0x0200, "aboardplds", 0 )
|
||||
ROM_LOAD( "buf1", 0x0000, 0x0117, CRC(eb122de7) SHA1(b26b5bfe258e3e184f069719f9fd008d6b8f6b9b) )
|
||||
ROM_LOAD( "ioa1", 0x0000, 0x0117, CRC(59c7ee3b) SHA1(fbb887c5b4f5cb8df77cec710eaac2985bc482a6) )
|
||||
ROM_LOAD( "prg1", 0x0000, 0x0117, CRC(f1129744) SHA1(a5300f301c1a08a7da768f0773fa0fe3f683b237) )
|
||||
ROM_LOAD( "rom1", 0x0000, 0x0117, CRC(41dc73b9) SHA1(7d4c9f1693c821fbf84e32dd6ef62ddf14967845) )
|
||||
ROM_LOAD( "sou1", 0x0000, 0x0117, CRC(84f4b2fe) SHA1(dcc9e86cc36316fe42eace02d6df75d08bc8bb6d) )
|
||||
|
||||
ROM_REGION( 0x0200, "bboardplds", 0 )
|
||||
ROM_LOAD( "lw621.1a", 0x0000, 0x0117, CRC(5eec6ce9) SHA1(5ec8b60f1f1bdba865b1fa2387987ce99ff4093a) )
|
||||
ROM_LOAD( "lwio.12b", 0x0000, 0x0117, CRC(ad52b90c) SHA1(f0fd6aeea515ee449320fe15684e6b3ab7f97bf4) )
|
||||
ROM_END
|
||||
|
||||
/* B-Board 88621B-2 */
|
||||
/*
|
||||
These ROMs read from a dead and very unique top board. All EPROMs are type 27C1000, except LW_00.13C which is a 27C512.
|
||||
There are 5 surface mounted ROMs each on it's own small 88621B-sub satellite board, type HN62404FP-18 package is QFP44.
|
||||
The ROMs on the satellite boards are named and located as follows:
|
||||
|
||||
LW-02 @ 6B
|
||||
LW-05 @ 6D (instead of LW_17.5C, LW_18.5E, LW_19.7C & LW_20.7E as above)
|
||||
LW-08 @ 9B
|
||||
LW-06 @ 9D
|
||||
LW-07 @ 10G
|
||||
|
||||
Also known to have LW-13 @ 10D instead of LW_25.10C, LW_26.10E, LW_27.11C & LW_28.11E
|
||||
|
||||
OTHER:
|
||||
2 PALs labeled LW621 (near LW_1.2A) and LWI0 (near LW_00.13C)
|
||||
Custom chip - CAPCOM CPS-B-01 (QFP160)
|
||||
NEC D4701AC
|
||||
*/
|
||||
/* Note that ROMs are labeled left to right, top to bottom, instead of top to bottom, left to right as usual. */
|
||||
ROM_START( forgottna )
|
||||
ROM_REGION( CODE_SIZE, "maincpu", 0 )
|
||||
ROM_LOAD16_BYTE( "lw11.12f", 0x00000, 0x20000, CRC(73e920b7) SHA1(2df12fc1a66f488d06b0927db909da81466d7d07) )
|
||||
ROM_LOAD16_BYTE( "lw15.12h", 0x00001, 0x20000, CRC(50d7012d) SHA1(f82a28a835f0a83b26c2c8170b824447b1d7409f) )
|
||||
@ -11748,7 +11822,8 @@ WRITE16_MEMBER( cps_state::sf2m3_layer_w )
|
||||
|
||||
/*************************************************** Game Macros *****************************************************/
|
||||
|
||||
GAME( 1988, forgottn, 0, cps1_10MHz, forgottn, cps_state, forgottn, ROT0, "Capcom", "Forgotten Worlds (World)", MACHINE_SUPPORTS_SAVE ) // (c) Capcom U.S.A. but World "warning"
|
||||
GAME( 1988, forgottn, 0, cps1_10MHz, forgottn, cps_state, forgottn, ROT0, "Capcom", "Forgotten Worlds (World, newer)", MACHINE_SUPPORTS_SAVE ) // (c) Capcom U.S.A. but World "warning"
|
||||
GAME( 1988, forgottna, forgottn, cps1_10MHz, forgottn, cps_state, forgottn, ROT0, "Capcom", "Forgotten Worlds (World)", MACHINE_SUPPORTS_SAVE ) // (c) Capcom U.S.A. but World "warning"
|
||||
GAME( 1988, forgottnu, forgottn, cps1_10MHz, forgottn, cps_state, forgottn, ROT0, "Capcom", "Forgotten Worlds (USA, B-Board 88621B-2, Rev. C)", MACHINE_SUPPORTS_SAVE )
|
||||
GAME( 1988, forgottnu1, forgottn, cps1_10MHz, forgottn, cps_state, forgottn, ROT0, "Capcom", "Forgotten Worlds (USA, B-Board 88618B-2, Rev. C)", MACHINE_SUPPORTS_SAVE )
|
||||
GAME( 1988, forgottnua, forgottn, cps1_10MHz, forgottn, cps_state, forgottn, ROT0, "Capcom", "Forgotten Worlds (USA, B-Board 88618B-2, Rev. A)", MACHINE_SUPPORTS_SAVE )
|
||||
|
||||
@ -3172,7 +3172,7 @@ GAME( 1998, ehrgeiz, 0, coh700, namcos12, namcos12_state, namcos12, R
|
||||
GAME( 1998, ehrgeizaa, ehrgeiz, coh700, namcos12, namcos12_state, namcos12, ROT0, "Square / Namco", "Ehrgeiz (Asia, EG2/VER.A)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) /* KC021 */
|
||||
GAME( 1998, ehrgeizja, ehrgeiz, coh700, namcos12, namcos12_state, namcos12, ROT0, "Square / Namco", "Ehrgeiz (Japan, EG1/VER.A)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) /* KC021 */
|
||||
GAME( 1998, mdhorse, 0, coh700, namcos12, namcos12_state, namcos12, ROT0, "MOSS / Namco", "Derby Quiz My Dream Horse (Japan, MDH1/VER.A2)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND | MACHINE_NOT_WORKING ) /* KC035 */
|
||||
GAME( 1998, aplarail, 0, aplarail, aplarail, namcos12_state, namcos12, ROT0, "Namco / Tomy", "Attack Pla Rail (Japan, AP1/VER.A)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND | MACHINE_NOT_WORKING ) /* KC032 */
|
||||
GAME( 1998, aplarail, 0, aplarail, aplarail, namcos12_state, namcos12, ROT0, "Namco / Tomy", "Attack Pla Rail (Japan, AP1/VER.A)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) /* KC032 */
|
||||
GAME( 1998, sws98, 0, coh700, namcos12, namcos12_state, namcos12, ROT0, "Namco", "Super World Stadium '98 (Japan, SS81/VER.A)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) /* KC0?? */
|
||||
GAME( 1998, technodr, 0, technodr, technodr, namcos12_state, namcos12, ROT0, "Namco", "Techno Drive (Japan, TD2/VER.B)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND | MACHINE_NOT_WORKING ) /* KC056 */
|
||||
GAME( 1998, tenkomor, 0, coh700, namcos12, namcos12_state, namcos12, ROT90,"Namco", "Tenkomori Shooting (Asia, TKM2/VER.A1)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) /* KC036 */
|
||||
|
||||
@ -294,6 +294,229 @@ CPU68 PCB:
|
||||
|
||||
JP2 /D-ST /VBL
|
||||
JP3
|
||||
|
||||
*****************************
|
||||
|
||||
Winning Run / Winning Run Suzuka GP/ Winning Run 91
|
||||
Namco 1988-91
|
||||
|
||||
These games run on Namco System 21 hardware. Note each set of PCBs for System 21 games are slightly different,
|
||||
with some common PCBs and some unique-to-that-game PCBs. This covers the Winning Run series.
|
||||
The PCBs are housed in a metal box. The front has a small filter board containing a 60-pin flat cable connector.
|
||||
Underneath is a connector that plugs into PCB #3.
|
||||
Inside at the bottom is a small MOTHER PCB containing 8 connectors where the PCBs plug in and the power input connector.
|
||||
On Winning Run there is an additional PCB for the controls and cabinet motion.
|
||||
The PAL labels suggest it was originally used with Metal Hawk. It may be used with other games too.
|
||||
|
||||
|
||||
PCB Layouts
|
||||
-----------
|
||||
|
||||
In the layouts below, the jumpers set the ROM type.
|
||||
If horizontally shorted the ROM type is 27C101
|
||||
If vertically shorted the ROM type is 27C301/27C1001
|
||||
ROM labels/locations shown are printed on the PCB. Not all ROM positions are used.
|
||||
See the ROM loading below (per game) for ROM usage and actual label names.
|
||||
|
||||
PCB#1 (top):
|
||||
|
||||
2252960601
|
||||
(2252970601)
|
||||
|--------------------------------------------------------------|
|
||||
| POINT3L.7P POINT3U.5P DIP28_SOCKET(2P) |
|
||||
| POINT2L.7N POINT2U.5N |-------| |
|
||||
| JP5 O=O JP6 O=O | TMS | 40MHz |
|
||||
| O=O 0=0 |320C25 | |
|
||||
| POINT1U.8L MB8422 |-------| |
|
||||
| PAL16L8 MB81C69 MB81C69 |
|
||||
| POINT0U.8J MB8422 (WR-D2.4J) |
|
||||
| MB81C69 MB81C69 |
|
||||
| |
|
||||
| |
|
||||
|JP3 O=O |
|
||||
| O=O |
|
||||
| POINT1L.2E MB8422 62256 62256 |
|
||||
| |
|
||||
| POINT0L.8D MB8422 |
|
||||
|JP4 O=O |
|
||||
| O=O |
|
||||
| |
|
||||
| |
|
||||
| PAL16L8 |
|
||||
| (WR-D1.3B) |
|
||||
| |
|
||||
| |
|
||||
|----|----------------------|----|------------------------|----|
|
||||
|----------------------| |------------------------|
|
||||
|
||||
|
||||
PCB#2 (2nd down):
|
||||
|
||||
2252960701
|
||||
(2252970701)
|
||||
|--------------------------------------------------------------|
|
||||
| |
|
||||
| 62256 62256 C157 C157 M5M5178 |
|
||||
| |
|
||||
| 62256 62256 C157 C157 M5M5178 |
|
||||
| |
|
||||
| 62256 62256 C157 C157 62256 |
|
||||
| C150 |
|
||||
| 62256 62256 C157 C157 62256 |
|
||||
| |
|
||||
| C157 C157 |
|
||||
| |
|
||||
| C157 C157 62256 |
|
||||
| |-------| |-------| |-------| |
|
||||
| |L7A0080| |L7A0080| |L7A0081| M5M5178 62256 |
|
||||
| |110FAI | |110FAI | |111MUR | |
|
||||
| |-------| |-------| |-------| M5M5178 62256 |
|
||||
| |
|
||||
| 2018 2018 |---------| 62256 |
|
||||
| 20MHz | | |
|
||||
| 2018 2018 2018 | C167 | |
|
||||
| C157 C157 | | PAL16L8 |
|
||||
| C157 C157 |---------| (WR-P1.1B)|
|
||||
| |
|
||||
|----|----------------------|----|------------------------|----|
|
||||
|----------------------| |------------------------|
|
||||
|
||||
|
||||
PCB#3 (3rd down):
|
||||
|
||||
2252960101
|
||||
(2252970101) RGB_CABLE |------------------------|
|
||||
|--------------------||||||------|------------------------|----|
|
||||
| TL084C |---| MB3771 |
|
||||
| MB87077 LB1760 |C65| PAL16L8 PC910 PC900|
|
||||
|MB87077 34063 |---| (SYS87B-2.3W) |
|
||||
|TL084C TL084C DSW1(8) M5M5179 |
|
||||
|LC7880 YM3012 PAL12L10 SYS2C65C.5P |----| |
|
||||
|MB8464 YM2151 (WR-C1.5P) |C139| |
|
||||
| |----| C137 3.579545MHz HN58C65 |----| |
|
||||
| |C121| 49.152MHz 8422 C149 |
|
||||
| |----| PAL12L10 65256 65256 |
|
||||
| (WR-C2.8K) |
|
||||
| 2018 2018 62256 62256 MPRU.3K MPRL.1K |
|
||||
| |
|
||||
| VOI3.11E MB8464 68000 |
|
||||
| |
|
||||
| VOI2.11D |------| SND1.7D C148 C148 DATA3U.3D DATA3L.1D|
|
||||
| | C140 | |
|
||||
| VOI1.11C |------| SND0.7C 65256 65256 DATA2U.3C DATA2L.1C|
|
||||
| |
|
||||
| VOI0.11B 6809 SPRU.6B SPRL.4B DATA1U.3B DATA1L.1B|
|
||||
| JP3 JP1 |
|
||||
| O=O 68000 OO DATA0U.3A DATAOL.1A|
|
||||
| O=O || |
|
||||
| OO |
|
||||
|----|----------------------|----|------------------------|----|
|
||||
|----------------------| |------------------------|
|
||||
|
||||
|
||||
PCB#4 (bottom):
|
||||
|
||||
2252960401
|
||||
(2252970401) RGB_CABLE
|
||||
|--------------------||||||------------------------------------|
|
||||
| |
|
||||
| |----| |----| |
|
||||
| |C164| |C148| 68000 |
|
||||
| |----| |----| |
|
||||
| MB3771 |
|
||||
| PAL20V8 62256 62256 |
|
||||
| (WR-G3.4S) |
|
||||
| 62256 GDT1L.3S GDT1U.1S |
|
||||
| MB81461 MB81461 JP10 O-O JP9 OO|
|
||||
| 62256 PAL16L8 GDT0L.3P GDT0U.1P |||
|
||||
| MB81461 MB81461 (WR-G2.4P) OO|
|
||||
| 62256 GPR1L.3L GPR1U.1L |
|
||||
| MB81461 MB81461 J J J JP8 OO|
|
||||
| P P P GPR0L.3J GPR0U.1J |||
|
||||
| MB81461 MB81461 |----| 6 5 4 OO|
|
||||
| |C138| O|O|O| JP12 |
|
||||
| MB81461 MB81461 |----| O|O|O| O| JP7 OO|
|
||||
| PAL16L8 O O O O| MB8422 |||
|
||||
| MB81461 MB81461 (WR-G4.7L) 49.152MHz O OO|
|
||||
| C165 MB8422 |
|
||||
| MB81461 MB81461 38.808MHz |
|
||||
| PAL16L8 |
|
||||
| MB81461 MB81461 (WR-G1.3A) |
|
||||
|----|----------------------|----|------------------------|----|
|
||||
|----------------------| |------------------------|
|
||||
|
||||
|
||||
I/O & Drive Board For Motion Cabinet
|
||||
------------------------------------
|
||||
|
||||
2286964100 (2286974100)
|
||||
|--------------------------------|
|
||||
|SW2 SW1 8255 8251 TLP521 |
|
||||
|DSW(6) EMPTY_SOCKET |
|
||||
| 4.9152MHz |
|
||||
|RESET MB3773 ADC0809 J201|
|
||||
| 68B09 EMPTY_SOCKET |
|
||||
| WR_DR1.5A S1WB |
|
||||
| 8464 LM324 |
|
||||
| TLP521 |
|
||||
| PAL20L10 S2VB |
|
||||
|(MH1-DR2) A490 J205|
|
||||
| A490 |
|
||||
|J206 TLP511 |
|
||||
| 8253 PAL14H8 TLP511|
|
||||
|TLP511 (MH1-DR3) |
|
||||
| J204 J202 J203 |
|
||||
|TLP511 |
|
||||
|BCR16DM BCR16DM BCR16DM BCR16DM |
|
||||
|--------------------------------|
|
||||
Notes:
|
||||
J201 - 50 pin flat cable connector for controls
|
||||
J202 - 6 pin Power connector
|
||||
J203 - 2-pin Power connector
|
||||
J204 - 3-pin Power connector
|
||||
J205 - 4-pin connector for DC feedback motor
|
||||
J206 - 5-pin connector for main board communication
|
||||
S1WB - Bridge Rectifier
|
||||
S2VB - Bridge Rectifier
|
||||
A490 - Transistor
|
||||
BCR16DM - Transistor
|
||||
TLP511 - Toshiba TLP511 GAAS Infrared & Photo Thyristor
|
||||
TLP521 - Toshiba TLP521 Programmable Controller AC/DC-Input Module Solid State Relay
|
||||
8255 - Mitsubishi M5L8255AP-5 Programmable Peripheral Interface
|
||||
8251 - Mitsubishi M5L8251AP-5 Programmable Communication Interface
|
||||
8253 - Mitsubishi M5L8253P-5 Programmable Interval Timer
|
||||
ADC0809 - National Semiconductor ADC0809CCN 8-Bit Microprocessor Compatible A/D Converters with 8-Channel Multiplexer
|
||||
68B09 - Hitachi HD68B09EP CPU
|
||||
8464 - 8k x8-bit SRAM
|
||||
LM324 - National Semiconductor LM324 General Purpose Operational Amplifier
|
||||
MB3773 - Fujitsu MB3773 Power Supply Monitor with Watch-Dog Timer
|
||||
|
||||
|
||||
Slot PCB
|
||||
--------
|
||||
2252960502 (2252970502)
|
||||
V21 MOTHER PCB
|
||||
|--------------------------------------------------------------|
|
||||
| PWR_CONN |
|
||||
| |--------SLOT1---------| |---------SLOT5----------| |
|
||||
| |--------SLOT2---------| |---------SLOT6----------| |
|
||||
| |--------SLOT3---------| |---------SLOT7----------| |
|
||||
| |--------SLOT4---------| |---------SLOT8----------| |
|
||||
|--------------------------------------------------------------|
|
||||
|
||||
|
||||
Filter Board
|
||||
------------
|
||||
2252960801 (2252970801)
|
||||
|--------------------------------|
|
||||
| |----------------------| |
|
||||
| |----------------------| |
|
||||
| |
|
||||
|-------|60-PIN FLAT CABLE|------|
|
||||
|-------CONN------|
|
||||
|
||||
****************************
|
||||
|
||||
*/
|
||||
#include "emu.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
|
||||
@ -128,8 +128,8 @@ Sega NAOMI Mainboard PCB Layout
|
||||
| LED2 14.7456MHz |
|
||||
|---------------------------------------------------|
|
||||
Notes:
|
||||
SH4 - Hitachi SH4 CPU (BGAxxx, with heatsink)
|
||||
POWERVR2 - NEC POWERVR2 Video Generator IC (large BGAxxx, with heatsink and fan)
|
||||
SH4 - Hitachi HD6417091 SH4 CPU (BGAxxx, with heatsink)
|
||||
POWERVR2 - VideoLogic/NEC 'CLX2/HOLLY' chipset and PowerVR2 GPU (large BGAxxx, with heatsink and fan)
|
||||
EPF8452AQC160-3 - Altera FLEX EPF8452AQC160-3 FPGA (QFP160)
|
||||
93C46 - 128 bytes serial EEPROM (SOIC8)
|
||||
BIOS.IC27 - 27C160 EPROM (DIP42)
|
||||
@ -137,10 +137,10 @@ EPF8452AQC160-3 - Altera FLEX EPF8452AQC160-3 FPGA (QFP160)
|
||||
HY57V161610 - Hynix HY57V161610DTC-8 512k x 16-bit x 2-banks (16Mbit) SDRAM (TSOPII-50)
|
||||
KM416S4030 - Samsung KM416S4030 1M x 16-bit x 4 Banks SDRAM (TSOPII-54)
|
||||
62256 - 32k x8-bit SRAM (SOP28)
|
||||
315-6145 - Sega Custom IC (QFP56)
|
||||
315-6146 - Sega Custom IC (QFP176)
|
||||
315-6145 - video DAC/encoder, BU1426KS equivalent (QFP56)
|
||||
315-6146 - Sega Custom Z80-based MCU (QFP176)
|
||||
315-6188 - Altera EPC1064PC8 FPGA Configuration Device with sticker '315-6188' at IC31 (DIP8)
|
||||
315-6232 - Sega Custom IC (QFP100)
|
||||
315-6232 - Yamaha AICA SPU (QFP100)
|
||||
CY2308SC-3 - Cypress CY2308SC-3 2-Bank 4-Output Tri-state PLL Programmable Clock Generator IC with 2X or 4X outputs and Zero Delay Buffer (SOIC16)
|
||||
C844 - NEC uPC844 Quad Operational Amplifier (SOIC14)
|
||||
A179B - TI SN75179B Differential Driver and Receiver Pair (DIP8)
|
||||
@ -184,7 +184,7 @@ Sega NAOMI 2 Mainboard PCB Layout
|
||||
| LED2 LED1 *CY2308 CY2292 3773|
|
||||
|---------------------------------------------------|
|
||||
Notes: (* - these parts on other side of PCB)
|
||||
SH4 - Hitachi SH4 CPU (BGAxxx, with heatsink)
|
||||
SH4 - Hitachi HD6417091 SH4 CPU (BGAxxx, with heatsink)
|
||||
BIOS.IC27 - 27C160 EPROM (DIP42)
|
||||
EPF8452 - Altera FLEX EPF8452AQC160-3 FPGA (QFP160)
|
||||
93C46 - 128 bytes serial EEPROM (SOIC8)
|
||||
@ -192,14 +192,14 @@ Notes: (* - these parts on other side of PCB)
|
||||
16M - Hynix HY57V161610DTC-8 512k x 16-bit x 2-banks (16Mbit) SDRAM (TSOP-II 50)
|
||||
64M - NEC D4564323 512k x 32-bit x 4-banks (64Mbit) SDRAM (TSOP-II 86)
|
||||
62256 - 32k x8-bit SRAM (SOP28)
|
||||
315-6146 - Sega Custom IC (QFP176)
|
||||
315-6146 - Sega Custom Z80-based MCU (QFP176)
|
||||
315-6188 - Altera EPC1064PC8 FPGA Configuration Device with sticker '315-6188' at IC31 (DIP8)
|
||||
315-6232 - Sega Custom IC (QFP100)
|
||||
315-6258 - Sega Custom IC (QFP56)
|
||||
315-6267 - NEC POWER-VR2 Video Generator IC (large BGAxxx, with heatsink and fan, x2)
|
||||
315-6232 - Yamaha AICA SPU (QFP100)
|
||||
315-6258 - video DAC/encoder, BU1426KS equivalent (QFP56, x2)
|
||||
315-6267 - VideoLogic/NEC 'CLX2/HOLLY' chipset and PowerVR2 GPU (large BGAxxx, with heatsink and fan, x2)
|
||||
315-6268 - Altera EPM7032AELC44-10 CPLD with sticker '315-6268' (PLCC44)
|
||||
315-6269 - Altera MAX EPM7064AETC100-10 CPLD with sticker '315-6269' (TQFP100)
|
||||
315-6289 - Sega custom IC (large BGAxxx, with heatsink)
|
||||
315-6289 - VideoLogic/NEC 'ELAN' T&L coprocessor (large BGAxxx, with heatsink)
|
||||
MC33470 - ON Semiconductor MC33470 Synchronous Rectification DC/DC Converter Programmable Integrated Controller (SOIC20)
|
||||
CY2308 - Cypress CY2308SC-3 2-Bank 4-Output Tri-state PLL Programmable Clock Generator IC with 2X or 4X outputs and Zero Delay Buffer (SOIC16)
|
||||
CY2292 - Cypress CY2292SL Three-PLL General-Purpose EPROM Programmable Clock Generator IC (SOIC16)
|
||||
|
||||
@ -37,44 +37,65 @@ used, and the value on the data bus is completley ignored.
|
||||
02 - Set BIT 9 signal (map bank 3 into F000-FFFF)
|
||||
03 - Clear BIT 9 signal (map bank 1/2 into F000-FFFF)
|
||||
|
||||
Selecting between bank 1 and bank 2 is also affected by M1 and IRQACK
|
||||
conditions using a set of three flipflops.
|
||||
|
||||
The serial speed configuration implements wiring changes recommended in the
|
||||
Osborne 1 Technical Manual. There's no way for software to read the
|
||||
selected baud rates, so it will always call the low speed "300" and the high
|
||||
speed "1200". You as the user have to keep this in mind using the system.
|
||||
|
||||
Serial communications can be flaky when 600/2400 is selected. This is not a
|
||||
bug in MAME. I've checked and double-checked the schematics to confirm it's
|
||||
an original bug. The division ratio from the master clock to the baud rates
|
||||
in this mode is effectively 16*24*64 or 16*24*16 giving actual data rates of
|
||||
650 baud or 2600 baud, about 8.3% too fast (16*26*64 and 16*26*16 would give
|
||||
the correct rates). MAME's bitbanger seems to be able to accept the ACIA
|
||||
output at this rate, but the ACIA screws up when consuming data from MAME's
|
||||
bitbanger.
|
||||
|
||||
|
||||
TODO:
|
||||
- Implement ROM/IO bank selection properly
|
||||
- Implement serial port
|
||||
- Implement reset key (generates NMI and affects bank selection)
|
||||
- Verify frequency of the beep/audio alarm.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "includes/osborne1.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
|
||||
|
||||
#define MAIN_CLOCK 15974400
|
||||
|
||||
|
||||
static ADDRESS_MAP_START( osborne1_mem, AS_PROGRAM, 8, osborne1_state )
|
||||
AM_RANGE( 0x0000, 0x0FFF ) AM_READ_BANK("bank1") AM_WRITE( osborne1_0000_w )
|
||||
AM_RANGE( 0x1000, 0x1FFF ) AM_READ_BANK("bank2") AM_WRITE( osborne1_1000_w )
|
||||
AM_RANGE( 0x2000, 0x3FFF ) AM_READWRITE( osborne1_2000_r, osborne1_2000_w )
|
||||
AM_RANGE( 0x0000, 0x0FFF ) AM_READ_BANK("bank_0xxx") AM_WRITE(bank_0xxx_w)
|
||||
AM_RANGE( 0x1000, 0x1FFF ) AM_READ_BANK("bank_1xxx") AM_WRITE(bank_1xxx_w)
|
||||
AM_RANGE( 0x2000, 0x3FFF ) AM_READWRITE(bank_2xxx_3xxx_r, bank_2xxx_3xxx_w)
|
||||
AM_RANGE( 0x4000, 0xEFFF ) AM_RAM
|
||||
AM_RANGE( 0xF000, 0xFFFF ) AM_READ_BANK("bank3") AM_WRITE( osborne1_videoram_w )
|
||||
AM_RANGE( 0xF000, 0xFFFF ) AM_READ_BANK("bank_fxxx") AM_WRITE(videoram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static ADDRESS_MAP_START( osborne1_op, AS_DECRYPTED_OPCODES, 8, osborne1_state )
|
||||
AM_RANGE( 0x0000, 0xFFFF ) AM_READ(opcode_r)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static ADDRESS_MAP_START( osborne1_io, AS_IO, 8, osborne1_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
ADDRESS_MAP_GLOBAL_MASK(0xff)
|
||||
AM_RANGE( 0x00, 0xff ) AM_WRITE( osborne1_bankswitch_w )
|
||||
AM_RANGE( 0x00, 0xff ) AM_WRITE(bankswitch_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static INPUT_PORTS_START( osborne1 )
|
||||
PORT_START("ROW0")
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('[') PORT_CHAR(']')
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('[') PORT_CHAR(']')
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('\'') PORT_CHAR('"')
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
|
||||
|
||||
@ -150,21 +171,28 @@ static INPUT_PORTS_START( osborne1 )
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
|
||||
PORT_START("RESET")
|
||||
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("RESET") PORT_CODE(KEYCODE_F12)
|
||||
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED)
|
||||
|
||||
PORT_START("CNF")
|
||||
PORT_CONFNAME(0x06, 0x00, "Serial Speed")
|
||||
PORT_CONFSETTING(0x00, "300/1200")
|
||||
PORT_CONFSETTING(0x02, "600/2400")
|
||||
PORT_CONFSETTING(0x04, "1200/4800")
|
||||
PORT_CONFSETTING(0x06, "2400/9600")
|
||||
PORT_CONFNAME(0x01, 0x00, "Video Output")
|
||||
PORT_CONFSETTING(0x00, "Standard")
|
||||
PORT_CONFSETTING(0x01, "SCREEN-PAC")
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
static const z80_daisy_config osborne1_daisy_chain[] =
|
||||
{
|
||||
/* { osborne1_z80_reset, osborne1_z80_irq_state, osborne1_z80_irq_ack, osborne1_z80_irq_reti, 0 }, */
|
||||
{ "osborne1_daisy" },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* The Osborne-1 supports the following disc formats:
|
||||
* - Osborne single density: 40 tracks, 10 sectors per track, 256-byte sectors (100 KByte)
|
||||
@ -176,37 +204,36 @@ static const z80_daisy_config osborne1_daisy_chain[] =
|
||||
*/
|
||||
|
||||
static SLOT_INTERFACE_START( osborne1_floppies )
|
||||
SLOT_INTERFACE( "525sssd", FLOPPY_525_SSSD ) // Siemens FDD 100-5, custom Osborne electronics
|
||||
SLOT_INTERFACE( "525ssdd", FLOPPY_525_SSDD ) // MPI 52(?), custom Osborne electronics
|
||||
SLOT_INTERFACE("525sssd", FLOPPY_525_SSSD) // Siemens FDD 100-5, custom Osborne electronics
|
||||
SLOT_INTERFACE("525ssdd", FLOPPY_525_SSDD) // MPI 52(?), custom Osborne electronics
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
|
||||
/* F4 Character Displayer */
|
||||
static const gfx_layout osborne1_charlayout =
|
||||
{
|
||||
8, 10, /* 8 x 10 characters */
|
||||
128, /* 128 characters */
|
||||
1, /* 1 bits per pixel */
|
||||
{ 0 }, /* no bitplanes */
|
||||
/* x offsets */
|
||||
8, 10, // 8 x 10 characters
|
||||
128, // 128 characters
|
||||
1, // 1 bits per pixel
|
||||
{ 0 }, // no bitplanes
|
||||
// x offsets
|
||||
{ 0, 1, 2, 3, 4, 5, 6, 7 },
|
||||
/* y offsets */
|
||||
// y offsets
|
||||
{ 0*128*8, 1*128*8, 2*128*8, 3*128*8, 4*128*8, 5*128*8, 6*128*8, 7*128*8, 8*128*8, 9*128*8 },
|
||||
8 /* every char takes 16 x 1 bytes */
|
||||
8 // every char takes 16 x 1 bytes
|
||||
};
|
||||
|
||||
static GFXDECODE_START( osborne1 )
|
||||
GFXDECODE_ENTRY( "chargen", 0x0000, osborne1_charlayout, 0, 1 )
|
||||
GFXDECODE_ENTRY("chargen", 0x0000, osborne1_charlayout, 0, 1)
|
||||
GFXDECODE_END
|
||||
|
||||
|
||||
static MACHINE_CONFIG_START( osborne1, osborne1_state )
|
||||
MCFG_CPU_ADD( "maincpu", Z80, MAIN_CLOCK/4 )
|
||||
MCFG_CPU_PROGRAM_MAP( osborne1_mem)
|
||||
MCFG_CPU_IO_MAP( osborne1_io)
|
||||
MCFG_CPU_CONFIG( osborne1_daisy_chain )
|
||||
|
||||
MCFG_DEVICE_ADD( "osborne1_daisy", OSBORNE1_DAISY, 0 )
|
||||
MCFG_CPU_ADD("maincpu", Z80, MAIN_CLOCK/4)
|
||||
MCFG_CPU_PROGRAM_MAP(osborne1_mem)
|
||||
MCFG_CPU_DECRYPTED_OPCODES_MAP(osborne1_op)
|
||||
MCFG_CPU_IO_MAP(osborne1_io)
|
||||
MCFG_Z80_SET_IRQACK_CALLBACK(WRITELINE(osborne1_state, irqack_w))
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(osborne1_state, screen_update)
|
||||
@ -228,12 +255,23 @@ static MACHINE_CONFIG_START( osborne1, osborne1_state )
|
||||
MCFG_PIA_CB2_HANDLER(DEVWRITELINE(IEEE488_TAG, ieee488_device, ren_w))
|
||||
MCFG_PIA_IRQA_HANDLER(WRITELINE(osborne1_state, ieee_pia_irq_a_func))
|
||||
|
||||
MCFG_DEVICE_ADD( "pia_1", PIA6821, 0)
|
||||
MCFG_DEVICE_ADD("pia_1", PIA6821, 0)
|
||||
MCFG_PIA_WRITEPA_HANDLER(WRITE8(osborne1_state, video_pia_port_a_w))
|
||||
MCFG_PIA_WRITEPB_HANDLER(WRITE8(osborne1_state, video_pia_port_b_w))
|
||||
MCFG_PIA_CB2_HANDLER(WRITELINE(osborne1_state, video_pia_out_cb2_dummy))
|
||||
MCFG_PIA_IRQA_HANDLER(WRITELINE(osborne1_state, video_pia_irq_a_func))
|
||||
|
||||
MCFG_DEVICE_ADD("acia", ACIA6850, 0)
|
||||
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
|
||||
MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
|
||||
MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(osborne1_state, serial_acia_irq_func))
|
||||
|
||||
MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, NULL)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_dcd))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
|
||||
MCFG_RS232_RI_HANDLER(DEVWRITELINE("pia_1", pia6821_device, ca2_w))
|
||||
|
||||
MCFG_DEVICE_ADD("mb8877", MB8877, MAIN_CLOCK/16)
|
||||
MCFG_WD_FDC_FORCE_READY
|
||||
MCFG_FLOPPY_DRIVE_ADD("mb8877:0", osborne1_floppies, "525ssdd", floppy_image_device::default_floppy_formats)
|
||||
@ -243,9 +281,9 @@ static MACHINE_CONFIG_START( osborne1, osborne1_state )
|
||||
MCFG_IEEE488_SRQ_CALLBACK(DEVWRITELINE("pia_0", pia6821_device, ca2_w))
|
||||
MCFG_SOFTWARE_LIST_ADD("flop_list","osborne1")
|
||||
|
||||
/* internal ram */
|
||||
// internal ram
|
||||
MCFG_RAM_ADD(RAM_TAG)
|
||||
MCFG_RAM_DEFAULT_SIZE("68K") /* 64KB Main RAM and 4Kbit video attribute RAM */
|
||||
MCFG_RAM_DEFAULT_SIZE("68K") // 64bB main RAM and 4kbit video attribute RAM
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
@ -1946,7 +1946,7 @@ PayTable 10s+ 2PR 3K STR FL FH 4K SF RF (Bonus)
|
||||
ROM_LOAD( "pp0045_a45-a74.u68", 0x00000, 0x10000, CRC(9c7cf6d7) SHA1(3da9829678b853d85146b66b40800257a8eaa151) ) /* Game Version: A45, Library Version: A74 */
|
||||
|
||||
ROM_REGION( 0x020000, "gfx1", 0 )
|
||||
ROM_LOAD( "mro-cg1072.u72", 0x00000, 0x8000, CRC(8e5cf3bf) SHA1(a8c2fde9105a37eddc218ae1476cdbfb0271e314) ) /* Custom Annie Oakely's Central City graphics */
|
||||
ROM_LOAD( "mro-cg1072.u72", 0x00000, 0x8000, CRC(8e5cf3bf) SHA1(a8c2fde9105a37eddc218ae1476cdbfb0271e314) ) /* Custom Annie Oakley's Central City graphics */
|
||||
ROM_LOAD( "mgo-cg1072.u73", 0x08000, 0x8000, CRC(a3c85c1b) SHA1(9b810c5779dde21db6da5bac5cf797bad65c2c1b) )
|
||||
ROM_LOAD( "mbo-cg1072.u74", 0x10000, 0x8000, CRC(833371e1) SHA1(5d7a994aee61a751f89171885423276b86e872b6) ) /* These graphics will work for many other standard poker sets */
|
||||
ROM_LOAD( "mxo-cg1072.u75", 0x18000, 0x8000, CRC(0df703b3) SHA1(2042251cc9c11687ff7fd920213a448974ff3050) ) /* However there is no support for Deuces Wild sets */
|
||||
@ -1956,6 +1956,27 @@ PayTable 10s+ 2PR 3K STR FL FH 4K SF RF (Bonus)
|
||||
ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
|
||||
ROM_END
|
||||
|
||||
ROM_START( pepp0045d ) /* Normal board : 10's or Better (PP0045) */
|
||||
/*
|
||||
PayTable 10s+ 2PR 3K STR FL FH 4K SF RF (Bonus)
|
||||
----------------------------------------------------------
|
||||
P8A 1 1 3 4 5 8 25 50 300 800
|
||||
% Range: 84.6-86.6% Optimum: 88.6% Hit Frequency: 49.2%
|
||||
Programs Available: PP0045, X000045P
|
||||
*/
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_LOAD( "pp0045_a45-a74.u68", 0x00000, 0x10000, CRC(9c7cf6d7) SHA1(3da9829678b853d85146b66b40800257a8eaa151) ) /* Game Version: A45, Library Version: A74 */
|
||||
|
||||
ROM_REGION( 0x020000, "gfx1", 0 )
|
||||
ROM_LOAD( "mro-cg881.u72", 0x00000, 0x8000, CRC(282a029f) SHA1(42b35761839d6379ddfb4eed20f90d9f7b145e64) ) /* Custom Las Vegas Rio graphics */
|
||||
ROM_LOAD( "mgo-cg881.u73", 0x08000, 0x8000, CRC(af433702) SHA1(fbd877c06eaab433332c94f135e13a8c041fa1a2) )
|
||||
ROM_LOAD( "mbo-cg881.u74", 0x10000, 0x8000, CRC(c5b0a0b3) SHA1(a989d21f4b10a09d3cfd0bbb9f53b4ad326561b9) ) /* These graphics will work for many other standard poker sets */
|
||||
ROM_LOAD( "mxo-cg881.u75", 0x18000, 0x8000, CRC(6a78bc1d) SHA1(7861465ab98df5219330d58a3e5a4bd37a393534) ) /* However there is no support for Deuces Wild sets */
|
||||
|
||||
ROM_REGION( 0x100, "proms", 0 )
|
||||
ROM_LOAD( "cap881.u50", 0x0000, 0x0100, CRC(e51990d5) SHA1(41946722b61e955d37808761d451fc894e6adc8a) )
|
||||
ROM_END
|
||||
|
||||
ROM_START( pepp0046 ) /* Normal board : 10's or Better (PP0046) */
|
||||
/*
|
||||
PayTable 10s+ 2PR 3K STR FL FH 4K SF RF (Bonus)
|
||||
@ -10832,6 +10853,7 @@ GAMEL(1987, pepp0045, pepp0002, peplus, peplus_poker, peplus_state, peplus,
|
||||
GAMEL(1987, pepp0045a, pepp0002, peplus, peplus_poker, peplus_state, peplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0045) 10's or Better (Gambler Downtown Reno)", 0, layout_pe_poker )
|
||||
GAMEL(1987, pepp0045b, pepp0002, peplus, peplus_poker, peplus_state, peplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0045) 10's or Better (Par-A-Dice Riverboat Casino)", MACHINE_WRONG_COLORS, layout_pe_poker ) /* CAP1150 not dumped */
|
||||
GAMEL(1987, pepp0045c, pepp0002, peplus, peplus_poker, peplus_state, peplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0045) 10's or Better (Annie Oakley's Central City)", MACHINE_WRONG_COLORS, layout_pe_poker ) /* CAP1072 not dumped */
|
||||
GAMEL(1987, pepp0045d, pepp0002, peplus, peplus_poker, peplus_state, peplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0045) 10's or Better (Las Vegas Rio)", 0, layout_pe_poker )
|
||||
GAMEL(1987, pepp0046, pepp0002, peplus, peplus_poker, peplus_state, peplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0046) 10's or Better (set 1)", 0, layout_pe_poker )
|
||||
GAMEL(1987, pepp0046a, pepp0002, peplus, peplus_poker, peplus_state, peplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0046) 10's or Better (International)",0, layout_pe_poker )
|
||||
GAMEL(1987, pepp0046b, pepp0002, peplus, peplus_poker, peplus_state, nonplus, ROT0, "IGT - International Game Technology", "Player's Edge Plus (PP0046) 10's or Better (set 2)", 0, layout_pe_poker )
|
||||
|
||||
@ -191,7 +191,8 @@ READ8_MEMBER( super6_state::fdc_r )
|
||||
|
||||
*/
|
||||
|
||||
fatalerror("Z80 WAIT not supported by MAME core\n");
|
||||
// don't crash please... but it's true, WAIT does nothing in our Z80
|
||||
//fatalerror("Z80 WAIT not supported by MAME core\n");
|
||||
m_maincpu->set_input_line(Z80_INPUT_LINE_WAIT, ASSERT_LINE);
|
||||
|
||||
return !m_fdc->intrq_r() << 7;
|
||||
@ -217,13 +218,16 @@ WRITE8_MEMBER( super6_state::fdc_w )
|
||||
6
|
||||
7
|
||||
|
||||
Codes passed to here during boot are 0x00, 0x08, 0x38
|
||||
*/
|
||||
|
||||
// disk drive select
|
||||
floppy_image_device *m_floppy = NULL;
|
||||
|
||||
if (BIT(data, 0)) m_floppy = m_floppy0->get_device();
|
||||
if (BIT(data, 1)) m_floppy = m_floppy1->get_device();
|
||||
if ((data & 3) == 0)
|
||||
m_floppy = m_floppy0->get_device();
|
||||
if ((data & 3) == 1)
|
||||
m_floppy = m_floppy1->get_device();
|
||||
|
||||
m_fdc->set_floppy(m_floppy);
|
||||
if (m_floppy) m_floppy->mon_w(0);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Curt Coder
|
||||
// copyright-holders:Curt Coder, Robbbert
|
||||
/*
|
||||
|
||||
Osborne 4 Vixen
|
||||
@ -47,9 +47,6 @@ Notes:
|
||||
|
||||
TODO:
|
||||
|
||||
- video line buffer
|
||||
- floppy
|
||||
- keyboard
|
||||
- RS232 RI interrupt
|
||||
- PCB layouts
|
||||
|
||||
@ -76,17 +73,17 @@ void vixen_state::update_interrupt()
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// ctl_w - command write
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE8_MEMBER( vixen_state::ctl_w )
|
||||
READ8_MEMBER( vixen_state::opram_r )
|
||||
{
|
||||
logerror("CTL %u\n", data);
|
||||
|
||||
membank("bank3")->set_entry(BIT(data, 0));
|
||||
membank("bank3")->set_entry(0); // read videoram
|
||||
return m_program->read_byte(offset);
|
||||
}
|
||||
|
||||
READ8_MEMBER( vixen_state::oprom_r )
|
||||
{
|
||||
membank("bank3")->set_entry(1); // read rom
|
||||
return m_rom[offset];
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// status_r - status read
|
||||
@ -256,12 +253,20 @@ READ8_MEMBER( vixen_state::port3_r )
|
||||
// ADDRESS_MAP( vixen_mem )
|
||||
//-------------------------------------------------
|
||||
|
||||
// when M1 is inactive: read and write of data
|
||||
static ADDRESS_MAP_START( vixen_mem, AS_PROGRAM, 8, vixen_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0xefff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
|
||||
AM_RANGE(0x0000, 0xefff) AM_RAM
|
||||
AM_RANGE(0xf000, 0xffff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank4") AM_SHARE("video_ram")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
// when M1 is active: read opcodes
|
||||
static ADDRESS_MAP_START( bios_mem, AS_DECRYPTED_OPCODES, 8, vixen_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0xefff) AM_READ(opram_r)
|
||||
AM_RANGE(0xf000, 0xffff) AM_READ(oprom_r)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// ADDRESS_MAP( vixen_io )
|
||||
@ -296,84 +301,84 @@ ADDRESS_MAP_END
|
||||
|
||||
INPUT_PORTS_START( vixen )
|
||||
PORT_START("KEY.0")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC) PORT_CHAR(0x1B)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("LOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("SHIFT") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0D)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x27) PORT_CHAR(0x22)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR(']')
|
||||
|
||||
PORT_START("KEY.1")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
|
||||
|
||||
PORT_START("KEY.2")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('q') PORT_CHAR(0x11)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('w') PORT_CHAR(0x17)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('e') PORT_CHAR(0x05)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('r') PORT_CHAR(0x12)
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('t') PORT_CHAR(0x14)
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('y') PORT_CHAR(0x19)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('u') PORT_CHAR(0x15)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('i') PORT_CHAR(0x09)
|
||||
|
||||
PORT_START("KEY.3")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('a') PORT_CHAR(0x01)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('s') PORT_CHAR(0x13)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('d') PORT_CHAR(0x04)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('f') PORT_CHAR(0x06)
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('g') PORT_CHAR(0x07)
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('h') PORT_CHAR(0x08)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('j') PORT_CHAR(0x0a)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('k') PORT_CHAR(0x0b)
|
||||
|
||||
PORT_START("KEY.4")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('z') PORT_CHAR(0x1a)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('x') PORT_CHAR(0x18)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('c') PORT_CHAR(0x03)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('v') PORT_CHAR(0x16)
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('b') PORT_CHAR(0x02)
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('n') PORT_CHAR(0x0e)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('m') PORT_CHAR(0x0d)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
|
||||
|
||||
PORT_START("KEY.5")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UP") PORT_CODE(KEYCODE_UP)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LEFT) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('p') PORT_CHAR(0x10)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('o') PORT_CHAR(0x0f)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
|
||||
|
||||
PORT_START("KEY.6")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RIGHT") PORT_CODE(KEYCODE_RIGHT)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("DOWN") PORT_CODE(KEYCODE_DOWN)
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("- _") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('_') PORT_CHAR(0x1F)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') PORT_CHAR(0x7E)
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("\\ |") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|') PORT_CHAR(0x1C)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('l')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+') PORT_CHAR(0x60)
|
||||
|
||||
PORT_START("KEY.7")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL) PORT_CHAR(127)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('{') PORT_CHAR('}')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNC") PORT_CODE(KEYCODE_END)
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
@ -412,16 +417,17 @@ void vixen_state::video_start()
|
||||
UINT32 vixen_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
const pen_t *pen = m_palette->pens();
|
||||
UINT8 x, y, chr, gfx, inv, ra;
|
||||
|
||||
for (int txadr = 0; txadr < 26; txadr++)
|
||||
for (y = 0; y < 26; y++)
|
||||
{
|
||||
for (int scan = 0; scan < 10; scan++)
|
||||
for (ra = 0; ra < 10; ra++)
|
||||
{
|
||||
for (int chadr = 0; chadr < 128; chadr++)
|
||||
for (x = 0; x < 128; x++)
|
||||
{
|
||||
UINT16 sync_addr = (txadr << 7) | chadr;
|
||||
UINT8 sync_data = m_sync_rom[sync_addr];
|
||||
int blank = BIT(sync_data, 4);
|
||||
UINT16 sync_addr = ((y+1) << 7) + x + 1; // it's out by a row and a column
|
||||
UINT8 sync_data = m_sync_rom[sync_addr & 0xfff];
|
||||
bool blank = BIT(sync_data, 4);
|
||||
/*
|
||||
int clrchadr = BIT(sync_data, 7);
|
||||
int hsync = BIT(sync_data, 6);
|
||||
@ -433,30 +439,26 @@ UINT32 vixen_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, c
|
||||
sync_addr,sync_data,txadr,scan,chadr,comp_sync,vsync,blank,clrtxadr,hsync,clrchadr);
|
||||
*/
|
||||
|
||||
int reverse = 0;
|
||||
|
||||
UINT16 video_addr = (txadr << 7) | chadr;
|
||||
UINT8 video_data = m_video_ram[video_addr];
|
||||
UINT16 char_addr = 0;
|
||||
chr = m_video_ram[(y<<7) + x];
|
||||
|
||||
if (m_256)
|
||||
{
|
||||
char_addr = (BIT(video_data, 7) << 11) | (scan << 7) | (video_data & 0x7f);
|
||||
reverse = m_alt;
|
||||
gfx = m_char_rom[(BIT(chr, 7) << 11) | (ra << 7) | (chr & 0x7f)];
|
||||
inv = m_alt ? 0xff : 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
char_addr = (scan << 7) | (video_data & 0x7f);
|
||||
reverse = BIT(video_data, 7);
|
||||
gfx = m_char_rom[(ra << 7) | (chr & 0x7f)];
|
||||
inv = BIT(chr, 7) ? 0xff : 0;
|
||||
}
|
||||
|
||||
UINT8 char_data = m_char_rom[char_addr];
|
||||
gfx = (blank) ? 0 : (gfx ^ inv);
|
||||
|
||||
for (int x = 0; x < 8; x++)
|
||||
for (int b = 0; b < 8; b++)
|
||||
{
|
||||
int color = (BIT(char_data, 7 - x) ^ reverse) & !blank;
|
||||
int color = BIT(gfx, 7 - b);
|
||||
|
||||
bitmap.pix32((txadr * 10) + scan, (chadr * 8) + x) = pen[color];
|
||||
bitmap.pix32((y * 10) + ra, (x * 8) + b) = pen[color];
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -517,7 +519,7 @@ WRITE8_MEMBER( vixen_state::i8155_pc_w )
|
||||
2 DDEN/
|
||||
3 ALT CHARSET/
|
||||
4 256 CHARS
|
||||
5 BEEP ENB
|
||||
5 BEEP ENABLE
|
||||
6
|
||||
7
|
||||
|
||||
@ -537,11 +539,11 @@ WRITE8_MEMBER( vixen_state::i8155_pc_w )
|
||||
m_fdc->dden_w(BIT(data, 2));
|
||||
|
||||
// charset
|
||||
m_alt = BIT(data, 3);
|
||||
m_256 = BIT(data, 4);
|
||||
m_alt = !BIT(data, 3);
|
||||
m_256 = !BIT(data, 4);
|
||||
|
||||
// beep enable
|
||||
m_discrete->write(space, NODE_01, BIT(data, 5));
|
||||
m_discrete->write(space, NODE_01, !BIT(data, 5));
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -690,13 +692,6 @@ IRQ_CALLBACK_MEMBER(vixen_state::vixen_int_ack)
|
||||
void vixen_state::machine_start()
|
||||
{
|
||||
// configure memory banking
|
||||
UINT8 *ram = m_ram->pointer();
|
||||
|
||||
membank("bank1")->configure_entry(0, ram);
|
||||
membank("bank1")->configure_entry(1, m_rom);
|
||||
|
||||
membank("bank2")->configure_entry(0, ram);
|
||||
membank("bank2")->configure_entry(1, m_video_ram);
|
||||
|
||||
membank("bank3")->configure_entry(0, m_video_ram);
|
||||
membank("bank3")->configure_entry(1, m_rom);
|
||||
@ -704,7 +699,6 @@ void vixen_state::machine_start()
|
||||
membank("bank4")->configure_entry(0, m_video_ram);
|
||||
|
||||
// register for state saving
|
||||
save_item(NAME(m_reset));
|
||||
save_item(NAME(m_col));
|
||||
save_item(NAME(m_cmd_d0));
|
||||
save_item(NAME(m_cmd_d1));
|
||||
@ -714,17 +708,8 @@ void vixen_state::machine_start()
|
||||
|
||||
void vixen_state::machine_reset()
|
||||
{
|
||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
program.install_read_bank(0x0000, 0xefff, 0xfff, 0, "bank1");
|
||||
program.install_write_bank(0x0000, 0xefff, 0xfff, 0, "bank2");
|
||||
|
||||
membank("bank1")->set_entry(1);
|
||||
membank("bank2")->set_entry(1);
|
||||
membank("bank3")->set_entry(1);
|
||||
|
||||
m_reset = 1;
|
||||
|
||||
m_vsync = 0;
|
||||
m_cmd_d0 = 0;
|
||||
m_cmd_d1 = 0;
|
||||
@ -733,6 +718,7 @@ void vixen_state::machine_reset()
|
||||
m_fdc->reset();
|
||||
m_io_i8155->reset();
|
||||
m_usart->reset();
|
||||
m_maincpu->set_state_int(Z80_PC, 0xf000);
|
||||
}
|
||||
|
||||
|
||||
@ -749,6 +735,7 @@ static MACHINE_CONFIG_START( vixen, vixen_state )
|
||||
// basic machine hardware
|
||||
MCFG_CPU_ADD(Z8400A_TAG, Z80, XTAL_23_9616MHz/6)
|
||||
MCFG_CPU_PROGRAM_MAP(vixen_mem)
|
||||
MCFG_CPU_DECRYPTED_OPCODES_MAP(bios_mem)
|
||||
MCFG_CPU_IO_MAP(vixen_io)
|
||||
MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(vixen_state,vixen_int_ack)
|
||||
|
||||
@ -793,7 +780,9 @@ static MACHINE_CONFIG_START( vixen, vixen_state )
|
||||
MCFG_FD1797_ADD(FDC1797_TAG, XTAL_23_9616MHz/24)
|
||||
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(vixen_state, fdc_intrq_w))
|
||||
MCFG_FLOPPY_DRIVE_ADD(FDC1797_TAG":0", vixen_floppies, "525dd", floppy_image_device::default_floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_SOUND(true)
|
||||
MCFG_FLOPPY_DRIVE_ADD(FDC1797_TAG":1", vixen_floppies, "525dd", floppy_image_device::default_floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_SOUND(true)
|
||||
MCFG_IEEE488_BUS_ADD()
|
||||
MCFG_IEEE488_SRQ_CALLBACK(WRITELINE(vixen_state, srq_w))
|
||||
MCFG_IEEE488_ATN_CALLBACK(WRITELINE(vixen_state, atn_w))
|
||||
@ -837,34 +826,10 @@ ROM_END
|
||||
// DRIVER_INIT( vixen )
|
||||
//-------------------------------------------------
|
||||
|
||||
DIRECT_UPDATE_MEMBER(vixen_state::vixen_direct_update_handler)
|
||||
{
|
||||
if (address >= 0xf000)
|
||||
{
|
||||
if (m_reset)
|
||||
{
|
||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
program.install_read_bank(0x0000, 0xefff, "bank1");
|
||||
program.install_write_bank(0x0000, 0xefff, "bank2");
|
||||
|
||||
membank("bank1")->set_entry(0);
|
||||
membank("bank2")->set_entry(0);
|
||||
|
||||
m_reset = 0;
|
||||
}
|
||||
|
||||
direct.explicit_configure(0xf000, 0xffff, 0xfff, m_rom);
|
||||
|
||||
return ~0;
|
||||
}
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(vixen_state,vixen)
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(vixen_state::vixen_direct_update_handler), this));
|
||||
m_program = &m_maincpu->space(AS_PROGRAM);
|
||||
}
|
||||
|
||||
|
||||
@ -873,5 +838,5 @@ DRIVER_INIT_MEMBER(vixen_state,vixen)
|
||||
// SYSTEM DRIVERS
|
||||
//**************************************************************************
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1984, vixen, 0, 0, vixen, vixen, vixen_state, vixen, "Osborne", "Vixen", MACHINE_NOT_WORKING )
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1984, vixen, 0, 0, vixen, vixen, vixen_state, vixen, "Osborne", "Vixen", 0 )
|
||||
|
||||
@ -11,7 +11,6 @@
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "cpu/z80/z80daisy.h"
|
||||
#include "sound/beep.h"
|
||||
#include "machine/6821pia.h"
|
||||
#include "machine/6850acia.h"
|
||||
@ -25,43 +24,75 @@ public:
|
||||
enum
|
||||
{
|
||||
TIMER_VIDEO,
|
||||
TIMER_ACIA_RXC_TXC,
|
||||
TIMER_SETUP
|
||||
};
|
||||
|
||||
osborne1_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
osborne1_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_pia0(*this, "pia_0"),
|
||||
m_pia1(*this, "pia_1"),
|
||||
m_acia(*this, "acia"),
|
||||
m_fdc(*this, "mb8877"),
|
||||
m_beep(*this, "beeper"),
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_ieee(*this, IEEE488_TAG),
|
||||
m_floppy0(*this, "mb8877:0:525ssdd"),
|
||||
m_floppy1(*this, "mb8877:1:525ssdd"),
|
||||
m_row0(*this, "ROW0"),
|
||||
m_row1(*this, "ROW1"),
|
||||
m_row2(*this, "ROW2"),
|
||||
m_row3(*this, "ROW3"),
|
||||
m_row4(*this, "ROW4"),
|
||||
m_row5(*this, "ROW5"),
|
||||
m_row6(*this, "ROW6"),
|
||||
m_row7(*this, "ROW7"),
|
||||
m_video_timer(NULL),
|
||||
m_keyb_row0(*this, "ROW0"),
|
||||
m_keyb_row1(*this, "ROW1"),
|
||||
m_keyb_row2(*this, "ROW2"),
|
||||
m_keyb_row3(*this, "ROW3"),
|
||||
m_keyb_row4(*this, "ROW4"),
|
||||
m_keyb_row5(*this, "ROW5"),
|
||||
m_keyb_row6(*this, "ROW6"),
|
||||
m_keyb_row7(*this, "ROW7"),
|
||||
m_btn_reset(*this, "RESET"),
|
||||
m_cnf(*this, "CNF"),
|
||||
m_bank1(*this, "bank1"),
|
||||
m_bank2(*this, "bank2"),
|
||||
m_bank3(*this, "bank3"),
|
||||
m_region_maincpu(*this, "maincpu") { }
|
||||
m_region_maincpu(*this, "maincpu"),
|
||||
m_bank_0xxx(*this, "bank_0xxx"),
|
||||
m_bank_1xxx(*this, "bank_1xxx"),
|
||||
m_bank_fxxx(*this, "bank_fxxx"),
|
||||
m_acia_rxc_txc_timer(NULL)
|
||||
{ }
|
||||
|
||||
|
||||
DECLARE_WRITE8_MEMBER(bank_0xxx_w);
|
||||
DECLARE_WRITE8_MEMBER(bank_1xxx_w);
|
||||
DECLARE_READ8_MEMBER(bank_2xxx_3xxx_r);
|
||||
DECLARE_WRITE8_MEMBER(bank_2xxx_3xxx_w);
|
||||
DECLARE_WRITE8_MEMBER(videoram_w);
|
||||
DECLARE_READ8_MEMBER(opcode_r);
|
||||
DECLARE_WRITE8_MEMBER(bankswitch_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(irqack_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(ieee_pia_pb_r);
|
||||
DECLARE_WRITE8_MEMBER(ieee_pia_pb_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ieee_pia_irq_a_func);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(video_pia_port_a_w);
|
||||
DECLARE_WRITE8_MEMBER(video_pia_port_b_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(video_pia_out_cb2_dummy);
|
||||
DECLARE_WRITE_LINE_MEMBER(video_pia_irq_a_func);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(serial_acia_irq_func);
|
||||
|
||||
DECLARE_DRIVER_INIT(osborne1);
|
||||
virtual void machine_reset();
|
||||
virtual void video_start();
|
||||
|
||||
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
||||
TIMER_CALLBACK_MEMBER(video_callback);
|
||||
TIMER_CALLBACK_MEMBER(setup_callback);
|
||||
|
||||
bitmap_ind16 m_bitmap;
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<pia6821_device> m_pia0;
|
||||
required_device<pia6821_device> m_pia1;
|
||||
required_device<acia6850_device> m_acia;
|
||||
required_device<mb8877_t> m_fdc;
|
||||
required_device<beep_device> m_beep;
|
||||
required_device<ram_device> m_ram;
|
||||
@ -69,79 +100,59 @@ public:
|
||||
required_device<floppy_image_device> m_floppy0;
|
||||
required_device<floppy_image_device> m_floppy1;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(osborne1_0000_w);
|
||||
DECLARE_WRITE8_MEMBER(osborne1_1000_w);
|
||||
DECLARE_READ8_MEMBER(osborne1_2000_r);
|
||||
DECLARE_WRITE8_MEMBER(osborne1_2000_w);
|
||||
DECLARE_WRITE8_MEMBER(osborne1_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(osborne1_bankswitch_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ieee_pia_irq_a_func);
|
||||
DECLARE_READ8_MEMBER(ieee_pia_pb_r);
|
||||
DECLARE_WRITE8_MEMBER(ieee_pia_pb_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(video_pia_out_cb2_dummy);
|
||||
DECLARE_WRITE8_MEMBER(video_pia_port_a_w);
|
||||
DECLARE_WRITE8_MEMBER(video_pia_port_b_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(video_pia_irq_a_func);
|
||||
DECLARE_DIRECT_UPDATE_MEMBER(osborne1_opbase);
|
||||
|
||||
bool m_bank2_enabled;
|
||||
UINT8 m_bit_9;
|
||||
/* IRQ states */
|
||||
bool m_pia_0_irq_state;
|
||||
bool m_pia_1_irq_state;
|
||||
/* video related */
|
||||
UINT8 m_screen_pac;
|
||||
UINT8 m_resolution;
|
||||
UINT8 m_hc_left;
|
||||
UINT8 m_new_start_x;
|
||||
UINT8 m_new_start_y;
|
||||
emu_timer *m_video_timer;
|
||||
UINT8 *m_p_chargen;
|
||||
/* bankswitch setting */
|
||||
UINT8 m_bankswitch;
|
||||
bool m_in_irq_handler;
|
||||
bool m_beep_state;
|
||||
DECLARE_DRIVER_INIT(osborne1);
|
||||
virtual void machine_reset();
|
||||
TIMER_CALLBACK_MEMBER(osborne1_video_callback);
|
||||
TIMER_CALLBACK_MEMBER(setup_osborne1);
|
||||
|
||||
protected:
|
||||
required_ioport m_row0;
|
||||
required_ioport m_row1;
|
||||
required_ioport m_row2;
|
||||
required_ioport m_row3;
|
||||
required_ioport m_row4;
|
||||
required_ioport m_row5;
|
||||
required_ioport m_row6;
|
||||
required_ioport m_row7;
|
||||
required_ioport m_cnf;
|
||||
required_memory_bank m_bank1;
|
||||
required_memory_bank m_bank2;
|
||||
required_memory_bank m_bank3;
|
||||
required_memory_region m_region_maincpu;
|
||||
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
bool set_rom_mode(UINT8 value);
|
||||
bool set_bit_9(UINT8 value);
|
||||
void update_irq();
|
||||
void update_acia_rxc_txc();
|
||||
|
||||
// user inputs
|
||||
required_ioport m_keyb_row0;
|
||||
required_ioport m_keyb_row1;
|
||||
required_ioport m_keyb_row2;
|
||||
required_ioport m_keyb_row3;
|
||||
required_ioport m_keyb_row4;
|
||||
required_ioport m_keyb_row5;
|
||||
required_ioport m_keyb_row6;
|
||||
required_ioport m_keyb_row7;
|
||||
required_ioport m_btn_reset;
|
||||
|
||||
// fake inputs for hardware configuration and things that need rewiring
|
||||
required_ioport m_cnf;
|
||||
|
||||
// pieces of memory
|
||||
required_memory_region m_region_maincpu;
|
||||
required_memory_bank m_bank_0xxx;
|
||||
required_memory_bank m_bank_1xxx;
|
||||
required_memory_bank m_bank_fxxx;
|
||||
|
||||
// configuration (reloaded on reset)
|
||||
UINT8 m_screen_pac;
|
||||
UINT8 m_acia_rxc_txc_div;
|
||||
UINT8 m_acia_rxc_txc_p_low;
|
||||
UINT8 m_acia_rxc_txc_p_high;
|
||||
|
||||
// bank switch control bits
|
||||
UINT8 m_ub4a_q;
|
||||
UINT8 m_ub6a_q;
|
||||
UINT8 m_rom_mode;
|
||||
UINT8 m_bit_9;
|
||||
|
||||
// serial state
|
||||
int m_acia_irq_state;
|
||||
int m_acia_rxc_txc_state;
|
||||
emu_timer *m_acia_rxc_txc_timer;
|
||||
};
|
||||
|
||||
|
||||
// ======================> osborne1_daisy_device
|
||||
|
||||
class osborne1_daisy_device : public device_t,
|
||||
public device_z80daisy_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
osborne1_daisy_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
private:
|
||||
virtual void device_start();
|
||||
// z80daisy_interface overrides
|
||||
virtual int z80daisy_irq_state();
|
||||
virtual int z80daisy_irq_ack();
|
||||
virtual void z80daisy_irq_reti();
|
||||
};
|
||||
|
||||
extern const device_type OSBORNE1_DAISY;
|
||||
|
||||
#endif /* OSBORNE1_H_ */
|
||||
|
||||
@ -53,6 +53,29 @@ public:
|
||||
m_txrdy(0)
|
||||
{ }
|
||||
|
||||
DECLARE_READ8_MEMBER( status_r );
|
||||
DECLARE_WRITE8_MEMBER( cmd_w );
|
||||
DECLARE_READ8_MEMBER( ieee488_r );
|
||||
DECLARE_READ8_MEMBER( port3_r );
|
||||
DECLARE_READ8_MEMBER( i8155_pa_r );
|
||||
DECLARE_WRITE8_MEMBER( i8155_pb_w );
|
||||
DECLARE_WRITE8_MEMBER( i8155_pc_w );
|
||||
DECLARE_WRITE8_MEMBER( io_i8155_pb_w );
|
||||
DECLARE_WRITE8_MEMBER( io_i8155_pc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( io_i8155_to_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( srq_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( atn_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rxrdy_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( txrdy_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w );
|
||||
DECLARE_DRIVER_INIT(vixen);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(vsync_tick);
|
||||
IRQ_CALLBACK_MEMBER(vixen_int_ack);
|
||||
DECLARE_READ8_MEMBER(opram_r);
|
||||
DECLARE_READ8_MEMBER(oprom_r);
|
||||
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<fd1797_t> m_fdc;
|
||||
required_device<i8155_device> m_io_i8155;
|
||||
@ -70,35 +93,15 @@ public:
|
||||
required_shared_ptr<UINT8> m_video_ram;
|
||||
required_ioport_array<8> m_key;
|
||||
|
||||
address_space *m_program;
|
||||
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
|
||||
virtual void video_start();
|
||||
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
void update_interrupt();
|
||||
|
||||
DECLARE_WRITE8_MEMBER( ctl_w );
|
||||
DECLARE_READ8_MEMBER( status_r );
|
||||
DECLARE_WRITE8_MEMBER( cmd_w );
|
||||
DECLARE_READ8_MEMBER( ieee488_r );
|
||||
DECLARE_READ8_MEMBER( port3_r );
|
||||
DECLARE_READ8_MEMBER( i8155_pa_r );
|
||||
DECLARE_WRITE8_MEMBER( i8155_pb_w );
|
||||
DECLARE_WRITE8_MEMBER( i8155_pc_w );
|
||||
DECLARE_WRITE8_MEMBER( io_i8155_pb_w );
|
||||
DECLARE_WRITE8_MEMBER( io_i8155_pc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( io_i8155_to_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( srq_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( atn_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rxrdy_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( txrdy_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w );
|
||||
DIRECT_UPDATE_MEMBER(vixen_direct_update_handler);
|
||||
|
||||
// memory state
|
||||
int m_reset;
|
||||
|
||||
// keyboard state
|
||||
UINT8 m_col;
|
||||
|
||||
@ -122,12 +125,8 @@ public:
|
||||
int m_enb_ring_int;
|
||||
|
||||
// video state
|
||||
int m_alt;
|
||||
int m_256;
|
||||
|
||||
DECLARE_DRIVER_INIT(vixen);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(vsync_tick);
|
||||
IRQ_CALLBACK_MEMBER(vixen_int_ack);
|
||||
bool m_alt;
|
||||
bool m_256;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -3,229 +3,155 @@
|
||||
/***************************************************************************
|
||||
|
||||
There are three IRQ sources:
|
||||
- IRQ0
|
||||
- IRQ0 = IRQ from the serial ACIA
|
||||
- IRQ1 = IRQA from the video PIA
|
||||
- IRQ2 = IRQA from the IEEE488 PIA
|
||||
|
||||
Interrupt handling on the Osborne-1 is a bit awkward. When an interrupt is
|
||||
taken by the Z80 the ROMMODE is enabled on each fetch of an instruction
|
||||
byte. During execution of an instruction the previous ROMMODE setting seems
|
||||
to be used. Side effect of this is that when an interrupt is taken and the
|
||||
stack pointer is pointing to 0000-3FFF then the return address will still
|
||||
be written to RAM if RAM was switched in.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "includes/osborne1.h"
|
||||
|
||||
#define RAMMODE (0x01)
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::osborne1_0000_w )
|
||||
WRITE8_MEMBER( osborne1_state::bank_0xxx_w )
|
||||
{
|
||||
/* Check whether regular RAM is enabled */
|
||||
if ( !m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE) )
|
||||
{
|
||||
m_ram->pointer()[ offset ] = data;
|
||||
}
|
||||
if (!m_rom_mode)
|
||||
m_ram->pointer()[offset] = data;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::osborne1_1000_w )
|
||||
WRITE8_MEMBER( osborne1_state::bank_1xxx_w )
|
||||
{
|
||||
/* Check whether regular RAM is enabled */
|
||||
if ( !m_bank2_enabled || ( m_in_irq_handler && m_bankswitch == RAMMODE) )
|
||||
{
|
||||
m_ram->pointer()[ 0x1000 + offset ] = data;
|
||||
}
|
||||
if (!m_rom_mode)
|
||||
m_ram->pointer()[0x1000 + offset] = data;
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER( osborne1_state::osborne1_2000_r )
|
||||
READ8_MEMBER( osborne1_state::bank_2xxx_3xxx_r )
|
||||
{
|
||||
if (!m_rom_mode)
|
||||
return m_ram->pointer()[0x2000 + offset];
|
||||
|
||||
// This isn't really accurate - bus fighting will occur for many values
|
||||
// since each peripheral only checks two bits. We just return 0xFF for
|
||||
// any undocumented address.
|
||||
UINT8 data = 0xFF;
|
||||
|
||||
/* Check whether regular RAM is enabled */
|
||||
if ( !m_bank2_enabled )
|
||||
switch (offset & 0x0F00)
|
||||
{
|
||||
data = m_ram->pointer()[ 0x2000 + offset ];
|
||||
}
|
||||
else
|
||||
{
|
||||
// This isn't really accurate - bus fighting will occur for many values
|
||||
// since each peripheral only checks two bits. We just return 0xFF for
|
||||
// any undocumented address.
|
||||
switch ( offset & 0x0F00 )
|
||||
{
|
||||
case 0x100: /* Floppy */
|
||||
data = m_fdc->read( space, offset & 0x03 );
|
||||
break;
|
||||
case 0x200: /* Keyboard */
|
||||
/* Row 0 */
|
||||
if ( offset & 0x01 ) data &= m_row0->read();
|
||||
/* Row 1 */
|
||||
if ( offset & 0x02 ) data &= m_row1->read();
|
||||
/* Row 2 */
|
||||
if ( offset & 0x04 ) data &= m_row3->read();
|
||||
/* Row 3 */
|
||||
if ( offset & 0x08 ) data &= m_row4->read();
|
||||
/* Row 4 */
|
||||
if ( offset & 0x10 ) data &= m_row5->read();
|
||||
/* Row 5 */
|
||||
if ( offset & 0x20 ) data &= m_row2->read();
|
||||
/* Row 6 */
|
||||
if ( offset & 0x40 ) data &= m_row6->read();
|
||||
/* Row 7 */
|
||||
if ( offset & 0x80 ) data &= m_row7->read();
|
||||
break;
|
||||
case 0x400: /* SCREEN-PAC */
|
||||
if (m_screen_pac) data &= 0xFB;
|
||||
break;
|
||||
case 0x900: /* IEEE488 PIA */
|
||||
data = m_pia0->read(space, offset & 0x03);
|
||||
break;
|
||||
case 0xA00: /* Serial */
|
||||
break;
|
||||
case 0xC00: /* Video PIA */
|
||||
data = m_pia1->read(space, offset & 0x03);
|
||||
break;
|
||||
}
|
||||
case 0x100: /* Floppy */
|
||||
data = m_fdc->read(space, offset & 0x03);
|
||||
break;
|
||||
case 0x200: /* Keyboard */
|
||||
if (offset & 0x01) data &= m_keyb_row0->read();
|
||||
if (offset & 0x02) data &= m_keyb_row1->read();
|
||||
if (offset & 0x04) data &= m_keyb_row3->read();
|
||||
if (offset & 0x08) data &= m_keyb_row4->read();
|
||||
if (offset & 0x10) data &= m_keyb_row5->read();
|
||||
if (offset & 0x20) data &= m_keyb_row2->read();
|
||||
if (offset & 0x40) data &= m_keyb_row6->read();
|
||||
if (offset & 0x80) data &= m_keyb_row7->read();
|
||||
break;
|
||||
case 0x400: /* SCREEN-PAC */
|
||||
if (m_screen_pac) data &= 0xFB;
|
||||
break;
|
||||
case 0x900: /* IEEE488 PIA */
|
||||
data = m_pia0->read(space, offset & 0x03);
|
||||
break;
|
||||
case 0xA00: /* Serial */
|
||||
if (offset & 0x01) data = m_acia->data_r(space, 0);
|
||||
else data = m_acia->status_r(space, 0);
|
||||
break;
|
||||
case 0xC00: /* Video PIA */
|
||||
data = m_pia1->read(space, offset & 0x03);
|
||||
break;
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::osborne1_2000_w )
|
||||
WRITE8_MEMBER( osborne1_state::bank_2xxx_3xxx_w )
|
||||
{
|
||||
#if 0
|
||||
/* Check whether regular RAM is enabled */
|
||||
if ( !m_bank2_enabled || (m_in_irq_handler && m_bankswitch == RAMMODE) )
|
||||
if (!m_rom_mode)
|
||||
{
|
||||
m_ram->pointer()[ 0x2000 + offset ] = data;
|
||||
m_ram->pointer()[0x2000 + offset] = data;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Handle writes to the I/O area */
|
||||
if ( 0x100 == (offset & 0x900) ) /* Floppy */
|
||||
// Handle writes to the I/O area
|
||||
if ((offset & 0x900) == 0x100) // Floppy
|
||||
m_fdc->write(space, offset & 0x03, data);
|
||||
if ( 0x400 == (offset & 0xC00) ) /* SCREEN-PAC */
|
||||
if ((offset & 0x900) == 0x900) // IEEE488 PIA
|
||||
m_pia0->write(space, offset & 0x03, data);
|
||||
if ((offset & 0xA00) == 0xA00) // Serial
|
||||
{
|
||||
if (offset & 0x01) m_acia->data_w(space, 0, data);
|
||||
else m_acia->control_w(space, 0, data);
|
||||
}
|
||||
if ((offset & 0xC00) == 0x400) // SCREEN-PAC
|
||||
{
|
||||
m_resolution = data & 0x01;
|
||||
m_hc_left = (data >> 1) & 0x01;
|
||||
}
|
||||
if ( 0x900 == (offset & 0x900) ) /* IEEE488 PIA */
|
||||
m_pia0->write(space, offset & 0x03, data);
|
||||
if ( 0xA00 == (offset & 0xA00) ) /* Serial */
|
||||
/* not implemented */;
|
||||
if ( 0xC00 == (offset & 0xC00) ) /* Video PIA */
|
||||
if ((offset & 0xC00) == 0xC00) // Video PIA
|
||||
m_pia1->write(space, offset & 0x03, data);
|
||||
}
|
||||
#else
|
||||
// This code is a nasty hack that doesn't reflect hardware operation,
|
||||
// but it gets us by while the bank selection implementation is inadequate
|
||||
if ( ! m_bank2_enabled )
|
||||
{
|
||||
m_ram->pointer()[ 0x2000 + offset ] = data;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( m_in_irq_handler && m_bankswitch == RAMMODE )
|
||||
{
|
||||
m_ram->pointer()[ 0x2000 + offset ] = data;
|
||||
}
|
||||
/* Handle writes to the I/O area */
|
||||
switch( offset & 0x1F00 )
|
||||
{
|
||||
case 0x100: /* Floppy */
|
||||
m_fdc->write(space, offset & 0x03, data);
|
||||
break;
|
||||
case 0x400: /* SCREEN-PAC */
|
||||
m_resolution = data & 0x01;
|
||||
m_hc_left = (data >> 1) & 0x01;
|
||||
break;
|
||||
case 0x900: /* IEEE488 PIA */
|
||||
m_pia0->write(space, offset & 0x03, data );
|
||||
break;
|
||||
case 0xA00: /* Serial */
|
||||
break;
|
||||
case 0xC00: /* Video PIA */
|
||||
m_pia1->write(space, offset & 0x03, data );
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::osborne1_videoram_w )
|
||||
WRITE8_MEMBER( osborne1_state::videoram_w )
|
||||
{
|
||||
/* Check whether the video attribute section is enabled */
|
||||
if ( m_bit_9 )
|
||||
data |= 0x7F;
|
||||
|
||||
reinterpret_cast<UINT8 *>(m_bank3->base())[offset] = data;
|
||||
// Attribute RAM is only one bit wide - low seven bits are discarded and read back high
|
||||
if (m_bit_9) data |= 0x7F;
|
||||
reinterpret_cast<UINT8 *>(m_bank_fxxx->base())[offset] = data;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::osborne1_bankswitch_w )
|
||||
READ8_MEMBER( osborne1_state::opcode_r )
|
||||
{
|
||||
switch ( offset & 0x03 )
|
||||
// Update the flipflops that control bank selection and NMI
|
||||
UINT8 const new_ub6a_q = (m_btn_reset->read() & 0x80) ? 1 : 0;
|
||||
if (!m_rom_mode)
|
||||
{
|
||||
set_rom_mode(m_ub4a_q ? 0 : 1);
|
||||
m_ub4a_q = m_ub6a_q;
|
||||
}
|
||||
m_ub6a_q = new_ub6a_q;
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, m_ub6a_q ? CLEAR_LINE : ASSERT_LINE);
|
||||
|
||||
// Now that's sorted out we can call the normal read handler
|
||||
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::bankswitch_w )
|
||||
{
|
||||
switch (offset & 0x03)
|
||||
{
|
||||
case 0x00:
|
||||
m_bank2_enabled = 1;
|
||||
m_bankswitch = 0x00;
|
||||
if (set_rom_mode(1))
|
||||
m_ub4a_q = m_ub6a_q;
|
||||
break;
|
||||
case 0x01:
|
||||
m_bank2_enabled = 0;
|
||||
m_bankswitch = 0x01;
|
||||
m_ub4a_q = 1;
|
||||
m_ub6a_q = 1;
|
||||
set_rom_mode(0);
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
|
||||
break;
|
||||
case 0x02:
|
||||
m_bit_9 = 1;
|
||||
set_bit_9(1);
|
||||
break;
|
||||
case 0x03:
|
||||
m_bit_9 = 0;
|
||||
set_bit_9(0);
|
||||
break;
|
||||
}
|
||||
if ( m_bank2_enabled )
|
||||
{
|
||||
m_bank1->set_base(m_region_maincpu->base());
|
||||
m_bank2->set_base(m_region_maincpu->base());
|
||||
}
|
||||
else
|
||||
{
|
||||
m_bank1->set_base(m_ram->pointer());
|
||||
m_bank2->set_base(m_ram->pointer() + 0x1000);
|
||||
}
|
||||
m_bank3->set_base(m_ram->pointer() + (m_bit_9 ? 0x10000 : 0xF000));
|
||||
m_in_irq_handler = 0;
|
||||
}
|
||||
|
||||
|
||||
DIRECT_UPDATE_MEMBER(osborne1_state::osborne1_opbase)
|
||||
WRITE_LINE_MEMBER( osborne1_state::irqack_w )
|
||||
{
|
||||
if ( ( address & 0xF000 ) == 0x2000 )
|
||||
{
|
||||
if ( ! m_bank2_enabled )
|
||||
{
|
||||
direct.explicit_configure(0x2000, 0x2fff, 0x0fff, m_ram->pointer() + 0x2000);
|
||||
return ~0;
|
||||
}
|
||||
}
|
||||
return address;
|
||||
}
|
||||
|
||||
|
||||
WRITE_LINE_MEMBER( osborne1_state::ieee_pia_irq_a_func )
|
||||
{
|
||||
m_pia_0_irq_state = state;
|
||||
m_maincpu->set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
|
||||
// Update the flipflops that control bank selection and NMI
|
||||
if (!m_rom_mode) set_rom_mode(m_ub4a_q ? 0 : 1);
|
||||
m_ub4a_q = 0;
|
||||
m_ub6a_q = (m_btn_reset->read() & 0x80) ? 1 : 0;
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, m_ub6a_q ? CLEAR_LINE : ASSERT_LINE);
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER( osborne1_state::ieee_pia_pb_r )
|
||||
{
|
||||
/*
|
||||
|
||||
bit description
|
||||
|
||||
0
|
||||
@ -236,9 +162,7 @@ READ8_MEMBER( osborne1_state::ieee_pia_pb_r )
|
||||
5 DAV
|
||||
6 NDAC
|
||||
7 NRFD
|
||||
|
||||
*/
|
||||
|
||||
UINT8 data = 0;
|
||||
|
||||
data |= m_ieee->eoi_r() << 3;
|
||||
@ -249,11 +173,9 @@ READ8_MEMBER( osborne1_state::ieee_pia_pb_r )
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::ieee_pia_pb_w )
|
||||
{
|
||||
/*
|
||||
|
||||
bit description
|
||||
|
||||
0
|
||||
@ -264,9 +186,7 @@ WRITE8_MEMBER( osborne1_state::ieee_pia_pb_w )
|
||||
5 DAV
|
||||
6 NDAC
|
||||
7 NRFD
|
||||
|
||||
*/
|
||||
|
||||
m_ieee->eoi_w(BIT(data, 3));
|
||||
m_ieee->atn_w(BIT(data, 4));
|
||||
m_ieee->dav_w(BIT(data, 5));
|
||||
@ -274,9 +194,9 @@ WRITE8_MEMBER( osborne1_state::ieee_pia_pb_w )
|
||||
m_ieee->nrfd_w(BIT(data, 7));
|
||||
}
|
||||
|
||||
|
||||
WRITE_LINE_MEMBER( osborne1_state::video_pia_out_cb2_dummy )
|
||||
WRITE_LINE_MEMBER( osborne1_state::ieee_pia_irq_a_func )
|
||||
{
|
||||
update_irq();
|
||||
}
|
||||
|
||||
|
||||
@ -293,7 +213,6 @@ WRITE8_MEMBER( osborne1_state::video_pia_port_a_w )
|
||||
//logerror("Video pia port a write: %02X, density set to %s\n", data, data & 1 ? "FM" : "MFM" );
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( osborne1_state::video_pia_port_b_w )
|
||||
{
|
||||
m_new_start_y = data & 0x1F;
|
||||
@ -317,63 +236,114 @@ WRITE8_MEMBER( osborne1_state::video_pia_port_b_w )
|
||||
//logerror("Video pia port b write: %02X\n", data );
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( osborne1_state::video_pia_out_cb2_dummy )
|
||||
{
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( osborne1_state::video_pia_irq_a_func )
|
||||
{
|
||||
m_pia_1_irq_state = state;
|
||||
m_maincpu->set_input_line(0, ( m_pia_1_irq_state ) ? ASSERT_LINE : CLEAR_LINE);
|
||||
update_irq();
|
||||
}
|
||||
|
||||
|
||||
//static const struct aica6850_interface osborne1_6850_config =
|
||||
//{
|
||||
// 10, /* tx_clock */
|
||||
// 10, /* rx_clock */
|
||||
// NULL, /* rx_pin */
|
||||
// NULL, /* tx_pin */
|
||||
// NULL, /* cts_pin */
|
||||
// NULL, /* rts_pin */
|
||||
// NULL, /* dcd_pin */
|
||||
// NULL /* int_callback */
|
||||
//};
|
||||
|
||||
|
||||
void osborne1_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
WRITE_LINE_MEMBER( osborne1_state::serial_acia_irq_func )
|
||||
{
|
||||
switch (id)
|
||||
{
|
||||
case TIMER_VIDEO:
|
||||
osborne1_video_callback(ptr, param);
|
||||
break;
|
||||
case TIMER_SETUP:
|
||||
setup_osborne1(ptr, param);
|
||||
break;
|
||||
default:
|
||||
assert_always(FALSE, "Unknown id in osborne1_state::device_timer");
|
||||
}
|
||||
m_acia_irq_state = state;
|
||||
update_irq();
|
||||
}
|
||||
|
||||
|
||||
TIMER_CALLBACK_MEMBER(osborne1_state::osborne1_video_callback)
|
||||
DRIVER_INIT_MEMBER( osborne1_state, osborne1 )
|
||||
{
|
||||
m_bank_0xxx->configure_entries(0, 1, m_ram->pointer(), 0);
|
||||
m_bank_0xxx->configure_entries(1, 1, m_region_maincpu->base(), 0);
|
||||
m_bank_1xxx->configure_entries(0, 1, m_ram->pointer() + 0x1000, 0);
|
||||
m_bank_1xxx->configure_entries(1, 1, m_region_maincpu->base(), 0);
|
||||
m_bank_fxxx->configure_entries(0, 1, m_ram->pointer() + 0xF000, 0);
|
||||
m_bank_fxxx->configure_entries(1, 1, m_ram->pointer() + 0x10000, 0);
|
||||
|
||||
m_video_timer = timer_alloc(TIMER_VIDEO);
|
||||
m_video_timer->adjust(machine().first_screen()->time_until_pos(1, 0));
|
||||
|
||||
m_acia_rxc_txc_timer = timer_alloc(TIMER_ACIA_RXC_TXC);
|
||||
|
||||
timer_set(attotime::zero, TIMER_SETUP);
|
||||
}
|
||||
|
||||
void osborne1_state::machine_reset()
|
||||
{
|
||||
// Refresh configuration
|
||||
m_screen_pac = 0 != (m_cnf->read() & 0x01);
|
||||
switch (m_cnf->read() & 0x06)
|
||||
{
|
||||
case 0x00:
|
||||
m_acia_rxc_txc_div = 16;
|
||||
m_acia_rxc_txc_p_low = 23;
|
||||
m_acia_rxc_txc_p_high = 29;
|
||||
break;
|
||||
case 0x02:
|
||||
m_acia_rxc_txc_div = 16;
|
||||
m_acia_rxc_txc_p_low = 9;
|
||||
m_acia_rxc_txc_p_high = 15;
|
||||
break;
|
||||
case 0x04:
|
||||
m_acia_rxc_txc_div = 16;
|
||||
m_acia_rxc_txc_p_low = 5;
|
||||
m_acia_rxc_txc_p_high = 8;
|
||||
break;
|
||||
case 0x06:
|
||||
m_acia_rxc_txc_div = 8;
|
||||
m_acia_rxc_txc_p_low = 5;
|
||||
m_acia_rxc_txc_p_high = 8;
|
||||
break;
|
||||
}
|
||||
|
||||
// Initialise memory configuration
|
||||
m_rom_mode = 0;
|
||||
m_bit_9 = 1;
|
||||
set_rom_mode(1);
|
||||
set_bit_9(0);
|
||||
|
||||
// Reset serial state
|
||||
m_acia_irq_state = 0;
|
||||
m_acia_rxc_txc_state = 0;
|
||||
update_acia_rxc_txc();
|
||||
|
||||
m_resolution = 0;
|
||||
m_hc_left = 0;
|
||||
m_p_chargen = memregion( "chargen" )->base();
|
||||
|
||||
for (unsigned i = 0; i < 0x1000; i++)
|
||||
m_ram->pointer()[0x10000 + i] |= 0x7F;
|
||||
}
|
||||
|
||||
void osborne1_state::video_start()
|
||||
{
|
||||
machine().first_screen()->register_screen_bitmap(m_bitmap);
|
||||
}
|
||||
|
||||
UINT32 osborne1_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, cliprect);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
TIMER_CALLBACK_MEMBER(osborne1_state::video_callback)
|
||||
{
|
||||
int const y = machine().first_screen()->vpos();
|
||||
UINT8 ra=0;
|
||||
UINT8 ra = 0;
|
||||
|
||||
/* Check for start of frame */
|
||||
if ( y == 0 )
|
||||
{
|
||||
/* Clear CA1 on video PIA */
|
||||
// Check for start/end of visible area and clear/set CA1 on video PIA
|
||||
if (y == 0)
|
||||
m_pia1->ca1_w(0);
|
||||
}
|
||||
if ( y == 240 )
|
||||
{
|
||||
/* Set CA1 on video PIA */
|
||||
else if (y == 240)
|
||||
m_pia1->ca1_w(1);
|
||||
}
|
||||
if ( y < 240 )
|
||||
|
||||
if (y < 240)
|
||||
{
|
||||
ra = y % 10;
|
||||
/* Draw a line of the display */
|
||||
// Draw a line of the display
|
||||
bool const hires = m_screen_pac & m_resolution;
|
||||
UINT16 const row = (m_new_start_y + (y/10)) * 128 & 0xF80;
|
||||
UINT16 const col = (m_new_start_x & (hires ? 0x60 : 0x7F)) - ((hires && m_hc_left) ? 8 : 0);
|
||||
@ -382,12 +352,12 @@ TIMER_CALLBACK_MEMBER(osborne1_state::osborne1_video_callback)
|
||||
for ( UINT16 x = 0; x < (hires ? 104 : 52); x++ )
|
||||
{
|
||||
UINT16 offs = row | ((col + x) & 0x7F);
|
||||
UINT8 const chr = m_ram->pointer()[ 0xF000 + offs ];
|
||||
UINT8 const dim = m_ram->pointer()[ 0x10000 + offs ] & 0x80;
|
||||
UINT8 const chr = m_ram->pointer()[0xF000 + offs];
|
||||
UINT8 const dim = m_ram->pointer()[0x10000 + offs] & 0x80;
|
||||
|
||||
UINT8 const gfx = ((chr & 0x80) && (ra == 9)) ? 0xFF : m_p_chargen[ (ra << 7) | (chr & 0x7F) ];
|
||||
UINT8 const gfx = ((chr & 0x80) && (ra == 9)) ? 0xFF : m_p_chargen[(ra << 7) | (chr & 0x7F)];
|
||||
|
||||
/* Display a scanline of a character */
|
||||
// Display a scanline of a character
|
||||
*p++ = BIT(gfx, 7) ? ( dim ? 2 : 1 ) : 0;
|
||||
if (!hires) { p[0] = p[-1]; p++; }
|
||||
*p++ = BIT(gfx, 6) ? ( dim ? 2 : 1 ) : 0;
|
||||
@ -407,133 +377,92 @@ TIMER_CALLBACK_MEMBER(osborne1_state::osborne1_video_callback)
|
||||
}
|
||||
}
|
||||
|
||||
if ( (ra==2) || (ra==6) )
|
||||
{
|
||||
m_beep->set_state( m_beep_state );
|
||||
}
|
||||
if ((ra == 2) || (ra == 6))
|
||||
m_beep->set_state(m_beep_state);
|
||||
else
|
||||
{
|
||||
m_beep->set_state( 0 );
|
||||
}
|
||||
m_beep->set_state(0);
|
||||
|
||||
m_video_timer->adjust(machine().first_screen()->time_until_pos(y + 1, 0 ));
|
||||
// Check reset key if necessary - it affects NMI
|
||||
if (!m_ub6a_q)
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, (m_btn_reset->read() && 0x80) ? CLEAR_LINE : ASSERT_LINE);
|
||||
|
||||
m_video_timer->adjust(machine().first_screen()->time_until_pos(y + 1, 0));
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(osborne1_state::setup_osborne1)
|
||||
TIMER_CALLBACK_MEMBER(osborne1_state::setup_callback)
|
||||
{
|
||||
m_beep->set_state( 0 );
|
||||
m_beep->set_frequency( 300 /* 60 * 240 / 2 */ );
|
||||
m_pia1->ca1_w(0);
|
||||
}
|
||||
|
||||
void osborne1_state::machine_reset()
|
||||
|
||||
void osborne1_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
{
|
||||
/* Initialize memory configuration */
|
||||
osborne1_bankswitch_w( m_maincpu->space(AS_IO), 0x00, 0 );
|
||||
|
||||
m_pia_0_irq_state = FALSE;
|
||||
m_pia_1_irq_state = FALSE;
|
||||
m_in_irq_handler = 0;
|
||||
|
||||
m_screen_pac = 0 != (m_cnf->read() & 0x01);
|
||||
m_resolution = 0;
|
||||
m_hc_left = 0;
|
||||
m_p_chargen = memregion( "chargen" )->base();
|
||||
|
||||
memset( m_ram->pointer() + 0x10000, 0xFF, 0x1000 );
|
||||
|
||||
address_space& space = m_maincpu->space(AS_PROGRAM);
|
||||
space.set_direct_update_handler(direct_update_delegate(FUNC(osborne1_state::osborne1_opbase), this));
|
||||
switch (id)
|
||||
{
|
||||
case TIMER_VIDEO:
|
||||
video_callback(ptr, param);
|
||||
break;
|
||||
case TIMER_ACIA_RXC_TXC:
|
||||
m_acia_rxc_txc_state = m_acia_rxc_txc_state ? 0 : 1;
|
||||
update_acia_rxc_txc();
|
||||
break;
|
||||
case TIMER_SETUP:
|
||||
setup_callback(ptr, param);
|
||||
break;
|
||||
default:
|
||||
assert_always(FALSE, "Unknown id in osborne1_state::device_timer");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
DRIVER_INIT_MEMBER(osborne1_state,osborne1)
|
||||
bool osborne1_state::set_rom_mode(UINT8 value)
|
||||
{
|
||||
/* Configure the 6850 ACIA */
|
||||
// acia6850_config( 0, &osborne1_6850_config );
|
||||
m_video_timer = timer_alloc(TIMER_VIDEO);
|
||||
m_video_timer->adjust(machine().first_screen()->time_until_pos(1, 0 ));
|
||||
|
||||
timer_set(attotime::zero, TIMER_SETUP);
|
||||
if (value != m_rom_mode)
|
||||
{
|
||||
m_rom_mode = value;
|
||||
m_bank_0xxx->set_entry(m_rom_mode);
|
||||
m_bank_1xxx->set_entry(m_rom_mode);
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void osborne1_state::video_start()
|
||||
bool osborne1_state::set_bit_9(UINT8 value)
|
||||
{
|
||||
machine().first_screen()->register_screen_bitmap(m_bitmap);
|
||||
if (value != m_bit_9)
|
||||
{
|
||||
m_bit_9 = value;
|
||||
m_bank_fxxx->set_entry(m_bit_9);
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
UINT32 osborne1_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
void osborne1_state::update_irq()
|
||||
{
|
||||
copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, cliprect);
|
||||
return 0;
|
||||
if (m_pia0->irq_a_state())
|
||||
m_maincpu->set_input_line_and_vector(INPUT_LINE_IRQ0, ASSERT_LINE, 0xF0);
|
||||
else if (m_pia1->irq_a_state())
|
||||
m_maincpu->set_input_line_and_vector(INPUT_LINE_IRQ0, ASSERT_LINE, 0xF8);
|
||||
else if (m_acia_irq_state)
|
||||
m_maincpu->set_input_line_and_vector(INPUT_LINE_IRQ0, ASSERT_LINE, 0xFC);
|
||||
else
|
||||
m_maincpu->set_input_line_and_vector(INPUT_LINE_IRQ0, CLEAR_LINE, 0xFE);
|
||||
}
|
||||
|
||||
/****************************************************************
|
||||
Osborne1 specific daisy chain code
|
||||
****************************************************************/
|
||||
|
||||
const device_type OSBORNE1_DAISY = &device_creator<osborne1_daisy_device>;
|
||||
|
||||
//**************************************************************************
|
||||
// LIVE DEVICE
|
||||
//**************************************************************************
|
||||
|
||||
//-------------------------------------------------
|
||||
// z80ctc_device - constructor
|
||||
//-------------------------------------------------
|
||||
osborne1_daisy_device::osborne1_daisy_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: device_t(mconfig, OSBORNE1_DAISY, "Osborne 1 daisy", tag, owner, clock, "osborne1_daisy", __FILE__),
|
||||
device_z80daisy_interface(mconfig, *this)
|
||||
{
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_start - device-specific startup
|
||||
//-------------------------------------------------
|
||||
|
||||
void osborne1_daisy_device::device_start()
|
||||
{
|
||||
}
|
||||
|
||||
//**************************************************************************
|
||||
// DAISY CHAIN INTERFACE
|
||||
//**************************************************************************
|
||||
|
||||
//-------------------------------------------------
|
||||
// z80daisy_irq_state - return the overall IRQ
|
||||
// state for this device
|
||||
//-------------------------------------------------
|
||||
|
||||
int osborne1_daisy_device::z80daisy_irq_state()
|
||||
{
|
||||
osborne1_state *state = machine().driver_data<osborne1_state>();
|
||||
return ( state->m_pia_1_irq_state ? Z80_DAISY_INT : 0 );
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// z80daisy_irq_ack - acknowledge an IRQ and
|
||||
// return the appropriate vector
|
||||
//-------------------------------------------------
|
||||
|
||||
int osborne1_daisy_device::z80daisy_irq_ack()
|
||||
{
|
||||
osborne1_state *state = machine().driver_data<osborne1_state>();
|
||||
/* Enable ROM and I/O when IRQ is acknowledged */
|
||||
UINT8 old_bankswitch = state->m_bankswitch;
|
||||
|
||||
state->osborne1_bankswitch_w( state->m_maincpu->space(AS_IO), 0, 0 );
|
||||
state->m_bankswitch = old_bankswitch;
|
||||
state->m_in_irq_handler = 1;
|
||||
return 0xF8;
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// z80daisy_irq_reti - clear the interrupt
|
||||
// pending state to allow other interrupts through
|
||||
//-------------------------------------------------
|
||||
|
||||
void osborne1_daisy_device::z80daisy_irq_reti()
|
||||
void osborne1_state::update_acia_rxc_txc()
|
||||
{
|
||||
m_acia->write_rxc(m_acia_rxc_txc_state);
|
||||
m_acia->write_txc(m_acia_rxc_txc_state);
|
||||
attoseconds_t const dividend = (ATTOSECONDS_PER_SECOND / 100) * (m_acia_rxc_txc_state ? m_acia_rxc_txc_p_high : m_acia_rxc_txc_p_low);
|
||||
attoseconds_t const divisor = (15974400 / 100) / m_acia_rxc_txc_div;
|
||||
m_acia_rxc_txc_timer->adjust(attotime(0, dividend / divisor));
|
||||
}
|
||||
|
||||
@ -22,7 +22,8 @@ Known A-board revisions:
|
||||
|
||||
Game Year B-board # B-board PALs C-board # CPS-B # C-board PALs
|
||||
----------------------------------------------------------- ---- --------- --------------------- ----------- ----------------------- ------------
|
||||
Forgotten Worlds (World) 1988 88621B-2 LW621 LWIO None CPS-B-01 DL-0411-10001 N/A
|
||||
Forgotten Worlds (World, newer) 1988 88621B-2 LW621 LWIO None CPS-B-01 DL-0411-10001 N/A
|
||||
Forgotten Worlds (World) 88621B-2 LW621 LWIO None CPS-B-01 DL-0411-10001 N/A
|
||||
Forgotten Worlds (USA, B-Board 88618B-2, Rev. A) 88618B-2 LWCHR LWIO None CPS-B-01 DL-0411-10001 N/A
|
||||
Forgotten Worlds (USA, B-Board 88618B-2, Rev. AA) 88618B-2 LWCHR LWIO None CPS-B-01 DL-0411-10001 N/A
|
||||
Forgotten Worlds (USA, B-Board 88618B-2, Rev. C) 88618B-2 LWCHR LWIO None CPS-B-01 DL-0411-10001 N/A
|
||||
@ -1388,6 +1389,7 @@ static const struct CPS1config cps1_config_table[]=
|
||||
{
|
||||
/* name CPSB gfx mapper in2 in3 out2 kludge */
|
||||
{"forgottn", CPS_B_01, mapper_LW621 },
|
||||
{"forgottna", CPS_B_01, mapper_LW621 },
|
||||
{"forgottnu", CPS_B_01, mapper_LW621 },
|
||||
{"forgottnu1", CPS_B_01, mapper_LWCHR },
|
||||
{"forgottnua", CPS_B_01, mapper_LWCHR },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user