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https://github.com/holub/mame
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PPCDRC: Generate some FPSCR flags [Phil Bennett]
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@ -20,6 +20,17 @@
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/***************************************************************************
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CONSTANTS
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***************************************************************************/
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#define DOUBLE_SIGN (U64(0x8000000000000000))
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#define DOUBLE_EXP (U64(0x7ff0000000000000))
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#define DOUBLE_FRAC (U64(0x000fffffffffffff))
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#define DOUBLE_ZERO (0)
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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@ -174,6 +185,98 @@ INLINE void set_decrementer(powerpc_state *ppc, UINT32 newdec)
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}
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/*-------------------------------------------------
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is_nan_double - is a double value a NaN
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-------------------------------------------------*/
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INLINE int is_nan_double(double x)
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{
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UINT64 xi = *(UINT64*)&x;
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return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) &&
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((xi & DOUBLE_FRAC) != DOUBLE_ZERO) );
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}
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/*-------------------------------------------------
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is_qnan_double - is a double value a
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quiet NaN
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-------------------------------------------------*/
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INLINE int is_qnan_double(double x)
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{
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UINT64 xi = *(UINT64*)&x;
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return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) &&
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((xi & U64(0x0007fffffffffff)) == U64(0x000000000000000)) &&
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((xi & U64(0x000800000000000)) == U64(0x000800000000000)) );
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}
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/*-------------------------------------------------
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is_snan_double - is a double value a
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signaling NaN
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-------------------------------------------------*/
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INLINE int is_snan_double(double x)
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{
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UINT64 xi = *(UINT64*)&x;
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return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) &&
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((xi & DOUBLE_FRAC) != DOUBLE_ZERO) &&
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((xi & U64(0x0008000000000000)) == DOUBLE_ZERO) );
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}
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/*-------------------------------------------------
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is_infinity_double - is a double value
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infinity
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-------------------------------------------------*/
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INLINE int is_infinity_double(double x)
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{
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UINT64 xi = *(UINT64*)&x;
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return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) &&
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((xi & DOUBLE_FRAC) == DOUBLE_ZERO) );
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}
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/*-------------------------------------------------
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is_normalized_double - is a double value
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normalized
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-------------------------------------------------*/
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INLINE int is_normalized_double(double x)
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{
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UINT64 exp;
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UINT64 xi = *(UINT64*)&x;
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exp = (xi & DOUBLE_EXP) >> 52;
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return (exp >= 1) && (exp <= 2046);
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}
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/*-------------------------------------------------
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is_denormalized_double - is a double value
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denormalized
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-------------------------------------------------*/
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INLINE int is_denormalized_double(double x)
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{
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UINT64 xi = *(UINT64*)&x;
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return( ((xi & DOUBLE_EXP) == 0) &&
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((xi & DOUBLE_FRAC) != DOUBLE_ZERO) );
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}
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/*-------------------------------------------------
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sign_double - return sign of a double value
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-------------------------------------------------*/
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INLINE int sign_double(double x)
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{
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UINT64 xi = *(UINT64*)&x;
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return ((xi & DOUBLE_SIGN) != 0);
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}
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/***************************************************************************
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INITIALIZATION AND SHUTDOWN
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@ -996,6 +1099,59 @@ void ppccom_execute_mtdcr(powerpc_state *ppc)
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/***************************************************************************
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FLOATING POINT STATUS FLAGS HANDLING
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***************************************************************************/
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/*-------------------------------------------------
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ppccom_update_fprf - update the FPRF field
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of the FPSCR register
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-------------------------------------------------*/
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void ppccom_update_fprf(powerpc_state *ppc)
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{
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UINT32 fprf;
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double f = ppc->f[ppc->param0];
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if (is_qnan_double(f))
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{
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fprf = 0x11;
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}
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else if (is_infinity_double(f))
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{
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if (sign_double(f)) /* -Infinity */
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fprf = 0x09;
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else /* +Infinity */
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fprf = 0x05;
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}
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else if (is_normalized_double(f))
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{
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if (sign_double(f)) /* -Normalized */
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fprf = 0x08;
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else /* +Normalized */
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fprf = 0x04;
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}
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else if (is_denormalized_double(f))
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{
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if (sign_double(f)) /* -Denormalized */
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fprf = 0x18;
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else /* +Denormalized */
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fprf = 0x14;
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}
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else
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{
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if (sign_double(f)) /* -Zero */
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fprf = 0x12;
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else /* +Zero */
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fprf = 0x02;
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}
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ppc->fpscr &= ~0x0001f000;
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ppc->fpscr |= fprf << 12;
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}
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/***************************************************************************
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COMMON GET/SET INFO
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***************************************************************************/
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@ -596,6 +596,8 @@ void ppccom_execute_mtspr(powerpc_state *ppc);
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void ppccom_execute_mfdcr(powerpc_state *ppc);
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void ppccom_execute_mtdcr(powerpc_state *ppc);
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void ppccom_update_fprf(powerpc_state *ppc);
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void ppc4xx_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info);
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void ppc4xx_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info);
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@ -2334,6 +2334,20 @@ static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, cons
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UML_OR(block, CR32(0), IREG(1), XERSO32); // or [cr0],i1,[xerso]
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}
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/*-------------------------------------------------
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generate_fp_flags - compute FPSCR floating
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point status flags
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-------------------------------------------------*/
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static void generate_fp_flags(powerpc_state *ppc, drcuml_block *block, const opcode_desc *desc, int updatefprf)
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{
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/* for now, only handle the FPRF field */
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if (updatefprf)
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{
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UML_MOV(block, MEM(&ppc->param0), IMM(G_RD(desc->opptr.l[0])));
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UML_CALLC(block, ppccom_update_fprf, ppc);
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}
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}
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/*-------------------------------------------------
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generate_branch - generate an unconditional
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@ -3795,6 +3809,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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return generate_instruction_3f(ppc, block, compiler, desc);
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UML_FDADD(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x14: /* FSUBSx */
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@ -3802,6 +3817,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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return generate_instruction_3f(ppc, block, compiler, desc);
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UML_FDSUB(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x19: /* FMULSx */
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@ -3809,6 +3825,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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return generate_instruction_3f(ppc, block, compiler, desc);
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x12: /* FDIVSx */
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@ -3816,6 +3833,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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return generate_instruction_3f(ppc, block, compiler, desc);
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UML_FDDIV(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x16: /* FSQRTSx */
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@ -3823,12 +3841,14 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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return generate_instruction_3f(ppc, block, compiler, desc);
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UML_FDSQRT(block, FREG(0), F64(G_RB(op))); // fdsqrt f0,rb
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x18: /* FRESx */
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UML_FSFRFLT(block, FREG(0), F64(G_RB(op)), QWORD); // fsfrlt f0,rb,qword
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UML_FSRECIP(block, FREG(0), FREG(0)); // fsrecip f0,f0
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UML_FDFRFLT(block, F64(G_RD(op)), FREG(0), DWORD); // fdfrflt rd,f0,dword
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1d: /* FMADDSx */
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@ -3837,6 +3857,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1c: /* FMSUBSx */
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@ -3845,6 +3866,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDSUB(block, FREG(0), FREG(0), F64(G_RB(op))); // fdsub f0,f0,rb
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1f: /* FNMADDSx */
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@ -3854,6 +3876,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
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UML_FDNEG(block, FREG(0), FREG(0)); // fdneg f0,f0
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1e: /* FNMSUBSx */
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@ -3862,6 +3885,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDSUB(block, FREG(0), F64(G_RB(op)), FREG(0)); // fdsub f0,rb,f0
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UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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}
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@ -3887,26 +3911,32 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp
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{
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case 0x15: /* FADDx */
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UML_FDADD(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdadd rd,ra,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x14: /* FSUBx */
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UML_FDSUB(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdsub rd,ra,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x19: /* FMULx */
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UML_FDMUL(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_REGC(op))); // fdmul rd,ra,rc
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x12: /* FDIVx */
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UML_FDDIV(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fddiv rd,ra,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x16: /* FSQRTx */
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UML_FDSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdsqrt rd,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1a: /* FRSQRTEx */
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UML_FDRSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdrsqrt rd,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x17: /* FSELx */
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@ -3918,22 +3948,26 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp
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case 0x1d: /* FMADDx */
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDADD(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdadd rd,f0,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1f: /* FNMADDx */
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb
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UML_FDNEG(block, F64(G_RD(op)), FREG(0)); // fdneg rd,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1c: /* FMSUBx */
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDSUB(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdsub rd,f0,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x1e: /* FNMSUBx */
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UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
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UML_FDSUB(block, F64(G_RD(op)), F64(G_RB(op)), FREG(0)); // fdsub rd,rb,f0
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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}
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}
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@ -3956,6 +3990,7 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp
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case 0x00c: /* FRSPx */
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UML_FDRNDS(block, F64(G_RD(op)), F64(G_RB(op))); // fdrnds rd,rb
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generate_fp_flags(ppc, block, desc, TRUE);
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return TRUE;
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case 0x00e: /* FCTIWx */
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@ -1243,6 +1243,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
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desc->cycles = 18; /* 603 */
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else
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desc->cycles = 17; /* ??? */
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FPSCR_MODIFIED(desc, 4);
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return TRUE;
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case 0x14: /* FSUBSx */
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@ -1252,6 +1253,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
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FPR_MODIFIED(desc, G_RD(op));
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if (op & M_RC)
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CR_MODIFIED(desc, 1);
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FPSCR_MODIFIED(desc, 4);
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return TRUE;
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case 0x19: /* FMULSx - not the same form as FSUB/FADD! */
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@ -1260,6 +1262,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
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FPR_MODIFIED(desc, G_RD(op));
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if (op & M_RC)
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CR_MODIFIED(desc, 1);
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FPSCR_MODIFIED(desc, 4);
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return TRUE;
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case 0x16: /* FSQRTSx */
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@ -1268,6 +1271,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
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FPR_MODIFIED(desc, G_RD(op));
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if (op & M_RC)
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CR_MODIFIED(desc, 1);
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FPSCR_MODIFIED(desc, 4);
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return TRUE;
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case 0x1c: /* FMSUBSx */
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@ -1280,6 +1284,7 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d
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FPR_MODIFIED(desc, G_RD(op));
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if (op & M_RC)
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CR_MODIFIED(desc, 1);
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FPSCR_MODIFIED(desc, 4);
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return TRUE;
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}
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@ -1317,6 +1322,7 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
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desc->cycles = 33; /* 603 */
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else
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desc->cycles = 31; /* ??? */
|
||||
FPSCR_MODIFIED(desc, 4);
|
||||
return TRUE;
|
||||
|
||||
case 0x19: /* FMULx */
|
||||
@ -1326,6 +1332,7 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
|
||||
if (op & M_RC)
|
||||
CR_MODIFIED(desc, 1);
|
||||
desc->cycles = 2; /* 601/603 */
|
||||
FPSCR_MODIFIED(desc, 4);
|
||||
return TRUE;
|
||||
|
||||
case 0x14: /* FSUBx */
|
||||
@ -1335,6 +1342,7 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
|
||||
FPR_MODIFIED(desc, G_RD(op));
|
||||
if (op & M_RC)
|
||||
CR_MODIFIED(desc, 1);
|
||||
FPSCR_MODIFIED(desc, 4);
|
||||
return TRUE;
|
||||
|
||||
case 0x16: /* FSQRTx */
|
||||
@ -1343,9 +1351,19 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
|
||||
FPR_MODIFIED(desc, G_RD(op));
|
||||
if (op & M_RC)
|
||||
CR_MODIFIED(desc, 1);
|
||||
FPSCR_MODIFIED(desc, 4);
|
||||
return TRUE;
|
||||
|
||||
case 0x17: /* FSELx */
|
||||
FPR_USED(desc, G_RA(op));
|
||||
FPR_USED(desc, G_RB(op));
|
||||
FPR_USED(desc, G_REGC(op));
|
||||
FPR_MODIFIED(desc, G_RD(op));
|
||||
if (op & M_RC)
|
||||
CR_MODIFIED(desc, 1);
|
||||
desc->cycles = 2; /* 601/603 */
|
||||
return TRUE;
|
||||
|
||||
case 0x1c: /* FMSUBx */
|
||||
case 0x1d: /* FMADDx */
|
||||
case 0x1e: /* FNMSUBx */
|
||||
@ -1357,6 +1375,7 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
|
||||
if (op & M_RC)
|
||||
CR_MODIFIED(desc, 1);
|
||||
desc->cycles = 2; /* 601/603 */
|
||||
FPSCR_MODIFIED(desc, 4);
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
@ -1379,6 +1398,7 @@ static int describe_instruction_3f(powerpc_state *ppc, UINT32 op, opcode_desc *d
|
||||
case 0x00c: /* FRSPx */
|
||||
case 0x00e: /* FCTIWx */
|
||||
case 0x00f: /* FCTIWZx */
|
||||
FPSCR_MODIFIED(desc, 4);
|
||||
case 0x028: /* FNEGx */
|
||||
case 0x048: /* FMRx */
|
||||
case 0x088: /* FNABSx */
|
||||
|
Loading…
Reference in New Issue
Block a user