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https://github.com/holub/mame
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new netlist device: 74164 - 8bit parallel output serial shift register
This commit is contained in:
Joakim Larsson Edstrom
parent
eed65a01ac
commit
f9f149a579
@ -78,6 +78,7 @@ namespace netlist
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ENTRYX(74123, TTL_74123, "")
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ENTRYX(74153, TTL_74153, "+C0,+C1,+C2,+C3,+A,+B,+G")
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ENTRYX(74161, TTL_74161, "+A,+B,+C,+D,+CLRQ,+LOADQ,+CLK,+ENABLEP,+ENABLET")
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ENTRYX(74164, TTL_74164, "+A,+B,+CLRQ,+CLK")
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ENTRYX(74165, TTL_74165, "+CLK,+CLKINH,+SH_LDQ,+SER,+A,+B,+C,+D,+E,+F,+G,+H")
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ENTRYX(74166, TTL_74166, "+CLK,+CLKINH,+SH_LDQ,+SER,+A,+B,+C,+D,+E,+F,+G,+H,+CLRQ")
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ENTRYX(74174, TTL_74174, "+CLK,+D1,+D2,+D3,+D4,+D5,+D6,+CLRQ")
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@ -126,6 +127,7 @@ namespace netlist
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ENTRYX(74123_dip, TTL_74123_DIP, "")
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ENTRYX(74153_dip, TTL_74153_DIP, "")
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ENTRYX(74161_dip, TTL_74161_DIP, "")
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ENTRYX(74164_dip, TTL_74164_DIP, "")
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ENTRYX(74165_dip, TTL_74165_DIP, "")
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ENTRYX(74166_dip, TTL_74166_DIP, "")
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ENTRYX(74174_dip, TTL_74174_DIP, "")
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@ -52,6 +52,7 @@
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#include "nld_74123.h"
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#include "nld_74153.h"
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#include "nld_74161.h"
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#include "nld_74164.h"
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#include "nld_74165.h"
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#include "nld_74166.h"
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#include "nld_74174.h"
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104
src/lib/netlist/devices/nld_74164.cpp
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104
src/lib/netlist/devices/nld_74164.cpp
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@ -0,0 +1,104 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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/*
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* nld_74164.cpp
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*
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* Thanks to the 74161 work of Ryan and the huge Netlist effort by Couriersud
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* implementing this was simple.
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*
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*/
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#include "nld_74164.h"
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#include "../nl_base.h"
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namespace netlist
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{
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namespace devices
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{
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NETLIB_OBJECT(74164)
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{
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NETLIB_CONSTRUCTOR(74164)
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, m_A(*this, "A")
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, m_B(*this, "B")
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, m_CLRQ(*this, "CLRQ")
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, m_CLK(*this, "CLK")
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, m_cnt(*this, "m_cnt", 0)
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, m_last_CLK(*this, "m_last_CLK", 0)
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, m_Q(*this, {{"QA", "QB", "QC", "QD", "QE", "QF", "QG", "QH"}})
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{
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}
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NETLIB_RESETI();
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NETLIB_UPDATEI();
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protected:
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logic_input_t m_A;
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logic_input_t m_B;
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logic_input_t m_CLRQ;
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logic_input_t m_CLK;
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state_var<unsigned> m_cnt;
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state_var<unsigned> m_last_CLK;
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object_array_t<logic_output_t, 8> m_Q;
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};
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NETLIB_OBJECT_DERIVED(74164_dip, 74164)
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{
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NETLIB_CONSTRUCTOR_DERIVED(74164_dip, 74164)
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{
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register_subalias("1", m_A);
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register_subalias("2", m_B);
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register_subalias("3", m_Q[0]);
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register_subalias("4", m_Q[1]);
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register_subalias("5", m_Q[2]);
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register_subalias("6", m_Q[3]);
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register_subalias("8", m_CLK);
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register_subalias("9", m_CLRQ);
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register_subalias("10", m_Q[4]);
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register_subalias("11", m_Q[5]);
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register_subalias("12", m_Q[6]);
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register_subalias("13", m_Q[7]);
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}
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};
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NETLIB_RESET(74164)
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{
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m_cnt = 0;
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m_last_CLK = 0;
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}
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NETLIB_UPDATE(74164)
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{
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if (!m_CLRQ())
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{
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m_cnt = 0;
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}
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else if (m_CLK() && !m_last_CLK)
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{
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m_cnt = (m_cnt << 1) & 0xfe;
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if (m_A() && m_B())
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{
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m_cnt |= 0x01;
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}
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else
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{
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m_cnt &= 0xfe;
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}
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}
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m_last_CLK = m_CLK();
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for (std::size_t i=0; i<8; i++)
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{
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m_Q[i].push((m_cnt >> i) & 1, NLTIME_FROM_NS(30));
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}
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}
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NETLIB_DEVICE_IMPL(74164)
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NETLIB_DEVICE_IMPL(74164_dip)
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} //namespace devices
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} // namespace netlist
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57
src/lib/netlist/devices/nld_74164.h
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57
src/lib/netlist/devices/nld_74164.h
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@ -0,0 +1,57 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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/*****************************************************************************
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5/74164 8-bit parallel-out serial shift registers
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***********************************************************************
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Connection Diagram:
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___ ___
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A 1 |* u | 14 Vcc
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B 2 | | 13 QH
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QA 3 | | 12 QG
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QB 4 | | 11 QF
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QC 5 | | 10 QE
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QD 6 | | 9 *Clear
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GND 7 |_______| 8 Clock
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***********************************************************************
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Function Table:
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+-------------------------+----------------+
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| Inputs | Qutputs* |
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+-------+-------+---------+----------------+
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| Clear | Clock | A B | QA QB ... QH |
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+-------+-------+---------+----------------+
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| L | X | X X | L L L |
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| H | L | X X | QA0 QB0 QH0 |
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| H | ^ | H H | H QAn QGn |
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| H | ^ | L X | L QAn QGn |
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| H | ^ | X L | L QAn QGn |
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+-------+-------+---------+----------------+
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H = High Level (steady state)
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L = Low Level (steady state)
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X = Don't Care
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^ = Transition from low to high level
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QA0, QB0 ... QH0 = The level of QA, QB ... QH before the indicated steady-state input conditions were established.
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QAn, QGn = The level of QA or QG before the most recent ^ transition of the clock; indicates a 1 bit shift.
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**********************************************************************/
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#ifndef NLD_74164_H_
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#define NLD_74164_H_
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#include "../nl_setup.h"
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#define TTL_74164(name, cA, cB, cCLRQ, cCLK) \
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NET_REGISTER_DEV(TTL_74164, name) \
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NET_CONNECT(name, A, cA) \
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NET_CONNECT(name, B, cB) \
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NET_CONNECT(name, CLRQ, cCLRQ) \
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NET_CONNECT(name, CLK, cCLK)
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#define TTL_74164_DIP(name) \
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NET_REGISTER_DEV(TTL_74164_DIP, name)
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#endif /* NLD_74164_H_ */
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