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From Luigi30:

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Clocks derived from crystals in in ace.c, asteroid.c, avalnche.c, blockade.c, boxer.c, bzone.c, cosmic.c, firetrk.c, galaga.c, lazercmd.c, meadows.c, missile.c, orbit.c, skydiver.c, sprint2.c, warpwarp.c, williams.c

Added diplocations to meadows.c, mugsmash.c, orbit.c

Unified sprint2.c memory map

Unified galaga.c CPU4 memory maps
This commit is contained in:
Aaron Giles 2008-11-24 03:12:56 +00:00
parent 186f8f5ca5
commit fa2204019f
19 changed files with 110 additions and 117 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/emu/drivers/xtal.h
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@ -69,6 +69,8 @@ enum
XTAL_7_8643MHz = 7864300, /* Used on InterFlip games as video clock */ XTAL_7_8643MHz = 7864300, /* Used on InterFlip games as video clock */
XTAL_8MHz = 8000000, /* Extremely common, used on 100's of PCBs */ XTAL_8MHz = 8000000, /* Extremely common, used on 100's of PCBs */
XTAL_8_664MHz = 8664000, /* Touchmaster */ XTAL_8_664MHz = 8664000, /* Touchmaster */
XTAL_8_945MHz = 8945000, /* Hit Me */
XTAL_9_828MHz = 9828000, /* Universal PCBs */
XTAL_9_987MHz = 9987000, /* Crazy Balloon */ XTAL_9_987MHz = 9987000, /* Crazy Balloon */
XTAL_10MHz = 10000000, XTAL_10MHz = 10000000,
XTAL_10_595MHz = 10595000, /* Mad Alien */ XTAL_10_595MHz = 10595000, /* Mad Alien */
@ -104,6 +106,7 @@ enum
XTAL_19_923MHz = 19923000, /* Cinematronics vectors */ XTAL_19_923MHz = 19923000, /* Cinematronics vectors */
XTAL_19_968MHz = 19968000, /* Used mostly by some Taito games */ XTAL_19_968MHz = 19968000, /* Used mostly by some Taito games */
XTAL_20MHz = 20000000, XTAL_20MHz = 20000000,
XTAL_20_079MHz = 20790000, /* Blockade-hardware Gremlin games */
XTAL_21MHz = 21000000, /* Lock-On pixel clock */ XTAL_21MHz = 21000000, /* Lock-On pixel clock */
XTAL_21_3MHz = 21300000, XTAL_21_3MHz = 21300000,
XTAL_21_4772MHz = 21477200, /* BMC bowling, some Data East 90's games */ XTAL_21_4772MHz = 21477200, /* BMC bowling, some Data East 90's games */

3
src/mame/drivers/ace.c
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@ -39,6 +39,7 @@ A1 2101 2101
#include "driver.h" #include "driver.h"
#define MASTER_CLOCK XTAL_18MHz
static UINT8 *ace_scoreram; static UINT8 *ace_scoreram;
static UINT8 *ace_ram2; static UINT8 *ace_ram2;
@ -306,7 +307,7 @@ GFXDECODE_END
static MACHINE_DRIVER_START( ace ) static MACHINE_DRIVER_START( ace )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", 8080, 18000000 / 9) /* 2 MHz ? */ MDRV_CPU_ADD("main", 8080, MASTER_CLOCK/9) /* 2 MHz ? */
MDRV_CPU_PROGRAM_MAP(main_map,0) MDRV_CPU_PROGRAM_MAP(main_map,0)
/* video hardware */ /* video hardware */

4
src/mame/drivers/artmagic.c
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@ -29,8 +29,8 @@
#include "sound/okim6295.h" #include "sound/okim6295.h"
#define MASTER_CLOCK_40MHz (40000000) #define MASTER_CLOCK_40MHz (XTAL_40MHz)
#define MASTER_CLOCK_25MHz (25000000) #define MASTER_CLOCK_25MHz (XTAL_25MHz)
static UINT16 *control; static UINT16 *control;

2
src/mame/drivers/asteroid.c
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@ -174,7 +174,7 @@ Kits are available immediately from your Atari Distributor. To determine which
#include "sound/discrete.h" #include "sound/discrete.h"
#include "sound/pokey.h" #include "sound/pokey.h"
#define MASTER_CLOCK (12096000) #define MASTER_CLOCK (XTAL_12_096MHz)
#define CLOCK_3KHZ (MASTER_CLOCK / 4096) #define CLOCK_3KHZ (MASTER_CLOCK / 4096)
/************************************* /*************************************

4
src/mame/drivers/avalnche.c
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@ -34,6 +34,8 @@
#include "avalnche.lh" #include "avalnche.lh"
#define MASTER_CLOCK XTAL_12_096MHz
/************************************* /*************************************
@ -217,7 +219,7 @@ INPUT_PORTS_END
static MACHINE_DRIVER_START( avalnche ) static MACHINE_DRIVER_START( avalnche )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", M6502,12096000/16) /* clock input is the "2H" signal divided by two */ MDRV_CPU_ADD("main", M6502,MASTER_CLOCK/16) /* clock input is the "2H" signal divided by two */
MDRV_CPU_PROGRAM_MAP(main_map,0) MDRV_CPU_PROGRAM_MAP(main_map,0)
MDRV_CPU_VBLANK_INT_HACK(avalnche_interrupt,8) MDRV_CPU_VBLANK_INT_HACK(avalnche_interrupt,8)

5
src/mame/drivers/blockade.c
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@ -34,6 +34,7 @@ Notes: Support is complete with the exception of the noise generator.
#include "sound/discrete.h" #include "sound/discrete.h"
#define BLOCKADE_LOG 0 #define BLOCKADE_LOG 0
#define MASTER_CLOCK XTAL_20_079MHz
/* These are used to simulate coin latch circuitry */ /* These are used to simulate coin latch circuitry */
@ -220,7 +221,7 @@ static INPUT_PORTS_START( blasto )
PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) ) PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) ) PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) ) PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
PORT_DIPNAME( 0x04, 0x04, "Boom Switch" ) PORT_DIPNAME( 0x04, 0x04, "Attract Sound" )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x04, DEF_STR( On ) ) PORT_DIPSETTING( 0x04, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Game_Time ) ) PORT_DIPNAME( 0x08, 0x08, DEF_STR( Game_Time ) )
@ -439,7 +440,7 @@ static PALETTE_INIT( bw )
static MACHINE_DRIVER_START( blockade ) static MACHINE_DRIVER_START( blockade )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", 8080, 2079000) MDRV_CPU_ADD("main", 8080, MASTER_CLOCK/10)
MDRV_CPU_PROGRAM_MAP(main_map,0) MDRV_CPU_PROGRAM_MAP(main_map,0)
MDRV_CPU_IO_MAP(main_io_map,0) MDRV_CPU_IO_MAP(main_io_map,0)
MDRV_CPU_VBLANK_INT("main", blockade_interrupt) MDRV_CPU_VBLANK_INT("main", blockade_interrupt)

4
src/mame/drivers/boxer.c
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@ -10,6 +10,8 @@ Atari Boxer (prototype) driver
#include "driver.h" #include "driver.h"
#define MASTER_CLOCK XTAL_12_096MHz
extern UINT8* boxer_tile_ram; extern UINT8* boxer_tile_ram;
extern UINT8* boxer_sprite_ram; extern UINT8* boxer_sprite_ram;
@ -289,7 +291,7 @@ GFXDECODE_END
static MACHINE_DRIVER_START(boxer) static MACHINE_DRIVER_START(boxer)
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", M6502, 12096000 / 16) MDRV_CPU_ADD("main", M6502, MASTER_CLOCK / 16)
MDRV_CPU_PROGRAM_MAP(boxer_map, 0) MDRV_CPU_PROGRAM_MAP(boxer_map, 0)
/* video hardware */ /* video hardware */

2
src/mame/drivers/btime.c
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@ -67,6 +67,8 @@ A few notes:
#include "sound/ay8910.h" #include "sound/ay8910.h"
#include "includes/btime.h" #include "includes/btime.h"
#define MASTER_CLOCK (XTAL_12MHz)
static WRITE8_HANDLER( audio_command_w ); static WRITE8_HANDLER( audio_command_w );
static UINT8 *decrypted; static UINT8 *decrypted;

2
src/mame/drivers/bzone.c
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@ -212,7 +212,7 @@
#include "bzone.lh" #include "bzone.lh"
#define MASTER_CLOCK (12096000) #define MASTER_CLOCK (XTAL_12_096MHz)
#define CLOCK_3KHZ (MASTER_CLOCK / 4096) #define CLOCK_3KHZ (MASTER_CLOCK / 4096)

4
src/mame/drivers/cosmic.c
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@ -32,6 +32,8 @@ a physical DSW B but only read when SWA:3,4 are both set to OFF. Currently,
#include "sound/samples.h" #include "sound/samples.h"
#include "sound/dac.h" #include "sound/dac.h"
#define MASTER_CLOCK (XTAL_9_828MHz)
PALETTE_INIT( panic ); PALETTE_INIT( panic );
PALETTE_INIT( cosmica ); PALETTE_INIT( cosmica );
@ -1150,7 +1152,7 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( cosmicg ) static MACHINE_DRIVER_START( cosmicg )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", TMS9980, 1228500) MDRV_CPU_ADD("main", TMS9980, MASTER_CLOCK/8)
/* 9.828 MHz Crystal */ /* 9.828 MHz Crystal */
/* R Nabet : huh ? This would imply the crystal frequency is somehow divided by 2 before being /* R Nabet : huh ? This would imply the crystal frequency is somehow divided by 2 before being
fed to the tms9904 or tms9980. Also, I have never heard of a tms9900/9980 operating under fed to the tms9904 or tms9980. Also, I have never heard of a tms9900/9980 operating under

12
src/mame/drivers/firetrk.c
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@ -9,9 +9,7 @@ Atari Fire Truck + Super Bug + Monte Carlo driver
#include "firetrk.h" #include "firetrk.h"
#include "sound/discrete.h" #include "sound/discrete.h"
#define FIRETRK_CPU_CLOCK_1MHZ (12096000 / 12) #define MASTER_CLOCK (XTAL_12_096MHz)
#define FIRETRK_CPU_CLOCK_750KZ (12096000 / 16)
static UINT8 in_service_mode; static UINT8 in_service_mode;
static UINT32 dial[2]; static UINT32 dial[2];
@ -28,7 +26,7 @@ static void set_service_mode(running_machine *machine, int enable)
watchdog_enable(machine, !enable); watchdog_enable(machine, !enable);
/* change CPU clock speed according to service switch change */ /* change CPU clock speed according to service switch change */
cpu_set_clock(machine->cpu[0], enable ? FIRETRK_CPU_CLOCK_750KZ : FIRETRK_CPU_CLOCK_1MHZ); cpu_set_clock(machine->cpu[0], enable ? (MASTER_CLOCK/12) : (MASTER_CLOCK/16));
} }
@ -873,7 +871,7 @@ GFXDECODE_END
static MACHINE_DRIVER_START( firetrk ) static MACHINE_DRIVER_START( firetrk )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", M6800, FIRETRK_CPU_CLOCK_1MHZ) /* 750Khz during service mode */ MDRV_CPU_ADD("main", M6800, MASTER_CLOCK/12) /* 750Khz during service mode */
MDRV_CPU_PROGRAM_MAP(firetrk_map, 0) MDRV_CPU_PROGRAM_MAP(firetrk_map, 0)
MDRV_CPU_VBLANK_INT("main", firetrk_interrupt) MDRV_CPU_VBLANK_INT("main", firetrk_interrupt)
MDRV_WATCHDOG_VBLANK_INIT(5) MDRV_WATCHDOG_VBLANK_INIT(5)
@ -908,7 +906,7 @@ static MACHINE_DRIVER_START( superbug )
/* basic machine hardware */ /* basic machine hardware */
MDRV_IMPORT_FROM(firetrk) MDRV_IMPORT_FROM(firetrk)
MDRV_CPU_REPLACE("main", M6800, FIRETRK_CPU_CLOCK_750KZ) MDRV_CPU_REPLACE("main", M6800, MASTER_CLOCK/12)
MDRV_CPU_PROGRAM_MAP(superbug_map, 0) MDRV_CPU_PROGRAM_MAP(superbug_map, 0)
/* video hardware */ /* video hardware */
@ -928,7 +926,7 @@ static MACHINE_DRIVER_START( montecar )
/* basic machine hardware */ /* basic machine hardware */
MDRV_IMPORT_FROM(firetrk) MDRV_IMPORT_FROM(firetrk)
MDRV_CPU_REPLACE("main", M6800, FIRETRK_CPU_CLOCK_1MHZ) /* 750Khz during service mode */ MDRV_CPU_REPLACE("main", M6800, MASTER_CLOCK/12) /* 750Khz during service mode */
MDRV_CPU_PROGRAM_MAP(montecar_map, 0) MDRV_CPU_PROGRAM_MAP(montecar_map, 0)
/* video hardware */ /* video hardware */

93
src/mame/drivers/galaga.c
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@ -706,6 +706,7 @@ TODO:
#include "audio/namco54.h" #include "audio/namco54.h"
#include "nam_cust.h" #include "nam_cust.h"
#define MASTER_CLOCK (XTAL_18_432MHz)
static emu_timer *cpu3_interrupt_timer; static emu_timer *cpu3_interrupt_timer;
@ -990,46 +991,26 @@ ADDRESS_MAP_END
/* bootleg 4th CPU replacing the 5xXX chips */ /* bootleg 4th CPU replacing the 5xXX chips */
static ADDRESS_MAP_START( readmem4_galaga, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( readmem4_galaga, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_ROM) AM_RANGE(0x0000, 0x0fff) AM_READWRITE(SMH_ROM, SMH_ROM)
AM_RANGE(0x1000, 0x107f) AM_READ(SMH_RAM) AM_RANGE(0x1000, 0x107f) AM_READWRITE(SMH_RAM, SMH_RAM)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( writemem4_galaga, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x0fff) AM_WRITE(SMH_ROM)
AM_RANGE(0x1000, 0x107f) AM_WRITE(SMH_RAM)
ADDRESS_MAP_END
static ADDRESS_MAP_START( readmem4_battles, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( readmem4_battles, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_ROM) AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_ROM)
AM_RANGE(0x4000, 0x4003) AM_READ(battles_input_port_r) AM_RANGE(0x4000, 0x4003) AM_READ(battles_input_port_r)
AM_RANGE(0x6000, 0x6000) AM_READ(battles_customio3_r)
AM_RANGE(0x7000, 0x7000) AM_READ(battles_customio_data3_r)
AM_RANGE(0x8000, 0x80ff) AM_READ(SMH_RAM)
ADDRESS_MAP_END
static ADDRESS_MAP_START( writemem4_battles, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x0fff) AM_WRITE(SMH_ROM)
AM_RANGE(0x4001, 0x4001) AM_WRITE(battles_CPU4_coin_w) AM_RANGE(0x4001, 0x4001) AM_WRITE(battles_CPU4_coin_w)
AM_RANGE(0x5000, 0x5000) AM_WRITE(battles_noise_sound_w) AM_RANGE(0x5000, 0x5000) AM_WRITE(battles_noise_sound_w)
AM_RANGE(0x6000, 0x6000) AM_WRITE(battles_customio3_w) AM_RANGE(0x6000, 0x6000) AM_READWRITE(battles_customio3_r, battles_customio3_w)
AM_RANGE(0x7000, 0x7000) AM_WRITE(battles_customio_data3_w) AM_RANGE(0x7000, 0x7000) AM_READWRITE(battles_customio_data3_r, battles_customio_data3_w)
AM_RANGE(0x8000, 0x80ff) AM_WRITE(SMH_RAM) AM_RANGE(0x8000, 0x80ff) AM_READWRITE(SMH_RAM, SMH_RAM)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( readmem4_dzigzag, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( readmem4_dzigzag, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_ROM) AM_RANGE(0x0000, 0x0fff) AM_READWRITE(SMH_ROM, SMH_ROM)
AM_RANGE(0x1000, 0x107f) AM_READ(SMH_RAM) AM_RANGE(0x1000, 0x107f) AM_READWRITE(SMH_RAM, SMH_RAM)
AM_RANGE(0x4000, 0x4007) AM_READ(SMH_RAM) // dip switches? bits 0 & 1 used AM_RANGE(0x4000, 0x4007) AM_READ(SMH_RAM) // dip switches? bits 0 & 1 used
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( writemem4_dzigzag, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x0fff) AM_WRITE(SMH_ROM)
AM_RANGE(0x1000, 0x107f) AM_WRITE(SMH_RAM)
ADDRESS_MAP_END
static INPUT_PORTS_START( bosco ) static INPUT_PORTS_START( bosco )
PORT_START("IN0") PORT_START("IN0")
@ -1639,28 +1620,28 @@ static const samples_interface battles_samples_interface =
static MACHINE_DRIVER_START( bosco ) static MACHINE_DRIVER_START( bosco )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("main", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(bosco_map,0) MDRV_CPU_PROGRAM_MAP(bosco_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(bosco_map,0) MDRV_CPU_PROGRAM_MAP(bosco_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub2", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(bosco_map,0) MDRV_CPU_PROGRAM_MAP(bosco_map,0)
MDRV_CPU_ADD(CPUTAG_50XX, MB8842, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */ MDRV_CPU_ADD(CPUTAG_50XX, MB8842, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
MDRV_CPU_PROGRAM_MAP(namco_50xx_map_program,0) MDRV_CPU_PROGRAM_MAP(namco_50xx_map_program,0)
MDRV_CPU_DATA_MAP(namco_50xx_map_data,0) MDRV_CPU_DATA_MAP(namco_50xx_map_data,0)
MDRV_CPU_IO_MAP(namco_50xx_map_io,0) MDRV_CPU_IO_MAP(namco_50xx_map_io,0)
MDRV_CPU_ADD(CPUTAG_50XX_2, MB8842, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */ MDRV_CPU_ADD(CPUTAG_50XX_2, MB8842, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
MDRV_CPU_PROGRAM_MAP(namco_50xx_2_map_program,0) MDRV_CPU_PROGRAM_MAP(namco_50xx_2_map_program,0)
MDRV_CPU_DATA_MAP(namco_50xx_2_map_data,0) MDRV_CPU_DATA_MAP(namco_50xx_2_map_data,0)
MDRV_CPU_IO_MAP(namco_50xx_2_map_io,0) MDRV_CPU_IO_MAP(namco_50xx_2_map_io,0)
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */ MDRV_CPU_ADD(CPUTAG_54XX, MB8844, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program,0) MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program,0)
MDRV_CPU_DATA_MAP(namco_54xx_map_data,0) MDRV_CPU_DATA_MAP(namco_54xx_map_data,0)
MDRV_CPU_IO_MAP(namco_54xx_map_io,0) MDRV_CPU_IO_MAP(namco_54xx_map_io,0)
@ -1690,11 +1671,11 @@ static MACHINE_DRIVER_START( bosco )
/* sound hardware */ /* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono") MDRV_SPEAKER_STANDARD_MONO("mono")
MDRV_SOUND_ADD("namco", NAMCO, 18432000/6/32) MDRV_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
MDRV_SOUND_CONFIG(namco_config) MDRV_SOUND_CONFIG(namco_config)
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
MDRV_SOUND_ADD("namco2", NAMCO_52XX, 18432000/12) /* 1.536 MHz */ MDRV_SOUND_ADD("namco2", NAMCO_52XX, MASTER_CLOCK/12) /* 1.536 MHz */
MDRV_SOUND_CONFIG(namco_52xx_config) MDRV_SOUND_CONFIG(namco_52xx_config)
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
@ -1708,18 +1689,18 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( galaga ) static MACHINE_DRIVER_START( galaga )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("main", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(galaga_map,0) MDRV_CPU_PROGRAM_MAP(galaga_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(galaga_map,0) MDRV_CPU_PROGRAM_MAP(galaga_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub2", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(galaga_map,0) MDRV_CPU_PROGRAM_MAP(galaga_map,0)
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */ MDRV_CPU_ADD(CPUTAG_54XX, MB8844, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program,0) MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program,0)
MDRV_CPU_DATA_MAP(namco_54xx_map_data,0) MDRV_CPU_DATA_MAP(namco_54xx_map_data,0)
MDRV_CPU_IO_MAP(namco_54xx_map_io,0) MDRV_CPU_IO_MAP(namco_54xx_map_io,0)
@ -1749,7 +1730,7 @@ static MACHINE_DRIVER_START( galaga )
/* sound hardware */ /* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono") MDRV_SPEAKER_STANDARD_MONO("mono")
MDRV_SOUND_ADD("namco", NAMCO, 18432000/6/32) MDRV_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
MDRV_SOUND_CONFIG(namco_config) MDRV_SOUND_CONFIG(namco_config)
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
@ -1766,8 +1747,8 @@ static MACHINE_DRIVER_START( galagab )
MDRV_CPU_REMOVE(CPUTAG_54XX) MDRV_CPU_REMOVE(CPUTAG_54XX)
MDRV_CPU_ADD("sub3", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(readmem4_galaga,writemem4_galaga) MDRV_CPU_PROGRAM_MAP(readmem4_galaga,0)
/* sound hardware */ /* sound hardware */
MDRV_SOUND_REMOVE("discrete") MDRV_SOUND_REMOVE("discrete")
@ -1777,23 +1758,23 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( xevious ) static MACHINE_DRIVER_START( xevious )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("main", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(xevious_map,0) MDRV_CPU_PROGRAM_MAP(xevious_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub", Z80,MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(xevious_map,0) MDRV_CPU_PROGRAM_MAP(xevious_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub2", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(xevious_map,0) MDRV_CPU_PROGRAM_MAP(xevious_map,0)
MDRV_CPU_ADD(CPUTAG_50XX, MB8842, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */ MDRV_CPU_ADD(CPUTAG_50XX, MB8842, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
MDRV_CPU_PROGRAM_MAP(namco_50xx_map_program,0) MDRV_CPU_PROGRAM_MAP(namco_50xx_map_program,0)
MDRV_CPU_DATA_MAP(namco_50xx_map_data,0) MDRV_CPU_DATA_MAP(namco_50xx_map_data,0)
MDRV_CPU_IO_MAP(namco_50xx_map_io,0) MDRV_CPU_IO_MAP(namco_50xx_map_io,0)
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */ MDRV_CPU_ADD(CPUTAG_54XX, MB8844, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program,0) MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program,0)
MDRV_CPU_DATA_MAP(namco_54xx_map_data,0) MDRV_CPU_DATA_MAP(namco_54xx_map_data,0)
MDRV_CPU_IO_MAP(namco_54xx_map_io,0) MDRV_CPU_IO_MAP(namco_54xx_map_io,0)
@ -1822,7 +1803,7 @@ static MACHINE_DRIVER_START( xevious )
/* sound hardware */ /* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono") MDRV_SPEAKER_STANDARD_MONO("mono")
MDRV_SOUND_ADD("namco", NAMCO, 18432000/6/32) MDRV_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
MDRV_SOUND_CONFIG(namco_config) MDRV_SOUND_CONFIG(namco_config)
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
@ -1840,8 +1821,8 @@ static MACHINE_DRIVER_START( battles )
MDRV_CPU_REMOVE(CPUTAG_50XX) MDRV_CPU_REMOVE(CPUTAG_50XX)
MDRV_CPU_REMOVE(CPUTAG_54XX) MDRV_CPU_REMOVE(CPUTAG_54XX)
MDRV_CPU_ADD("sub3", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(readmem4_battles,writemem4_battles) MDRV_CPU_PROGRAM_MAP(readmem4_battles,0)
MDRV_CPU_VBLANK_INT("main", battles_interrupt_4) MDRV_CPU_VBLANK_INT("main", battles_interrupt_4)
MDRV_MACHINE_RESET(battles) MDRV_MACHINE_RESET(battles)
@ -1861,15 +1842,15 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( digdug ) static MACHINE_DRIVER_START( digdug )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("main", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(digdug_map,0) MDRV_CPU_PROGRAM_MAP(digdug_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(digdug_map,0) MDRV_CPU_PROGRAM_MAP(digdug_map,0)
MDRV_CPU_VBLANK_INT("main", irq0_line_assert) MDRV_CPU_VBLANK_INT("main", irq0_line_assert)
MDRV_CPU_ADD("sub2", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(digdug_map,0) MDRV_CPU_PROGRAM_MAP(digdug_map,0)
MDRV_INTERLEAVE(100) /* 100 CPU slices per frame - an high value to ensure proper */ MDRV_INTERLEAVE(100) /* 100 CPU slices per frame - an high value to ensure proper */
@ -1896,7 +1877,7 @@ static MACHINE_DRIVER_START( digdug )
/* sound hardware */ /* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono") MDRV_SPEAKER_STANDARD_MONO("mono")
MDRV_SOUND_ADD("namco", NAMCO, 18432000/6/32) MDRV_SOUND_ADD("namco", NAMCO, MASTER_CLOCK/6/32)
MDRV_SOUND_CONFIG(namco_config) MDRV_SOUND_CONFIG(namco_config)
MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0) MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90 * 10.0 / 16.0)
MACHINE_DRIVER_END MACHINE_DRIVER_END
@ -1906,8 +1887,8 @@ static MACHINE_DRIVER_START( dzigzag )
/* basic machine hardware */ /* basic machine hardware */
MDRV_IMPORT_FROM(digdug) MDRV_IMPORT_FROM(digdug)
MDRV_CPU_ADD("sub3", Z80, 18432000/6) /* 3.072 MHz */ MDRV_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
MDRV_CPU_PROGRAM_MAP(readmem4_dzigzag,writemem4_dzigzag) MDRV_CPU_PROGRAM_MAP(readmem4_dzigzag,0)
MACHINE_DRIVER_END MACHINE_DRIVER_END

4
src/mame/drivers/hitme.c
View File

@ -18,6 +18,8 @@
#include "hitme.h" #include "hitme.h"
#include "sound/discrete.h" #include "sound/discrete.h"
#define MASTER_CLOCK (XTAL_8_945MHz) /* confirmed on schematic */
static tilemap *hitme_tilemap; static tilemap *hitme_tilemap;
static attotime timeout_time; static attotime timeout_time;
static UINT8 *hitme_vidram; static UINT8 *hitme_vidram;
@ -300,7 +302,7 @@ GFXDECODE_END
static MACHINE_DRIVER_START( hitme ) static MACHINE_DRIVER_START( hitme )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", 8080, 8945000/16) MDRV_CPU_ADD("main", 8080, MASTER_CLOCK/16)
MDRV_CPU_PROGRAM_MAP(hitme_map,0) MDRV_CPU_PROGRAM_MAP(hitme_map,0)
MDRV_CPU_IO_MAP(hitme_portmap,0) MDRV_CPU_IO_MAP(hitme_portmap,0)

7
src/mame/drivers/lazercmd.c
View File

@ -229,6 +229,7 @@
#include "rendlay.h" #include "rendlay.h"
#include "lazercmd.lh" #include "lazercmd.lh"
#define MASTER_CLOCK XTAL_8MHz
/************************************************************* /*************************************************************
* *
@ -614,7 +615,7 @@ static PALETTE_INIT( lazercmd )
static MACHINE_DRIVER_START( lazercmd ) static MACHINE_DRIVER_START( lazercmd )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", S2650,8064000/12) /* 672 kHz? */ MDRV_CPU_ADD("main", S2650,MASTER_CLOCK/12) /* 672 kHz? */
/* Main Clock is 8MHz divided by 12 /* Main Clock is 8MHz divided by 12
but memory and IO access is only possible but memory and IO access is only possible
within the line and frame blanking period within the line and frame blanking period
@ -649,7 +650,7 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( medlanes ) static MACHINE_DRIVER_START( medlanes )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", S2650,8064000/12) /* 672 kHz? */ MDRV_CPU_ADD("main", S2650,MASTER_CLOCK/12) /* 666 kHz */
/* Main Clock is 8MHz divided by 12 /* Main Clock is 8MHz divided by 12
but memory and IO access is only possible but memory and IO access is only possible
within the line and frame blanking period within the line and frame blanking period
@ -684,7 +685,7 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( bbonk ) static MACHINE_DRIVER_START( bbonk )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", S2650,8064000/12) /* 672 kHz? */ MDRV_CPU_ADD("main", S2650,MASTER_CLOCK/12) /* 666 kHz */
/* Main Clock is 8MHz divided by 12 /* Main Clock is 8MHz divided by 12
but memory and IO access is only possible but memory and IO access is only possible
within the line and frame blanking period within the line and frame blanking period

32
src/mame/drivers/meadows.c
View File

@ -125,6 +125,8 @@
#include "deadeye.lh" #include "deadeye.lh"
#include "gypsyjug.lh" #include "gypsyjug.lh"
#define MASTER_CLOCK XTAL_5MHz
/************************************* /*************************************
@ -412,7 +414,7 @@ static INPUT_PORTS_START( meadows )
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
PORT_START("DSW") PORT_START("DSW")
PORT_DIPNAME( 0x07, 0x01, DEF_STR( Lives ) ) PORT_DIPNAME( 0x07, 0x01, DEF_STR( Lives ) ) PORT_DIPLOCATION("DSW1:3,2,1")
PORT_DIPSETTING( 0x00, "2" ) PORT_DIPSETTING( 0x00, "2" )
PORT_DIPSETTING( 0x01, "3" ) PORT_DIPSETTING( 0x01, "3" )
PORT_DIPSETTING( 0x02, "4" ) PORT_DIPSETTING( 0x02, "4" )
@ -421,15 +423,15 @@ static INPUT_PORTS_START( meadows )
PORT_DIPSETTING( 0x05, "7" ) PORT_DIPSETTING( 0x05, "7" )
PORT_DIPSETTING( 0x06, "8" ) PORT_DIPSETTING( 0x06, "8" )
PORT_DIPSETTING( 0x07, "9" ) PORT_DIPSETTING( 0x07, "9" )
PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coinage ) ) PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("DSW1:5,4")
PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) ) PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x18, DEF_STR( Free_Play ) ) PORT_DIPSETTING( 0x18, DEF_STR( Free_Play ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DSW1:6")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) ) PORT_DIPSETTING( 0x20, DEF_STR( On ) )
PORT_DIPNAME( 0xc0, 0x40, DEF_STR( Bonus_Life ) ) PORT_DIPNAME( 0xc0, 0x40, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("DSW1:8,7")
PORT_DIPSETTING( 0x40, "5000") PORT_DIPSETTING( 0x40, "5000")
PORT_DIPSETTING( 0x80, "15000") PORT_DIPSETTING( 0x80, "15000")
PORT_DIPSETTING( 0xc0, "35000") PORT_DIPSETTING( 0xc0, "35000")
@ -461,37 +463,37 @@ static INPUT_PORTS_START( minferno )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("DSW1") PORT_START("DSW1")
PORT_DIPNAME( 0x01, 0x01, "Coin Option" ) PORT_DIPNAME( 0x01, 0x01, "Coin Option" ) PORT_DIPLOCATION("DSW1:4")
PORT_DIPSETTING( 0x00, "1 Game/Coin" ) PORT_DIPSETTING( 0x00, "1 Game/Coin" )
PORT_DIPSETTING( 0x01, "1 Player/Coin" ) PORT_DIPSETTING( 0x01, "1 Player/Coin" )
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DSW1:3")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 ) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 )
PORT_START("DSW2") PORT_START("DSW2")
PORT_DIPNAME( 0x03, 0x00, DEF_STR( Game_Time ) ) PORT_DIPNAME( 0x03, 0x00, DEF_STR( Game_Time ) ) PORT_DIPLOCATION("DSW1:2,1")
PORT_DIPSETTING( 0x00, "60s" ) PORT_DIPSETTING( 0x00, "60s" )
PORT_DIPSETTING( 0x01, "90s" ) PORT_DIPSETTING( 0x01, "90s" )
PORT_DIPSETTING( 0x02, "120s" ) PORT_DIPSETTING( 0x02, "120s" )
PORT_DIPSETTING( 0x03, "180s" ) PORT_DIPSETTING( 0x03, "180s" )
PORT_DIPNAME( 0x0c, 0x04, "Extended Play Score" ) PORT_DIPNAME( 0x0c, 0x04, "Extended Play Score" ) PORT_DIPLOCATION("DSW1:6,5")
PORT_DIPSETTING( 0x00, "3000/6000" ) PORT_DIPSETTING( 0x00, "3000/6000" )
PORT_DIPSETTING( 0x04, "4000/7000" ) PORT_DIPSETTING( 0x04, "4000/7000" )
PORT_DIPSETTING( 0x08, "5000/8000" ) PORT_DIPSETTING( 0x08, "5000/8000" )
PORT_DIPSETTING( 0x0c, "6000/9000" ) PORT_DIPSETTING( 0x0c, "6000/9000" )
PORT_DIPNAME( 0x30, 0x10, "Extended Play Time" ) PORT_DIPNAME( 0x30, 0x10, "Extended Play Time" ) PORT_DIPLOCATION("DSW1:7,8")
PORT_DIPSETTING( 0x00, DEF_STR( None ) ) PORT_DIPSETTING( 0x00, DEF_STR( None ) )
PORT_DIPSETTING( 0x10, "20s" ) PORT_DIPSETTING( 0x10, "20s" )
PORT_DIPSETTING( 0x20, "40s" ) PORT_DIPSETTING( 0x20, "40s" )
PORT_DIPSETTING( 0x30, "60s" ) PORT_DIPSETTING( 0x30, "60s" )
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) /* PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unused ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x40, DEF_STR( On ) ) PORT_DIPSETTING( 0x40, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unused ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) ) PORT_DIPSETTING( 0x80, DEF_STR( On ) ) */
INPUT_PORTS_END INPUT_PORTS_END
@ -587,11 +589,11 @@ static const samples_interface bowl3d_samples_interface =
static MACHINE_DRIVER_START( meadows ) static MACHINE_DRIVER_START( meadows )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", S2650, 5000000/8) /* 5MHz / 8 = 625 kHz */ MDRV_CPU_ADD("main", S2650, MASTER_CLOCK/8) /* 5MHz / 8 = 625 kHz */
MDRV_CPU_PROGRAM_MAP(meadows_main_map,0) MDRV_CPU_PROGRAM_MAP(meadows_main_map,0)
MDRV_CPU_VBLANK_INT("main", meadows_interrupt) /* one interrupt per frame!? */ MDRV_CPU_VBLANK_INT("main", meadows_interrupt) /* one interrupt per frame!? */
MDRV_CPU_ADD("audio", S2650, 5000000/8) /* 5MHz / 8 = 625 kHz */ MDRV_CPU_ADD("audio", S2650, MASTER_CLOCK/8) /* 5MHz / 8 = 625 kHz */
MDRV_CPU_PROGRAM_MAP(audio_map,0) MDRV_CPU_PROGRAM_MAP(audio_map,0)
MDRV_CPU_PERIODIC_INT(audio_interrupt, (double)5000000/131072) MDRV_CPU_PERIODIC_INT(audio_interrupt, (double)5000000/131072)
@ -626,7 +628,7 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( minferno ) static MACHINE_DRIVER_START( minferno )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", S2650, 5000000/8/3) /* 5MHz / 8 = 625 kHz */ MDRV_CPU_ADD("main", S2650, MASTER_CLOCK/24) /* 5MHz / 8 / 3 = 208.33 kHz */
MDRV_CPU_PROGRAM_MAP(minferno_main_map,0) MDRV_CPU_PROGRAM_MAP(minferno_main_map,0)
MDRV_CPU_IO_MAP(minferno_io_map,0) MDRV_CPU_IO_MAP(minferno_io_map,0)
MDRV_CPU_VBLANK_INT("main", minferno_interrupt) MDRV_CPU_VBLANK_INT("main", minferno_interrupt)

2
src/mame/drivers/missile.c
View File

@ -331,7 +331,7 @@ Notes:
#include "sound/pokey.h" #include "sound/pokey.h"
#define MASTER_CLOCK (10000000) #define MASTER_CLOCK XTAL_10MHz
#define PIXEL_CLOCK (MASTER_CLOCK/2) #define PIXEL_CLOCK (MASTER_CLOCK/2)
#define HTOTAL (320) #define HTOTAL (320)

26
src/mame/drivers/mugsmash.c
View File

@ -251,8 +251,8 @@ static INPUT_PORTS_START( mugsmash )
PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("DSW1") /* Fake IN3 (SW1) */ PORT_START("DSW1") /* Fake IN3 (SW1) */
PORT_SERVICE( 0x01, IP_ACTIVE_LOW ) // SW1-1 PORT_SERVICE( 0x01, IP_ACTIVE_LOW ) PORT_DIPLOCATION("DSW1:1") // SW1-1
PORT_DIPNAME( 0x0e, 0x00, DEF_STR( Coinage ) ) // SW1-2 to SW1-4 PORT_DIPNAME( 0x0e, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("DSW1:2,3,4") // SW1-2 to SW1-4
PORT_DIPSETTING( 0x0c, DEF_STR( 4C_1C ) ) PORT_DIPSETTING( 0x0c, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x0a, DEF_STR( 3C_1C ) ) PORT_DIPSETTING( 0x0a, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) ) PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
@ -261,40 +261,38 @@ static INPUT_PORTS_START( mugsmash )
PORT_DIPSETTING( 0x04, DEF_STR( 1C_3C ) ) PORT_DIPSETTING( 0x04, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x06, DEF_STR( 1C_4C ) ) PORT_DIPSETTING( 0x06, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0x0e, DEF_STR( Free_Play ) ) PORT_DIPSETTING( 0x0e, DEF_STR( Free_Play ) )
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Allow_Continue ) ) // SW1-5 PORT_DIPNAME( 0x10, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("DSW1:5") // SW1-5
PORT_DIPSETTING( 0x10, DEF_STR( No ) ) PORT_DIPSETTING( 0x10, DEF_STR( No ) )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPNAME( 0x20, 0x20, "Sound Test" ) // SW1-6 (in "test mode" only) PORT_DIPNAME( 0x20, 0x20, "Sound Test" ) PORT_DIPLOCATION("DSW1:6") // SW1-6 (in "test mode" only)
PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, "Color Test" ) // SW1-7 (in "test mode" only) PORT_DIPNAME( 0x40, 0x40, "Color Test" ) PORT_DIPLOCATION("DSW1:7") // SW1-7 (in "test mode" only)
PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, "Draw SF." ) // SW1-8 (in "test mode" only) PORT_DIPNAME( 0x80, 0x80, "Draw SF." ) PORT_DIPLOCATION("DSW1:8") // SW1-8 (in "test mode" only)
PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW2") /* Fake IN4 (SW2) */ PORT_START("DSW2") /* Fake IN4 (SW2) */
PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) ) // SW2-1 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DSW2:1") // SW2-1
PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x06, 0x02, DEF_STR( Lives ) ) // SW2-2 and SW2-3 PORT_DIPNAME( 0x06, 0x02, DEF_STR( Lives ) ) PORT_DIPLOCATION("DSW2:2,3") // SW2-2 and SW2-3
PORT_DIPSETTING( 0x00, "1" ) PORT_DIPSETTING( 0x00, "1" )
PORT_DIPSETTING( 0x02, "2" ) PORT_DIPSETTING( 0x02, "2" )
PORT_DIPSETTING( 0x04, "3" ) PORT_DIPSETTING( 0x04, "3" )
PORT_DIPSETTING( 0x06, "4" ) PORT_DIPSETTING( 0x06, "4" )
PORT_DIPNAME( 0x08, 0x08, "Unused SW 2-4" ) // SW2-4 PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "DSW2:4" )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) PORT_DIPNAME( 0x30, 0x10, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("DSW2:5,6") // SW2-5 and SW2-6
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x30, 0x10, DEF_STR( Difficulty ) ) // SW2-5 and SW2-6
PORT_DIPSETTING( 0x00, DEF_STR( Very_Easy) ) PORT_DIPSETTING( 0x00, DEF_STR( Very_Easy) )
PORT_DIPSETTING( 0x10, DEF_STR( Easy ) ) PORT_DIPSETTING( 0x10, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x20, DEF_STR( Hard ) ) PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x30, DEF_STR( Very_Hard ) ) PORT_DIPSETTING( 0x30, DEF_STR( Very_Hard ) )
PORT_DIPNAME( 0x40, 0x40, "Draw Objects" ) // SW2-7 (in "test mode" only) PORT_DIPNAME( 0x40, 0x40, "Draw Objects" ) PORT_DIPLOCATION("DSW2:7") // SW2-7 (in "test mode" only)
PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, "Freeze" ) // SW2-8 (= "Screen Pause" in "test mode") PORT_DIPNAME( 0x80, 0x80, "Freeze" ) PORT_DIPLOCATION("DSW2:8") // SW2-8 (= "Screen Pause" in "test mode")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END INPUT_PORTS_END

14
src/mame/drivers/orbit.c
View File

@ -168,7 +168,7 @@ static INPUT_PORTS_START( orbit )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_START("DSW1") /* 1800 */ PORT_START("DSW1") /* 1800 */
PORT_DIPNAME( 0x07, 0x00, "Play Time Per Credit" ) PORT_DIPNAME( 0x07, 0x00, "Play Time Per Credit" ) PORT_DIPLOCATION("DSW1:1,2,3")
PORT_DIPSETTING( 0x00, "0:30" ) PORT_DIPSETTING( 0x00, "0:30" )
PORT_DIPSETTING( 0x01, "1:00" ) PORT_DIPSETTING( 0x01, "1:00" )
PORT_DIPSETTING( 0x02, "1:30" ) PORT_DIPSETTING( 0x02, "1:30" )
@ -177,20 +177,16 @@ static INPUT_PORTS_START( orbit )
PORT_DIPSETTING( 0x05, "3:00" ) PORT_DIPSETTING( 0x05, "3:00" )
PORT_DIPSETTING( 0x06, "3:30" ) PORT_DIPSETTING( 0x06, "3:30" )
PORT_DIPSETTING( 0x07, "4:00" ) PORT_DIPSETTING( 0x07, "4:00" )
PORT_DIPNAME( 0x18, 0x00, DEF_STR( Language ) ) PORT_DIPNAME( 0x18, 0x00, DEF_STR( Language ) ) PORT_DIPLOCATION("DSW1:4,5")
PORT_DIPSETTING( 0x00, DEF_STR( English ) ) PORT_DIPSETTING( 0x00, DEF_STR( English ) )
PORT_DIPSETTING( 0x08, DEF_STR( Spanish ) ) PORT_DIPSETTING( 0x08, DEF_STR( Spanish ) )
PORT_DIPSETTING( 0x10, DEF_STR( French ) ) PORT_DIPSETTING( 0x10, DEF_STR( French ) )
PORT_DIPSETTING( 0x18, DEF_STR( German ) ) PORT_DIPSETTING( 0x18, DEF_STR( German ) )
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Free_Play )) PORT_DIPNAME( 0x20, 0x00, DEF_STR( Free_Play )) PORT_DIPLOCATION("DSW1:6")
PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x00, DEF_STR( Off ))
PORT_DIPSETTING( 0x20, DEF_STR( On )) PORT_DIPSETTING( 0x20, DEF_STR( On ))
PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown )) /* probably unused */ PORT_DIPUNUSED_DIPLOC( 0x40, 0x00, "DSW1:7" )
PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPUNUSED_DIPLOC( 0x80, 0x00, "DSW1:8" )
PORT_DIPSETTING( 0x40, DEF_STR( On ))
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown )) /* probably unused */
PORT_DIPSETTING( 0x00, DEF_STR( Off ))
PORT_DIPSETTING( 0x80, DEF_STR( On ))
PORT_START("DSW2") /* 2000 */ PORT_START("DSW2") /* 2000 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Game Reset") PORT_CODE(KEYCODE_PLUS_PAD) PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Game Reset") PORT_CODE(KEYCODE_PLUS_PAD)

4
src/mame/drivers/skydiver.c
View File

@ -91,6 +91,8 @@
#include "skydiver.h" #include "skydiver.h"
#include "sound/discrete.h" #include "sound/discrete.h"
#define MASTER_CLOCK (XTAL_12_096MHz)
static int skydiver_nmion; static int skydiver_nmion;
@ -371,7 +373,7 @@ GFXDECODE_END
static MACHINE_DRIVER_START( skydiver ) static MACHINE_DRIVER_START( skydiver )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("main", M6800,3000000/4) /* ???? */ MDRV_CPU_ADD("main", M6800,MASTER_CLOCK/16) /* ???? */
MDRV_CPU_PROGRAM_MAP(skydiver_map, 0) MDRV_CPU_PROGRAM_MAP(skydiver_map, 0)
MDRV_CPU_VBLANK_INT_HACK(skydiver_interrupt, 5) MDRV_CPU_VBLANK_INT_HACK(skydiver_interrupt, 5)
MDRV_WATCHDOG_VBLANK_INIT(8) // 128V clocks the same as VBLANK MDRV_WATCHDOG_VBLANK_INIT(8) // 128V clocks the same as VBLANK