From fac1ca581b31525279ead471282c1eed1790daab Mon Sep 17 00:00:00 2001 From: Olivier Galibert Date: Tue, 6 Nov 2012 16:27:39 +0000 Subject: [PATCH] 6502: Rewrite modern, cycle-exact and interruptible [O. Galibert] --- .gitattributes | 18 - docs/m6502.txt | 470 ++++++++ src/emu/cpu/cpu.mak | 148 ++- src/emu/cpu/m6502/6502dasm.c | 767 ------------ src/emu/cpu/m6502/ddeco16.lst | 18 + src/emu/cpu/m6502/deco16.c | 76 ++ src/emu/cpu/m6502/deco16.h | 88 ++ src/emu/cpu/m6502/dm4510.lst | 18 + src/emu/cpu/m6502/dm6502.lst | 18 + src/emu/cpu/m6502/dm6509.lst | 18 + src/emu/cpu/m6502/dm6510.lst | 18 + src/emu/cpu/m6502/dm65c02.lst | 18 + src/emu/cpu/m6502/dm65ce02.lst | 18 + src/emu/cpu/m6502/dn2a03.lst | 18 + src/emu/cpu/m6502/dr65c02.lst | 18 + src/emu/cpu/m6502/ill02.h | 344 ------ src/emu/cpu/m6502/m4510.c | 561 ++------- src/emu/cpu/m6502/m4510.h | 135 ++- src/emu/cpu/m6502/m6502.c | 1498 +++++++++-------------- src/emu/cpu/m6502/m6502.h | 548 +++++---- src/emu/cpu/m6502/m6502make.c | 259 ++++ src/emu/cpu/m6502/m6504.c | 89 ++ src/emu/cpu/m6502/m6504.h | 76 ++ src/emu/cpu/m6502/m6509.c | 528 ++------- src/emu/cpu/m6502/m6509.h | 135 ++- src/emu/cpu/m6502/m6510.c | 193 +++ src/emu/cpu/m6502/m6510.h | 126 ++ src/emu/cpu/m6502/m6510t.c | 48 + src/emu/cpu/m6502/m6510t.h | 63 + src/emu/cpu/m6502/m65c02.c | 61 + src/emu/cpu/m6502/m65c02.h | 105 ++ src/emu/cpu/m6502/m65ce02.c | 435 ++----- src/emu/cpu/m6502/m65ce02.h | 202 +++- src/emu/cpu/m6502/m65sc02.c | 48 + src/emu/cpu/m6502/m65sc02.h | 58 + src/emu/cpu/m6502/m7501.c | 48 + src/emu/cpu/m6502/m7501.h | 63 + src/emu/cpu/m6502/m8502.c | 48 + src/emu/cpu/m6502/m8502.h | 63 + src/emu/cpu/m6502/minc4510.h | 70 -- src/emu/cpu/m6502/mincce02.h | 69 -- src/emu/cpu/m6502/n2a03.c | 105 ++ src/emu/cpu/m6502/n2a03.h | 96 ++ src/emu/cpu/m6502/odeco16.lst | 65 + src/emu/cpu/m6502/om4510.lst | 12 + src/emu/cpu/m6502/om6502.lst | 1962 +++++++++++++++++++++++++++++++ src/emu/cpu/m6502/om6509.lst | 20 + src/emu/cpu/m6502/om6510.lst | 46 + src/emu/cpu/m6502/om65c02.lst | 581 +++++++++ src/emu/cpu/m6502/om65ce02.lst | 1532 ++++++++++++++++++++++++ src/emu/cpu/m6502/on2a03.lst | 297 +++++ src/emu/cpu/m6502/ops02.h | 808 ------------- src/emu/cpu/m6502/ops09.h | 221 ---- src/emu/cpu/m6502/ops4510.h | 66 -- src/emu/cpu/m6502/opsc02.h | 359 ------ src/emu/cpu/m6502/opsce02.h | 989 ---------------- src/emu/cpu/m6502/opsn2a03.h | 38 - src/emu/cpu/m6502/r65c02.c | 60 + src/emu/cpu/m6502/r65c02.h | 65 + src/emu/cpu/m6502/t6502.c | 360 ------ src/emu/cpu/m6502/t6509.c | 352 ------ src/emu/cpu/m6502/t6510.c | 361 ------ src/emu/cpu/m6502/t65c02.c | 410 ------- src/emu/cpu/m6502/t65ce02.c | 399 ------- src/emu/cpu/m6502/t65sc02.c | 80 -- src/emu/cpu/m6502/tdeco16.c | 428 ------- src/emu/cpu/m6502/tn2a03.c | 114 -- src/emu/sound/nes_apu.c | 8 +- src/mame/audio/dkong.c | 2 +- src/mame/drivers/4roses.c | 2 +- src/mame/drivers/allied.c | 2 +- src/mame/drivers/alvg.c | 2 +- src/mame/drivers/bwing.c | 2 +- src/mame/drivers/calomega.c | 1 + src/mame/drivers/cham24.c | 2 +- src/mame/drivers/cmmb.c | 2 +- src/mame/drivers/exprraid.c | 1 + src/mame/drivers/famibox.c | 2 +- src/mame/drivers/funworld.c | 3 +- src/mame/drivers/gts3.c | 2 +- src/mame/drivers/liberate.c | 1 + src/mame/drivers/multigam.c | 2 +- src/mame/drivers/playch10.c | 2 +- src/mame/drivers/punchout.c | 2 +- src/mame/drivers/rgum.c | 2 +- src/mame/drivers/seta.c | 2 +- src/mame/drivers/snookr10.c | 2 +- src/mame/drivers/tceptor.c | 2 +- src/mame/drivers/thedeep.c | 2 +- src/mame/drivers/vsnes.c | 2 +- src/mame/video/liberate.c | 1 + src/mess/drivers/apple2.c | 1 + src/mess/drivers/apple3.c | 4 +- src/mess/drivers/bbc.c | 1 + src/mess/drivers/c128.c | 16 +- src/mess/drivers/c64.c | 49 +- src/mess/drivers/clcd.c | 4 +- src/mess/drivers/lisa.c | 2 +- src/mess/drivers/lynx.c | 2 +- src/mess/drivers/mephisto.c | 9 +- src/mess/drivers/mmodular.c | 8 +- src/mess/drivers/nes.c | 2 +- src/mess/drivers/plus4.c | 32 +- src/mess/drivers/sbc6510.c | 15 +- src/mess/drivers/svision.c | 4 +- src/mess/drivers/vic10.c | 14 +- src/mess/includes/c128.h | 4 +- src/mess/includes/c64.h | 3 +- src/mess/includes/plus4.h | 3 +- src/mess/includes/vic10.h | 3 +- src/mess/includes/vic20.h | 4 +- src/mess/machine/c1541.h | 2 +- src/mess/machine/c1551.c | 13 +- src/mess/machine/c1551.h | 4 +- src/mess/machine/c2040.h | 5 +- src/mess/machine/c64.c | 4 +- src/mess/machine/c65.c | 6 +- src/mess/machine/e01.h | 4 +- src/mess/machine/fd2000.h | 4 +- src/mess/machine/isa_finalchs.c | 2 +- src/mess/machine/lynx.c | 2 +- src/mess/machine/serialbox.h | 4 +- src/tools/unidasm.c | 14 - 123 files changed, 8794 insertions(+), 8929 deletions(-) delete mode 100644 src/emu/cpu/m6502/6502dasm.c delete mode 100644 src/emu/cpu/m6502/ill02.h delete mode 100644 src/emu/cpu/m6502/minc4510.h delete mode 100644 src/emu/cpu/m6502/mincce02.h delete mode 100644 src/emu/cpu/m6502/ops02.h delete mode 100644 src/emu/cpu/m6502/ops09.h delete mode 100644 src/emu/cpu/m6502/ops4510.h delete mode 100644 src/emu/cpu/m6502/opsc02.h delete mode 100644 src/emu/cpu/m6502/opsce02.h delete mode 100644 src/emu/cpu/m6502/opsn2a03.h delete mode 100644 src/emu/cpu/m6502/t6502.c delete mode 100644 src/emu/cpu/m6502/t6509.c delete mode 100644 src/emu/cpu/m6502/t6510.c delete mode 100644 src/emu/cpu/m6502/t65c02.c delete mode 100644 src/emu/cpu/m6502/t65ce02.c delete mode 100644 src/emu/cpu/m6502/t65sc02.c delete mode 100644 src/emu/cpu/m6502/tdeco16.c delete mode 100644 src/emu/cpu/m6502/tn2a03.c diff --git a/.gitattributes b/.gitattributes index 1c50f0cffc2..cf349a1ed72 100644 --- a/.gitattributes +++ b/.gitattributes @@ -480,7 +480,6 @@ src/emu/cpu/m37710/m37710o3.c svneol=native#text/plain src/emu/cpu/m37710/m37710op.h svneol=native#text/plain src/emu/cpu/m37710/m7700ds.c svneol=native#text/plain src/emu/cpu/m37710/m7700ds.h svneol=native#text/plain -src/emu/cpu/m6502/6502dasm.c svneol=native#text/plain src/emu/cpu/m6502/ddeco16.lst svneol=native#text/plain src/emu/cpu/m6502/deco16.c svneol=native#text/plain src/emu/cpu/m6502/deco16.h svneol=native#text/plain @@ -492,7 +491,6 @@ src/emu/cpu/m6502/dm65c02.lst svneol=native#text/plain src/emu/cpu/m6502/dm65ce02.lst svneol=native#text/plain src/emu/cpu/m6502/dn2a03.lst svneol=native#text/plain src/emu/cpu/m6502/dr65c02.lst svneol=native#text/plain -src/emu/cpu/m6502/ill02.h svneol=native#text/plain src/emu/cpu/m6502/m4510.c svneol=native#text/plain src/emu/cpu/m6502/m4510.h svneol=native#text/plain src/emu/cpu/m6502/m6502.c svneol=native#text/plain @@ -517,8 +515,6 @@ src/emu/cpu/m6502/m7501.c svneol=native#text/plain src/emu/cpu/m6502/m7501.h svneol=native#text/plain src/emu/cpu/m6502/m8502.c svneol=native#text/plain src/emu/cpu/m6502/m8502.h svneol=native#text/plain -src/emu/cpu/m6502/minc4510.h svneol=native#text/plain -src/emu/cpu/m6502/mincce02.h svneol=native#text/plain src/emu/cpu/m6502/n2a03.c svneol=native#text/plain src/emu/cpu/m6502/n2a03.h svneol=native#text/plain src/emu/cpu/m6502/odeco16.lst svneol=native#text/plain @@ -529,22 +525,8 @@ src/emu/cpu/m6502/om6510.lst svneol=native#text/plain src/emu/cpu/m6502/om65c02.lst svneol=native#text/plain src/emu/cpu/m6502/om65ce02.lst svneol=native#text/plain src/emu/cpu/m6502/on2a03.lst svneol=native#text/plain -src/emu/cpu/m6502/ops02.h svneol=native#text/plain -src/emu/cpu/m6502/ops09.h svneol=native#text/plain -src/emu/cpu/m6502/ops4510.h svneol=native#text/plain -src/emu/cpu/m6502/opsc02.h svneol=native#text/plain -src/emu/cpu/m6502/opsce02.h svneol=native#text/plain -src/emu/cpu/m6502/opsn2a03.h svneol=native#text/plain src/emu/cpu/m6502/r65c02.c svneol=native#text/plain src/emu/cpu/m6502/r65c02.h svneol=native#text/plain -src/emu/cpu/m6502/t6502.c svneol=native#text/plain -src/emu/cpu/m6502/t6509.c svneol=native#text/plain -src/emu/cpu/m6502/t6510.c svneol=native#text/plain -src/emu/cpu/m6502/t65c02.c svneol=native#text/plain -src/emu/cpu/m6502/t65ce02.c svneol=native#text/plain -src/emu/cpu/m6502/t65sc02.c svneol=native#text/plain -src/emu/cpu/m6502/tdeco16.c svneol=native#text/plain -src/emu/cpu/m6502/tn2a03.c svneol=native#text/plain src/emu/cpu/m6800/6800dasm.c svneol=native#text/plain src/emu/cpu/m6800/6800ops.c svneol=native#text/plain src/emu/cpu/m6800/6800tbl.c svneol=native#text/plain diff --git a/docs/m6502.txt b/docs/m6502.txt index e69de29bb2d..6b010e64ab0 100644 --- a/docs/m6502.txt +++ b/docs/m6502.txt @@ -0,0 +1,470 @@ +The new 6502 family implementation +---------------------------------- + + 1. Introduction + +The new 6502 family implementation has been created to reach +sub-instruction accuracy in observable behaviour. It is designed with +3 goals in mind: + +- every bus cycle must happen at the exact time it would happen in a + real cpu, and every access the real cpu does is done + +- instructions can be interrupted at any time in the middle then + restarted at that point transparently + +- instructions can be interrupted even from within a memory handler + for bus contention/wait states emulation purposes + +Point 1 has been ensured through bisimulation with the gate-level +simulation perfect6502. Point 2 has been ensured structurally through +a code generator which will be explained in section 8. Point 3 is not +done yet due to lack of support on the memory subsystem side, but +section 9 shows how it will be handled. + + + 2. The 6502 family + +The MOS 6502 family has been large and productive. A large number of +variants exist, varying on bus sizes, i/o, and even opcodes. Some +offshots (g65c816, hu6280) even exist that live elsewhere in the mame +tree. The final class hierarchy is this: + + 6502 + | + +------+--------+--+--+-------+-------+ + | | | | | | + 6510 deco16 6504 6509 n2a03 65c02 + | | + +-----+-----+ r65c02 + | | | | +6510t 7501 8502 +---+---+ + | | + 65ce02 65sc02 + | + 4510 + +The 6510 adds an up to 8 bits i/o port, with the 6510t, 7501 and 8502 +being software-identical variants with different pin count (hence i/o +count), die process (nmos, hnmos, etc) and clock support. + +The deco16 is a Deco variant with a small number of not really understood +additional instructions and some i/o. + +The 6504 is a pin and address-bus reduced version. + +The 6509 adds internal support for paging. + +The n2a03 is the nes variant with the D flag disabled and sound +functionality integrated. + +The 65c02 is the very first cmos variant with some additional +instructions, some fixes, and most of the undocumented instructions +turned into nops. The R (rockwell, but eventually produced by wdc too +among others) variant adds a number of bitwise instructions and also +stp and wai. The sc variant, used by the Lynx portable console, looks +identical to the R variant. The 's' probably indicates a +static-ram-cell process allowing full dc-to-max clock control. + +The 65ce02 is the final evolution of the ISA in this hierarchy, with +additional instructions, registers, and removals of a lot of dummy +accesses that slowed the original 6502 down by at least 25%. The 4510 +is a 65ce02 with integrated mmu and gpio support. + + + 3. Usage of the classes + +All the cpus are standard modern cpu devices, with all the normal +interaction with the device infrastructure. To include one of these +cpu in your driver you need to include "cpu/m6502/.h" and then do +a MCFG_CPU_ADD("tag", , clock). + +6510 variants port i/o callbacks are setup through: + MCFG__PORT_CALLBACKS(READ8(type, read_method), WRITE8(type, write_method)) + +And the pullup and floating lines mask is given through: + MCFG__PORT_PULLS(pullups, floating) + +In order to see all bus accesses on the memory handlers it is possible +to disable accesses through the direct map (at a cpu cost, of course) +with: + MCFG_M6502_DISABLE_DIRECT() + +In that case, transparent decryption support is also disabled, +everything goes through normal memory-map read/write calls. The state +of the sync line is given by the cpu method get_sync(), making +implementing the decryption in the handler possible. + +In a final addition, the cpu method get_cycle() gives the current time +in cycles since the start of the machine from the point of view of the +cpu. Or, in other words, what is usually called the cycle number for +the cpu when somebody talks about bus contention or wait states. The +call is designed to be fast (no system-wide sync, usually no call to +machine.time()) and is precise. Cycle number for every access is +exact at the sub-instruction level. + +The 4510 special nomap line is accessible through get_nomap(). + +Other than these specifics, these are perfectly normal cpu classes. + + + 4. General structure of the emulations + +Each variant is emulated through up to 4 files: +- .h = header for the cpu class +- .c = implementation of most of the cpu class +- d.lst = dispatch table for the cpu +- o.lst = opcode implementation code for the cpu + +The last two are optional. They're used to generate a .inc file +in the object directory which is included by the .c file. + +At a minimum, the class must include a constructor and an enum picking +up the correct input line ids. See m65sc02 for a minimalist example. +The header can also include specific configuration macros (see m8502) +and also the class can include specific memory accessors (more on +these later, simple example in m6504). + +If the cpu has its own dispatch table, the class must also include the +declaration (but not definition) of disasm_entries, do_exec_full and +do_exec_partial, the declaration and definition of disasm_disassemble +(identical for all classes but refers to the class-specific +disasm_entries array) and include the .inc file (which provides the +missing definitions). Support for the generation must also be added +to cpu.mak. + +If the cpu has in addition its own opcodes, their declaration must be +done through a macro, see f.i. m65c02. The .inc file will provide the +definitions. + + + 5. Dispatch tables + +Each d.lst is the dispatch table for the cpu. Lines starting +with '#' are comments. The file must include 257 entries, the first +256 being opcodes and the 257th what the cpu should do on reset. In +the 6502 irq and nmi actually magically call the "brk" opcode, hence +the lack of specific description for them. + +Entries 0 to 255, i.e. the opcodes, must have one of these two +structures: +- opcode_addressing-mode +- opcode_middle_addressing-mode + +Opcode is traditionally a three-character value. Addressing mode must +be a 3-letter value corresponding to one of the DASM_* macros in +m6502.h. Opcode and addressing mode are used to generate the +disassembly table. The full entry text is used in the opcode +description file and the dispatching methods, allowing for per-cpu +variants for identical-looking opcodes. + +An entry of "." was usable for unimplemented/unknown opcodes, +generating "???" in the disassembly, but is not a good idea at this +point since it will infloop in execute() if encountered. + + + 6. Opcode descriptions + +Each o.lst file includes the cpu-specific opcodes descriptions. +An opcode description is a series of lines starting by an opcode entry +by itself and followed by a series of indented lines with code +executing the opcode. + +For instance the asl opcode looks like this: + +asl_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +First the low part of the address is read, then the high part (read_pc +is auto-incrementing). Then, now that the address is available the +value to shift is read, then re-written (yes, the 6502 does that), +shifted then the final result is written (do_asl takes care of the +flags). The instruction finishes with a prefetch of the next +instruction, as all non-cpu-crashing instructions do. + +Available bus-accessing functions are: +- read(adr) - standard read +- read_direct(adr) - read from program space +- read_pc() - read at the PC address and increment it +- read_pc_noinc() - read at the PC address +- read_9() - 6509 indexed-y banked read +- write(adr, val) - standard write +- prefetch() - instruction prefetch +- prefetch_noirq() - instruction prefetch without irq check + +Cycle counting is done by the code generator which detects (through +string matching) the accesses and generates the appropriate code. In +addition to the bus-accessing functions a special line can be used to +wait for the next event (irq or whatever). "eat-all-cycles;" on a +line will do that wait then continue. It is used by wai_imp and +stp_imp for the m65c02. + +Due to the constraints of the code generation, some rules have to be +followed: + +- in general, stay with one instruction/expression per line + +- there must be no side effects in the parameters of a bus-accessing + function + +- local variables lifetime must not go past a bus access. In general, + it's better to leave them to helper methods (like do_asl) which do not + do bus accesses. Note that "TMP" and "TMP2" are not local variables, + they're variables of the class. + +- single-line then or else constructs must have braces around them if + they're calling a bus-accessing function + +The per-opcode generated code are methods of the cpu class. As such +they have complete access to other methods of the class, variables of +the class, everything. + + + 7. Memory interface + +For better opcode reuse with the mmu/banking variants, a memory access +subclass has been created. It's called memory_interface, declared in +m6502_device, and provides the following accessors: + +- UINT8 read(UINT16 adr) - normal read +- UINT8 read_direct(UINT16 adr) - direct read +- UINT8 read_decrypted(UINT16 adr) - decrypted data read +- void write(UINT16 adr, UINT8 val) - normal write + +- UINT8 read_9(UINT16 adr) - special y-indexed 6509 read, defaults to read() +- void write_9(UINT16 adr, UINT8 val); - special y-indexed 6509 write, defaults to write() + +Two implementations are given by default, one usual, +mi_default_normal, one disabling direct access, mi_default_nd. A cpu +that wants its own interface (see 6504 or 6509 for instance) must +override device_start, intialize mintf there then call init(). + + + 8. The generated code + +A code generator is used to support interrupting and restarting an +instruction in the middle. This is done through a two-level state +machine with updates only at the boundaries. More precisely, +inst_state tells you which main state you're in. It's equal to the +opcode byte when 0-255, and 256 means reset. It's always valid and +used by instructions like rmb. inst_substate indicates at which step +we are in an instruction, but it set only when an instruction has been +interrupted. Let's go back to the asl code: + +asl_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + + +The complete generated code is: +void m6502_device::asl_aba_partial() +{ +switch(inst_substate) { +case 0: + if(icount == 0) { inst_substate = 1; return; } +case 1: + TMP = read_pc(); + icount--; + if(icount == 0) { inst_substate = 2; return; } +case 2: + TMP = set_h(TMP, read_pc()); + icount--; + if(icount == 0) { inst_substate = 3; return; } +case 3: + TMP2 = read(TMP); + icount--; + if(icount == 0) { inst_substate = 4; return; } +case 4: + write(TMP, TMP2); + icount--; + TMP2 = do_asl(TMP2); + if(icount == 0) { inst_substate = 5; return; } +case 5: + write(TMP, TMP2); + icount--; + if(icount == 0) { inst_substate = 6; return; } +case 6: + prefetch(); + icount--; +} + inst_substate = 0; +} + + +One can see that the initial switch() restarts the instruction at the +appropriate substate, that icount is updated after each access, and +upon reaching 0 the instruction is interrupted and the substate +updated. Since most instructions are started from the beginning a +specific variant is generated for when inst_substate is known to be 0: + +void m6502_device::asl_aba_full() +{ + if(icount == 0) { inst_substate = 1; return; } + TMP = read_pc(); + icount--; + if(icount == 0) { inst_substate = 2; return; } + TMP = set_h(TMP, read_pc()); + icount--; + if(icount == 0) { inst_substate = 3; return; } + TMP2 = read(TMP); + icount--; + if(icount == 0) { inst_substate = 4; return; } + write(TMP, TMP2); + icount--; + TMP2 = do_asl(TMP2); + if(icount == 0) { inst_substate = 5; return; } + write(TMP, TMP2); + icount--; + if(icount == 0) { inst_substate = 6; return; } + prefetch(); + icount--; +} + +That variant removes the switch, avoiding a costly computed branch and +also an inst_substate write. There is in addition a fair chance that +the decrement-test with zero pair is compiled into something +efficient. + +All these opcode functions are called through two virtual methods, +do_exec_full and do_exec_partial, which are generated into a 257-entry +switch statement. Pointers-to-methods being expensive to call, a +virtual function implementing a switch has a fair chance of being +better. + +The execute main call ends up very simple: +void m6502_device::execute_run() +{ + if(inst_substate) + do_exec_partial(); + + while(icount > 0) { + if(inst_state < 0x100) { + PPC = NPC; + inst_state = IR; + if(machine().debug_flags & DEBUG_FLAG_ENABLED) + debugger_instruction_hook(this, NPC); + } + do_exec_full(); + } +} + +If an instruction was partially executed finish it (icount will then +be zero if it still doesn't finish). Then try to run complete +instructions. The NPC/IR dance is due to the fact that the 6502 does +instruction prefetching, so the instruction PC and opcode come from +the prefetch results. + + + 9. Future bus contention/delay slot support + +Supporting bus contention and delay slots in the context of the code +generator only requires being able to abort a bus access when not +enough cycles are available into icount, and restart it when cycles +have become available again. The implementation plan is to: + +- Have a delay() method on the cpu that removes cycles from icount. + If icount becomes zero or less, having it throw a suspend() exception. + +- Change the code generator to generate this: +void m6502_device::asl_aba_partial() +{ +switch(inst_substate) { +case 0: + if(icount == 0) { inst_substate = 1; return; } +case 1: + try { + TMP = read_pc(); + } catch(suspend) { inst_substate = 1; return; } + icount--; + if(icount == 0) { inst_substate = 2; return; } +case 2: + try { + TMP = set_h(TMP, read_pc()); + } catch(suspend) { inst_substate = 2; return; } + icount--; + if(icount == 0) { inst_substate = 3; return; } +case 3: + try { + TMP2 = read(TMP); + } catch(suspend) { inst_substate = 3; return; } + icount--; + if(icount == 0) { inst_substate = 4; return; } +case 4: + try { + write(TMP, TMP2); + } catch(suspend) { inst_substate = 4; return; } + icount--; + TMP2 = do_asl(TMP2); + if(icount == 0) { inst_substate = 5; return; } +case 5: + try { + write(TMP, TMP2); + } catch(suspend) { inst_substate = 5; return; } + icount--; + if(icount == 0) { inst_substate = 6; return; } +case 6: + try { + prefetch(); + } catch(suspend) { inst_substate = 6; return; } + icount--; +} + inst_substate = 0; +} + +A modern try/catch costs nothing if an exception is not thrown. Using +this the control will go back to the main loop, which will then look +like this: + +void m6502_device::execute_run() +{ + if(waiting_cycles) { + icount -= waiting_cycles; + waiting_cycles = 0; + } + + if(icount > 0 && inst_substate) + do_exec_partial(); + + while(icount > 0) { + if(inst_state < 0x100) { + PPC = NPC; + inst_state = IR; + if(machine().debug_flags & DEBUG_FLAG_ENABLED) + debugger_instruction_hook(this, NPC); + } + do_exec_full(); + } + + waiting_cycles = -icount; + icount = 0; +} + +A negative icount means that the cpu won't be able to do anything for +some time in the future, because it's either waiting for the bus to be +free or for a peripheral to answer. These cycles will be counted +until elapsed and then normal processing will go on. It's important +to note that the exception path only happens when the contention/wait +state goes further than the scheduling slice of the cpu. That should +not usually be the case, so the cost should be minimal. + + 10. Current TODO + +- Implement the bus contention/wait states stuff, but that requires + support on the memory map side first. + +- Integrate the i/o subsystems in the 4510 + +- Possibly integrate the sound subsytem in the n2a03 + +- Add decent hookups for the apple 3 madness diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak index ba45a26d3b7..937e5c527d0 100644 --- a/src/emu/cpu/cpu.mak +++ b/src/emu/cpu/cpu.mak @@ -1003,36 +1003,144 @@ $(CPUOBJ)/m37710/m7700ds.o: $(CPUSRC)/m37710/m7700ds.c \ ifneq ($(filter M6502,$(CPUS)),) OBJDIRS += $(CPUOBJ)/m6502 -CPUOBJS += $(CPUOBJ)/m6502/m6502.o -CPUOBJS += $(CPUOBJ)/m6502/m6509.o -CPUOBJS += $(CPUOBJ)/m6502/m65ce02.o -CPUOBJS += $(CPUOBJ)/m6502/m4510.o -DASMOBJS += $(CPUOBJ)/m6502/6502dasm.o +CPUOBJS += $(CPUOBJ)/m6502/deco16.o \ + $(CPUOBJ)/m6502/m4510.o \ + $(CPUOBJ)/m6502/m6502.o \ + $(CPUOBJ)/m6502/m65c02.o \ + $(CPUOBJ)/m6502/m65ce02.o \ + $(CPUOBJ)/m6502/m65sc02.o \ + $(CPUOBJ)/m6502/m6504.o \ + $(CPUOBJ)/m6502/m6509.o \ + $(CPUOBJ)/m6502/m6510.o \ + $(CPUOBJ)/m6502/m6510t.o \ + $(CPUOBJ)/m6502/m7501.o \ + $(CPUOBJ)/m6502/m8502.o \ + $(CPUOBJ)/m6502/n2a03.o \ + $(CPUOBJ)/m6502/r65c02.o +DASMOBJS += +M6502MAKE += $(BUILDOUT)/m6502make$(BUILD_EXE) endif +$(CPUOBJ)/m6502/deco16.o: $(CPUSRC)/m6502/deco16.c \ + $(CPUOBJ)/m6502/deco16.inc \ + $(CPUSRC)/m6502/deco16.h \ + $(CPUSRC)/m6502/m6502.h + $(CPUOBJ)/m6502/m4510.o: $(CPUSRC)/m6502/m4510.c \ - $(CPUSRC)/m6502/t65ce02.c + $(CPUOBJ)/m6502/m4510.inc \ + $(CPUSRC)/m6502/m4510.h \ + $(CPUSRC)/m6502/m65ce02.h \ + $(CPUSRC)/m6502/m65c02.h \ + $(CPUSRC)/m6502/m6502.h $(CPUOBJ)/m6502/m6502.o: $(CPUSRC)/m6502/m6502.c \ - $(CPUSRC)/m6502/m6502.h \ - $(CPUSRC)/m6502/ops02.h \ - $(CPUSRC)/m6502/t6502.c \ - $(CPUSRC)/m6502/t65c02.c \ - $(CPUSRC)/m6502/t65sc02.c \ - $(CPUSRC)/m6502/t6510.c \ - $(CPUSRC)/m6502/tn2a03.c \ - $(CPUSRC)/m6502/tdeco16.c + $(CPUOBJ)/m6502/m6502.inc \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/m65c02.o: $(CPUSRC)/m6502/m65c02.c \ + $(CPUOBJ)/m6502/m65c02.inc \ + $(CPUSRC)/m6502/m65c02.h \ + $(CPUSRC)/m6502/m6502.h $(CPUOBJ)/m6502/m65ce02.o: $(CPUSRC)/m6502/m65ce02.c \ + $(CPUOBJ)/m6502/m65ce02.inc \ $(CPUSRC)/m6502/m65ce02.h \ - $(CPUSRC)/m6502/opsce02.h \ - $(CPUSRC)/m6502/t65ce02.c + $(CPUSRC)/m6502/m65c02.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/m65sc02.o: $(CPUSRC)/m6502/m65sc02.c \ + $(CPUSRC)/m6502/m65sc02.h \ + $(CPUSRC)/m6502/r65c02.h \ + $(CPUSRC)/m6502/m65c02.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/m6504.o: $(CPUSRC)/m6502/m6504.c \ + $(CPUSRC)/m6502/m6504.h \ + $(CPUSRC)/m6502/m6502.h $(CPUOBJ)/m6502/m6509.o: $(CPUSRC)/m6502/m6509.c \ - $(CPUSRC)/m6502/m6509.h \ - $(CPUSRC)/m6502/ops09.h \ - $(CPUSRC)/m6502/t6509.c + $(CPUOBJ)/m6502/m6509.inc \ + $(CPUSRC)/m6502/m6509.h +$(CPUOBJ)/m6502/m6510.o: $(CPUSRC)/m6502/m6510.c \ + $(CPUOBJ)/m6502/m6510.inc \ + $(CPUSRC)/m6502/m6510.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/m6510t.o: $(CPUSRC)/m6502/m6510t.c \ + $(CPUSRC)/m6502/m6510t.h \ + $(CPUSRC)/m6502/m6510.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/m7501.o: $(CPUSRC)/m6502/m7501.c \ + $(CPUSRC)/m6502/m7501.h \ + $(CPUSRC)/m6502/m6510.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/m8502.o: $(CPUSRC)/m6502/m8502.c \ + $(CPUSRC)/m6502/m8502.h \ + $(CPUSRC)/m6502/m6510.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/n2a03.o: $(CPUSRC)/m6502/n2a03.c \ + $(CPUOBJ)/m6502/n2a03.inc \ + $(CPUSRC)/m6502/n2a03.h \ + $(CPUSRC)/m6502/m6502.h + +$(CPUOBJ)/m6502/r65c02.o: $(CPUSRC)/m6502/r65c02.c \ + $(CPUOBJ)/m6502/r65c02.inc \ + $(CPUSRC)/m6502/r65c02.h \ + $(CPUSRC)/m6502/m65c02.h \ + $(CPUSRC)/m6502/m6502.h + +# rule to generate the C files +$(CPUOBJ)/m6502/deco16.inc: $(M6502MAKE) $(CPUSRC)/m6502/odeco16.lst $(CPUSRC)/m6502/ddeco16.lst + @echo Generating DECO16 source file... + $(M6502MAKE) deco16_device $(CPUSRC)/m6502/odeco16.lst $(CPUSRC)/m6502/ddeco16.lst $@ + +$(CPUOBJ)/m6502/m4510.inc: $(M6502MAKE) $(CPUSRC)/m6502/om4510.lst $(CPUSRC)/m6502/dm4510.lst + @echo Generating M4510 source file... + $(M6502MAKE) m4510_device $(CPUSRC)/m6502/om4510.lst $(CPUSRC)/m6502/dm4510.lst $@ + +$(CPUOBJ)/m6502/m6502.inc: $(M6502MAKE) $(CPUSRC)/m6502/om6502.lst $(CPUSRC)/m6502/dm6502.lst + @echo Generating M6502 source file... + $(M6502MAKE) m6502_device $(CPUSRC)/m6502/om6502.lst $(CPUSRC)/m6502/dm6502.lst $@ + +$(CPUOBJ)/m6502/m65c02.inc: $(M6502MAKE) $(CPUSRC)/m6502/om65c02.lst $(CPUSRC)/m6502/dm65c02.lst + @echo Generating M65C02 source file... + $(M6502MAKE) m65c02_device $(CPUSRC)/m6502/om65c02.lst $(CPUSRC)/m6502/dm65c02.lst $@ + +$(CPUOBJ)/m6502/m65ce02.inc: $(M6502MAKE) $(CPUSRC)/m6502/om65ce02.lst $(CPUSRC)/m6502/dm65ce02.lst + @echo Generating M65CE02 source file... + $(M6502MAKE) m65ce02_device $(CPUSRC)/m6502/om65ce02.lst $(CPUSRC)/m6502/dm65ce02.lst $@ + +$(CPUOBJ)/m6502/m6509.inc: $(M6502MAKE) $(CPUSRC)/m6502/om6509.lst $(CPUSRC)/m6502/dm6509.lst + @echo Generating M6509 source file... + $(M6502MAKE) m6509_device $(CPUSRC)/m6502/om6509.lst $(CPUSRC)/m6502/dm6509.lst $@ + +$(CPUOBJ)/m6502/m6510.inc: $(M6502MAKE) $(CPUSRC)/m6502/om6510.lst $(CPUSRC)/m6502/dm6510.lst + @echo Generating M6510 source file... + $(M6502MAKE) m6510_device $(CPUSRC)/m6502/om6510.lst $(CPUSRC)/m6502/dm6510.lst $@ + +$(CPUOBJ)/m6502/n2a03.inc: $(M6502MAKE) $(CPUSRC)/m6502/on2a03.lst $(CPUSRC)/m6502/dn2a03.lst + @echo Generating N2A03 source file... + $(M6502MAKE) n2a03_device $(CPUSRC)/m6502/on2a03.lst $(CPUSRC)/m6502/dn2a03.lst $@ + +$(CPUOBJ)/m6502/r65c02.inc: $(M6502MAKE) $(CPUSRC)/m6502/dr65c02.lst + @echo Generating R65C02 source file... + $(M6502MAKE) r65c02_device - $(CPUSRC)/m6502/dr65c02.lst $@ + + +# rule to build the generator +ifneq ($(CROSS_BUILD),1) + +BUILD += $(M6502MAKE) + +$(M6502MAKE): $(CPUOBJ)/m6502/m6502make.o + @echo Linking $@... + $(LD) $(LDFLAGS) $(OSDBGLDFLAGS) $^ -o $@ + +endif #------------------------------------------------- @@ -1203,7 +1311,7 @@ $(CPUOBJ)/dsp56k/tables.o: $(CPUSRC)/dsp56k/tables.c \ $(CPUOBJ)/dsp56k/dsp56dsm.o: $(CPUSRC)/dsp56k/opcode.c \ $(CPUSRC)/dsp56k/opcode.h \ $(CPUSRC)/dsp56k/inst.c \ - $(CPUSRC)/dsp56k/inst.h \ + $(CPUSRC)/dsp56k/inst.h \ $(CPUSRC)/dsp56k/pmove.c \ $(CPUSRC)/dsp56k/pmove.h \ $(CPUSRC)/dsp56k/tables.c \ diff --git a/src/emu/cpu/m6502/6502dasm.c b/src/emu/cpu/m6502/6502dasm.c deleted file mode 100644 index f8343f40715..00000000000 --- a/src/emu/cpu/m6502/6502dasm.c +++ /dev/null @@ -1,767 +0,0 @@ -/***************************************************************************** - * - * 6502dasm.c - * 6502/65c02/6510 disassembler - * - * Copyright Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ -/* 2. February 2000 PeT added support for 65sc02 subtype */ -/* 2. February 2000 PeT added support for 65ce02 variant */ -/* 3. February 2000 PeT bbr bbs displayment */ -/* 4. February 2000 PeT ply inw dew */ -/* 4. February 2000 PeT fixed relative word operand */ -/* 9. May 2000 PeT added m4510 */ -/* 18.April 2008 Roberto Fresca fixed bbr, bbs, rmb & smb displayment, - showing the correct bit to operate */ - -#include "emu.h" -#include "debugger.h" -#include "m6502.h" -#include "m65ce02.h" -#include "m6509.h" -#include "m4510.h" - -enum addr_mode { - non, /* no additional arguments */ - imp, /* implicit */ - acc, /* accumulator */ - imm, /* immediate */ - iw2, /* immediate word (65ce02) */ - iw3, /* augment (65ce02) */ - adr, /* absolute address (jmp,jsr) */ - aba, /* absolute */ - zpg, /* zero page */ - zpx, /* zero page + X */ - zpy, /* zero page + Y */ - zpi, /* zero page indirect (65c02) */ - zpb, /* zero page and branch (65c02 bbr,bbs) */ - abx, /* absolute + X */ - aby, /* absolute + Y */ - rel, /* relative */ - rw2, /* relative word (65cs02, 65ce02) */ - idx, /* zero page pre indexed */ - idy, /* zero page post indexed */ - idz, /* zero page post indexed (65ce02) */ - isy, /* zero page pre indexed sp and post indexed y (65ce02) */ - ind, /* indirect (jmp) */ - iax /* indirect + X (65c02 jmp) */ -}; - -enum opcodes { - adc, and_,asl, bcc, bcs, beq, bit, bmi, - bne, bpl, m6502_brk, bvc, bvs, clc, cld, cli, - clv, cmp, cpx, cpy, dec, dex, dey, eor, - inc, inx, iny, jmp, jsr, lda, ldx, ldy, - lsr, nop, ora, pha, php, pla, plp, rol, - ror, rti, rts, sbc, sec, sed, sei, sta, - stx, sty, tax, tay, tsx, txa, txs, tya, - ill, -/* 65c02 (only) mnemonics */ - bbr, bbs, bra, rmb, smb, stz, trb, tsb, -/* 65sc02 (only) mnemonics */ - bsr, -/* 6510 + 65c02 mnemonics */ - anc, asr, ast, arr, asx, axa, dcp, dea, - dop, ina, isb, lax, phx, phy, plx, ply, - rla, rra, sax, slo, sre, sah, say, ssh, - sxh, syh, top, oal, kil, -/* 65ce02 mnemonics */ - cle, see, rtn, aug, - tab, tba, taz, tza, tys, tsy, - ldz, stz2/* real register store */, - dez, inz, cpz, phz, plz, - neg, asr2/* arithmetic shift right */, - asw, row, dew, inw, phw, -/* 4510 mnemonics */ - map, - -/* Deco CPU16 mnemonics */ - vbl, u13, u8F, uAB, u87, u0B, uA3, u4B, - u3F, uBB, u23 -}; - - -static const char *const token[]= -{ - "adc", "and", "asl", "bcc", "bcs", "beq", "bit", "bmi", - "bne", "bpl", "m6502_brk", "bvc", "bvs", "clc", "cld", "cli", - "clv", "cmp", "cpx", "cpy", "dec", "dex", "dey", "eor", - "inc", "inx", "iny", "jmp", "jsr", "lda", "ldx", "ldy", - "lsr", "nop", "ora", "pha", "php", "pla", "plp", "rol", - "ror", "rti", "rts", "sbc", "sec", "sed", "sei", "sta", - "stx", "sty", "tax", "tay", "tsx", "txa", "txs", "tya", - "ill", -/* 65c02 mnemonics */ - "bbr", "bbs", "bra", "rmb", "smb", "stz", "trb", "tsb", -/* 65sc02 mnemonics */ - "bsr", -/* 6510 mnemonics */ - "anc", "asr", "ast", "arr", "asx", "axa", "dcp", "dea", - "dop", "ina", "isb", "lax", "phx", "phy", "plx", "ply", - "rla", "rra", "sax", "slo", "sre", "sah", "say", "ssh", - "sxh", "syh", "top", "oal", "kil", -/* 65ce02 mnemonics */ - "cle", "see", "rtn", "aug", - "tab", "tba", "taz", "tza", "tys", "tsy", - "ldz", "stz", - "dez", "inz", "cpz", "phz", "plz", - "neg", "asr", - "asw", "row", "dew", "inw", "phw", -/* 4510 mnemonics */ - "map", - -/* Deco CPU16 mnemonics */ - "VBL", "u13", "u8F", "uAB", "u87", "u0B", "uA3", "u4B", - "u3F", "uBB", "u23" -}; - -struct op6502_info -{ - UINT8 opc; - UINT8 arg; -}; - -static const struct op6502_info op6502[256] = { - {m6502_brk,imm},{ora,idx},{kil,non},{slo,idx},/* 00 */ - {nop,zpg},{ora,zpg},{asl,zpg},{slo,zpg}, - {php,imp},{ora,imm},{asl,acc},{anc,imm}, - {nop,aba},{ora,aba},{asl,aba},{slo,aba}, - {bpl,rel},{ora,idy},{kil,non},{slo,idy},/* 10 */ - {nop,zpx},{ora,zpx},{asl,zpx},{slo,zpx}, - {clc,imp},{ora,aby},{nop,imp},{slo,aby}, - {nop,abx},{ora,abx},{asl,abx},{slo,abx}, - {jsr,adr},{and_,idx},{kil,non},{rla,idx},/* 20 */ - {bit,zpg},{and_,zpg},{rol,zpg},{rla,zpg}, - {plp,imp},{and_,imm},{rol,acc},{anc,imm}, - {bit,aba},{and_,aba},{rol,aba},{rla,aba}, - {bmi,rel},{and_,idy},{kil,non},{rla,idy},/* 30 */ - {nop,zpx},{and_,zpx},{rol,zpx},{rla,zpx}, - {sec,imp},{and_,aby},{nop,imp},{rla,aby}, - {nop,abx},{and_,abx},{rol,abx},{rla,abx}, - {rti,imp},{eor,idx},{kil,non},{sre,idx},/* 40 */ - {nop,zpg},{eor,zpg},{lsr,zpg},{sre,zpg}, - {pha,imp},{eor,imm},{lsr,acc},{asr,imm}, - {jmp,adr},{eor,aba},{lsr,aba},{sre,aba}, - {bvc,rel},{eor,idy},{kil,non},{sre,idy},/* 50 */ - {nop,zpx},{eor,zpx},{lsr,zpx},{sre,zpx}, - {cli,imp},{eor,aby},{nop,imp},{sre,aby}, - {nop,abx},{eor,abx},{lsr,abx},{sre,abx}, - {rts,imp},{adc,idx},{kil,non},{rra,idx},/* 60 */ - {nop,zpg},{adc,zpg},{ror,zpg},{rra,zpg}, - {pla,imp},{adc,imm},{ror,acc},{arr,imm}, - {jmp,ind},{adc,aba},{ror,aba},{rra,aba}, - {bvs,rel},{adc,idy},{kil,non},{rra,idy},/* 70 */ - {nop,zpx},{adc,zpx},{ror,zpx},{rra,zpx}, - {sei,imp},{adc,aby},{nop,imp},{rra,aby}, - {nop,abx},{adc,abx},{ror,abx},{rra,abx}, - {nop,imm},{sta,idx},{nop,imm},{sax,idx},/* 80 */ - {sty,zpg},{sta,zpg},{stx,zpg},{sax,zpg}, - {dey,imp},{nop,imm},{txa,imp},{axa,imm}, - {sty,aba},{sta,aba},{stx,aba},{sax,aba}, - {bcc,rel},{sta,idy},{kil,non},{say,idy},/* 90 */ - {sty,zpx},{sta,zpx},{stx,zpy},{sax,zpy}, - {tya,imp},{sta,aby},{txs,imp},{ssh,aby}, - {syh,abx},{sta,abx},{sxh,aby},{sah,aby}, - {ldy,imm},{lda,idx},{ldx,imm},{lax,idx},/* a0 */ - {ldy,zpg},{lda,zpg},{ldx,zpg},{lax,zpg}, - {tay,imp},{lda,imm},{tax,imp},{oal,imm}, - {ldy,aba},{lda,aba},{ldx,aba},{lax,aba}, - {bcs,rel},{lda,idy},{kil,non},{lax,idy},/* b0 */ - {ldy,zpx},{lda,zpx},{ldx,zpy},{lax,zpy}, - {clv,imp},{lda,aby},{tsx,imp},{ast,aby}, - {ldy,abx},{lda,abx},{ldx,aby},{lax,aby}, - {cpy,imm},{cmp,idx},{nop,imm},{dcp,idx},/* c0 */ - {cpy,zpg},{cmp,zpg},{dec,zpg},{dcp,zpg}, - {iny,imp},{cmp,imm},{dex,imp},{asx,imm}, - {cpy,aba},{cmp,aba},{dec,aba},{dcp,aba}, - {bne,rel},{cmp,idy},{kil,non},{dcp,idy},/* d0 */ - {nop,zpx},{cmp,zpx},{dec,zpx},{dcp,zpx}, - {cld,imp},{cmp,aby},{nop,imp},{dcp,aby}, - {nop,abx},{cmp,abx},{dec,abx},{dcp,abx}, - {cpx,imm},{sbc,idx},{nop,imm},{isb,idx},/* e0 */ - {cpx,zpg},{sbc,zpg},{inc,zpg},{isb,zpg}, - {inx,imp},{sbc,imm},{nop,imp},{sbc,imm}, - {cpx,aba},{sbc,aba},{inc,aba},{isb,aba}, - {beq,rel},{sbc,idy},{kil,non},{isb,idy},/* f0 */ - {nop,zpx},{sbc,zpx},{inc,zpx},{isb,zpx}, - {sed,imp},{sbc,aby},{nop,imp},{isb,aby}, - {nop,abx},{sbc,abx},{inc,abx},{isb,abx} -}; - -static const struct op6502_info op65c02[256] = { - {m6502_brk,imm},{ora,idx},{ill,non},{ill,non},/* 00 */ - {tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg}, - {php,imp},{ora,imm},{asl,acc},{ill,non}, - {tsb,aba},{ora,aba},{asl,aba},{bbr,zpb}, - {bpl,rel},{ora,idy},{ora,zpi},{ill,non},/* 10 */ - {trb,zpg},{ora,zpx},{asl,zpx},{rmb,zpg}, - {clc,imp},{ora,aby},{ina,imp},{ill,non}, - {trb,aba},{ora,abx},{asl,abx},{bbr,zpb}, - {jsr,adr},{and_,idx},{ill,non},{ill,non},/* 20 */ - {bit,zpg},{and_,zpg},{rol,zpg},{rmb,zpg}, - {plp,imp},{and_,imm},{rol,acc},{ill,non}, - {bit,aba},{and_,aba},{rol,aba},{bbr,zpb}, - {bmi,rel},{and_,idy},{and_,zpi},{ill,non},/* 30 */ - {bit,zpx},{and_,zpx},{rol,zpx},{rmb,zpg}, - {sec,imp},{and_,aby},{dea,imp},{ill,non}, - {bit,abx},{and_,abx},{rol,abx},{bbr,zpb}, - {rti,imp},{eor,idx},{ill,non},{ill,non},/* 40 */ - {ill,non},{eor,zpg},{lsr,zpg},{rmb,zpg}, - {pha,imp},{eor,imm},{lsr,acc},{ill,non}, - {jmp,adr},{eor,aba},{lsr,aba},{bbr,zpb}, - {bvc,rel},{eor,idy},{eor,zpi},{ill,non},/* 50 */ - {ill,non},{eor,zpx},{lsr,zpx},{rmb,zpg}, - {cli,imp},{eor,aby},{phy,imp},{ill,non}, - {ill,non},{eor,abx},{lsr,abx},{bbr,zpb}, - {rts,imp},{adc,idx},{ill,non},{ill,non},/* 60 */ - {stz,zpg},{adc,zpg},{ror,zpg},{rmb,zpg}, - {pla,imp},{adc,imm},{ror,acc},{ill,non}, - {jmp,ind},{adc,aba},{ror,aba},{bbr,zpb}, - {bvs,rel},{adc,idy},{adc,zpi},{ill,non},/* 70 */ - {stz,zpx},{adc,zpx},{ror,zpx},{rmb,zpg}, - {sei,imp},{adc,aby},{ply,imp},{ill,non}, - {jmp,iax},{adc,abx},{ror,abx},{bbr,zpb}, - {bra,rel},{sta,idx},{ill,non},{ill,non},/* 80 */ - {sty,zpg},{sta,zpg},{stx,zpg},{smb,zpg}, - {dey,imp},{bit,imm},{txa,imp},{ill,non}, - {sty,aba},{sta,aba},{stx,aba},{bbs,zpb}, - {bcc,rel},{sta,idy},{sta,zpi},{ill,non},/* 90 */ - {sty,zpx},{sta,zpx},{stx,zpy},{smb,zpg}, - {tya,imp},{sta,aby},{txs,imp},{ill,non}, - {stz,aba},{sta,abx},{stz,abx},{bbs,zpb}, - {ldy,imm},{lda,idx},{ldx,imm},{ill,non},/* a0 */ - {ldy,zpg},{lda,zpg},{ldx,zpg},{smb,zpg}, - {tay,imp},{lda,imm},{tax,imp},{ill,non}, - {ldy,aba},{lda,aba},{ldx,aba},{bbs,zpb}, - {bcs,rel},{lda,idy},{lda,zpi},{ill,non},/* b0 */ - {ldy,zpx},{lda,zpx},{ldx,zpy},{smb,zpg}, - {clv,imp},{lda,aby},{tsx,imp},{ill,non}, - {ldy,abx},{lda,abx},{ldx,aby},{bbs,zpb}, - {cpy,imm},{cmp,idx},{ill,non},{ill,non},/* c0 */ - {cpy,zpg},{cmp,zpg},{dec,zpg},{smb,zpg}, - {iny,imp},{cmp,imm},{dex,imp},{ill,non}, - {cpy,aba},{cmp,aba},{dec,aba},{bbs,zpb}, - {bne,rel},{cmp,idy},{cmp,zpi},{ill,non},/* d0 */ - {ill,non},{cmp,zpx},{dec,zpx},{smb,zpg}, - {cld,imp},{cmp,aby},{phx,imp},{ill,non}, - {ill,non},{cmp,abx},{dec,abx},{bbs,zpb}, - {cpx,imm},{sbc,idx},{ill,non},{ill,non},/* e0 */ - {cpx,zpg},{sbc,zpg},{inc,zpg},{smb,zpg}, - {inx,imp},{sbc,imm},{nop,imp},{ill,non}, - {cpx,aba},{sbc,aba},{inc,aba},{bbs,zpb}, - {beq,rel},{sbc,idy},{sbc,zpi},{ill,non},/* f0 */ - {ill,non},{sbc,zpx},{inc,zpx},{smb,zpg}, - {sed,imp},{sbc,aby},{plx,imp},{ill,non}, - {ill,non},{sbc,abx},{inc,abx},{bbs,zpb} -}; - -/* only bsr additional to 65c02 yet */ -static const struct op6502_info op65sc02[256] = { - {m6502_brk,imm},{ora,idx},{ill,non},{ill,non},/* 00 */ - {tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg}, - {php,imp},{ora,imm},{asl,acc},{ill,non}, - {tsb,aba},{ora,aba},{asl,aba},{bbr,zpb}, - {bpl,rel},{ora,idy},{ora,zpi},{ill,non},/* 10 */ - {trb,zpg},{ora,zpx},{asl,zpx},{rmb,zpg}, - {clc,imp},{ora,aby},{ina,imp},{ill,non}, - {trb,aba},{ora,abx},{asl,abx},{bbr,zpb}, - {jsr,adr},{and_,idx},{ill,non},{ill,non},/* 20 */ - {bit,zpg},{and_,zpg},{rol,zpg},{rmb,zpg}, - {plp,imp},{and_,imm},{rol,acc},{ill,non}, - {bit,aba},{and_,aba},{rol,aba},{bbr,zpb}, - {bmi,rel},{and_,idy},{and_,zpi},{ill,non},/* 30 */ - {bit,zpx},{and_,zpx},{rol,zpx},{rmb,zpg}, - {sec,imp},{and_,aby},{dea,imp},{ill,non}, - {bit,abx},{and_,abx},{rol,abx},{bbr,zpb}, - {rti,imp},{eor,idx},{ill,non},{ill,non},/* 40 */ - {ill,non},{eor,zpg},{lsr,zpg},{rmb,zpg}, - {pha,imp},{eor,imm},{lsr,acc},{ill,non}, - {jmp,adr},{eor,aba},{lsr,aba},{bbr,zpb}, - {bvc,rel},{eor,idy},{eor,zpi},{ill,non},/* 50 */ - {ill,non},{eor,zpx},{lsr,zpx},{rmb,zpg}, - {cli,imp},{eor,aby},{phy,imp},{ill,non}, - {ill,non},{eor,abx},{lsr,abx},{bbr,zpb}, - {rts,imp},{adc,idx},{ill,non},{bsr,rw2},/* 60 */ - {stz,zpg},{adc,zpg},{ror,zpg},{rmb,zpg}, - {pla,imp},{adc,imm},{ror,acc},{ill,non}, - {jmp,ind},{adc,aba},{ror,aba},{bbr,zpb}, - {bvs,rel},{adc,idy},{adc,zpi},{ill,non},/* 70 */ - {stz,zpx},{adc,zpx},{ror,zpx},{rmb,zpg}, - {sei,imp},{adc,aby},{ply,imp},{ill,non}, - {jmp,iax},{adc,abx},{ror,abx},{bbr,zpb}, - {bra,rel},{sta,idx},{ill,non},{ill,non},/* 80 */ - {sty,zpg},{sta,zpg},{stx,zpg},{smb,zpg}, - {dey,imp},{bit,imm},{txa,imp},{ill,non}, - {sty,aba},{sta,aba},{stx,aba},{bbs,zpb}, - {bcc,rel},{sta,idy},{sta,zpi},{ill,non},/* 90 */ - {sty,zpx},{sta,zpx},{stx,zpy},{smb,zpg}, - {tya,imp},{sta,aby},{txs,imp},{ill,non}, - {stz,aba},{sta,abx},{stz,abx},{bbs,zpb}, - {ldy,imm},{lda,idx},{ldx,imm},{ill,non},/* a0 */ - {ldy,zpg},{lda,zpg},{ldx,zpg},{smb,zpg}, - {tay,imp},{lda,imm},{tax,imp},{ill,non}, - {ldy,aba},{lda,aba},{ldx,aba},{bbs,zpb}, - {bcs,rel},{lda,idy},{lda,zpi},{ill,non},/* b0 */ - {ldy,zpx},{lda,zpx},{ldx,zpy},{smb,zpg}, - {clv,imp},{lda,aby},{tsx,imp},{ill,non}, - {ldy,abx},{lda,abx},{ldx,aby},{bbs,zpb}, - {cpy,imm},{cmp,idx},{ill,non},{ill,non},/* c0 */ - {cpy,zpg},{cmp,zpg},{dec,zpg},{smb,zpg}, - {iny,imp},{cmp,imm},{dex,imp},{ill,non}, - {cpy,aba},{cmp,aba},{dec,aba},{bbs,zpb}, - {bne,rel},{cmp,idy},{cmp,zpi},{ill,non},/* d0 */ - {ill,non},{cmp,zpx},{dec,zpx},{smb,zpg}, - {cld,imp},{cmp,aby},{phx,imp},{ill,non}, - {ill,non},{cmp,abx},{dec,abx},{bbs,zpb}, - {cpx,imm},{sbc,idx},{ill,non},{ill,non},/* e0 */ - {cpx,zpg},{sbc,zpg},{inc,zpg},{smb,zpg}, - {inx,imp},{sbc,imm},{nop,imp},{ill,non}, - {cpx,aba},{sbc,aba},{inc,aba},{bbs,zpb}, - {beq,rel},{sbc,idy},{sbc,zpi},{ill,non},/* f0 */ - {ill,non},{sbc,zpx},{inc,zpx},{smb,zpg}, - {sed,imp},{sbc,aby},{plx,imp},{ill,non}, - {ill,non},{sbc,abx},{inc,abx},{bbs,zpb} -}; - -static const struct op6502_info op65ce02[256] = { - {m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */ - {tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg}, - {php,imp},{ora,imm},{asl,acc},{tsy,imp}, - {tsb,aba},{ora,aba},{asl,aba},{bbr,zpb}, - {bpl,rel},{ora,idy},{ora,idz},{bpl,rw2},/* 10 */ - {trb,zpg},{ora,zpx},{asl,zpx},{rmb,zpg}, - {clc,imp},{ora,aby},{ina,imp},{inz,imp}, - {trb,aba},{ora,abx},{asl,abx},{bbr,zpb}, - {jsr,adr},{and_,idx},{jsr,ind},{jsr,iax},/* 20 */ - {bit,zpg},{and_,zpg},{rol,zpg},{rmb,zpg}, - {plp,imp},{and_,imm},{rol,acc},{tys,imp}, - {bit,aba},{and_,aba},{rol,aba},{bbr,zpb}, - {bmi,rel},{and_,idz},{and_,zpi},{bmi,rw2},/* 30 */ - {bit,zpx},{and_,zpx},{rol,zpx},{rmb,zpg}, - {sec,imp},{and_,aby},{dea,imp},{dez,imp}, - {bit,abx},{and_,abx},{rol,abx},{bbr,zpb}, - {rti,imp},{eor,idx},{neg,imp},{asr2,imp},/* 40 */ - {asr2,zpg},{eor,zpg},{lsr,zpg},{rmb,zpg}, - {pha,imp},{eor,imm},{lsr,acc},{taz,imp}, - {jmp,adr},{eor,aba},{lsr,aba},{bbr,zpb}, - {bvc,rel},{eor,idy},{eor,idz},{bvc,rw2},/* 50 */ - {asr2,zpx},{eor,zpx},{lsr,zpx},{rmb,zpg}, - {cli,imp},{eor,aby},{phy,imp},{tab,imp}, - {aug,iw3},{eor,abx},{lsr,abx},{bbr,zpb}, - {rts,imp},{adc,idx},{rtn,imm},{bsr,rw2},/* 60 */ - {stz2,zpg},{adc,zpg},{ror,zpg},{rmb,zpg}, - {pla,imp},{adc,imm},{ror,acc},{tza,imp}, - {jmp,ind},{adc,aba},{ror,aba},{bbr,zpb}, - {bvs,rel},{adc,idy},{adc,zpi},{bvs,rw2},/* 70 */ - {stz2,zpx},{adc,zpx},{ror,zpx},{rmb,zpg}, - {sei,imp},{adc,aby},{ply,imp},{tba,imp}, - {jmp,iax},{adc,abx},{ror,abx},{bbr,zpb}, - {bra,rel},{sta,idx},{sta,isy},{bra,rw2},/* 80 */ - {sty,zpg},{sta,zpg},{stx,zpg},{smb,zpg}, - {dey,imp},{bit,imm},{txa,imp},{sty,abx}, - {sty,aba},{sta,aba},{stx,aba},{bbs,zpb}, - {bcc,rel},{sta,idy},{sta,inz},{bcc,rw2},/* 90 */ - {sty,zpx},{sta,zpx},{stx,zpy},{smb,zpg}, - {tya,imp},{sta,aby},{txs,imp},{stx,aby}, - {stz2,aba},{sta,abx},{stz2,abx},{bbs,zpb}, - {ldy,imm},{lda,idx},{ldx,imm},{ldz,imm},/* a0 */ - {ldy,zpg},{lda,zpg},{ldx,zpg},{smb,zpg}, - {tay,imp},{lda,imm},{tax,imp},{ldz,aba}, - {ldy,aba},{lda,aba},{ldx,aba},{bbs,zpb}, - {bcs,rel},{lda,idy},{lda,inz},{bcs,rw2},/* b0 */ - {ldy,zpx},{lda,zpx},{ldx,zpy},{smb,zpg}, - {clv,imp},{lda,aby},{tsx,imp},{ldz,abx}, - {ldy,abx},{lda,abx},{ldx,aby},{bbs,zpb}, - {cpy,imm},{cmp,idx},{cpz,imm},{dew,zpg},/* c0 */ - {cpy,zpg},{cmp,zpg},{dec,zpg},{smb,zpg}, - {iny,imp},{cmp,imm},{dex,imp},{asw,aba}, - {cpy,aba},{cmp,aba},{dec,aba},{bbs,zpb}, - {bne,rel},{cmp,idy},{cmp,idz},{bne,rw2},/* d0 */ - {cpz,zpg},{cmp,zpx},{dec,zpx},{smb,zpg}, - {cld,imp},{cmp,aby},{phx,imp},{phz,imp}, - {cpz,aba},{cmp,abx},{dec,abx},{bbs,zpb}, - {cpx,imm},{sbc,idx},{lda,isy},{inw,zpg},/* e0 */ - {cpx,zpg},{sbc,zpg},{inc,zpg},{smb,zpg}, - {inx,imp},{sbc,imm},{nop,imp},{row,aba}, - {cpx,aba},{sbc,aba},{inc,aba},{bbs,zpb}, - {beq,rel},{sbc,idy},{sbc,idz},{beq,rw2},/* f0 */ - {phw,iw2},{sbc,zpx},{inc,zpx},{smb,zpg}, - {sed,imp},{sbc,aby},{plx,imp},{plz,imp}, - {phw,aba},{sbc,abx},{inc,abx},{bbs,zpb} -}; - -// only map instead of aug and 20 bit memory management -static const struct op6502_info op4510[256] = { - {m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */ - {tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg}, - {php,imp},{ora,imm},{asl,acc},{tsy,imp}, - {tsb,aba},{ora,aba},{asl,aba},{bbr,zpb}, - {bpl,rel},{ora,idy},{ora,idz},{bpl,rw2},/* 10 */ - {trb,zpg},{ora,zpx},{asl,zpx},{rmb,zpg}, - {clc,imp},{ora,aby},{ina,imp},{inz,imp}, - {trb,aba},{ora,abx},{asl,abx},{bbr,zpb}, - {jsr,adr},{and_,idx},{jsr,ind},{jsr,iax},/* 20 */ - {bit,zpg},{and_,zpg},{rol,zpg},{rmb,zpg}, - {plp,imp},{and_,imm},{rol,acc},{tys,imp}, - {bit,aba},{and_,aba},{rol,aba},{bbr,zpb}, - {bmi,rel},{and_,idz},{and_,zpi},{bmi,rw2},/* 30 */ - {bit,zpx},{and_,zpx},{rol,zpx},{rmb,zpg}, - {sec,imp},{and_,aby},{dea,imp},{dez,imp}, - {bit,abx},{and_,abx},{rol,abx},{bbr,zpb}, - {rti,imp},{eor,idx},{neg,imp},{asr2,imp},/* 40 */ - {asr2,zpg},{eor,zpg},{lsr,zpg},{rmb,zpg}, - {pha,imp},{eor,imm},{lsr,acc},{taz,imp}, - {jmp,adr},{eor,aba},{lsr,aba},{bbr,zpb}, - {bvc,rel},{eor,idy},{eor,idz},{bvc,rw2},/* 50 */ - {asr2,zpx},{eor,zpx},{lsr,zpx},{rmb,zpg}, - {cli,imp},{eor,aby},{phy,imp},{tab,imp}, - {map,imp},{eor,abx},{lsr,abx},{bbr,zpb}, - {rts,imp},{adc,idx},{rtn,imm},{bsr,rw2},/* 60 */ - {stz2,zpg},{adc,zpg},{ror,zpg},{rmb,zpg}, - {pla,imp},{adc,imm},{ror,acc},{tza,imp}, - {jmp,ind},{adc,aba},{ror,aba},{bbr,zpb}, - {bvs,rel},{adc,idy},{adc,zpi},{bvs,rw2},/* 70 */ - {stz2,zpx},{adc,zpx},{ror,zpx},{rmb,zpg}, - {sei,imp},{adc,aby},{ply,imp},{tba,imp}, - {jmp,iax},{adc,abx},{ror,abx},{bbr,zpb}, - {bra,rel},{sta,idx},{sta,isy},{bra,rw2},/* 80 */ - {sty,zpg},{sta,zpg},{stx,zpg},{smb,zpg}, - {dey,imp},{bit,imm},{txa,imp},{sty,abx}, - {sty,aba},{sta,aba},{stx,aba},{bbs,zpb}, - {bcc,rel},{sta,idy},{sta,inz},{bcc,rw2},/* 90 */ - {sty,zpx},{sta,zpx},{stx,zpy},{smb,zpg}, - {tya,imp},{sta,aby},{txs,imp},{stx,aby}, - {stz2,aba},{sta,abx},{stz2,abx},{bbs,zpb}, - {ldy,imm},{lda,idx},{ldx,imm},{ldz,imm},/* a0 */ - {ldy,zpg},{lda,zpg},{ldx,zpg},{smb,zpg}, - {tay,imp},{lda,imm},{tax,imp},{ldz,aba}, - {ldy,aba},{lda,aba},{ldx,aba},{bbs,zpb}, - {bcs,rel},{lda,idy},{lda,inz},{bcs,rw2},/* b0 */ - {ldy,zpx},{lda,zpx},{ldx,zpy},{smb,zpg}, - {clv,imp},{lda,aby},{tsx,imp},{ldz,abx}, - {ldy,abx},{lda,abx},{ldx,aby},{bbs,zpb}, - {cpy,imm},{cmp,idx},{cpz,imm},{dew,zpg},/* c0 */ - {cpy,zpg},{cmp,zpg},{dec,zpg},{smb,zpg}, - {iny,imp},{cmp,imm},{dex,imp},{asw,aba}, - {cpy,aba},{cmp,aba},{dec,aba},{bbs,zpb}, - {bne,rel},{cmp,idy},{cmp,idz},{bne,rw2},/* d0 */ - {cpz,zpg},{cmp,zpx},{dec,zpx},{smb,zpg}, - {cld,imp},{cmp,aby},{phx,imp},{phz,imp}, - {cpz,aba},{cmp,abx},{dec,abx},{bbs,zpb}, - {cpx,imm},{sbc,idx},{lda,isy},{inw,zpg},/* e0 */ - {cpx,zpg},{sbc,zpg},{inc,zpg},{smb,zpg}, - {inx,imp},{sbc,imm},{nop,imp},{row,aba}, - {cpx,aba},{sbc,aba},{inc,aba},{bbs,zpb}, - {beq,rel},{sbc,idy},{sbc,idz},{beq,rw2},/* f0 */ - {phw,iw2},{sbc,zpx},{inc,zpx},{smb,zpg}, - {sed,imp},{sbc,aby},{plx,imp},{plz,imp}, - {phw,aba},{sbc,abx},{inc,abx},{bbs,zpb} -}; - -static const struct op6502_info opdeco16[256] = -{ - {m6502_brk,imp},{ora,idx},{ill,non},{ill,non},/* 00 */ - {ill,non},{ora,zpg},{asl,zpg},{ill,non}, - {php,imp},{ora,imm},{asl,acc},{u0B,zpg}, - {ill,non},{ora,aba},{asl,aba},{ill,non}, - {bpl,rel},{ora,idy},{ill,non},{u13,zpg},/* 10 */ - {ill,non},{ora,zpx},{asl,zpx},{ill,non}, - {clc,imp},{ora,aby},{ill,non},{ill,non}, - {ill,non},{ora,abx},{asl,abx},{ill,non}, - {jsr,adr},{and_,idx},{ill,non},{u23,zpg},/* 20 */ - {bit,zpg},{and_,zpg},{rol,zpg},{ill,non}, - {plp,imp},{and_,imm},{rol,acc},{ill,non}, - {bit,aba},{and_,aba},{rol,aba},{ill,non}, - {bmi,rel},{and_,idy},{ill,non},{ill,non},/* 30 */ - {ill,non},{and_,zpx},{rol,zpx},{ill,non}, - {sec,imp},{and_,aby},{ill,non},{ill,non}, - {ill,non},{and_,abx},{rol,abx},{u3F,zpg}, - {rti,imp},{eor,idx},{ill,non},{ill,non},/* 40 */ - {ill,non},{eor,zpg},{lsr,zpg},{ill,non}, - {pha,imp},{eor,imm},{lsr,acc},{u4B,zpg}, - {jmp,adr},{eor,aba},{lsr,aba},{ill,non}, - {bvc,rel},{eor,idy},{ill,non},{ill,non},/* 50 */ - {ill,non},{eor,zpx},{lsr,zpx},{ill,non}, - {cli,imp},{eor,aby},{ill,non},{ill,non}, - {ill,non},{eor,abx},{lsr,abx},{ill,non}, - {rts,imp},{adc,idx},{ill,non},{ill,non},/* 60 */ - {ill,non},{adc,zpg},{ror,zpg},{vbl,zpg}, // MISH - {pla,imp},{adc,imm},{ror,acc},{ill,non}, - {jmp,ind},{adc,aba},{ror,aba},{ill,non}, - {bvs,rel},{adc,idy},{ill,non},{ill,non},/* 70 */ - {ill,non},{adc,zpx},{ror,zpx},{ill,non}, - {sei,imp},{adc,aby},{ill,non},{ill,non}, - {ill,non},{adc,abx},{ror,abx},{ill,non}, - {ill,non},{sta,idx},{ill,non},{ill,non},/* 80 */ - {sty,zpg},{sta,zpg},{stx,zpg},{u87,zpg}, - {dey,imp},{ill,non},{txa,imp},{ill,non}, - {sty,aba},{sta,aba},{stx,aba},{u8F,zpg}, - {bcc,rel},{sta,idy},{ill,non},{ill,non},/* 90 */ - {sty,zpx},{sta,zpx},{stx,zpy},{ill,non}, - {tya,imp},{sta,aby},{txs,imp},{ill,non}, - {ill,non},{sta,abx},{ill,non},{ill,non}, - {ldy,imm},{lda,idx},{ldx,imm},{uA3,zpg},/* a0 */ - {ldy,zpg},{lda,zpg},{ldx,zpg},{ill,non}, - {tay,imp},{lda,imm},{tax,imp},{uAB,zpg}, - {ldy,aba},{lda,aba},{ldx,aba},{ill,non}, - {bcs,rel},{lda,idy},{ill,non},{ill,non},/* b0 */ - {ldy,zpx},{lda,zpx},{ldx,zpy},{ill,non}, - {clv,imp},{lda,aby},{tsx,imp},{uBB,zpg}, - {ldy,abx},{lda,abx},{ldx,aby},{ill,non}, - {cpy,imm},{cmp,idx},{ill,non},{ill,non},/* c0 */ - {cpy,zpg},{cmp,zpg},{dec,zpg},{ill,non}, - {iny,imp},{cmp,imm},{dex,imp},{ill,non}, - {cpy,aba},{cmp,aba},{dec,aba},{ill,non}, - {bne,rel},{cmp,idy},{ill,non},{ill,non},/* d0 */ - {ill,non},{cmp,zpx},{dec,zpx},{ill,non}, - {cld,imp},{cmp,aby},{ill,non},{ill,non}, - {ill,non},{cmp,abx},{dec,abx},{ill,non}, - {cpx,imm},{sbc,idx},{ill,non},{ill,non},/* e0 */ - {cpx,zpg},{sbc,zpg},{inc,zpg},{ill,non}, - {inx,imp},{sbc,imm},{nop,imp},{ill,non}, - {cpx,aba},{sbc,aba},{inc,aba},{ill,non}, - {beq,rel},{sbc,idy},{ill,non},{ill,non},/* f0 */ - {ill,non},{sbc,zpx},{inc,zpx},{ill,non}, - {sed,imp},{sbc,aby},{ill,non},{ill,non}, - {ill,non},{sbc,abx},{inc,abx},{ill,non} -}; - -/***************************************************************************** - * Disassemble a single opcode starting at pc - *****************************************************************************/ -static unsigned internal_m6502_dasm(const struct op6502_info *opinfo, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram) -{ - char *dst = buffer; - INT8 offset; - INT16 offset16; - unsigned PC = pc; - UINT16 addr; - UINT8 op, opc, arg, value; - UINT32 flags; - int pos = 0; - - op = oprom[pos++]; - pc++; - - opc = opinfo[op].opc; - arg = opinfo[op].arg; - - /* determine dasmflags */ - switch(opc) - { - case jsr: - case bsr: - flags = DASMFLAG_SUPPORTED | DASMFLAG_STEP_OVER; - break; - - case rts: - case rti: - case rtn: - flags = DASMFLAG_SUPPORTED | DASMFLAG_STEP_OUT; - break; - - default: - flags = DASMFLAG_SUPPORTED; - break; - } - - dst += sprintf(dst, "%-5s", token[opc]); - if( opc == bbr || opc == bbs || opc == rmb || opc == smb ) - dst += sprintf(dst, "%d,", (op >> 4) & 7); - - switch(arg) - { - case imp: - break; - - case acc: - dst += sprintf(dst,"a"); - break; - - case rel: - offset = (INT8) opram[pos++]; - pc++; - dst += sprintf(dst, "$%04X", (pc + offset) & 0xFFFF); - break; - - case rw2: - offset16 = (opram[pos] | (opram[pos+1] << 8)) -1; - pos += 2; - pc += 2; - dst += sprintf(dst, "$%04X", (pc + offset16) & 0xFFFF); - break; - - case imm: - value = opram[pos++]; - pc++; - dst += sprintf(dst,"#$%02X", value); - break; - - case zpg: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"$%02X", addr); - break; - - case zpx: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"$%02X,x", addr); - break; - - case zpy: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"$%02X,y", addr); - break; - - case idx: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"($%02X,x)", addr); - break; - - case idy: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"($%02X),y", addr); - break; - - case zpi: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"($%02X)", addr); - break; - - case zpb: - addr = opram[pos++]; - pc++; - dst += sprintf(dst,"$%02X", addr); - offset = (INT8) opram[pos++]; - pc++; - dst += sprintf(dst,",$%04X", pc + offset); - break; - - case adr: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst, "$%04X", addr); - break; - - case aba: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst, "$%04X", addr); - break; - - case abx: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst,"$%04X,x", addr); - break; - - case aby: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst,"$%04X,y", addr); - break; - - case ind: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst,"($%04X)", addr); - break; - - case iax: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst,"($%04X),X", addr); - break; - - case iw2: - addr = (opram[pos] | (opram[pos+1] << 8)); - pos += 2; - pc += 2; - dst += sprintf(dst,"#%04X", addr); - break; - - case iw3: - addr = (opram[pos] | (opram[pos+1] << 8) | (opram[pos+2] << 16)); - pos += 3; - pc += 3; - dst += sprintf(dst,"#%06x", addr); - break; - - case idz: - addr = (INT8) opram[pos++]; - pc++; - dst += sprintf(dst,"($%02X),z", addr); - break; - - case isy: - op = opram[pos++]; - pc++; - addr = op; - dst += sprintf(dst,"(s,$%02X),y", addr); - break; - - default: - dst += sprintf(dst,"$%02X", op); - break; - } - return (pc - PC) | flags; -} - -CPU_DISASSEMBLE( m6502 ) -{ - return internal_m6502_dasm(op6502, buffer, pc, oprom, opram); -} - -CPU_DISASSEMBLE( m65sc02 ) -{ - return internal_m6502_dasm(op65sc02, buffer, pc, oprom, opram); -} - -CPU_DISASSEMBLE( m65c02 ) -{ - return internal_m6502_dasm(op65c02, buffer, pc, oprom, opram); -} - -CPU_DISASSEMBLE( m65ce02 ) -{ - return internal_m6502_dasm(op65ce02, buffer, pc, oprom, opram); -} - -CPU_DISASSEMBLE( m6510 ) -{ - return internal_m6502_dasm(op6502, buffer, pc, oprom, opram); -} - -CPU_DISASSEMBLE( deco16 ) -{ - return internal_m6502_dasm(opdeco16, buffer, pc, oprom, opram); -} - -CPU_DISASSEMBLE( m4510 ) -{ - return internal_m6502_dasm(op4510, buffer, pc, oprom, opram); -} diff --git a/src/emu/cpu/m6502/ddeco16.lst b/src/emu/cpu/m6502/ddeco16.lst index e69de29bb2d..e5c8fa7a8e3 100644 --- a/src/emu/cpu/m6502/ddeco16.lst +++ b/src/emu/cpu/m6502/ddeco16.lst @@ -0,0 +1,18 @@ +# deco16 - deco variant +brk_imp ora_idx ill_non ill_non ill_non ora_zpg asl_zpg ill_non php_imp ora_imm asl_acc u0B_zpg ill_non ora_aba asl_aba ill_non +bpl_rel ora_idy ill_non u13_zpg ill_non ora_zpx asl_zpx ill_non clc_imp ora_aby ill_non ill_non ill_non ora_abx asl_abx ill_non +jsr_adr and_idx ill_non u23_zpg bit_zpg and_zpg rol_zpg ill_non plp_imp and_imm rol_acc ill_non bit_aba and_aba rol_aba ill_non +bmi_rel and_idy ill_non ill_non ill_non and_zpx rol_zpx ill_non sec_imp and_aby ill_non ill_non ill_non and_abx rol_abx u3F_zpg +rti_imp eor_idx ill_non ill_non ill_non eor_zpg lsr_zpg ill_non pha_imp eor_imm lsr_acc u4B_zpg jmp_adr eor_aba lsr_aba ill_non +bvc_rel eor_idy ill_non ill_non ill_non eor_zpx lsr_zpx ill_non cli_imp eor_aby ill_non ill_non ill_non eor_abx lsr_abx ill_non +rts_imp adc_idx ill_non ill_non ill_non adc_zpg ror_zpg vbl_zpg pla_imp adc_imm ror_acc ill_non jmp_ind adc_aba ror_aba ill_non +bvs_rel adc_idy ill_non ill_non ill_non adc_zpx ror_zpx ill_non sei_imp adc_aby ill_non ill_non ill_non adc_abx ror_abx ill_non +ill_non sta_idx ill_non ill_non sty_zpg sta_zpg stx_zpg u87_zpg dey_imp ill_non txa_imp ill_non sty_aba sta_aba stx_aba u8F_zpg +bcc_rel sta_idy ill_non ill_non sty_zpx sta_zpx stx_zpy ill_non tya_imp sta_aby txs_imp ill_non ill_non sta_abx ill_non ill_non +ldy_imm lda_idx ldx_imm uA3_zpg ldy_zpg lda_zpg ldx_zpg ill_non tay_imp lda_imm tax_imp ill_non ldy_aba lda_aba ldx_aba ill_non +bcs_rel lda_idy ill_non ill_non ldy_zpx lda_zpx ldx_zpy ill_non clv_imp lda_aby tsx_imp uBB_zpg ldy_abx lda_abx ldx_aby ill_non +cpy_imm cmp_idx ill_non ill_non cpy_zpg cmp_zpg dec_zpg ill_non iny_imp cmp_imm dex_imp ill_non cpy_aba cmp_aba dec_aba ill_non +bne_rel cmp_idy ill_non ill_non ill_non cmp_zpx dec_zpx ill_non cld_imp cmp_aby ill_non ill_non ill_non cmp_abx dec_abx ill_non +cpx_imm sbc_idx ill_non ill_non cpx_zpg sbc_zpg inc_zpg ill_non inx_imp sbc_imm nop_imp ill_non cpx_aba sbc_aba inc_aba ill_non +beq_rel sbc_idy ill_non ill_non ill_non sbc_zpx inc_zpx ill_non sed_imp sbc_aby ill_non ill_non ill_non sbc_abx inc_abx ill_non +reset diff --git a/src/emu/cpu/m6502/deco16.c b/src/emu/cpu/m6502/deco16.c index e69de29bb2d..4be9028acb2 100644 --- a/src/emu/cpu/m6502/deco16.c +++ b/src/emu/cpu/m6502/deco16.c @@ -0,0 +1,76 @@ +/*************************************************************************** + + deco16.c + + 6502, reverse-engineered DECO variant + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "deco16.h" + +#define DECO16_VERBOSE 1 + +const device_type DECO16 = &device_creator; + +deco16_device::deco16_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, DECO16, "DECO16", tag, owner, clock), + io_config("io", ENDIANNESS_LITTLE, 8, 16) +{ +} + +offs_t deco16_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); +} + + +void deco16_device::device_start() +{ + if(direct_disabled) + mintf = new mi_default_nd; + else + mintf = new mi_default_normal; + + init(); + + io = &space(AS_IO); +} + +const address_space_config *deco16_device::memory_space_config(address_spacenum spacenum) const +{ + return spacenum == AS_PROGRAM ? &program_config : spacenum == AS_IO ? &io_config : NULL; +} + +#include "cpu/m6502/deco16.inc" diff --git a/src/emu/cpu/m6502/deco16.h b/src/emu/cpu/m6502/deco16.h index e69de29bb2d..1d7548a06a7 100644 --- a/src/emu/cpu/m6502/deco16.h +++ b/src/emu/cpu/m6502/deco16.h @@ -0,0 +1,88 @@ +/*************************************************************************** + + deco16.h + + 6502, reverse-engineered DECO variant + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __DECO16_H__ +#define __DECO16_H__ + +#include "m6502.h" + +class deco16_device : public m6502_device { +public: + deco16_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + +protected: + address_space *io; + address_space_config io_config; + + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; + virtual void device_start(); + +#define O(o) void o ## _full(); void o ## _partial() + + O(ill_non); + O(u0B_zpg); + O(u13_zpg); + O(u23_zpg); + O(u3F_zpg); + O(u4B_zpg); + O(u87_zpg); + O(u8F_zpg); + O(uA3_zpg); + O(uAB_zpg); + O(uBB_zpg); + O(vbl_zpg); + +#undef O +}; + +enum { + DECO16_IRQ_LINE = m6502_device::IRQ_LINE, + DECO16_NMI_LINE = m6502_device::NMI_LINE, + DECO16_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type DECO16; + +#endif diff --git a/src/emu/cpu/m6502/dm4510.lst b/src/emu/cpu/m6502/dm4510.lst index e69de29bb2d..63de577c42a 100644 --- a/src/emu/cpu/m6502/dm4510.lst +++ b/src/emu/cpu/m6502/dm4510.lst @@ -0,0 +1,18 @@ +# m4510 - 65ce02 with a mmu +brk_ce_imp ora_ce_idx cle_imp see_imp tsb_ce_zpg ora_ce_zpg asl_ce_zpg rmb_ce_bzp php_ce_imp ora_imm asl_ce_acc tsy_imp tsb_ce_aba ora_aba asl_ce_aba bbr_ce_zpb +bpl_ce_rel ora_ce_idy ora_idz bpl_rw2 trb_ce_zpg ora_ce_zpx asl_ce_zpx rmb_ce_bzp clc_ce_imp ora_ce_aby inc_ce_acc inz_imp trb_ce_aba ora_ce_abx asl_ce_abx bbr_ce_zpb +jsr_ce_adr and_ce_idx jsr_ind jsr_iax bit_ce_zpg and_ce_zpg rol_ce_zpg rmb_ce_bzp plp_ce_imp and_imm rol_ce_acc tys_imp bit_aba and_aba rol_ce_aba bbr_ce_zpb +bmi_ce_rel and_ce_idy and_idz bmi_rw2 bit_ce_zpx and_ce_zpx rol_ce_zpx rmb_ce_bzp sec_ce_imp and_ce_aby dec_ce_acc dez_imp bit_ce_abx and_ce_abx rol_ce_abx bbr_ce_zpb +rti_ce_imp eor_ce_idx neg_acc asr_acc asr_zpg eor_ce_zpg lsr_ce_zpg rmb_ce_bzp pha_ce_imp eor_imm lsr_ce_acc taz_imp jmp_adr eor_aba lsr_ce_aba bbr_ce_zpb +bvc_ce_rel eor_ce_idy eor_idz bvc_rw2 asr_zpx eor_ce_zpx lsr_ce_zpx rmb_ce_bzp cli_ce_imp eor_ce_aby phy_ce_imp tab_imp map_imp eor_ce_abx lsr_ce_abx bbr_ce_zpb +rts_ce_imp adc_ce_idx rtn_imm bsr_rw2 stz_ce_zpg adc_ce_zpg ror_ce_zpg rmb_ce_bzp pla_ce_imp adc_ce_imm ror_ce_acc tza_imp jmp_ce_ind adc_ce_aba ror_ce_aba bbr_ce_zpb +bvs_ce_rel adc_ce_idy adc_idz bvs_rw2 stz_ce_zpx adc_ce_zpx ror_ce_zpx rmb_ce_bzp sei_ce_imp adc_ce_aby ply_ce_imp tba_imp jmp_ce_iax adc_ce_abx ror_ce_abx bbr_ce_zpb +bra_ce_rel sta_ce_idx sta_isy bra_rw2 sty_ce_zpg sta_ce_zpg stx_ce_zpg smb_ce_bzp dey_ce_imp bit_ce_imm txa_ce_imp sty_abx sty_aba sta_aba stx_aba bbs_ce_zpb +bcc_ce_rel sta_ce_idy sta_idz bcc_rw2 sty_ce_zpx sta_ce_zpx stx_ce_zpy smb_ce_bzp tya_ce_imp sta_ce_aby txs_ce_imp stx_aby stz_ce_aba sta_ce_abx stz_ce_abx bbs_ce_zpb +ldy_imm lda_ce_idx ldx_imm ldz_imm ldy_ce_zpg lda_ce_zpg ldx_ce_zpg smb_ce_bzp tay_ce_imp lda_imm tax_ce_imp ldz_aba ldy_aba lda_aba ldx_aba bbs_ce_zpb +bcs_ce_rel lda_ce_idy lda_idz bcs_rw2 ldy_ce_zpx lda_ce_zpx ldx_ce_zpy smb_ce_bzp clv_ce_imp lda_ce_aby tsx_ce_imp ldz_abx ldy_ce_abx lda_ce_abx ldx_ce_aby bbs_ce_zpb +cpy_imm cmp_ce_idx cpz_imm dew_zpg cpy_ce_zpg cmp_ce_zpg dec_ce_zpg smb_ce_bzp iny_ce_imp cmp_imm dex_ce_imp asw_aba cpy_aba cmp_aba dec_ce_aba bbs_ce_zpb +bne_ce_rel cmp_ce_idy cmp_idz bne_rw2 cpz_zpg cmp_ce_zpx dec_ce_zpx smb_ce_bzp cld_ce_imp cmp_ce_aby phx_ce_imp phz_imp cpz_aba cmp_ce_abx dec_ce_abx bbs_ce_zpb +cpx_imm sbc_ce_idx lda_isy inw_zpg cpx_ce_zpg sbc_ce_zpg inc_ce_zpg smb_ce_bzp inx_ce_imp sbc_ce_imm eom_imp row_aba cpx_aba sbc_ce_aba inc_ce_aba bbs_ce_zpb +beq_ce_rel sbc_ce_idy sbc_idz beq_rw2 phw_iw2 sbc_ce_zpx inc_ce_zpx smb_ce_bzp sed_ce_imp sbc_ce_aby plx_ce_imp plz_imp phw_aba sbc_ce_abx inc_ce_abx bbs_ce_zpb +reset diff --git a/src/emu/cpu/m6502/dm6502.lst b/src/emu/cpu/m6502/dm6502.lst index e69de29bb2d..5dfe9cb0333 100644 --- a/src/emu/cpu/m6502/dm6502.lst +++ b/src/emu/cpu/m6502/dm6502.lst @@ -0,0 +1,18 @@ +# m6502_family_device - 6502, 6504 +brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba +bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx +jsr_adr and_idx kil_non rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba +bmi_rel and_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx +rti_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba +bvc_rel eor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx +rts_imp adc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba +bvs_rel adc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx +nop_imp sta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba +bcc_rel sta_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby +ldy_imm lda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba +bcs_rel lda_idy kil_non lax_idy ldy_zpx lda_zpx ldx_zpy lax_zpy clv_imp lda_aby tsx_imp las_aby ldy_abx lda_abx ldx_aby lax_aby +cpy_imm cmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba +bne_rel cmp_idy kil_non dcp_idy nop_zpx cmp_zpx dec_zpx dcp_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx +cpx_imm sbc_idx nop_imm isb_idx cpx_zpg sbc_zpg inc_zpg isb_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba +beq_rel sbc_idy kil_non isb_idy nop_zpx sbc_zpx inc_zpx isb_zpx sed_imp sbc_aby nop_imp isb_aby nop_abx sbc_abx inc_abx isb_abx +reset diff --git a/src/emu/cpu/m6502/dm6509.lst b/src/emu/cpu/m6502/dm6509.lst index e69de29bb2d..a0be552a85b 100644 --- a/src/emu/cpu/m6502/dm6509.lst +++ b/src/emu/cpu/m6502/dm6509.lst @@ -0,0 +1,18 @@ +# m6509 - special banking on two specific instructions, and banking in general +brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba +bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx +jsr_adr and_idx kil_non rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba +bmi_rel and_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx +rti_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba +bvc_rel eor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx +rts_imp adc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba +bvs_rel adc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx +nop_imp sta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba +bcc_rel sta_9_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby +ldy_imm lda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba +bcs_rel lda_9_idy kil_non lax_idy ldy_zpx lda_zpx ldx_zpy lax_zpy clv_imp lda_aby tsx_imp las_aby ldy_abx lda_abx ldx_aby lax_aby +cpy_imm cmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba +bne_rel cmp_idy kil_non dcp_idy nop_zpx cmp_zpx dec_zpx dcp_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx +cpx_imm sbc_idx nop_imm isb_idx cpx_zpg sbc_zpg inc_zpg isb_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba +beq_rel sbc_idy kil_non isb_idy nop_zpx sbc_zpx inc_zpx isb_zpx sed_imp sbc_aby nop_imp isb_aby nop_abx sbc_abx inc_abx isb_abx +reset diff --git a/src/emu/cpu/m6502/dm6510.lst b/src/emu/cpu/m6502/dm6510.lst index e69de29bb2d..f0cb4d065be 100644 --- a/src/emu/cpu/m6502/dm6510.lst +++ b/src/emu/cpu/m6502/dm6510.lst @@ -0,0 +1,18 @@ +# m6510_family - identical to 6502, except for some undocumented instructions that have to be handled specifically +brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_10_imm nop_aba ora_aba asl_aba slo_aba +bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx +jsr_adr and_idx kil_non rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_10_imm bit_aba and_aba rol_aba rla_aba +bmi_rel and_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx +rti_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_10_imm jmp_adr eor_aba lsr_aba sre_aba +bvc_rel eor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx +rts_imp adc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_10_imm jmp_ind adc_aba ror_aba rra_aba +bvs_rel adc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx +nop_imp sta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_10_imm sty_aba sta_aba stx_aba sax_aba +bcc_rel sta_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby +ldy_imm lda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_10_imm ldy_aba lda_aba ldx_aba lax_aba +bcs_rel lda_idy kil_non lax_idy ldy_zpx lda_zpx ldx_zpy lax_zpy clv_imp lda_aby tsx_imp las_10_aby ldy_abx lda_abx ldx_aby lax_aby +cpy_imm cmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba +bne_rel cmp_idy kil_non dcp_idy nop_zpx cmp_zpx dec_zpx dcp_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx +cpx_imm sbc_idx nop_imm isb_idx cpx_zpg sbc_zpg inc_zpg isb_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba +beq_rel sbc_idy kil_non isb_idy nop_zpx sbc_zpx inc_zpx isb_zpx sed_imp sbc_aby nop_imp isb_aby nop_abx sbc_abx inc_abx isb_abx +reset diff --git a/src/emu/cpu/m6502/dm65c02.lst b/src/emu/cpu/m6502/dm65c02.lst index e69de29bb2d..85e6784056d 100644 --- a/src/emu/cpu/m6502/dm65c02.lst +++ b/src/emu/cpu/m6502/dm65c02.lst @@ -0,0 +1,18 @@ +# m65c02 +brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_zpg nop_c_imp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_aba nop_c_imp +bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_zpx nop_c_imp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx nop_c_imp +jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_zpg nop_c_imp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_aba nop_c_imp +bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_zpx nop_c_imp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx nop_c_imp +rti_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_zpg nop_c_imp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_aba nop_c_imp +bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_zpx nop_c_imp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx nop_c_imp +rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_zpg nop_c_imp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_aba nop_c_imp +bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_zpx nop_c_imp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx nop_c_imp +bra_rel sta_idx nop_imm nop_c_imp sty_zpg sta_zpg stx_zpg nop_c_imp dey_imp bit_imm txa_imp nop_c_imp sty_aba sta_aba stx_aba nop_c_imp +bcc_rel sta_idy sta_zpi nop_c_imp sty_zpx sta_zpx stx_zpy nop_c_imp tya_imp sta_aby txs_imp nop_c_imp stz_aba sta_abx stz_abx nop_c_imp +ldy_imm lda_idx ldx_imm nop_c_imp ldy_zpg lda_zpg ldx_zpg nop_c_imp tay_imp lda_imm tax_imp nop_c_imp ldy_aba lda_aba ldx_aba nop_c_imp +bcs_rel lda_idy lda_zpi nop_c_imp ldy_zpx lda_zpx ldx_zpy nop_c_imp clv_imp lda_aby tsx_imp nop_c_imp ldy_abx lda_abx ldx_aby nop_c_imp +cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_zpg nop_c_imp iny_imp cmp_imm dex_imp nop_c_imp cpy_aba cmp_aba dec_aba nop_c_imp +bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_zpx nop_c_imp cld_imp cmp_aby phx_imp nop_c_imp nop_c_abx cmp_abx dec_abx nop_c_imp +cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_zpg nop_c_imp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_aba nop_c_imp +beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_zpx nop_c_imp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_abx nop_c_imp +reset diff --git a/src/emu/cpu/m6502/dm65ce02.lst b/src/emu/cpu/m6502/dm65ce02.lst index e69de29bb2d..bbf12afe435 100644 --- a/src/emu/cpu/m6502/dm65ce02.lst +++ b/src/emu/cpu/m6502/dm65ce02.lst @@ -0,0 +1,18 @@ +# m65ce02 - Adds the B and Z registers to the r65c02, a bunch of instructions, and changes most of the timings +brk_ce_imp ora_ce_idx cle_imp see_imp tsb_ce_zpg ora_ce_zpg asl_ce_zpg rmb_ce_bzp php_ce_imp ora_imm asl_ce_acc tsy_imp tsb_ce_aba ora_aba asl_ce_aba bbr_ce_zpb +bpl_ce_rel ora_ce_idy ora_idz bpl_rw2 trb_ce_zpg ora_ce_zpx asl_ce_zpx rmb_ce_bzp clc_ce_imp ora_ce_aby inc_ce_acc inz_imp trb_ce_aba ora_ce_abx asl_ce_abx bbr_ce_zpb +jsr_ce_adr and_ce_idx jsr_ind jsr_iax bit_ce_zpg and_ce_zpg rol_ce_zpg rmb_ce_bzp plp_ce_imp and_imm rol_ce_acc tys_imp bit_aba and_aba rol_ce_aba bbr_ce_zpb +bmi_ce_rel and_ce_idy and_idz bmi_rw2 bit_ce_zpx and_ce_zpx rol_ce_zpx rmb_ce_bzp sec_ce_imp and_ce_aby dec_ce_acc dez_imp bit_ce_abx and_ce_abx rol_ce_abx bbr_ce_zpb +rti_ce_imp eor_ce_idx neg_acc asr_acc asr_zpg eor_ce_zpg lsr_ce_zpg rmb_ce_bzp pha_ce_imp eor_imm lsr_ce_acc taz_imp jmp_adr eor_aba lsr_ce_aba bbr_ce_zpb +bvc_ce_rel eor_ce_idy eor_idz bvc_rw2 asr_zpx eor_ce_zpx lsr_ce_zpx rmb_ce_bzp cli_ce_imp eor_ce_aby phy_ce_imp tab_imp aug_iw3 eor_ce_abx lsr_ce_abx bbr_ce_zpb +rts_ce_imp adc_ce_idx rtn_imm bsr_rw2 stz_ce_zpg adc_ce_zpg ror_ce_zpg rmb_ce_bzp pla_ce_imp adc_ce_imm ror_ce_acc tza_imp jmp_ce_ind adc_ce_aba ror_ce_aba bbr_ce_zpb +bvs_ce_rel adc_ce_idy adc_idz bvs_rw2 stz_ce_zpx adc_ce_zpx ror_ce_zpx rmb_ce_bzp sei_ce_imp adc_ce_aby ply_ce_imp tba_imp jmp_ce_iax adc_ce_abx ror_ce_abx bbr_ce_zpb +bra_ce_rel sta_ce_idx sta_isy bra_rw2 sty_ce_zpg sta_ce_zpg stx_ce_zpg smb_ce_bzp dey_ce_imp bit_ce_imm txa_ce_imp sty_abx sty_aba sta_aba stx_aba bbs_ce_zpb +bcc_ce_rel sta_ce_idy sta_idz bcc_rw2 sty_ce_zpx sta_ce_zpx stx_ce_zpy smb_ce_bzp tya_ce_imp sta_ce_aby txs_ce_imp stx_aby stz_ce_aba sta_ce_abx stz_ce_abx bbs_ce_zpb +ldy_imm lda_ce_idx ldx_imm ldz_imm ldy_ce_zpg lda_ce_zpg ldx_ce_zpg smb_ce_bzp tay_ce_imp lda_imm tax_ce_imp ldz_aba ldy_aba lda_aba ldx_aba bbs_ce_zpb +bcs_ce_rel lda_ce_idy lda_idz bcs_rw2 ldy_ce_zpx lda_ce_zpx ldx_ce_zpy smb_ce_bzp clv_ce_imp lda_ce_aby tsx_ce_imp ldz_abx ldy_ce_abx lda_ce_abx ldx_ce_aby bbs_ce_zpb +cpy_imm cmp_ce_idx cpz_imm dew_zpg cpy_ce_zpg cmp_ce_zpg dec_ce_zpg smb_ce_bzp iny_ce_imp cmp_imm dex_ce_imp asw_aba cpy_aba cmp_aba dec_ce_aba bbs_ce_zpb +bne_ce_rel cmp_ce_idy cmp_idz bne_rw2 cpz_zpg cmp_ce_zpx dec_ce_zpx smb_ce_bzp cld_ce_imp cmp_ce_aby phx_ce_imp phz_imp cpz_aba cmp_ce_abx dec_ce_abx bbs_ce_zpb +cpx_imm sbc_ce_idx lda_isy inw_zpg cpx_ce_zpg sbc_ce_zpg inc_ce_zpg smb_ce_bzp inx_ce_imp sbc_ce_imm nop_c_imp row_aba cpx_aba sbc_ce_aba inc_ce_aba bbs_ce_zpb +beq_ce_rel sbc_ce_idy sbc_idz beq_rw2 phw_iw2 sbc_ce_zpx inc_ce_zpx smb_ce_bzp sed_ce_imp sbc_ce_aby plx_ce_imp plz_imp phw_aba sbc_ce_abx inc_ce_abx bbs_ce_zpb +reset diff --git a/src/emu/cpu/m6502/dn2a03.lst b/src/emu/cpu/m6502/dn2a03.lst index e69de29bb2d..cc858c5c35a 100644 --- a/src/emu/cpu/m6502/dn2a03.lst +++ b/src/emu/cpu/m6502/dn2a03.lst @@ -0,0 +1,18 @@ +# n2a03 - D flag is disabled but present in the P register +brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba +bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx +jsr_adr and_idx kil_non rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba +bmi_rel and_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx +rti_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba +bvc_rel eor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx +rts_imp adc_nd_idx kil_non rra_nd_idx nop_zpg adc_nd_zpg ror_zpg rra_nd_zpg pla_imp adc_nd_imm ror_acc arr_nd_imm jmp_ind adc_nd_aba ror_aba rra_nd_aba +bvs_rel adc_nd_idy kil_non rra_nd_idy nop_zpx adc_nd_zpx ror_zpx rra_nd_zpx sei_imp adc_nd_aby nop_imp rra_nd_aby nop_abx adc_nd_abx ror_abx rra_nd_abx +nop_imp sta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba +bcc_rel sta_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby +ldy_imm lda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba +bcs_rel lda_idy kil_non lax_idy ldy_zpx lda_zpx ldx_zpy lax_zpy clv_imp lda_aby tsx_imp las_aby ldy_abx lda_abx ldx_aby lax_aby +cpy_imm cmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba +bne_rel cmp_idy kil_non dcp_idy nop_zpx cmp_zpx dec_zpx dcp_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx +cpx_imm sbc_nd_idx nop_imm isb_nd_idx cpx_zpg sbc_nd_zpg inc_zpg isb_nd_zpg inx_imp sbc_nd_imm nop_imp sbc_nd_imm cpx_aba sbc_nd_aba inc_aba isb_nd_aba +beq_rel sbc_nd_idy kil_non isb_nd_idy nop_zpx sbc_nd_zpx inc_zpx isb_nd_zpx sed_imp sbc_nd_aby nop_imp isb_nd_aby nop_abx sbc_nd_abx inc_abx isb_nd_abx +reset diff --git a/src/emu/cpu/m6502/dr65c02.lst b/src/emu/cpu/m6502/dr65c02.lst index e69de29bb2d..64b38466738 100644 --- a/src/emu/cpu/m6502/dr65c02.lst +++ b/src/emu/cpu/m6502/dr65c02.lst @@ -0,0 +1,18 @@ +# r65c02 - rockwell variant, with the bitwise instructions and stp/wai +brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_zpg rmb_bzp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_aba bbr_zpb +bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_zpx rmb_bzp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx bbr_zpb +jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_zpg rmb_bzp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_aba bbr_zpb +bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_zpx rmb_bzp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx bbr_zpb +rti_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_zpg rmb_bzp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_aba bbr_zpb +bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_zpx rmb_bzp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx bbr_zpb +rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_zpg rmb_bzp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_aba bbr_zpb +bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_zpx rmb_bzp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx bbr_zpb +bra_rel sta_idx nop_imm nop_c_imp sty_zpg sta_zpg stx_zpg smb_bzp dey_imp bit_imm txa_imp nop_c_imp sty_aba sta_aba stx_aba bbs_zpb +bcc_rel sta_idy sta_zpi nop_c_imp sty_zpx sta_zpx stx_zpy smb_bzp tya_imp sta_aby txs_imp nop_c_imp stz_aba sta_abx stz_abx bbs_zpb +ldy_imm lda_idx ldx_imm nop_c_imp ldy_zpg lda_zpg ldx_zpg smb_bzp tay_imp lda_imm tax_imp nop_c_imp ldy_aba lda_aba ldx_aba bbs_zpb +bcs_rel lda_idy lda_zpi nop_c_imp ldy_zpx lda_zpx ldx_zpy smb_bzp clv_imp lda_aby tsx_imp nop_c_imp ldy_abx lda_abx ldx_aby bbs_zpb +cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_zpg smb_bzp iny_imp cmp_imm dex_imp wai_imp cpy_aba cmp_aba dec_aba bbs_zpb +bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_zpx smb_bzp cld_imp cmp_aby phx_imp stp_imp nop_c_abx cmp_abx dec_abx bbs_zpb +cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_zpg smb_bzp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_aba bbs_zpb +beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_zpx smb_bzp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_abx bbs_zpb +reset diff --git a/src/emu/cpu/m6502/ill02.h b/src/emu/cpu/m6502/ill02.h deleted file mode 100644 index fa21452c444..00000000000 --- a/src/emu/cpu/m6502/ill02.h +++ /dev/null @@ -1,344 +0,0 @@ -#pragma once - -#ifndef __ILL02_H__ -#define __ILL02_H__ - -/***************************************************************************** - * - * ill02.h - * Addressing mode and opcode macros for the NMOS 6502 illegal opcodes - * - * Copyright Juergen Buchmueller, all rights reserved. - * 65sc02 core Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - -/* test with the excellent C64 Emulator test suite - ? at www.funet.fi/pub/cbm/documents/chipdata/tsuit215.zip - good reference in the vice emulator (source) distribution doc/64doc.txt - - $ab=OAL like in 6502-NMOS.extra.opcodes, vice so in vice (lxa) -*/ - -/*************************************************************** - *************************************************************** - * Macros to emulate the 6510 opcodes - *************************************************************** - ***************************************************************/ - -/* 6510 ******************************************************** - * ANC logical and, set carry from bit of A - ***************************************************************/ -#define ANC \ - P &= ~F_C; \ - A = (UINT8)(A & tmp); \ - if (A & 0x80) \ - P |= F_C; \ - SET_NZ(A) - -/* 6510 ******************************************************** - * ASR logical and, logical shift right - ***************************************************************/ -#define ASR \ - tmp &= A; \ - LSR - -/* 6510 ******************************************************** - * AST and stack; transfer to accumulator and index X - * logical and stack (LSB) with data, transfer result to S - * transfer result to accumulator and index X also - ***************************************************************/ -#define AST \ - S &= tmp; \ - A = X = S; \ - SET_NZ(A) - -/* 6510 ******************************************************** - * ARR logical and, rotate right - ***************************************************************/ -#define ARR \ - if( P & F_D ) \ - { \ - int lo, hi, t; \ - tmp &= A; \ - t = tmp; \ - hi = tmp &0xf0; \ - lo = tmp &0x0f; \ - if( P & F_C ) \ - { \ - tmp = (tmp >> 1) | 0x80; \ - P |= F_N; \ - } \ - else \ - { \ - tmp >>= 1; \ - P &= ~F_N; \ - } \ - if( tmp ) \ - P &= ~F_Z; \ - else \ - P |= F_Z; \ - if( (t^tmp) & 0x40 ) \ - P|=F_V; \ - else \ - P &= ~F_V; \ - if( lo + (lo & 0x01) > 0x05 ) \ - tmp = (tmp & 0xf0) | ((tmp+6) & 0xf); \ - if( hi + (hi & 0x10) > 0x50 ) \ - { \ - P |= F_C; \ - tmp = (tmp+0x60) & 0xff; \ - } \ - else \ - P &= ~F_C; \ - } \ - else \ - { \ - tmp &= A; \ - ROR; \ - P &=~(F_V|F_C); \ - if( tmp & 0x40 ) \ - P|=F_C; \ - if( (tmp & 0x60) == 0x20 || (tmp & 0x60) == 0x40 ) \ - P|=F_V; \ - } - -/* 6510 ******************************************************** - * ASX logical and X w/ A, subtract data from X - ***************************************************************/ -#define ASX \ - P &= ~F_C; \ - X &= A; \ - if (X >= tmp) \ - P |= F_C; \ - X = (UINT8)(X - tmp); \ - SET_NZ(X) - -/* 6510 ******************************************************** - * AXA transfer index X to accumulator, logical and - * depends on the data of the dma device (videochip) fetched - * between opcode read and operand read - ***************************************************************/ -#define AXA \ - A = (UINT8)( (A|0xee)& X & tmp); \ - SET_NZ(A) - -/* 6510 ******************************************************** - * DCP decrement data and compare - ***************************************************************/ -#define DCP \ - tmp = (UINT8)(tmp-1); \ - P &= ~F_C; \ - if (A >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(A - tmp)) - -/* 6502 ******************************************************** - * DOP double no operation - ***************************************************************/ -#define DOP \ - RDOPARG() - -/* 6510 ******************************************************** - * ISB increment and subtract with carry - ***************************************************************/ -#define ISB \ - tmp = (UINT8)(tmp+1); \ - SBC - -/* 6510 ******************************************************** - * LAX load accumulator and index X - ***************************************************************/ -#define LAX \ - A = X = (UINT8)tmp; \ - SET_NZ(A) - -/* 6502 ******************************************************** - * OAL load accumulator and index X - ***************************************************************/ -#define OAL \ - A = X = (UINT8)(A&tmp); \ - SET_NZ(A) - -/* 6510 ******************************************************** - * OAL load accumulator and index X - ***************************************************************/ -#define OAL_6510 \ - A = X = (UINT8)((A|0xee)&tmp); \ - SET_NZ(A) - -/* 6510 ******************************************************** - * RLA rotate left and logical and accumulator - * new C <- [7][6][5][4][3][2][1][0] <- C - ***************************************************************/ -#define RLA \ - tmp = (tmp << 1) | (P & F_C); \ - P = (P & ~F_C) | ((tmp >> 8) & F_C); \ - tmp = (UINT8)tmp; \ - A &= tmp; \ - SET_NZ(A) - -/* 6510 ******************************************************** - * RRA rotate right and add with carry - * C -> [7][6][5][4][3][2][1][0] -> C - ***************************************************************/ -#define RRA \ - tmp |= (P & F_C) << 8; \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)(tmp >> 1); \ - ADC - -/* 6510 ******************************************************** - * SAX logical and accumulator with index X and store - ***************************************************************/ -#define SAX \ - tmp = A & X - -/* 6510 ******************************************************** - * SLO shift left and logical or - ***************************************************************/ -#define SLO \ - P = (P & ~F_C) | ((tmp >> 7) & F_C); \ - tmp = (UINT8)(tmp << 1); \ - A |= tmp; \ - SET_NZ(A) - -/* 6510 ******************************************************** - * SRE logical shift right and logical exclusive or - * 0 -> [7][6][5][4][3][2][1][0] -> C - ***************************************************************/ -#define SRE \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)tmp >> 1; \ - A ^= tmp; \ - SET_NZ(A) - -/* 6510 ******************************************************** - * SAH store accumulator and index X and high + 1 - * result = accumulator and index X and memory [PC+1] + 1 - ***************************************************************/ -#define SAH tmp = A & X & (EAH+1) - -/* 6510 ******************************************************** - * SSH store stack high - * logical and accumulator with index X, transfer result to S - * logical and result with memory [PC+1] + 1 - ***************************************************************/ -#define SSH \ - S = A & X; \ - tmp = S & (EAH+1) -#if 0 -#define SSH \ - tmp = S = A & X; \ - tmp &= (UINT8)(cpustate->direct->read_raw_byte((PCW + 1) & 0xffff) + 1) -#endif - -/* 6510 ******************************************************** - * SXH store index X high - * logical and index X with memory[PC+1] and store the result - ***************************************************************/ -#define SXH tmp = X & (EAH+1) - -/* 6510 ******************************************************** - * SYH store index Y and (high + 1) - * logical and index Y with memory[PC+1] + 1 and store the result - ***************************************************************/ -#define SYH tmp = Y & (EAH+1) - -/* 6510 ******************************************************** - * TOP triple no operation - ***************************************************************/ -#define TOP \ - PCW+=2 - -/* 6510 ******************************************************** - * KIL Illegal opcode - * processor halted: no hardware interrupt will help, - * only reset - ***************************************************************/ -#define KIL \ - PCW--; \ - logerror("M6510 KILL opcode %04x: %02x\n", \ - PCW, cpustate->direct->read_decrypted_byte(PCW)) - -/* N2A03 ******************************************************* - * ARR logical and, rotate right - no decimal mode - ***************************************************************/ -#define ARR_NES \ - { \ - tmp &= A; \ - ROR; \ - P &=~(F_V|F_C); \ - if( tmp & 0x40 ) \ - P|=F_C; \ - if( (tmp & 0x60) == 0x20 || (tmp & 0x60) == 0x40 ) \ - P|=F_V; \ - } - -/* N2A03 ******************************************************* - * ISB increment and subtract with carry - ***************************************************************/ -#define ISB_NES \ - tmp = (UINT8)(tmp+1); \ - SBC_NES - -/* N2A03 ******************************************************* - * RRA rotate right and add with carry - * C -> [7][6][5][4][3][2][1][0] -> C - ***************************************************************/ -#define RRA_NES \ - tmp |= (P & F_C) << 8; \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)(tmp >> 1); \ - ADC_NES - -/* N2A03 ******************************************************* - * OAL load accumulator and index X - ***************************************************************/ -#define OAL_NES \ - A = X = (UINT8)((A|0xff)&tmp); \ - SET_NZ(A) - -/* N2A03 ******************************************************* - * SXH store index X high - * logical and index X with memory[PC+1] and store the result - * - * This instruction writes to an odd address when crossing - * a page boundary. The one known test case can be explained - * with a shift of Y. More testing will be needed to determine - * if this is correct. - * - ***************************************************************/ -#define SXH_NES \ - if ( Y && Y > EAL ) \ - EAH |= ( Y << 1 ); \ - tmp = X & (EAH+1) - -/* N2A03 ******************************************************* - * SYH store index Y and (high + 1) - * logical and index Y with memory[PC+1] + 1 and store the result - * - * This instruction writs to an odd address when crossing a - * a page boundary. The one known test case can be explained - * with a shoft of X. More testing will be needed to determine - * if this is correct. - * - ***************************************************************/ -#define SYH_NES \ - if ( X && X > EAL ) \ - EAH |= ( X << 1 ); \ - tmp = Y & (EAH+1) - -#endif /* __ILL02_H__ */ diff --git a/src/emu/cpu/m6502/m4510.c b/src/emu/cpu/m6502/m4510.c index aef6c8a8196..390422c5679 100644 --- a/src/emu/cpu/m6502/m4510.c +++ b/src/emu/cpu/m6502/m4510.c @@ -1,544 +1,117 @@ -/***************************************************************************** - * - * m4510.c - * Portable 4510 emulator V1.0beta1 - * - * Copyright Peter Trauner, all rights reserved - * documentation preliminary databook - * documentation by michael steil mist@c64.org - * available at ftp://ftp.funet.fi/pub/cbm/c65 - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ +/*************************************************************************** -/* - c65 memory management - (reset) - c64 ff - c65 20 (interface) + m4510.c -a (c65 mode) - a:00 x:e3 y:00 z:b3 - c65 64 (interface) - c64 ff + 65ce02 with a mmu and a cia integrated -b (c65 dosmode?) - c65 65 (interface, full colorram) - a:00 x:11 y:80 z:31 - c64 ff +**************************************************************************** -c (?) - c64 07 - a:00 x:00 y:00 z:00 + Copyright Olivier Galibert + All rights reserved. - a c65 mode + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: - diskcontroller accesses + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. - monitor - c64 ff - a:a0 x:82 y:00 z:83 - - c64 mode - c65 0 - c65 2f:0 ! - c64 ff - a:00 x:00 y:00 z:00 - -internal 8 mb to 64k switching (jmp routine in rom) -( seams to be incomplete, in chapter 1 1megabyte memory mapper ) - a x y z -g 0 00 e0 00 f0 -g 10000 00 e1 00 f1 -g 20000 00 e2 00 f2 -g 30000 00 e3 00 f3 -g 40000 00 e4 00 f4 -g 50000 00 e5 00 f5 -g 60000 00 e6 00 f6 -. -. -g f0000 00 ef 00 ff -the same for 100000 .. 700000 -g 800000 00 e3 00 b3 - -thesis: -a: ?0?0 0000 - ? ? only in monitor mode set -x: xxxx address bits a19 .. a16 for memory accesses with a15 0 ? - 0000 c64 mode - 0001 dosmode - 1110 c65 mode, plain ram access - (0000-1fff contains the switching code, so not switchable!?) - 1000 monitor - 1 map 6000-7fff - 1 map 4000-5fff - 1 map 2000-3fff - 1 map 0000-1fff -y: ?000 0000 - ? only in dos mode set -z: xxxx address bits a19 .. a16 for memory accesses with a15 1 ? - 0000 c64 mode - 0011 dosmode - 1000 monitor - 1011 c65 mode - 1111 plain ram access - 1 map e000-ffff - 1 map c000-dfff - 1 map a000-bfff - 1 map 8000-9fff - */ +***************************************************************************/ #include "emu.h" -#include "debugger.h" -#include "m6502.h" #include "m4510.h" -#include "minc4510.h" -#include "opsce02.h" -#include "ops4510.h" +const device_type M4510 = &device_creator; -#define M6502_NMI_VEC 0xfffa -#define M6502_RST_VEC 0xfffc -#define M6502_IRQ_VEC 0xfffe -#define M4510_RST_VEC M6502_RST_VEC -#define M4510_IRQ_VEC M6502_IRQ_VEC -#define M4510_NMI_VEC M6502_NMI_VEC - -#define VERBOSE 0 - -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) - -struct m4510_Regs { - void (*const *insn)(m4510_Regs *); /* pointer to the function pointer table */ - PAIR ppc; /* previous program counter */ - PAIR pc; /* program counter */ - PAIR sp; /* stack pointer (always 100 - 1FF) */ - PAIR zp; /* zero page address */ - /* contains B register zp.b.h */ - PAIR ea; /* effective address */ - UINT8 a; /* Accumulator */ - UINT8 x; /* X index register */ - UINT8 y; /* Y index register */ - UINT8 z; /* Z index register */ - UINT8 p; /* Processor status */ - UINT8 interrupt_inhibit; /* Some instructions, like MAP, inhibit interrupt */ - UINT8 pending_irq; /* nonzero if an IRQ is pending */ - UINT8 after_cli; /* pending IRQ and last insn cleared I */ - UINT8 nmi_state; - UINT8 irq_state; - UINT16 low, high; - UINT32 mem[8]; - - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *space; - direct_read_data *direct; - int icount; - - devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ - devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ - - UINT8 ddr; - UINT8 port; - - devcb_resolved_read8 in_port_func; - devcb_resolved_write8 out_port_func; -}; - -INLINE m4510_Regs *get_safe_token(device_t *device) +m4510_device::m4510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m65ce02_device(mconfig, M4510, "M4510", tag, owner, clock) { - assert(device != NULL); - assert(device->type() == M4510); - return (m4510_Regs *)downcast(device)->token(); + program_config.m_addrbus_width = 20; + program_config.m_logaddr_width = 16; + program_config.m_page_shift = 13; } -/*************************************************************** - * include the opcode macros, functions and tables - ***************************************************************/ - -INLINE int m4510_cpu_readop(m4510_Regs *cpustate) +offs_t m4510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - register UINT16 t=cpustate->pc.w.l++; - return cpustate->direct->read_decrypted_byte(M4510_MEM(t)); + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); } -INLINE int m4510_cpu_readop_arg(m4510_Regs *cpustate) +void m4510_device::device_start() { - register UINT16 t=cpustate->pc.w.l++; - return cpustate->direct->read_raw_byte(M4510_MEM(t)); -} - -#define M4510 -#include "t65ce02.c" - -static CPU_INIT( m4510 ) -{ - m4510_Regs *cpustate = get_safe_token(device); - const m6502_interface *intf = (const m6502_interface *)device->static_config(); - - cpustate->interrupt_inhibit = 0; - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->space = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->space->direct(); - - if ( intf ) - { - cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); - cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); - cpustate->in_port_func.resolve(intf->in_port_func, *device); - cpustate->out_port_func.resolve(intf->out_port_func, *device); - } + if(direct_disabled) + mintf = new mi_4510_nd(this); else - { - devcb_read8 nullrcb = DEVCB_NULL; - devcb_write8 nullwcb = DEVCB_NULL; + mintf = new mi_4510_normal(this); - cpustate->rdmem_id.resolve(nullrcb, *device); - cpustate->wrmem_id.resolve(nullwcb, *device); - cpustate->in_port_func.resolve(nullrcb, *device); - cpustate->out_port_func.resolve(nullwcb, *device); - } + m65ce02_device::device_start(); + + save_item(NAME(map_offset)); + save_item(NAME(map_enable)); } -static CPU_RESET( m4510 ) +void m4510_device::device_reset() { - m4510_Regs *cpustate = get_safe_token(device); - - cpustate->insn = insn4510; - - /* wipe out the rest of the m65ce02 structure */ - /* read the reset vector into PC */ - /* reset z index and b bank */ - PCL = RDMEM(M4510_RST_VEC); - PCH = RDMEM(M4510_RST_VEC+1); - - /* after reset in 6502 compatibility mode */ - cpustate->sp.d = 0x01ff; /* high byte descriped in databook */ - cpustate->z = 0; - B = 0; - cpustate->p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */ - cpustate->interrupt_inhibit = 0; - cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ - cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ - cpustate->irq_callback = NULL; - - /* don't know */ - cpustate->high=0x8200; - cpustate->mem[7]=0x20000; - - cpustate->port = 0xff; - cpustate->ddr = 0x00; + map_offset[0] = map_offset[1] = 0; + map_enable = 0; + nomap = true; } -static CPU_EXIT( m4510 ) +m4510_device::mi_4510_normal::mi_4510_normal(m4510_device *_base) { - /* nothing to do yet */ + base = _base; } -INLINE void m4510_take_irq(m4510_Regs *cpustate) +UINT8 m4510_device::mi_4510_normal::read(UINT16 adr) { - if(( !(P & F_I) ) && (cpustate->interrupt_inhibit == 0)) - { - EAD = M4510_IRQ_VEC; - cpustate->icount -= 7; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P = (P & ~F_D) | F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M4510 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD)); - /* call back the cpuintrf to let it clear the line */ - if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); - } - cpustate->pending_irq = 0; + return program->read_byte(base->map(adr)); } -static CPU_EXECUTE( m4510 ) +UINT8 m4510_device::mi_4510_normal::read_direct(UINT16 adr) { - m4510_Regs *cpustate = get_safe_token(device); - - do - { - UINT8 op; - PPC = PCD; - - debugger_instruction_hook(device, PCD); - - /* if an irq is pending, take it now */ - if( cpustate->pending_irq ) - m4510_take_irq(cpustate); - - op = RDOP(); - (*insn4510[op])(cpustate); - - /* check if the I flag was just reset (interrupts enabled) */ - if( cpustate->after_cli ) - { - LOG(("M4510 '%s' after_cli was >0", cpustate->device->tag())); - cpustate->after_cli = 0; - if (cpustate->irq_state != CLEAR_LINE) - { - LOG((": irq line is asserted: set pending IRQ\n")); - cpustate->pending_irq = 1; - } - else - { - LOG((": irq line is clear\n")); - } - } - else - if( cpustate->pending_irq ) - m4510_take_irq(cpustate); - - } while (cpustate->icount > 0); + return direct->read_raw_byte(base->map(adr)); } -static void m4510_set_irq_line(m4510_Regs *cpustate, int irqline, int state) +UINT8 m4510_device::mi_4510_normal::read_decrypted(UINT16 adr) { - if (irqline == INPUT_LINE_NMI) - { - if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; - if( state != CLEAR_LINE ) - { - LOG(("M4510 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag())); - EAD = M4510_NMI_VEC; - cpustate->icount -= 7; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P = (P & ~F_D) | F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M4510 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD)); - } - } - else - { - cpustate->irq_state = state; - if( state != CLEAR_LINE ) - { - LOG(("M4510 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag())); - cpustate->pending_irq = 1; - } - } + return direct->read_decrypted_byte(base->map(adr)); } -UINT8 m4510_get_port(legacy_cpu_device *device) +void m4510_device::mi_4510_normal::write(UINT16 adr, UINT8 val) { - m4510_Regs *cpustate = get_safe_token(device); - return (cpustate->port & cpustate->ddr) | (cpustate->ddr ^ 0xff); + program->write_byte(base->map(adr), val); } -static READ8_HANDLER( m4510_read_0000 ) + +m4510_device::mi_4510_nd::mi_4510_nd(m4510_device *_base) : mi_4510_normal(_base) { - UINT8 result = 0x00; - m4510_Regs *cpustate = get_safe_token(&space.device()); - - switch(offset) - { - case 0x0000: /* DDR */ - result = cpustate->ddr; - break; - case 0x0001: /* Data Port */ - result = cpustate->in_port_func(0); - result = (cpustate->ddr & cpustate->port) | (~cpustate->ddr & result); - break; - } - return result; } -static WRITE8_HANDLER( m4510_write_0000 ) +UINT8 m4510_device::mi_4510_nd::read_direct(UINT16 adr) { - m4510_Regs *cpustate = get_safe_token(&space.device()); - - switch(offset) - { - case 0x0000: /* DDR */ - cpustate->ddr = data; - break; - case 0x0001: /* Data Port */ - cpustate->port = data; - break; - } - - cpustate->out_port_func(0, m4510_get_port(downcast(&space.device()))); + return read(adr); } -static ADDRESS_MAP_START(m4510_mem, AS_PROGRAM, 8, legacy_cpu_device) - AM_RANGE(0x0000, 0x0001) AM_READWRITE_LEGACY(m4510_read_0000, m4510_write_0000) -ADDRESS_MAP_END - -static CPU_TRANSLATE( m4510 ) +UINT8 m4510_device::mi_4510_nd::read_decrypted(UINT16 adr) { - m4510_Regs *cpustate = get_safe_token(device); - - if (space == AS_PROGRAM) - *address = M4510_MEM(*address); - return TRUE; + return read(adr); } -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( m4510 ) -{ - m4510_Regs *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: m4510_set_irq_line(cpustate, M4510_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m4510_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - - case CPUINFO_INT_PC: PCW = info->i; break; - case CPUINFO_INT_REGISTER + M4510_PC: cpustate->pc.w.l = info->i; break; - case CPUINFO_INT_SP: SPL = info->i; break; - case CPUINFO_INT_REGISTER + M4510_S: cpustate->sp.b.l = info->i; break; - case CPUINFO_INT_REGISTER + M4510_P: cpustate->p = info->i; break; - case CPUINFO_INT_REGISTER + M4510_A: cpustate->a = info->i; break; - case CPUINFO_INT_REGISTER + M4510_X: cpustate->x = info->i; break; - case CPUINFO_INT_REGISTER + M4510_Y: cpustate->y = info->i; break; - case CPUINFO_INT_REGISTER + M4510_Z: cpustate->z = info->i; break; - case CPUINFO_INT_REGISTER + M4510_B: cpustate->zp.b.h = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM_LOW: cpustate->low = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM_HIGH: cpustate->high = info->i; break; - case CPUINFO_INT_REGISTER + M4510_EA: cpustate->ea.w.l = info->i; break; - case CPUINFO_INT_REGISTER + M4510_ZP: cpustate->zp.w.l = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM0: cpustate->mem[0] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM1: cpustate->mem[1] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM2: cpustate->mem[2] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM3: cpustate->mem[3] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM4: cpustate->mem[4] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM5: cpustate->mem[5] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM6: cpustate->mem[6] = info->i; break; - case CPUINFO_INT_REGISTER + M4510_MEM7: cpustate->mem[7] = info->i; break; - } -} - - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( m4510 ) -{ - m4510_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m4510_Regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 10; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 16; break; - case CPUINFO_INT_PAGE_SHIFT_PROGRAM: info->i = 13; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: info->i = cpustate->irq_state; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc.w.l; break; - - case CPUINFO_INT_PC: info->i = PCD; break; - case CPUINFO_INT_REGISTER + M4510_PC: info->i = cpustate->pc.w.l; break; - case CPUINFO_INT_SP: info->i = SPL; break; - case CPUINFO_INT_REGISTER + M4510_S: info->i = cpustate->sp.b.l; break; - case CPUINFO_INT_REGISTER + M4510_P: info->i = cpustate->p; break; - case CPUINFO_INT_REGISTER + M4510_A: info->i = cpustate->a; break; - case CPUINFO_INT_REGISTER + M4510_X: info->i = cpustate->x; break; - case CPUINFO_INT_REGISTER + M4510_Y: info->i = cpustate->y; break; - case CPUINFO_INT_REGISTER + M4510_Z: info->i = cpustate->z; break; - case CPUINFO_INT_REGISTER + M4510_B: info->i = cpustate->zp.b.h; break; - case CPUINFO_INT_REGISTER + M4510_MEM_LOW: info->i = cpustate->low; break; - case CPUINFO_INT_REGISTER + M4510_MEM_HIGH: info->i = cpustate->high; break; - case CPUINFO_INT_REGISTER + M4510_EA: info->i = cpustate->ea.w.l; break; - case CPUINFO_INT_REGISTER + M4510_ZP: info->i = cpustate->zp.w.l; break; - case CPUINFO_INT_REGISTER + M4510_MEM0: info->i = cpustate->mem[0]; break; - case CPUINFO_INT_REGISTER + M4510_MEM1: info->i = cpustate->mem[1]; break; - case CPUINFO_INT_REGISTER + M4510_MEM2: info->i = cpustate->mem[2]; break; - case CPUINFO_INT_REGISTER + M4510_MEM3: info->i = cpustate->mem[3]; break; - case CPUINFO_INT_REGISTER + M4510_MEM4: info->i = cpustate->mem[4]; break; - case CPUINFO_INT_REGISTER + M4510_MEM5: info->i = cpustate->mem[5]; break; - case CPUINFO_INT_REGISTER + M4510_MEM6: info->i = cpustate->mem[6]; break; - case CPUINFO_INT_REGISTER + M4510_MEM7: info->i = cpustate->mem[7]; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m4510); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m4510); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m4510); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m4510); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m4510); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m4510); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(m4510_mem); break; - case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(m4510); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M4510"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "CBM Semiconductor Group CSG 65CE02"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0beta"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller\nCopyright Peter Trauner\nall rights reserved."); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - cpustate->p & 0x80 ? 'N':'.', - cpustate->p & 0x40 ? 'V':'.', - cpustate->p & 0x20 ? 'R':'.', - cpustate->p & 0x10 ? 'B':'.', - cpustate->p & 0x08 ? 'D':'.', - cpustate->p & 0x04 ? 'I':'.', - cpustate->p & 0x02 ? 'Z':'.', - cpustate->p & 0x01 ? 'C':'.'); - break; - - case CPUINFO_STR_REGISTER + M4510_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break; - case CPUINFO_STR_REGISTER + M4510_S: sprintf(info->s, "S:%02X", cpustate->sp.b.l); break; - case CPUINFO_STR_REGISTER + M4510_P: sprintf(info->s, "P:%02X", cpustate->p); break; - case CPUINFO_STR_REGISTER + M4510_A: sprintf(info->s, "A:%02X", cpustate->a); break; - case CPUINFO_STR_REGISTER + M4510_X: sprintf(info->s, "X:%02X", cpustate->x); break; - case CPUINFO_STR_REGISTER + M4510_Y: sprintf(info->s, "Y:%02X", cpustate->y); break; - case CPUINFO_STR_REGISTER + M4510_Z: sprintf(info->s, "Z:%02X", cpustate->z); break; - case CPUINFO_STR_REGISTER + M4510_B: sprintf(info->s, "B:%02X", cpustate->zp.b.h); break; - case CPUINFO_STR_REGISTER + M4510_MEM_LOW: sprintf(info->s, "M0:%01X", cpustate->low); break; - case CPUINFO_STR_REGISTER + M4510_MEM_HIGH: sprintf(info->s, "M1:%01X", cpustate->high); break; - case CPUINFO_STR_REGISTER + M4510_EA: sprintf(info->s, "EA:%04X", cpustate->ea.w.l); break; - case CPUINFO_STR_REGISTER + M4510_ZP: sprintf(info->s, "ZP:%03X", cpustate->zp.w.l); break; - } -} - -#undef M4510 -DEFINE_LEGACY_CPU_DEVICE(M4510, m4510); +#include "cpu/m6502/m4510.inc" diff --git a/src/emu/cpu/m6502/m4510.h b/src/emu/cpu/m6502/m4510.h index e896a9bf5b3..46aa2b8a593 100644 --- a/src/emu/cpu/m6502/m4510.h +++ b/src/emu/cpu/m6502/m4510.h @@ -1,49 +1,108 @@ -/***************************************************************************** - * - * m4510.c - * Portable 4510 emulator V1.0beta - * - * Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ +/*************************************************************************** -#pragma once + m4510.h + + 65ce02 with a mmu and a port + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ #ifndef __M4510_H__ #define __M4510_H__ -#include "m6502.h" +#include "m65ce02.h" +class m4510_device : public m65ce02_device { +public: + m4510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); -enum -{ - M4510_PC=1, M4510_S, M4510_P, M4510_A, M4510_X, M4510_Y, - M4510_Z, M4510_B, M4510_EA, M4510_ZP, - M4510_NMI_STATE, M4510_IRQ_STATE, - M4510_MEM_LOW,M4510_MEM_HIGH, - M4510_MEM0, M4510_MEM1, M4510_MEM2, M4510_MEM3, - M4510_MEM4, M4510_MEM5, M4510_MEM6, M4510_MEM7 + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + + bool get_nomap() const { return nomap; } + +protected: + UINT32 map_offset[2]; + UINT8 map_enable; + bool nomap; + + class mi_4510_normal : public memory_interface { + public: + m4510_device *base; + + mi_4510_normal(m4510_device *base); + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + }; + + class mi_4510_nd : public mi_4510_normal { + public: + mi_4510_nd(m4510_device *base); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + }; + + virtual void device_start(); + virtual void device_reset(); + + inline UINT32 map(UINT16 adr) { + if(map_enable & (1 << (adr >> 13))) { + nomap = false; + return adr + map_offset[adr >> 15]; + } + nomap = true; + return adr; + } + +#define O(o) void o ## _full(); void o ## _partial() + + // 4510 opcodes + O(eom_imp); + O(map_imp); + +#undef O }; -#define M4510_IRQ_LINE M6502_IRQ_LINE +enum { + M4510_IRQ_LINE = m6502_device::IRQ_LINE, + M4510_NMI_LINE = m6502_device::NMI_LINE, +}; -DECLARE_LEGACY_CPU_DEVICE(M4510, m4510); +extern const device_type M4510; - -extern CPU_DISASSEMBLE( m4510 ); - -UINT8 m4510_get_port(legacy_cpu_device *device); - -#endif /* __M4510_H__ */ +#endif diff --git a/src/emu/cpu/m6502/m6502.c b/src/emu/cpu/m6502/m6502.c index d7dd22e8d5d..aa158940f90 100644 --- a/src/emu/cpu/m6502/m6502.c +++ b/src/emu/cpu/m6502/m6502.c @@ -1,1022 +1,688 @@ -/***************************************************************************** - * - * m6502.c - * Portable 6502/65c02/65sc02/6510/n2a03 emulator V1.2 - * - * Copyright Juergen Buchmueller, all rights reserved. - * 65sc02 core Copyright Peter Trauner. - * Deco16 portions Copyright Bryan McPhail. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ -/* 2.February 2000 PeT added 65sc02 subtype */ -/* 10.March 2000 PeT added 6502 set overflow input line */ -/* 13.September 2000 PeT N2A03 jmp indirect */ +/*************************************************************************** + + m6502.c + + Mostek 6502, original NMOS variant + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ #include "emu.h" #include "debugger.h" #include "m6502.h" -#include "ops02.h" -#include "ill02.h" +const device_type M6502 = &device_creator; -#define M6502_NMI_VEC 0xfffa -#define M6502_RST_VEC 0xfffc -#define M6502_IRQ_VEC 0xfffe - -#define DECO16_RST_VEC 0xfff0 -#define DECO16_IRQ_VEC 0xfff2 -#define DECO16_NMI_VEC 0xfff4 - -#define VERBOSE 0 - -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) - - - -/**************************************************************************** - * The 6502 registers. - ****************************************************************************/ -struct m6502_Regs +m6502_device::m6502_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + cpu_device(mconfig, M6502, "M6502", tag, owner, clock), + program_config("program", ENDIANNESS_LITTLE, 8, 16) { - UINT8 subtype; /* currently selected cpu sub type */ - void (*const *insn)(m6502_Regs *); /* pointer to the function pointer table */ - PAIR ppc; /* previous program counter */ - PAIR pc; /* program counter */ - PAIR sp; /* stack pointer (always 100 - 1FF) */ - PAIR zp; /* zero page address */ - PAIR ea; /* effective address */ - UINT8 a; /* Accumulator */ - UINT8 x; /* X index register */ - UINT8 y; /* Y index register */ - UINT8 p; /* Processor status */ - UINT8 pending_irq; /* nonzero if an IRQ is pending */ - UINT8 after_cli; /* pending IRQ and last insn cleared I */ - UINT8 nmi_state; - UINT8 irq_state; - UINT8 so_state; - - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *space; - direct_read_data *direct; - address_space *io; - int int_occured; - int icount; - - devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ - devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ - - UINT8 ddr; - UINT8 port; - UINT8 mask; - UINT8 pullup; - UINT8 pulldown; - - devcb_resolved_read8 in_port_func; - devcb_resolved_write8 out_port_func; -}; - -INLINE m6502_Regs *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == M6502 || - device->type() == M6504 || - device->type() == M6510 || - device->type() == M6510T || - device->type() == M7501 || - device->type() == M8502 || - device->type() == N2A03 || - device->type() == M65C02 || - device->type() == M65SC02 || - device->type() == DECO16); - return (m6502_Regs *)downcast(device)->token(); + direct_disabled = false; } -/*************************************************************** - * include the opcode macros, functions and tables - ***************************************************************/ -#include "t6502.c" - -#include "t6510.c" - -#include "opsn2a03.h" - -#include "tn2a03.c" - -#include "opsc02.h" - -#include "t65c02.c" - -#include "t65sc02.c" - -#include "tdeco16.c" - -/***************************************************************************** - * - * 6502 CPU interface functions - * - *****************************************************************************/ - -static void m6502_common_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, UINT8 subtype, void (*const *insn)(m6502_Regs *cpustate), const char *type) +m6502_device::m6502_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : + cpu_device(mconfig, type, name, tag, owner, clock), + program_config("program", ENDIANNESS_LITTLE, 8, 16) { - m6502_Regs *cpustate = get_safe_token(device); - const m6502_interface *intf = (const m6502_interface *)device->static_config(); + direct_disabled = false; +} - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->space = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->space->direct(); - cpustate->subtype = subtype; - cpustate->insn = insn; - - if ( intf ) - { - cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); - cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); - cpustate->in_port_func.resolve(intf->in_port_func, *device); - cpustate->out_port_func.resolve(intf->out_port_func, *device); - - cpustate->pullup = intf->external_port_pullup; - cpustate->pulldown = intf->external_port_pulldown; - } +void m6502_device::device_start() +{ + if(direct_disabled) + mintf = new mi_default_nd; else - { - devcb_read8 nullrcb = DEVCB_NULL; - devcb_write8 nullwcb = DEVCB_NULL; + mintf = new mi_default_normal; - cpustate->rdmem_id.resolve(nullrcb, *device); - cpustate->wrmem_id.resolve(nullwcb, *device); - cpustate->in_port_func.resolve(nullrcb, *device); - cpustate->out_port_func.resolve(nullwcb, *device); - - cpustate->pullup = 0; - cpustate->pulldown = 0; - } - - device->save_item(NAME(cpustate->pc.w.l)); - device->save_item(NAME(cpustate->sp.w.l)); - device->save_item(NAME(cpustate->p)); - device->save_item(NAME(cpustate->a)); - device->save_item(NAME(cpustate->x)); - device->save_item(NAME(cpustate->y)); - device->save_item(NAME(cpustate->pending_irq)); - device->save_item(NAME(cpustate->after_cli)); - device->save_item(NAME(cpustate->nmi_state)); - device->save_item(NAME(cpustate->irq_state)); - device->save_item(NAME(cpustate->so_state)); - - if (subtype == SUBTYPE_6510) - { - device->save_item(NAME(cpustate->port)); - device->save_item(NAME(cpustate->mask)); - device->save_item(NAME(cpustate->ddr)); - device->save_item(NAME(cpustate->pullup)); - device->save_item(NAME(cpustate->pulldown)); - } + init(); } -static CPU_INIT( m6502 ) +void m6502_device::init() { - m6502_common_init(device, irqcallback, SUBTYPE_6502, insn6502, "m6502"); + mintf->program = &space(AS_PROGRAM); + mintf->direct = &mintf->program->direct(); + + state_add(STATE_GENPC, "GENPC", NPC).noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", PPC).noshow(); + state_add(STATE_GENSP, "GENSP", SP).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", P).callimport().formatstr("%6s").noshow(); + state_add(M6502_PC, "PC", NPC); + state_add(M6502_A, "A", A); + state_add(M6502_X, "X", X); + state_add(M6502_Y, "Y", Y); + state_add(M6502_P, "P", P).callimport(); + state_add(M6502_S, "SP", SP); + state_add(M6502_IR, "IR", IR); + + save_item(NAME(PC)); + save_item(NAME(NPC)); + save_item(NAME(A)); + save_item(NAME(X)); + save_item(NAME(Y)); + save_item(NAME(P)); + save_item(NAME(SP)); + save_item(NAME(TMP)); + save_item(NAME(TMP2)); + save_item(NAME(IR)); + save_item(NAME(nmi_state)); + save_item(NAME(irq_state)); + save_item(NAME(v_state)); + save_item(NAME(inst_state)); + save_item(NAME(inst_substate)); + save_item(NAME(irq_taken)); + save_item(NAME(inhibit_interrupts)); + + m_icountptr = &icount; + + PC = 0x0000; + NPC = 0x0000; + A = 0x00; + X = 0x80; + Y = 0x00; + P = 0x36; + SP = 0x01bd; + TMP = 0x0000; + TMP2 = 0x00; + IR = 0x00; + nmi_state = false; + irq_state = false; + irq_taken = false; + v_state = false; + inst_state = STATE_RESET; + inst_substate = 0; + sync = false; + end_cycles = 0; } -static CPU_RESET( m6502 ) +void m6502_device::device_reset() { - m6502_Regs *cpustate = get_safe_token(device); - /* wipe out the rest of the m6502 structure */ - /* read the reset vector into PC */ - PCL = RDMEM(M6502_RST_VEC); - PCH = RDMEM(M6502_RST_VEC+1); - - cpustate->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */ - cpustate->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */ - cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ - cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ - cpustate->irq_state = 0; - cpustate->nmi_state = 0; + inst_state = STATE_RESET; + inst_substate = 0; + nmi_state = false; + irq_state = false; + irq_taken = false; + v_state = false; + end_cycles = 0; + sync = false; + inhibit_interrupts = false; } -static CPU_EXIT( m6502 ) + +UINT32 m6502_device::execute_min_cycles() const { - /* nothing to do yet */ + return 1; } -INLINE void m6502_take_irq(m6502_Regs *cpustate) +UINT32 m6502_device::execute_max_cycles() const { - if( !(P & F_I) ) - { - EAD = M6502_IRQ_VEC; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P |= F_I; /* set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M6502 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD)); - /* call back the cpuintrf to let it clear the line */ - if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); - } - cpustate->pending_irq = 0; + return 10; } -static CPU_EXECUTE( m6502 ) +UINT32 m6502_device::execute_input_lines() const { - m6502_Regs *cpustate = get_safe_token(device); - - do - { - UINT8 op; - PPC = PCD; - - debugger_instruction_hook(device, PCD); - - /* if an irq is pending, take it now */ - if( cpustate->pending_irq ) - m6502_take_irq(cpustate); - - op = RDOP(); - (*cpustate->insn[op])(cpustate); - - /* check if the I flag was just reset (interrupts enabled) */ - if( cpustate->after_cli ) - { - LOG(("M6502 '%s' after_cli was >0", cpustate->device->tag())); - cpustate->after_cli = 0; - if (cpustate->irq_state != CLEAR_LINE) - { - LOG((": irq line is asserted: set pending IRQ\n")); - cpustate->pending_irq = 1; - } - else - { - LOG((": irq line is clear\n")); - } - } - else { - if ( cpustate->pending_irq == 2 ) { - if ( cpustate->int_occured - cpustate->icount > 1 ) { - cpustate->pending_irq = 1; - } - } - if( cpustate->pending_irq == 1 ) - m6502_take_irq(cpustate); - if ( cpustate->pending_irq == 2 ) { - cpustate->pending_irq = 1; - } - } - - } while (cpustate->icount > 0); + return 3; } -static void m6502_set_irq_line(m6502_Regs *cpustate, int irqline, int state) +void m6502_device::do_adc_d(UINT8 val) { - if (irqline == INPUT_LINE_NMI) - { - if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6502 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag())); - EAD = M6502_NMI_VEC; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P |= F_I; /* set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M6502 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD)); - } - } + UINT8 c = P & F_C ? 1 : 0; + P &= ~(F_N|F_V|F_Z|F_C); + UINT8 al = (A & 15) + (val & 15) + c; + if(al > 9) + al += 6; + UINT8 ah = (A >> 4) + (val >> 4) + (al > 15); + if(!UINT8(A + val + c)) + P |= F_Z; + else if(ah & 8) + P |= F_N; + if(~(A^val) & (A^(ah << 4)) & 0x80) + P |= F_V; + if(ah > 9) + ah += 6; + if(ah > 15) + P |= F_C; + A = (ah << 4) | (al & 15); +} + +void m6502_device::do_adc_nd(UINT8 val) +{ + UINT16 sum; + sum = A + val + (P & F_C ? 1 : 0); + P &= ~(F_N|F_V|F_Z|F_C); + if(!UINT8(sum)) + P |= F_Z; + else if(INT8(sum) < 0) + P |= F_N; + if(~(A^val) & (A^sum) & 0x80) + P |= F_V; + if(sum & 0xff00) + P |= F_C; + A = sum; +} + +void m6502_device::do_adc(UINT8 val) +{ + if(P & F_D) + do_adc_d(val); else - { - if( irqline == M6502_SET_OVERFLOW ) - { - if( cpustate->so_state && !state ) - { - LOG(( "M6502 '%s' set overflow\n", cpustate->device->tag())); - P|=F_V; - } - cpustate->so_state=state; - return; - } - cpustate->irq_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6502 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag())); - cpustate->pending_irq = 1; -// cpustate->pending_irq = 2; - cpustate->int_occured = cpustate->icount; - } + do_adc_nd(val); +} + +void m6502_device::do_arr_nd() +{ + bool c = P & F_C; + P &= ~(F_N|F_Z|F_C|F_V); + A >>= 1; + if(c) + A |= 0x80; + if(!A) + P |= F_Z; + else if(INT8(A)<0) + P |= F_N; + if(A & 0x40) + P |= F_V|F_C; + if(A & 0x20) + P ^= F_V; +} + +void m6502_device::do_arr_d() +{ + // The adc/ror interaction gives an extremely weird result + bool c = P & F_C; + P &= ~(F_N|F_Z|F_C|F_V); + UINT8 a = A >> 1; + if(c) + a |= 0x80; + if(!a) + P |= F_Z; + else if(INT8(a) < 0) + P |= F_N; + if((a ^ A) & 0x40) + P |= F_V; + + if((A & 0x0f) >= 0x05) + a = ((a + 6) & 0x0f) | (a & 0xf0); + + if((A & 0xf0) >= 0x50) { + a += 0x60; + P |= F_C; } + A = a; } - - -/**************************************************************************** - * 2A03 section - ****************************************************************************/ - -static CPU_INIT( n2a03 ) +void m6502_device::do_arr() { - m6502_common_init(device, irqcallback, SUBTYPE_2A03, insn2a03, "n2a03"); -} - -/* The N2A03 is integrally tied to its PSG (they're on the same die). - Bit 7 of address $4011 (the PSG's DPCM control register), when set, - causes an IRQ to be generated. This function allows the IRQ to be called - from the PSG core when such an occasion arises. */ -void n2a03_irq(device_t *device) -{ - m6502_Regs *cpustate = get_safe_token(device); - - m6502_take_irq(cpustate); -} - - -/**************************************************************************** - * 6510 section - ****************************************************************************/ - -static CPU_INIT( m6510 ) -{ - m6502_common_init(device, irqcallback, SUBTYPE_6510, insn6510, "m6510"); -} - -static CPU_RESET( m6510 ) -{ - m6502_Regs *cpustate = get_safe_token(device); - - CPU_RESET_CALL(m6502); - cpustate->port = 0xff; - cpustate->mask = 0xff; - cpustate->ddr = 0x00; -} - -UINT8 m6510_get_port(legacy_cpu_device *device) -{ - m6502_Regs *cpustate = get_safe_token(device); - return (cpustate->port & cpustate->ddr) | (cpustate->ddr ^ 0xff); -} - -static READ8_HANDLER( m6510_read_0000 ) -{ - m6502_Regs *cpustate = get_safe_token(&space.device()); - UINT8 result = 0x00; - - switch(offset) - { - case 0x0000: /* DDR */ - result = cpustate->ddr; - break; - - case 0x0001: /* Data Port */ - { - UINT8 input = cpustate->in_port_func(0) & ~cpustate->ddr; - UINT8 mask = cpustate->mask & ~cpustate->ddr; - UINT8 output = cpustate->port & cpustate->ddr; - UINT8 pulldown = ~(cpustate->pulldown & ~cpustate->ddr); - - result = (input | mask | output) & (input | pulldown); - } - break; - } - - return result; -} - -static WRITE8_HANDLER( m6510_write_0000 ) -{ - m6502_Regs *cpustate = get_safe_token(&space.device()); - - switch(offset) - { - case 0x0000: /* DDR */ - if (cpustate->ddr != data) - { - cpustate->ddr = data; - cpustate->mask = cpustate->port; - } - break; - - case 0x0001: /* Data Port */ - cpustate->port = data; - break; - } - - UINT8 output = (cpustate->port & cpustate->ddr) | (cpustate->pullup & ~cpustate->ddr); - - cpustate->out_port_func(0, output); - - // TODO assert write with floating data lines - //WRMEM(offset, 0xff); -} - -static ADDRESS_MAP_START(m6510_mem, AS_PROGRAM, 8, legacy_cpu_device) - AM_RANGE(0x0000, 0x0001) AM_READWRITE_LEGACY(m6510_read_0000, m6510_write_0000) -ADDRESS_MAP_END - - - -/**************************************************************************** - * 65C02 section - ****************************************************************************/ - -static CPU_INIT( m65c02 ) -{ - m6502_common_init(device, irqcallback, SUBTYPE_65C02, insn65c02, "m65c02"); -} - -static CPU_RESET( m65c02 ) -{ - m6502_Regs *cpustate = get_safe_token(device); - - CPU_RESET_CALL(m6502); - P &=~F_D; -} - -INLINE void m65c02_take_irq(m6502_Regs *cpustate) -{ - if( !(P & F_I) ) - { - EAD = M6502_IRQ_VEC; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P = (P & ~F_D) | F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M65c02 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD)); - /* call back the cpuintrf to let it clear the line */ - if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); - } - cpustate->pending_irq = 0; -} - -static CPU_EXECUTE( m65c02 ) -{ - m6502_Regs *cpustate = get_safe_token(device); - - do - { - UINT8 op; - PPC = PCD; - - debugger_instruction_hook(device, PCD); - - op = RDOP(); - (*cpustate->insn[op])(cpustate); - - /* if an irq is pending, take it now */ - if( cpustate->pending_irq ) - m65c02_take_irq(cpustate); - - - /* check if the I flag was just reset (interrupts enabled) */ - if( cpustate->after_cli ) - { - LOG(("M6502 '%s' after_cli was >0", cpustate->device->tag())); - cpustate->after_cli = 0; - if (cpustate->irq_state != CLEAR_LINE) - { - LOG((": irq line is asserted: set pending IRQ\n")); - cpustate->pending_irq = 1; - } - else - { - LOG((": irq line is clear\n")); - } - } - else - if( cpustate->pending_irq ) - m65c02_take_irq(cpustate); - - } while (cpustate->icount > 0); -} - -static void m65c02_set_irq_line(m6502_Regs *cpustate, int irqline, int state) -{ - if (irqline == INPUT_LINE_NMI) - { - if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6502 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag())); - EAD = M6502_NMI_VEC; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P = (P & ~F_D) | F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M6502 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD)); - } - } + if(P & F_D) + do_arr_d(); else - m6502_set_irq_line(cpustate, irqline,state); + do_arr_nd(); } -/**************************************************************************** - * 65SC02 section - ****************************************************************************/ -static CPU_INIT( m65sc02 ) +void m6502_device::do_cmp(UINT8 val1, UINT8 val2) { - m6502_common_init(device, irqcallback, SUBTYPE_65SC02, insn65sc02, "m65sc02"); + P &= ~(F_N|F_Z|F_C); + UINT16 r = val1-val2; + if(!r) + P |= F_Z; + else if(INT8(r) < 0) + P |= F_N; + if(!(r & 0xff00)) + P |= F_C; } -/**************************************************************************** - * DECO16 section - ****************************************************************************/ - -static CPU_INIT( deco16 ) +void m6502_device::do_sbc_d(UINT8 val) { - m6502_Regs *cpustate = get_safe_token(device); - m6502_common_init(device, irqcallback, SUBTYPE_DECO16, insndeco16, "deco16"); - cpustate->io = &device->space(AS_IO); + UINT8 c = P & F_C ? 0 : 1; + P &= ~(F_N|F_V|F_Z|F_C); + UINT16 diff = A - val - c; + UINT8 al = (A & 15) - (val & 15) - c; + if(INT8(al) < 0) + al -= 6; + UINT8 ah = (A >> 4) - (val >> 4) - (INT8(al) < 0); + if(!UINT8(diff)) + P |= F_Z; + else if(diff & 0x80) + P |= F_N; + if((A^val) & (A^diff) & 0x80) + P |= F_V; + if(!(diff & 0xff00)) + P |= F_C; + if(INT8(ah) < 0) + ah -= 6; + A = (ah << 4) | (al & 15); } - -static CPU_RESET( deco16 ) +void m6502_device::do_sbc_nd(UINT8 val) { - m6502_Regs *cpustate = get_safe_token(device); - - CPU_RESET_CALL(m6502); - cpustate->subtype = SUBTYPE_DECO16; - cpustate->insn = insndeco16; - - PCL = RDMEM(DECO16_RST_VEC+1); - PCH = RDMEM(DECO16_RST_VEC); - - cpustate->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */ - cpustate->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */ - cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ - cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ + UINT16 diff = A - val - (P & F_C ? 0 : 1); + P &= ~(F_N|F_V|F_Z|F_C); + if(!UINT8(diff)) + P |= F_Z; + else if(INT8(diff) < 0) + P |= F_N; + if((A^val) & (A^diff) & 0x80) + P |= F_V; + if(!(diff & 0xff00)) + P |= F_C; + A = diff; } -INLINE void deco16_take_irq(m6502_Regs *cpustate) +void m6502_device::do_sbc(UINT8 val) { - if( !(P & F_I) ) - { - EAD = DECO16_IRQ_VEC; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P |= F_I; /* set I flag */ - PCL = RDMEM(EAD+1); - PCH = RDMEM(EAD); - LOG(("M6502 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD)); - /* call back the cpuintrf to let it clear the line */ - if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); - } - cpustate->pending_irq = 0; -} - -static void deco16_set_irq_line(m6502_Regs *cpustate, int irqline, int state) -{ - if (irqline == INPUT_LINE_NMI) - { - if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6502 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag())); - EAD = DECO16_NMI_VEC; - cpustate->icount -= 7; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P |= F_I; /* set I flag */ - PCL = RDMEM(EAD+1); - PCH = RDMEM(EAD); - LOG(("M6502 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD)); - } - } + if(P & F_D) + do_sbc_d(val); else - { - if( irqline == M6502_SET_OVERFLOW ) - { - if( cpustate->so_state && !state ) - { - LOG(( "M6502 '%s' set overflow\n", cpustate->device->tag())); - P|=F_V; - } - cpustate->so_state=state; - return; - } - cpustate->irq_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6502 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag())); - cpustate->pending_irq = 1; + do_sbc_nd(val); +} + +void m6502_device::do_bit(UINT8 val) +{ + P &= ~(F_N|F_Z|F_V); + UINT8 r = A & val; + if(!r) + P |= F_Z; + if(val & 0x80) + P |= F_N; + if(val & 0x40) + P |= F_V; +} + +UINT8 m6502_device::do_asl(UINT8 v) +{ + P &= ~(F_N|F_Z|F_C); + UINT8 r = v<<1; + if(!r) + P |= F_Z; + else if(INT8(r) < 0) + P |= F_N; + if(v & 0x80) + P |= F_C; + return r; +} + +UINT8 m6502_device::do_lsr(UINT8 v) +{ + P &= ~(F_N|F_Z|F_C); + if(v & 1) + P |= F_C; + v >>= 1; + if(!v) + P |= F_Z; + return v; +} + +UINT8 m6502_device::do_ror(UINT8 v) +{ + bool c = P & F_C; + P &= ~(F_N|F_Z|F_C); + if(v & 1) + P |= F_C; + v >>= 1; + if(c) + v |= 0x80; + if(!v) + P |= F_Z; + else if(INT8(v)<0) + P |= F_N; + return v; +} + +UINT8 m6502_device::do_rol(UINT8 v) +{ + bool c = P & F_C; + P &= ~(F_N|F_Z|F_C); + if(v & 0x80) + P |= F_C; + v <<= 1; + if(c) + v |= 0x01; + if(!v) + P |= F_Z; + else if(INT8(v)<0) + P |= F_N; + return v; +} + +UINT8 m6502_device::do_asr(UINT8 v) +{ + P &= ~(F_N|F_Z|F_C); + if(v & 1) + P |= F_C; + v >>= 1; + if(!v) + P |= F_Z; + else if(v & 0x40) { + P |= F_N; + v |= 0x80; + } + return v; +} + +UINT64 m6502_device::get_cycle() +{ + return end_cycles == 0 || icount <= 0 ? machine().time().as_ticks(clock()) : end_cycles - icount; +} + +void m6502_device::execute_run() +{ + end_cycles = machine().time().as_ticks(clock()) + icount; + if(inst_substate) + do_exec_partial(); + + while(icount > 0) { + if(inst_state < 0x100) { + PPC = NPC; + inst_state = IR; + if(machine().debug_flags & DEBUG_FLAG_ENABLED) + debugger_instruction_hook(this, NPC); } + do_exec_full(); } + end_cycles = 0; } -static CPU_EXECUTE( deco16 ) +void m6502_device::execute_set_input(int inputnum, int state) { - m6502_Regs *cpustate = get_safe_token(device); - - do - { - UINT8 op; - PPC = PCD; - - debugger_instruction_hook(device, PCD); - - op = RDOP(); - (*cpustate->insn[op])(cpustate); - - /* if an irq is pending, take it now */ - if( cpustate->pending_irq ) - deco16_take_irq(cpustate); - - - /* check if the I flag was just reset (interrupts enabled) */ - if( cpustate->after_cli ) - { - LOG(("M6502 %s after_cli was >0", cpustate->device->tag())); - cpustate->after_cli = 0; - if (cpustate->irq_state != CLEAR_LINE) - { - LOG((": irq line is asserted: set pending IRQ\n")); - cpustate->pending_irq = 1; - } - else - { - LOG((": irq line is clear\n")); - } - } - else - if( cpustate->pending_irq ) - deco16_take_irq(cpustate); - - } while (cpustate->icount > 0); -} - - -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( m6502 ) -{ - m6502_Regs *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: m6502_set_irq_line(cpustate, M6502_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: m6502_set_irq_line(cpustate, M6502_SET_OVERFLOW, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6502_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - - case CPUINFO_INT_PC: PCW = info->i; break; - case CPUINFO_INT_REGISTER + M6502_PC: cpustate->pc.w.l = info->i; break; - case CPUINFO_INT_SP: S = info->i; break; - case CPUINFO_INT_REGISTER + M6502_S: cpustate->sp.b.l = info->i; break; - case CPUINFO_INT_REGISTER + M6502_P: cpustate->p = info->i; break; - case CPUINFO_INT_REGISTER + M6502_A: cpustate->a = info->i; break; - case CPUINFO_INT_REGISTER + M6502_X: cpustate->x = info->i; break; - case CPUINFO_INT_REGISTER + M6502_Y: cpustate->y = info->i; break; - case CPUINFO_INT_REGISTER + M6502_EA: cpustate->ea.w.l = info->i; break; - case CPUINFO_INT_REGISTER + M6502_ZP: cpustate->zp.w.l = info->i; break; + switch(inputnum) { + case IRQ_LINE: irq_state = state == ASSERT_LINE; break; + case NMI_LINE: nmi_state = nmi_state || (state == ASSERT_LINE); break; + case V_LINE: + if(!v_state && state == ASSERT_LINE) + P |= F_V; + v_state = state == ASSERT_LINE; + break; } } - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( m6502 ) +const address_space_config *m6502_device::memory_space_config(address_spacenum spacenum) const { - m6502_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; + return (spacenum == AS_PROGRAM) ? &program_config : NULL; +} - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6502_Regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 10; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: info->i = cpustate->irq_state; break; - case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: info->i = cpustate->so_state; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc.w.l; break; - - case CPUINFO_INT_PC: info->i = PCD; break; - case CPUINFO_INT_REGISTER + M6502_PC: info->i = cpustate->pc.w.l; break; - case CPUINFO_INT_SP: info->i = S; break; - case CPUINFO_INT_REGISTER + M6502_S: info->i = cpustate->sp.b.l; break; - case CPUINFO_INT_REGISTER + M6502_P: info->i = cpustate->p; break; - case CPUINFO_INT_REGISTER + M6502_A: info->i = cpustate->a; break; - case CPUINFO_INT_REGISTER + M6502_X: info->i = cpustate->x; break; - case CPUINFO_INT_REGISTER + M6502_Y: info->i = cpustate->y; break; - case CPUINFO_INT_REGISTER + M6502_EA: info->i = cpustate->ea.w.l; break; - case CPUINFO_INT_REGISTER + M6502_ZP: info->i = cpustate->zp.w.l; break; - case CPUINFO_INT_REGISTER + M6502_SUBTYPE: info->i = cpustate->subtype; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m6502); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m6502); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m6502); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m6502); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m6502); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m6502); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M6502"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Mostek 6502"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.2"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - cpustate->p & 0x80 ? 'N':'.', - cpustate->p & 0x40 ? 'V':'.', - cpustate->p & 0x20 ? 'R':'.', - cpustate->p & 0x10 ? 'B':'.', - cpustate->p & 0x08 ? 'D':'.', - cpustate->p & 0x04 ? 'I':'.', - cpustate->p & 0x02 ? 'Z':'.', - cpustate->p & 0x01 ? 'C':'.'); - break; - - case CPUINFO_STR_REGISTER + M6502_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break; - case CPUINFO_STR_REGISTER + M6502_S: sprintf(info->s, "S:%02X", cpustate->sp.b.l); break; - case CPUINFO_STR_REGISTER + M6502_P: sprintf(info->s, "P:%02X", cpustate->p); break; - case CPUINFO_STR_REGISTER + M6502_A: sprintf(info->s, "A:%02X", cpustate->a); break; - case CPUINFO_STR_REGISTER + M6502_X: sprintf(info->s, "X:%02X", cpustate->x); break; - case CPUINFO_STR_REGISTER + M6502_Y: sprintf(info->s, "Y:%02X", cpustate->y); break; - case CPUINFO_STR_REGISTER + M6502_EA: sprintf(info->s, "EA:%04X", cpustate->ea.w.l); break; - case CPUINFO_STR_REGISTER + M6502_ZP: sprintf(info->s, "ZP:%03X", cpustate->zp.w.l); break; +void m6502_device::state_import(const device_state_entry &entry) +{ + switch(entry.index()) { + case STATE_GENFLAGS: + case M6502_P: + P = P | (F_B|F_E); + break; } } -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( m6504 ) +void m6502_device::state_export(const device_state_entry &entry) { - switch (state) - { - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M6504"); break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 13; break; - - default: CPU_GET_INFO_CALL(m6502); break; - } } -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( n2a03 ) +void m6502_device::state_string_export(const device_state_entry &entry, astring &string) { - switch (state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(n2a03); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "N2A03"); break; - - default: CPU_GET_INFO_CALL(m6502); break; + switch(entry.index()) { + case STATE_GENFLAGS: + case M6502_P: + string.printf("%c%c%c%c%c%c", + P & F_N ? 'N' : '.', + P & F_V ? 'V' : '.', + P & F_D ? 'D' : '.', + P & F_I ? 'I' : '.', + P & F_Z ? 'Z' : '.', + P & F_C ? 'C' : '.'); + break; } } -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -static CPU_SET_INFO( m6510 ) +UINT32 m6502_device::disasm_min_opcode_bytes() const { - switch (state) - { - default: CPU_SET_INFO_CALL(m6502); break; - } + return 1; } -CPU_GET_INFO( m6510 ) +UINT32 m6502_device::disasm_max_opcode_bytes() const { - switch (state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m6510); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m6510); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m6510); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m6510); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(m6510_mem); break; + return 4; +} - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M6510"); break; +offs_t m6502_device::disassemble_generic(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options, const disasm_entry *table) +{ + const disasm_entry &e = table[oprom[0]]; + UINT32 flags = e.flags | DASMFLAG_SUPPORTED; + buffer += sprintf(buffer, "%-5s", e.opcode); + if(e.per_bit) + buffer += sprintf(buffer, "%d, ", (oprom[0] >> 4) & 7); - default: CPU_GET_INFO_CALL(m6502); break; + switch(table[oprom[0]].mode) { + case DASM_non: + flags |= 1; + break; + + case DASM_aba: + sprintf(buffer, " $%02x%02x", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_abx: + sprintf(buffer, " $%02x%02x, x", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_aby: + sprintf(buffer, " $%02x%02x, y", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_acc: + sprintf(buffer, " a"); + flags |= 1; + break; + + case DASM_adr: + sprintf(buffer, " $%02x%02x", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_bzp: + sprintf(buffer, "%d $%02x", oprom[0] & 7, opram[1]); + flags |= 2; + break; + + case DASM_iax: + sprintf(buffer, " ($%02x%02x, x)", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_idx: + sprintf(buffer, " ($%02x, x)", opram[1]); + flags |= 2; + break; + + case DASM_idy: + sprintf(buffer, " ($%02x), y", opram[1]); + flags |= 2; + break; + + case DASM_idz: + sprintf(buffer, " ($%02x), z", opram[1]); + flags |= 2; + break; + + case DASM_imm: + sprintf(buffer, " #$%02x", opram[1]); + flags |= 2; + break; + + case DASM_imp: + flags |= 1; + break; + + case DASM_ind: + sprintf(buffer, " ($%02x%02x)", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_isy: + sprintf(buffer, " ($%02x, s), y", opram[1]); + flags |= 2; + break; + + case DASM_iw2: + sprintf(buffer, " #$%02x%02x", opram[2], opram[1]); + flags |= 3; + break; + + case DASM_iw3: + sprintf(buffer, " #$%02x%02x%02x", opram[3], opram[2], opram[1]); + flags |= 4; + break; + + case DASM_rel: + sprintf(buffer, " $%04x", (pc & 0xf0000) | UINT16(pc + 2 + INT8(opram[1]))); + flags |= 2; + break; + + case DASM_rw2: + sprintf(buffer, " $%04x", (pc & 0xf0000) | UINT16(pc + 3 + INT16((opram[2] << 8) | opram[1]))); + flags |= 3; + break; + + case DASM_zpb: + sprintf(buffer, "%d $%02x, $%04x", oprom[0] & 7, opram[1], (pc & 0xf0000) | UINT16(pc + 3 + INT8(opram[2]))); + flags |= 3; + break; + + case DASM_zpg: + sprintf(buffer, " $%02x", opram[1]); + flags |= 2; + break; + + case DASM_zpi: + sprintf(buffer, " ($%02x)", opram[1]); + flags |= 2; + break; + + case DASM_zpx: + sprintf(buffer, " $%02x, x", opram[1]); + flags |= 2; + break; + + case DASM_zpy: + sprintf(buffer, " $%02x, y", opram[1]); + flags |= 2; + break; + + default: + fprintf(stderr, "Unhandled dasm mode %d\n", table[oprom[0]].mode); + abort(); } + return flags; +} + +void m6502_device::prefetch() +{ + sync = true; + NPC = PC; + IR = mintf->read_decrypted(PC); + sync = false; + + if((nmi_state || (irq_state && !(P & F_I))) && !inhibit_interrupts) { + irq_taken = true; + IR = 0x00; + } else + PC++; +} + +void m6502_device::prefetch_noirq() +{ + sync = true; + NPC = PC; + IR = mintf->read_decrypted(PC); + sync = false; + PC++; +} + +void m6502_device::set_nz(UINT8 v) +{ + P &= ~(F_Z|F_N); + if(v & 0x80) + P |= F_N; + if(!v) + P |= F_Z; +} + +offs_t m6502_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); } -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( m6510t ) +UINT8 m6502_device::memory_interface::read_9(UINT16 adr) { - switch (state) - { - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M6510T"); break; + return read(adr); +} - default: CPU_GET_INFO_CALL(m6510); break; - } +void m6502_device::memory_interface::write_9(UINT16 adr, UINT8 val) +{ + write(adr, val); } -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( m7501 ) +UINT8 m6502_device::mi_default_normal::read(UINT16 adr) { - switch (state) - { - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M7501"); break; - - default: CPU_GET_INFO_CALL(m6510); break; - } + return program->read_byte(adr); } - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( m8502 ) +UINT8 m6502_device::mi_default_normal::read_direct(UINT16 adr) { - switch (state) - { - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M8502"); break; - - default: CPU_GET_INFO_CALL(m6510); break; - } + return direct->read_raw_byte(adr); } - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -static CPU_SET_INFO( m65c02 ) +UINT8 m6502_device::mi_default_normal::read_decrypted(UINT16 adr) { - m6502_Regs *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m65c02_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - - default: CPU_SET_INFO_CALL(m6502); break; - } + return direct->read_decrypted_byte(adr); } -CPU_GET_INFO( m65c02 ) +void m6502_device::mi_default_normal::write(UINT16 adr, UINT8 val) { - switch (state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m65c02); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m65c02); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m65c02); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m65c02); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m65c02); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M65C02"); break; - - default: CPU_GET_INFO_CALL(m6502); break; - } + program->write_byte(adr, val); } - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( m65sc02 ) +UINT8 m6502_device::mi_default_nd::read_direct(UINT16 adr) { - switch (state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m65sc02); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m65sc02); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M65SC02"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Metal Oxid Semiconductor MOS 6502"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0beta"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller\nCopyright Peter Trauner\nall rights reserved."); break; - - default: CPU_GET_INFO_CALL(m65c02); break; - } + return read(adr); } - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -static CPU_SET_INFO( deco16 ) +UINT8 m6502_device::mi_default_nd::read_decrypted(UINT16 adr) { - m6502_Regs *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: deco16_set_irq_line(cpustate, M6502_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: deco16_set_irq_line(cpustate, M6502_SET_OVERFLOW, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: deco16_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - - default: CPU_SET_INFO_CALL(m6502); break; - } + return read(adr); } -CPU_GET_INFO( deco16 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(deco16); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(deco16); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(deco16); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(deco16); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(deco16); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "DECO CPU16"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "DECO"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "0.1"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller\nCopyright Bryan McPhail\nall rights reserved."); break; - - default: CPU_GET_INFO_CALL(m6502); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(M6502, m6502); -DEFINE_LEGACY_CPU_DEVICE(M6504, m6504); -DEFINE_LEGACY_CPU_DEVICE(M6510, m6510); -DEFINE_LEGACY_CPU_DEVICE(M6510T, m6510t); -DEFINE_LEGACY_CPU_DEVICE(M7501, m7501); -DEFINE_LEGACY_CPU_DEVICE(M8502, m8502); -DEFINE_LEGACY_CPU_DEVICE(N2A03, n2a03); -DEFINE_LEGACY_CPU_DEVICE(M65C02, m65c02); -DEFINE_LEGACY_CPU_DEVICE(M65SC02, m65sc02); -DEFINE_LEGACY_CPU_DEVICE(DECO16, deco16); +#include "cpu/m6502/m6502.inc" diff --git a/src/emu/cpu/m6502/m6502.h b/src/emu/cpu/m6502/m6502.h index 7edf5be8ffc..48bd60929c5 100644 --- a/src/emu/cpu/m6502/m6502.h +++ b/src/emu/cpu/m6502/m6502.h @@ -1,230 +1,342 @@ -/***************************************************************************** - * - * m6502.h - * Portable 6502/65c02/65sc02/6510/n2a03 emulator interface - * - * Copyright Juergen Buchmueller, all rights reserved. - * 65sc02 core Copyright Peter Trauner. - * Deco16 portions Copyright Bryan McPhail. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ -/* 2.February 2000 PeT added 65sc02 subtype */ +/*************************************************************************** -#pragma once + m6502.h -#ifndef __M6502_H__ -#define __M6502_H__ + Mostek 6502, original NMOS variant +**************************************************************************** -/* set to 1 to test cur_mrhard/cur_wmhard to avoid calls */ -#define FAST_MEMORY 0 + Copyright Olivier Galibert + All rights reserved. -#define SUBTYPE_6502 0 -#define SUBTYPE_65C02 1 -#define SUBTYPE_6510 2 -#define SUBTYPE_2A03 3 -#define SUBTYPE_65SC02 4 -#define SUBTYPE_DECO16 5 + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: -enum -{ - M6502_PC=1, M6502_S, M6502_P, M6502_A, M6502_X, M6502_Y, - M6502_EA, M6502_ZP, - M6502_SUBTYPE + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M6502FAM_H__ +#define __M6502FAM_H__ + +#define MCFG_M6502_DISABLE_DIRECT() \ + downcast(device)->disable_direct(); + +class m6502_device : public cpu_device { +public: + enum { + IRQ_LINE, NMI_LINE, V_LINE + }; + + m6502_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + m6502_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); + + UINT64 get_cycle(); + bool get_sync() const { return sync; } + +protected: + class memory_interface { + public: + address_space *program; + direct_read_data *direct; + + virtual UINT8 read(UINT16 adr) = 0; + virtual UINT8 read_9(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr) = 0; + virtual UINT8 read_decrypted(UINT16 adr) = 0; + virtual void write(UINT16 adr, UINT8 val) = 0; + virtual void write_9(UINT16 adr, UINT8 val); + }; + + class mi_default_normal : public memory_interface { + public: + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + }; + + class mi_default_nd : public mi_default_normal { + public: + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + }; + + struct disasm_entry { + const char *opcode; + int mode; + offs_t flags; + bool per_bit; + }; + + enum { + STATE_RESET = 0x100, + }; + + enum { + DASM_non, /* no additional arguments */ + DASM_aba, /* absolute */ + DASM_abx, /* absolute + X */ + DASM_aby, /* absolute + Y */ + DASM_acc, /* accumulator */ + DASM_adr, /* absolute address (jmp,jsr) */ + DASM_bzp, /* zero page with bit selection */ + DASM_iax, /* indirect + X (65c02 jmp) */ + DASM_idx, /* zero page pre indexed */ + DASM_idy, /* zero page post indexed */ + DASM_idz, /* zero page post indexed (65ce02) */ + DASM_imm, /* immediate */ + DASM_imp, /* implicit */ + DASM_ind, /* indirect (jmp) */ + DASM_isy, /* zero page pre indexed sp and post indexed Y (65ce02) */ + DASM_iw2, /* immediate word (65ce02) */ + DASM_iw3, /* augment (65ce02) */ + DASM_rel, /* relative */ + DASM_rw2, /* relative word (65cs02, 65ce02) */ + DASM_zpb, /* zero page and branch (65c02 bbr, bbs) */ + DASM_zpg, /* zero page */ + DASM_zpi, /* zero page indirect (65c02) */ + DASM_zpx, /* zero page + X */ + DASM_zpy, /* zero page + Y */ + }; + + enum { + F_N = 0x80, + F_V = 0x40, + F_E = 0x20, // 65ce02 + F_B = 0x10, + F_D = 0x08, + F_I = 0x04, + F_Z = 0x02, + F_C = 0x01 + }; + + virtual void init(); + + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const; + virtual UINT32 execute_max_cycles() const; + virtual UINT32 execute_input_lines() const; + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; + + // device_state_interface overrides + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + virtual void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const; + virtual UINT32 disasm_max_opcode_bytes() const; + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + address_space_config program_config; + + UINT16 PPC; /* previous program counter */ + UINT16 NPC; /* next start-of-instruction program counter */ + UINT16 PC; /* program counter */ + UINT16 SP; /* stack pointer (always 100 - 1FF) */ + UINT16 TMP; /* temporary internal values */ + UINT8 TMP2; /* another temporary internal value, 8 bits this time */ + UINT8 A; /* Accumulator */ + UINT8 X; /* X index register */ + UINT8 Y; /* Y index register */ + UINT8 P; /* Processor status */ + UINT8 IR; /* Prefetched instruction register */ + + memory_interface *mintf; + int inst_state, inst_substate; + int icount; + bool nmi_state, irq_state, v_state; + bool irq_taken, sync, direct_disabled, inhibit_interrupts; + UINT64 end_cycles; + + static const disasm_entry disasm_entries[0x100]; + + offs_t disassemble_generic(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options, const disasm_entry *table); + UINT8 read(UINT16 adr) { return mintf->read(adr); } + UINT8 read_9(UINT16 adr) { return mintf->read_9(adr); } + void write(UINT16 adr, UINT8 val) { mintf->write(adr, val); } + void write_9(UINT16 adr, UINT8 val) { mintf->write_9(adr, val); } + UINT8 read_direct(UINT16 adr) { return mintf->read_direct(adr); } + UINT8 read_pc() { return mintf->read_direct(PC++); } + UINT8 read_pc_noinc() { return mintf->read_direct(PC); } + void prefetch(); + void prefetch_noirq(); + void set_nz(UINT8 v); + + virtual void do_exec_full(); + virtual void do_exec_partial(); + + // inline helpers + static inline bool page_changing(UINT16 base, int delta) { return ((base + delta) ^ base) & 0xff00; } + static inline UINT16 set_l(UINT16 base, UINT8 val) { return (base & 0xff00) | val; } + static inline UINT16 set_h(UINT16 base, UINT8 val) { return (base & 0x00ff) | (val << 8); } + + inline void dec_SP() { SP = set_l(SP, SP-1); } + inline void inc_SP() { SP = set_l(SP, SP+1); } + + void do_adc_d(UINT8 val); + void do_adc_nd(UINT8 val); + void do_sbc_d(UINT8 val); + void do_sbc_nd(UINT8 val); + void do_arr_d(); + void do_arr_nd(); + + void do_adc(UINT8 val); + void do_cmp(UINT8 val1, UINT8 val2); + void do_sbc(UINT8 val); + void do_bit(UINT8 val); + void do_arr(); + UINT8 do_asl(UINT8 v); + UINT8 do_lsr(UINT8 v); + UINT8 do_ror(UINT8 v); + UINT8 do_rol(UINT8 v); + UINT8 do_asr(UINT8 v); + +#define O(o) void o ## _full(); void o ## _partial() + + // NMOS 6502 opcodes + // documented opcodes + O(adc_aba); O(adc_abx); O(adc_aby); O(adc_idx); O(adc_idy); O(adc_imm); O(adc_zpg); O(adc_zpx); + O(and_aba); O(and_abx); O(and_aby); O(and_imm); O(and_idx); O(and_idy); O(and_zpg); O(and_zpx); + O(asl_aba); O(asl_abx); O(asl_acc); O(asl_zpg); O(asl_zpx); + O(bcc_rel); + O(bcs_rel); + O(beq_rel); + O(bit_aba); O(bit_zpg); + O(bmi_rel); + O(bne_rel); + O(bpl_rel); + O(brk_imp); + O(bvc_rel); + O(bvs_rel); + O(clc_imp); + O(cld_imp); + O(cli_imp); + O(clv_imp); + O(cmp_aba); O(cmp_abx); O(cmp_aby); O(cmp_idx); O(cmp_idy); O(cmp_imm); O(cmp_zpg); O(cmp_zpx); + O(cpx_aba); O(cpx_imm); O(cpx_zpg); + O(cpy_aba); O(cpy_imm); O(cpy_zpg); + O(dec_aba); O(dec_abx); O(dec_zpg); O(dec_zpx); + O(dex_imp); + O(dey_imp); + O(eor_aba); O(eor_abx); O(eor_aby); O(eor_idx); O(eor_idy); O(eor_imm); O(eor_zpg); O(eor_zpx); + O(inc_aba); O(inc_abx); O(inc_zpg); O(inc_zpx); + O(inx_imp); + O(iny_imp); + O(jmp_adr); O(jmp_ind); + O(jsr_adr); + O(lda_aba); O(lda_abx); O(lda_aby); O(lda_idx); O(lda_idy); O(lda_imm); O(lda_zpg); O(lda_zpx); + O(ldx_aba); O(ldx_aby); O(ldx_imm); O(ldx_zpg); O(ldx_zpy); + O(ldy_aba); O(ldy_abx); O(ldy_imm); O(ldy_zpg); O(ldy_zpx); + O(lsr_aba); O(lsr_abx); O(lsr_acc); O(lsr_zpg); O(lsr_zpx); + O(nop_imp); + O(ora_aba); O(ora_abx); O(ora_aby); O(ora_imm); O(ora_idx); O(ora_idy); O(ora_zpg); O(ora_zpx); + O(pha_imp); + O(php_imp); + O(pla_imp); + O(plp_imp); + O(rol_aba); O(rol_abx); O(rol_acc); O(rol_zpg); O(rol_zpx); + O(ror_aba); O(ror_abx); O(ror_acc); O(ror_zpg); O(ror_zpx); + O(rti_imp); + O(rts_imp); + O(sbc_aba); O(sbc_abx); O(sbc_aby); O(sbc_idx); O(sbc_idy); O(sbc_imm); O(sbc_zpg); O(sbc_zpx); + O(sec_imp); + O(sed_imp); + O(sei_imp); + O(sta_aba); O(sta_abx); O(sta_aby); O(sta_idx); O(sta_idy); O(sta_zpg); O(sta_zpx); + O(stx_aba); O(stx_zpg); O(stx_zpy); + O(sty_aba); O(sty_zpg); O(sty_zpx); + O(tax_imp); + O(tay_imp); + O(tsx_imp); + O(txa_imp); + O(txs_imp); + O(tya_imp); + + // exceptions + O(reset); + + // undocumented reliable instructions + O(dcp_aba); O(dcp_abx); O(dcp_aby); O(dcp_idx); O(dcp_idy); O(dcp_zpg); O(dcp_zpx); + O(isb_aba); O(isb_abx); O(isb_aby); O(isb_idx); O(isb_idy); O(isb_zpg); O(isb_zpx); + O(lax_aba); O(lax_aby); O(lax_idx); O(lax_idy); O(lax_zpg); O(lax_zpy); + O(rla_aba); O(rla_abx); O(rla_aby); O(rla_idx); O(rla_idy); O(rla_zpg); O(rla_zpx); + O(rra_aba); O(rra_abx); O(rra_aby); O(rra_idx); O(rra_idy); O(rra_zpg); O(rra_zpx); + O(sax_aba); O(sax_idx); O(sax_zpg); O(sax_zpy); + O(sbx_imm); + O(sha_aby); O(sha_idy); + O(shs_aby); + O(shx_aby); + O(shy_abx); + O(slo_aba); O(slo_abx); O(slo_aby); O(slo_idx); O(slo_idy); O(slo_zpg); O(slo_zpx); + O(sre_aba); O(sre_abx); O(sre_aby); O(sre_idx); O(sre_idy); O(sre_zpg); O(sre_zpx); + + // undocumented unreliable instructions + // behaviour differs between visual6502 and online docs, which + // is a clear sign reliability is not to be expected + // implemented version follows visual6502 + O(anc_imm); + O(ane_imm); + O(arr_imm); + O(asr_imm); + O(las_aby); + O(lxa_imm); + + // nop variants + O(nop_imm); O(nop_aba); O(nop_abx); O(nop_zpg); O(nop_zpx); + + // system killers + O(kil_non); + +#undef O }; -#define M6502_IRQ_LINE 0 -/* use cpudevice->execute().set_input_line(M6502_SET_OVERFLOW, level) - to change level of the so input line - positiv edge sets overflow flag */ -#define M6502_SET_OVERFLOW 1 - - -/* Optional interface to set callbacks */ -#define M6510_INTERFACE(name) \ - const m6502_interface (name) = - -struct m6502_interface -{ - devcb_read8 read_indexed_func; - devcb_write8 write_indexed_func; - devcb_read8 in_port_func; - devcb_write8 out_port_func; - UINT8 external_port_pullup; - UINT8 external_port_pulldown; +enum { + M6502_PC = 1, + M6502_A, + M6502_X, + M6502_Y, + M6502_P, + M6502_S, + M6502_IR }; -DECLARE_LEGACY_CPU_DEVICE(M6502, m6502); -DECLARE_LEGACY_CPU_DEVICE(M6504, m6504); -extern CPU_DISASSEMBLE( m6502 ); +enum { + M6502_IRQ_LINE = m6502_device::IRQ_LINE, + M6502_NMI_LINE = m6502_device::NMI_LINE, + M6502_SET_OVERFLOW = m6502_device::V_LINE, +}; -/**************************************************************************** - * The 6510 - ****************************************************************************/ -#define M6510_A M6502_A -#define M6510_X M6502_X -#define M6510_Y M6502_Y -#define M6510_S M6502_S -#define M6510_PC M6502_PC -#define M6510_P M6502_P -#define M6510_EA M6502_EA -#define M6510_ZP M6502_ZP -#define M6510_NMI_STATE M6502_NMI_STATE -#define M6510_IRQ_STATE M6502_IRQ_STATE +extern const device_type M6502; -#define M6510_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(M6510, m6510); - -extern CPU_DISASSEMBLE( m6510 ); - -UINT8 m6510_get_port(legacy_cpu_device *device); - -#define M6510T_A M6502_A -#define M6510T_X M6502_X -#define M6510T_Y M6502_Y -#define M6510T_S M6502_S -#define M6510T_PC M6502_PC -#define M6510T_P M6502_P -#define M6510T_EA M6502_EA -#define M6510T_ZP M6502_ZP -#define M6510T_NMI_STATE M6502_NMI_STATE -#define M6510T_IRQ_STATE M6502_IRQ_STATE - -#define M6510T_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(M6510T, m6510t); - - -#define M7501_A M6502_A -#define M7501_X M6502_X -#define M7501_Y M6502_Y -#define M7501_S M6502_S -#define M7501_PC M6502_PC -#define M7501_P M6502_P -#define M7501_EA M6502_EA -#define M7501_ZP M6502_ZP -#define M7501_NMI_STATE M6502_NMI_STATE -#define M7501_IRQ_STATE M6502_IRQ_STATE - -#define M7501_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(M7501, m7501); - -#define M8502_A M6502_A -#define M8502_X M6502_X -#define M8502_Y M6502_Y -#define M8502_S M6502_S -#define M8502_PC M6502_PC -#define M8502_P M6502_P -#define M8502_EA M6502_EA -#define M8502_ZP M6502_ZP -#define M8502_NMI_STATE M6502_NMI_STATE -#define M8502_IRQ_STATE M6502_IRQ_STATE - -#define M8502_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(M8502, m8502); - - -/**************************************************************************** - * The 2A03 (NES 6502 without decimal mode ADC/SBC) - ****************************************************************************/ -#define N2A03_A M6502_A -#define N2A03_X M6502_X -#define N2A03_Y M6502_Y -#define N2A03_S M6502_S -#define N2A03_PC M6502_PC -#define N2A03_P M6502_P -#define N2A03_EA M6502_EA -#define N2A03_ZP M6502_ZP -#define N2A03_NMI_STATE M6502_NMI_STATE -#define N2A03_IRQ_STATE M6502_IRQ_STATE - -#define N2A03_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(N2A03, n2a03); - -#define N2A03_DEFAULTCLOCK (21477272.724 / 12) - -/* The N2A03 is integrally tied to its PSG (they're on the same die). - Bit 7 of address $4011 (the PSG's DPCM control register), when set, - causes an IRQ to be generated. This function allows the IRQ to be called - from the PSG core when such an occasion arises. */ -extern void n2a03_irq(device_t *device); - - -/**************************************************************************** - * The 65C02 - ****************************************************************************/ -#define M65C02_A M6502_A -#define M65C02_X M6502_X -#define M65C02_Y M6502_Y -#define M65C02_S M6502_S -#define M65C02_PC M6502_PC -#define M65C02_P M6502_P -#define M65C02_EA M6502_EA -#define M65C02_ZP M6502_ZP -#define M65C02_NMI_STATE M6502_NMI_STATE -#define M65C02_IRQ_STATE M6502_IRQ_STATE - -#define M65C02_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(M65C02, m65c02); - -extern CPU_DISASSEMBLE( m65c02 ); - - -/**************************************************************************** - * The 65SC02 - ****************************************************************************/ -#define M65SC02_A M6502_A -#define M65SC02_X M6502_X -#define M65SC02_Y M6502_Y -#define M65SC02_S M6502_S -#define M65SC02_PC M6502_PC -#define M65SC02_P M6502_P -#define M65SC02_EA M6502_EA -#define M65SC02_ZP M6502_ZP -#define M65SC02_NMI_STATE M6502_NMI_STATE -#define M65SC02_IRQ_STATE M6502_IRQ_STATE - -#define M65SC02_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(M65SC02, m65sc02); - -extern CPU_DISASSEMBLE( m65sc02 ); - -/**************************************************************************** - * The DECO CPU16 - ****************************************************************************/ -#define DECO16_A M6502_A -#define DECO16_X M6502_X -#define DECO16_Y M6502_Y -#define DECO16_S M6502_S -#define DECO16_PC M6502_PC -#define DECO16_P M6502_P -#define DECO16_EA M6502_EA -#define DECO16_ZP M6502_ZP -#define DECO16_NMI_STATE M6502_NMI_STATE -#define DECO16_IRQ_STATE M6502_IRQ_STATE - -#define DECO16_IRQ_LINE M6502_IRQ_LINE - -DECLARE_LEGACY_CPU_DEVICE(DECO16, deco16); - -extern CPU_DISASSEMBLE( deco16 ); - -#endif /* __M6502_H__ */ +#endif diff --git a/src/emu/cpu/m6502/m6502make.c b/src/emu/cpu/m6502/m6502make.c index e69de29bb2d..4e4a65e3573 100644 --- a/src/emu/cpu/m6502/m6502make.c +++ b/src/emu/cpu/m6502/m6502make.c @@ -0,0 +1,259 @@ +#include +#include +#include +#include +#include +#include +#include "osdcomm.h" + +#include +#include + +using namespace std; + +enum { STATES = 0x101 }; + +const char *snames[STATES-0x100] = { + "STATE_RESET" +}; + +struct opcode { + string name; + vector instructions; +}; + +vector opcodes; + +struct table_t { + string opcodes[STATES]; +}; + +table_t table; + +string device_name; + +static void load_opcodes(const char *fname) +{ + char buf[4096]; + FILE *f; + + sprintf(buf, "Error opening %s for reading\n", fname); + f = fopen(fname, "r"); + if(!f) { + perror(buf); + exit(1); + } + + while(fgets(buf, sizeof(buf), f)) { + char *p = buf; + if(p[0] == '#' || p[0] == '\r' || p[0] == '\n' || p[0] == 0) + continue; + + for(char *q = p; *q; q++) + if(*q == '\r' || *q == '\n') { + *q = 0; + break; + } + + if(p[0] != ' ' && p[0] != '\t') { + opcodes.resize(opcodes.size()+1); + opcodes.back().name = p; + } else + opcodes.back().instructions.push_back(p); + } + fclose(f); +} + +static void load_disp(const char *fname) +{ + char buf[4096]; + FILE *f; + + sprintf(buf, "Error opening %s for reading\n", fname); + f = fopen(fname, "r"); + if(!f) { + perror(buf); + exit(1); + } + + int state = 0; + + while(fgets(buf, sizeof(buf), f)) { + char *p = buf; + if(p[0] == '#' || p[0] == '\r' || p[0] == '\n' || p[0] == 0) + continue; + + while(state < STATES) { + while(*p && (*p == '\n' || *p == '\r' || *p == ' ' || *p == '\t')) + p++; + if(!*p) + break; + + char *q = p; + while(*p != '\n' && *p != '\r' && *p != ' ' && *p != '\t') + p++; + table.opcodes[state++] = string(q, p); + } + } + fclose(f); +} + +enum { NONE, EAT_ALL, MEMORY }; + +static int identify_line_type(string inst) +{ + if(inst.find("eat-all-cycles") != string::npos) + return EAT_ALL; + if(inst.find("read") != string::npos || + inst.find("write") != string::npos || + inst.find("prefetch(") != string::npos || + inst.find("prefetch_noirq(") != string::npos) + return MEMORY; + return NONE; +} + +static void save_opcodes(FILE *f) +{ + for(unsigned int i=0; i != opcodes.size(); i++) { + int substate; + opcode &o = opcodes[i]; + + fprintf(f, "void %s::%s_full()\n", device_name.c_str(), o.name.c_str()); + fprintf(f, "{\n"); + substate = 1; + for(unsigned int j=0; j != o.instructions.size(); j++) { + string inst = o.instructions[j]; + int type = identify_line_type(inst); + if(type == EAT_ALL) { + fprintf(f, "\ticount=0; inst_substate = %d; return;", substate); + substate++; + } else { + if(type == MEMORY) + fprintf(f, "\tif(icount == 0) { inst_substate = %d; return; }\n", substate); + fprintf(f, "%s\n", inst.c_str()); + if(type == MEMORY) { + fprintf(f, "\ticount--;\n"); + substate++; + } + } + } + fprintf(f, "}\n"); + + fprintf(f, "void %s::%s_partial()\n", device_name.c_str(), o.name.c_str()); + fprintf(f, "{\n"); + fprintf(f, "switch(inst_substate) {\n"); + fprintf(f, "case 0:\n"); + substate = 1; + for(unsigned int j=0; j != o.instructions.size(); j++) { + string inst = o.instructions[j]; + int type = identify_line_type(inst); + if(type == EAT_ALL) { + fprintf(f, "\ticount=0; inst_substate = %d; return;", substate); + fprintf(f, "case %d:;\n", substate); + substate++; + } else { + if(type == MEMORY) { + fprintf(f, "\tif(icount == 0) { inst_substate = %d; return; }\n", substate); + fprintf(f, "case %d:\n", substate); + } + fprintf(f, "%s\n", inst.c_str()); + if(type == MEMORY) { + fprintf(f, "\ticount--;\n"); + substate++; + } + } + } + fprintf(f, "}\n"); + fprintf(f, "\tinst_substate = 0;\n"); + fprintf(f, "}\n"); + fprintf(f, "\n"); + } + fprintf(f, "\n"); +} + +static void save_tables(FILE *f) +{ + fprintf(f, "void %s::do_exec_full()\n", device_name.c_str()); + fprintf(f, "{\n"); + fprintf(f, "\tswitch(inst_state) {\n"); + for(int j=0; j; + +m6504_device::m6504_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, M6504, "M6504", tag, owner, clock) +{ + program_config.m_addrbus_width = 13; +} + +void m6504_device::device_start() +{ + if(direct_disabled) + mintf = new mi_6504_nd; + else + mintf = new mi_6504_normal; + + init(); +} + +UINT8 m6504_device::mi_6504_normal::read(UINT16 adr) +{ + return program->read_byte(adr & 0x1fff); +} + +UINT8 m6504_device::mi_6504_normal::read_direct(UINT16 adr) +{ + return direct->read_raw_byte(adr & 0x1fff); +} + +UINT8 m6504_device::mi_6504_normal::read_decrypted(UINT16 adr) +{ + return direct->read_decrypted_byte(adr & 0x1fff); +} + +void m6504_device::mi_6504_normal::write(UINT16 adr, UINT8 val) +{ + program->write_byte(adr & 0x1fff, val); +} + +UINT8 m6504_device::mi_6504_nd::read_direct(UINT16 adr) +{ + return read(adr); +} + +UINT8 m6504_device::mi_6504_nd::read_decrypted(UINT16 adr) +{ + return read(adr); +} diff --git a/src/emu/cpu/m6502/m6504.h b/src/emu/cpu/m6502/m6504.h index e69de29bb2d..73ddccde2ef 100644 --- a/src/emu/cpu/m6502/m6504.h +++ b/src/emu/cpu/m6502/m6504.h @@ -0,0 +1,76 @@ +/*************************************************************************** + + m6504.h + + Mostek 6502, NMOS variant with reduced address bus + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M6504_H__ +#define __M6504_H__ + +#include "m6502.h" + +class m6504_device : public m6502_device { +public: + m6504_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + class mi_6504_normal : public memory_interface { + public: + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + }; + + class mi_6504_nd : public mi_6504_normal { + public: + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + }; + + virtual void device_start(); +}; + + +enum { + M6504_IRQ_LINE = m6502_device::IRQ_LINE, + M6504_NMI_LINE = m6502_device::NMI_LINE, + M6504_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type M6504; + +#endif diff --git a/src/emu/cpu/m6502/m6509.c b/src/emu/cpu/m6502/m6509.c index 9e042832bcb..007d6effd8d 100644 --- a/src/emu/cpu/m6502/m6509.c +++ b/src/emu/cpu/m6502/m6509.c @@ -1,441 +1,165 @@ -/***************************************************************************** - * - * m6509.c - * Portable 6509 emulator V1.0beta1 - * - * Copyright Peter Trauner, all rights reserved. - * documentation by vice emulator team - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ -/* - 2000 March 10 PeT added SO input line +/*************************************************************************** -The basic difference is the amount of RAM these machines have been supplied with. The B128 and the CBM *10 -models had 128k RAM, the others 256k. This implies some banking scheme, as the 6502 can only address 64k. And -indeed those machines use a 6509, that can address 1 MByte of RAM. It has 2 registers at addresses 0 and 1. The -indirect bank register at address 1 determines the bank (0-15) where the opcodes LDA (zp),Y and STA (zp),Y -take the data from. The exec bank register at address 0 determines the bank where all other read and write -addresses take place. + m6509.c - vice writes to bank register only with zeropage operand - 0, 1 are bank register in all banks + 6502 with banking and extended address bus - lda (zp),y - sta (zp),y +**************************************************************************** -*/ + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ #include "emu.h" -#include "debugger.h" #include "m6509.h" -#include "ops02.h" -#include "ill02.h" -#include "ops09.h" +const device_type M6509 = &device_creator; -#define M6502_NMI_VEC 0xfffa -#define M6502_RST_VEC 0xfffc -#define M6502_IRQ_VEC 0xfffe -#define M6509_RST_VEC M6502_RST_VEC -#define M6509_IRQ_VEC M6502_IRQ_VEC -#define M6509_NMI_VEC M6502_NMI_VEC - -#define VERBOSE 0 - -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) - -struct m6509_Regs { - UINT8 subtype; /* currently selected cpu sub type */ - void (*const *insn)(m6509_Regs *); /* pointer to the function pointer table */ - PAIR ppc; /* previous program counter */ - /* pc.w.h contains the current page pc_bank.w.h for better speed */ - PAIR pc; /* program counter */ - PAIR sp; /* stack pointer (always 100 - 1FF) */ - PAIR zp; /* zero page address */ - PAIR ea; /* effective address */ - UINT8 a; /* Accumulator */ - UINT8 x; /* X index register */ - UINT8 y; /* Y index register */ - PAIR pc_bank; /* 4 bits, addressed over address 0 */ - PAIR ind_bank; /* 4 bits, addressed over address 1 */ - UINT8 p; /* Processor status */ - UINT8 pending_irq; /* nonzero if an IRQ is pending */ - UINT8 after_cli; /* pending IRQ and last insn cleared I */ - UINT8 nmi_state; - UINT8 irq_state; - UINT8 so_state; - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *space; - direct_read_data *direct; - - int int_occured; - int icount; - - devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ - devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ -}; - -INLINE m6509_Regs *get_safe_token(device_t *device) +m6509_device::m6509_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, M6509, "M6509", tag, owner, clock) { - assert(device != NULL); - assert(device->type() == M6509); - return (m6509_Regs *)downcast(device)->token(); + program_config.m_addrbus_width = 20; + program_config.m_logaddr_width = 16; + program_config.m_page_shift = 13; } -/*************************************************************** - * include the opcode macros, functions and tables - ***************************************************************/ - -#include "t6509.c" - -static READ8_HANDLER( m6509_read_00000 ) +void m6509_device::device_start() { - m6509_Regs *cpustate = get_safe_token(&space.device()); - - return cpustate->pc_bank.b.h2; -} - -static READ8_HANDLER( m6509_read_00001 ) -{ - m6509_Regs *cpustate = get_safe_token(&space.device()); - - return cpustate->ind_bank.b.h2; -} - -static WRITE8_HANDLER( m6509_write_00000 ) -{ - m6509_Regs *cpustate = get_safe_token(&space.device()); - - cpustate->pc_bank.b.h2=data&0xf; - cpustate->pc.w.h=cpustate->pc_bank.w.h; -} - -static WRITE8_HANDLER( m6509_write_00001 ) -{ - m6509_Regs *cpustate = get_safe_token(&space.device()); - - cpustate->ind_bank.b.h2=data&0xf; -} - -static ADDRESS_MAP_START(m6509_mem, AS_PROGRAM, 8, legacy_cpu_device) - AM_RANGE(0x00000, 0x00000) AM_MIRROR(0xF0000) AM_READWRITE_LEGACY(m6509_read_00000, m6509_write_00000) - AM_RANGE(0x00001, 0x00001) AM_MIRROR(0xF0000) AM_READWRITE_LEGACY(m6509_read_00001, m6509_write_00001) -ADDRESS_MAP_END - -static CPU_INIT( m6509 ) -{ - m6509_Regs *cpustate = get_safe_token(device); - const m6502_interface *intf = (const m6502_interface *)device->static_config(); - - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->space = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->space->direct(); - - if ( intf ) - { - cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); - cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); - } + if(direct_disabled) + mintf = new mi_6509_nd(this); else - { - devcb_read8 nullrcb = DEVCB_NULL; - devcb_write8 nullwcb = DEVCB_NULL; + mintf = new mi_6509_normal(this); - cpustate->rdmem_id.resolve(nullrcb, *device); - cpustate->wrmem_id.resolve(nullwcb, *device); - } + init(); - device->save_item(NAME(cpustate->pc.w.l)); - device->save_item(NAME(cpustate->sp.w.l)); - device->save_item(NAME(cpustate->p)); - device->save_item(NAME(cpustate->a)); - device->save_item(NAME(cpustate->x)); - device->save_item(NAME(cpustate->y)); - device->save_item(NAME(cpustate->pending_irq)); - device->save_item(NAME(cpustate->after_cli)); - device->save_item(NAME(cpustate->nmi_state)); - device->save_item(NAME(cpustate->irq_state)); - device->save_item(NAME(cpustate->so_state)); + state_add(M6509_BI, "BI", bank_i); + state_add(M6509_BY, "BY", bank_y); } -static CPU_RESET( m6509 ) +void m6509_device::device_reset() { - m6509_Regs *cpustate = get_safe_token(device); - - cpustate->insn = insn6509; - - cpustate->pc_bank.d=cpustate->ind_bank.d=0; - cpustate->pc_bank.b.h2=cpustate->ind_bank.b.h2=0xf; /* cbm500 needs this */ - cpustate->pc.w.h=cpustate->pc_bank.w.h; - /* wipe out the rest of the m6509 structure */ - /* read the reset vector into PC */ - PCL = RDMEM(M6509_RST_VEC|PB); - PCH = RDMEM((M6509_RST_VEC+1)|PB); - - cpustate->sp.d = 0x01ff; - cpustate->p = F_T|F_B|F_I|F_Z|(P&F_D); /* set T, I and Z flags */ - cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ - cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ - cpustate->irq_state = 0; - cpustate->nmi_state = 0; + bank_i = 0x0f; + bank_y = 0x0f; } -static CPU_EXIT( m6509 ) +offs_t m6509_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - /* nothing to do yet */ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); } -INLINE void m6509_take_irq( m6509_Regs *cpustate) + +m6509_device::mi_6509_normal::mi_6509_normal(m6509_device *_base) { - - if( !(P & F_I) ) - { - EAD = M6509_IRQ_VEC; - EAWH = PBWH; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P |= F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M6509 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD)); - /* call back the cpuintrf to let it clear the line */ - if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); - } - cpustate->pending_irq = 0; + base = _base; } -static CPU_EXECUTE( m6509 ) +UINT8 m6509_device::mi_6509_normal::read(UINT16 adr) { - m6509_Regs *cpustate = get_safe_token(device); - - do - { - UINT8 op; - PPC = PCD; - - debugger_instruction_hook(device, PCD); - - /* if an irq is pending, take it now */ - if( cpustate->pending_irq ) - m6509_take_irq(cpustate); - - op = RDOP(); - (*cpustate->insn[op])(cpustate); - - /* check if the I flag was just reset (interrupts enabled) */ - if( cpustate->after_cli ) - { - LOG(("M6509 '%s' after_cli was >0", cpustate->device->tag())); - cpustate->after_cli = 0; - if (cpustate->irq_state != CLEAR_LINE) - { - LOG((": irq line is asserted: set pending IRQ\n")); - cpustate->pending_irq = 1; - } - else - { - LOG((": irq line is clear\n")); - } - } - else { - if ( cpustate->pending_irq == 2 ) { - if ( cpustate->int_occured - cpustate->icount > 1 ) { - cpustate->pending_irq = 1; - } - } - if( cpustate->pending_irq == 1 ) - m6509_take_irq(cpustate); - if ( cpustate->pending_irq == 2 ) { - cpustate->pending_irq = 1; - } - } - - } while (cpustate->icount > 0); + UINT8 res = program->read_byte(adr); + if(adr == 0x0000) + res = base->bank_i_r(); + else if(adr == 0x0001) + res = base->bank_y_r(); + return res; } -static void m6509_set_irq_line(m6509_Regs *cpustate, int irqline, int state) +UINT8 m6509_device::mi_6509_normal::read_direct(UINT16 adr) { - if (irqline == INPUT_LINE_NMI) - { - if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6509 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag())); - EAD = M6509_NMI_VEC; - EAWH = PBWH; - cpustate->icount -= 2; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P |= F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M6509 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD)); - } - } - else - { - if( irqline == M6509_SET_OVERFLOW ) - { - if( cpustate->so_state && !state ) - { - LOG(( "M6509 '%s' set overflow\n", cpustate->device->tag())); - P|=F_V; - } - cpustate->so_state=state; - return; - } - cpustate->irq_state = state; - if( state != CLEAR_LINE ) - { - LOG(( "M6509 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag())); - cpustate->pending_irq = 1; - cpustate->int_occured = cpustate->icount; - } - } + UINT8 res = direct->read_raw_byte(base->adr_in_bank_i(adr)); + if(adr == 0x0000) + res = base->bank_i_r(); + else if(adr == 0x0001) + res = base->bank_y_r(); + return res; } -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( m6509 ) +UINT8 m6509_device::mi_6509_normal::read_decrypted(UINT16 adr) { - m6509_Regs *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M6509_IRQ_LINE: m6509_set_irq_line(cpustate, M6509_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:m6509_set_irq_line(cpustate, M6509_SET_OVERFLOW, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6509_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - - case CPUINFO_INT_PC: PCW = info->i; break; - case CPUINFO_INT_REGISTER + M6509_PC: cpustate->pc.w.l = info->i; break; - case CPUINFO_INT_SP: S = info->i; break; - case CPUINFO_INT_REGISTER + M6509_S: cpustate->sp.b.l = info->i; break; - case CPUINFO_INT_REGISTER + M6509_P: cpustate->p = info->i; break; - case CPUINFO_INT_REGISTER + M6509_A: cpustate->a = info->i; break; - case CPUINFO_INT_REGISTER + M6509_X: cpustate->x = info->i; break; - case CPUINFO_INT_REGISTER + M6509_Y: cpustate->y = info->i; break; - case CPUINFO_INT_REGISTER + M6509_PC_BANK: cpustate->pc_bank.b.h2 = info->i; break; - case CPUINFO_INT_REGISTER + M6509_IND_BANK: cpustate->ind_bank.b.h2 = info->i; break; - case CPUINFO_INT_REGISTER + M6509_EA: cpustate->ea.w.l = info->i; break; - case CPUINFO_INT_REGISTER + M6509_ZP: cpustate->zp.w.l = info->i; break; - } + UINT8 res = direct->read_decrypted_byte(base->adr_in_bank_i(adr)); + if(adr == 0x0000) + res = base->bank_i_r(); + else if(adr == 0x0001) + res = base->bank_y_r(); + return res; } - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( m6509 ) +UINT8 m6509_device::mi_6509_normal::read_9(UINT16 adr) { - m6509_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6509_Regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 10; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + M6509_IRQ_LINE: info->i = cpustate->irq_state; break; - case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:info->i = cpustate->so_state; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc.w.l; break; - - case CPUINFO_INT_PC: info->i = PCD; break; - case CPUINFO_INT_REGISTER + M6509_PC: info->i = cpustate->pc.w.l; break; - case CPUINFO_INT_SP: info->i = S; break; - case CPUINFO_INT_REGISTER + M6509_S: info->i = cpustate->sp.b.l; break; - case CPUINFO_INT_REGISTER + M6509_P: info->i = cpustate->p; break; - case CPUINFO_INT_REGISTER + M6509_A: info->i = cpustate->a; break; - case CPUINFO_INT_REGISTER + M6509_X: info->i = cpustate->x; break; - case CPUINFO_INT_REGISTER + M6509_Y: info->i = cpustate->y; break; - case CPUINFO_INT_REGISTER + M6509_PC_BANK: info->i = cpustate->pc_bank.b.h2; break; - case CPUINFO_INT_REGISTER + M6509_IND_BANK: info->i = cpustate->ind_bank.b.h2; break; - case CPUINFO_INT_REGISTER + M6509_EA: info->i = cpustate->ea.w.l; break; - case CPUINFO_INT_REGISTER + M6509_ZP: info->i = cpustate->zp.w.l; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m6509); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m6509); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m6509); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m6509); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m6509); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m6502); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(m6509_mem); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M6509"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "MOS Technology 6509"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0beta"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller\nCopyright Peter Trauner\nall rights reserved."); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - cpustate->p & 0x80 ? 'N':'.', - cpustate->p & 0x40 ? 'V':'.', - cpustate->p & 0x20 ? 'R':'.', - cpustate->p & 0x10 ? 'B':'.', - cpustate->p & 0x08 ? 'D':'.', - cpustate->p & 0x04 ? 'I':'.', - cpustate->p & 0x02 ? 'Z':'.', - cpustate->p & 0x01 ? 'C':'.'); - break; - - case CPUINFO_STR_REGISTER + M6509_PC: sprintf(info->s, "PC:%05X", cpustate->pc.d); break; - case CPUINFO_STR_REGISTER + M6509_S: sprintf(info->s, "S:%02X", cpustate->sp.b.l); break; - case CPUINFO_STR_REGISTER + M6509_P: sprintf(info->s, "P:%02X", cpustate->p); break; - case CPUINFO_STR_REGISTER + M6509_A: sprintf(info->s, "A:%02X", cpustate->a); break; - case CPUINFO_STR_REGISTER + M6509_X: sprintf(info->s, "X:%02X", cpustate->x); break; - case CPUINFO_STR_REGISTER + M6509_Y: sprintf(info->s, "Y:%02X", cpustate->y); break; - case CPUINFO_STR_REGISTER + M6509_PC_BANK: sprintf(info->s, "M0:%01X", cpustate->pc_bank.b.h2); break; - case CPUINFO_STR_REGISTER + M6509_IND_BANK: sprintf(info->s, "M1:%01X", cpustate->ind_bank.b.h2); break; - case CPUINFO_STR_REGISTER + M6509_EA: sprintf(info->s, "EA:%05X", cpustate->ea.d); break; - case CPUINFO_STR_REGISTER + M6509_ZP: sprintf(info->s, "ZP:%03X", cpustate->zp.w.l); break; - } + UINT8 res = program->read_byte(base->adr_in_bank_y(adr)); + if(adr == 0x0000) + res = base->bank_i_r(); + else if(adr == 0x0001) + res = base->bank_y_r(); + return res; } -DEFINE_LEGACY_CPU_DEVICE(M6509, m6509); +void m6509_device::mi_6509_normal::write(UINT16 adr, UINT8 val) +{ + program->write_byte(adr, val); + if(adr == 0x0000) + base->bank_i_w(val); + else if(adr == 0x0001) + base->bank_y_w(val); +} + +void m6509_device::mi_6509_normal::write_9(UINT16 adr, UINT8 val) +{ + program->write_byte(base->adr_in_bank_y(adr), val); + if(adr == 0x0000) + base->bank_i_w(val); + else if(adr == 0x0001) + base->bank_y_w(val); +} + +m6509_device::mi_6509_nd::mi_6509_nd(m6509_device *_base) : mi_6509_normal(_base) +{ +} + +UINT8 m6509_device::mi_6509_nd::read_direct(UINT16 adr) +{ + UINT8 res = program->read_byte(base->adr_in_bank_i(adr)); + if(adr == 0x0000) + res = base->bank_i_r(); + else if(adr == 0x0001) + res = base->bank_y_r(); + return res; +} + +UINT8 m6509_device::mi_6509_nd::read_decrypted(UINT16 adr) +{ + UINT8 res = program->read_byte(base->adr_in_bank_i(adr)); + if(adr == 0x0000) + res = base->bank_i_r(); + else if(adr == 0x0001) + res = base->bank_y_r(); + return res; +} + +#include "cpu/m6502/m6509.inc" diff --git a/src/emu/cpu/m6502/m6509.h b/src/emu/cpu/m6502/m6509.h index 22e2f70b06e..c036511c356 100644 --- a/src/emu/cpu/m6502/m6509.h +++ b/src/emu/cpu/m6502/m6509.h @@ -1,44 +1,111 @@ -/***************************************************************************** - * - * m6509.h - * Portable 6509 emulator V1.0beta - * - * Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ +/*************************************************************************** -#pragma once + m6509.h + + 6502 with banking and extended address bus + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ #ifndef __M6509_H__ -#define _M6509_H +#define __M6509_H__ #include "m6502.h" -enum -{ - M6509_PC=1, M6509_S, M6509_P, M6509_A, M6509_X, M6509_Y, - M6509_EA, M6509_ZP, M6509_NMI_STATE, M6509_IRQ_STATE, M6509_SO_STATE, - M6509_PC_BANK, M6509_IND_BANK +class m6509_device : public m6502_device { +public: + m6509_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + +protected: + class mi_6509_normal : public memory_interface { + public: + m6509_device *base; + + mi_6509_normal(m6509_device *base); + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_9(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + virtual void write_9(UINT16 adr, UINT8 val); + }; + + class mi_6509_nd : public mi_6509_normal { + public: + mi_6509_nd(m6509_device *base); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + }; + + virtual void device_start(); + virtual void device_reset(); + + UINT8 bank_i, bank_y; + + UINT8 bank_i_r() { return bank_i; } + UINT8 bank_y_r() { return bank_y; } + void bank_i_w(UINT8 data) { bank_i = data; } + void bank_y_w(UINT8 data) { bank_y = data; } + + UINT32 adr_in_bank_i(UINT16 adr) { return adr | ((bank_i & 0xf) << 16); } + UINT32 adr_in_bank_y(UINT16 adr) { return adr | ((bank_y & 0xf) << 16); } + +#define O(o) void o ## _full(); void o ## _partial() + + // 6509 opcodes + O(lda_9_idy); + O(sta_9_idy); + +#undef O }; -#define M6509_IRQ_LINE M6502_IRQ_LINE -/* use cpudevice->execute().set_input_line(M6509_SET_OVERFLOW, level) - to change level of the so input line - positiv edge sets overflow flag */ -#define M6509_SET_OVERFLOW 3 +enum { + M6509_IRQ_LINE = m6502_device::IRQ_LINE, + M6509_NMI_LINE = m6502_device::NMI_LINE, + M6509_SET_OVERFLOW = m6502_device::V_LINE, +}; -DECLARE_LEGACY_CPU_DEVICE(M6509, m6509); +enum { + M6509_BI = M6502_IR+1, + M6509_BY +}; -#endif /* __M6509_H__ */ +extern const device_type M6509; + +#endif diff --git a/src/emu/cpu/m6502/m6510.c b/src/emu/cpu/m6502/m6510.c index e69de29bb2d..55ef1a4efcf 100644 --- a/src/emu/cpu/m6502/m6510.c +++ b/src/emu/cpu/m6502/m6510.c @@ -0,0 +1,193 @@ +/*************************************************************************** + + m6510.c + + 6502 with 6 i/o pins, also known as 8500 + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "m6510.h" + +const device_type M6510 = &device_creator; + +m6510_device::m6510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, M6510, "M6510", tag, owner, clock), + read_port(*this), + write_port(*this) +{ + pullup = 0x00; + floating = 0x00; +} + +m6510_device::m6510_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, type, name, tag, owner, clock), + read_port(*this), + write_port(*this) +{ + pullup = 0x00; + floating = 0x00; +} + +void m6510_device::set_pulls(UINT8 _pullup, UINT8 _floating) +{ + pullup = _pullup; + floating = _floating; +} + +offs_t m6510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); +} + +void m6510_device::device_start() +{ + read_port.resolve_safe(0); + write_port.resolve_safe(); + + if(direct_disabled) + mintf = new mi_6510_nd(this); + else + mintf = new mi_6510_normal(this); + + init(); + + save_item(NAME(pullup)); + save_item(NAME(floating)); + save_item(NAME(dir)); + save_item(NAME(port)); + save_item(NAME(drive)); +} + +void m6510_device::device_reset() +{ + dir = 0x00; + port = 0x00; + drive = 0x00; + update_port(); +} + +void m6510_device::update_port() +{ + drive = (port & dir) | (drive & ~dir); + write_port((port & dir) | (pullup & ~dir)); +} + +UINT8 m6510_device::get_port() +{ + return (port & dir) | (pullup & ~dir); +} + +UINT8 m6510_device::dir_r() +{ + return dir; +} + +UINT8 m6510_device::port_r() +{ + return ((read_port() | (floating & drive)) & ~dir) | (port & dir); +} + +void m6510_device::dir_w(UINT8 data) +{ + dir = data; + update_port(); +} + +void m6510_device::port_w(UINT8 data) +{ + port = data; + update_port(); +} + + +m6510_device::mi_6510_normal::mi_6510_normal(m6510_device *_base) +{ + base = _base; +} + +UINT8 m6510_device::mi_6510_normal::read(UINT16 adr) +{ + UINT8 res = program->read_byte(adr); + if(adr == 0x0000) + res = base->dir_r(); + else if(adr == 0x0001) + res = base->port_r(); + return res; +} + +UINT8 m6510_device::mi_6510_normal::read_direct(UINT16 adr) +{ + UINT8 res = direct->read_raw_byte(adr); + if(adr == 0x0000) + res = base->dir_r(); + else if(adr == 0x0001) + res = base->port_r(); + return res; +} + +UINT8 m6510_device::mi_6510_normal::read_decrypted(UINT16 adr) +{ + UINT8 res = direct->read_decrypted_byte(adr); + if(adr == 0x0000) + res = base->dir_r(); + else if(adr == 0x0001) + res = base->port_r(); + return res; +} + +void m6510_device::mi_6510_normal::write(UINT16 adr, UINT8 val) +{ + program->write_byte(adr, val); + if(adr == 0x0000) + base->dir_w(val); + else if(adr == 0x0001) + base->port_w(val); +} + +m6510_device::mi_6510_nd::mi_6510_nd(m6510_device *_base) : mi_6510_normal(_base) +{ +} + +UINT8 m6510_device::mi_6510_nd::read_direct(UINT16 adr) +{ + return read(adr); +} + +UINT8 m6510_device::mi_6510_nd::read_decrypted(UINT16 adr) +{ + return read(adr); +} + +#include "cpu/m6502/m6510.inc" diff --git a/src/emu/cpu/m6502/m6510.h b/src/emu/cpu/m6502/m6510.h index e69de29bb2d..6a53cad6d3e 100644 --- a/src/emu/cpu/m6502/m6510.h +++ b/src/emu/cpu/m6502/m6510.h @@ -0,0 +1,126 @@ +/*************************************************************************** + + m6510.h + + 6502 with 6 i/o pins, also known as 8500 + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M6510FAM_H__ +#define __M6510FAM_H__ + +#include "m6502.h" + +#define MCFG_M6510_PORT_CALLBACKS(_read, _write) \ + downcast(device)->set_callbacks(DEVCB2_##_read, DEVCB2_##_write); + +#define MCFG_M6510_PORT_PULLS(_up, _down) \ + downcast(device)->set_pulls(_up, _down); + +class m6510_device : public m6502_device { +public: + m6510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + m6510_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); + + UINT8 get_port(); + void set_port(UINT8 val); + void set_pulls(UINT8 pullup, UINT8 pulldown); + + template void set_callbacks(_read rd, _write wr) { + read_port.set_callback(rd); + write_port.set_callback(wr); + } + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + +protected: + class mi_6510_normal : public memory_interface { + public: + m6510_device *base; + + mi_6510_normal(m6510_device *base); + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + }; + + class mi_6510_nd : public mi_6510_normal { + public: + mi_6510_nd(m6510_device *base); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + }; + + devcb2_read8 read_port; + devcb2_write8 write_port; + + UINT8 pullup, floating, dir, port, drive; + + virtual void device_start(); + virtual void device_reset(); + + UINT8 dir_r(); + void dir_w(UINT8 data); + UINT8 port_r(); + void port_w(UINT8 data); + + void update_port(); + +#define O(o) void o ## _full(); void o ## _partial() + + // 6510 undocumented instructions in a C64 context + // implementation follows what the test suites expect (usually an extra and) + O(anc_10_imm); + O(ane_10_imm); + O(arr_10_imm); + O(asr_10_imm); + O(las_10_aby); + O(lxa_10_imm); + +#undef O +}; + +enum { + M6510_IRQ_LINE = m6502_device::IRQ_LINE, + M6510_NMI_LINE = m6502_device::NMI_LINE, +}; + +extern const device_type M6510; + +#endif diff --git a/src/emu/cpu/m6502/m6510t.c b/src/emu/cpu/m6502/m6510t.c index e69de29bb2d..bc6881c1b98 100644 --- a/src/emu/cpu/m6502/m6510t.c +++ b/src/emu/cpu/m6502/m6510t.c @@ -0,0 +1,48 @@ +/*************************************************************************** + + m6510t.c + + 6510 with the full 8 i/o pins at the expense of the NMI and RDY lines. + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "m6510t.h" + +const device_type M6510T = &device_creator; + +m6510t_device::m6510t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6510_device(mconfig, M6510T, "M6510T", tag, owner, clock) +{ +} diff --git a/src/emu/cpu/m6502/m6510t.h b/src/emu/cpu/m6502/m6510t.h index e69de29bb2d..82e1baecf29 100644 --- a/src/emu/cpu/m6502/m6510t.h +++ b/src/emu/cpu/m6502/m6510t.h @@ -0,0 +1,63 @@ +/*************************************************************************** + + m6510t.h + + 6510 with the full 8 i/o pins at the expense of the NMI and RDY lines. + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M6510T_H__ +#define __M6510T_H__ + +#include "m6510.h" + +#define MCFG_M6510T_PORT_CALLBACKS(_read, _write) \ + downcast(device)->set_callbacks(DEVCB2_##_read, DEVCB2_##_write); + +#define MCFG_M6510T_PORT_PULLS(_up, _down) \ + downcast(device)->set_pulls(_up, _down); + +class m6510t_device : public m6510_device { +public: + m6510t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +enum { + M6510T_IRQ_LINE = m6502_device::IRQ_LINE, + M6510T_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type M6510T; + +#endif diff --git a/src/emu/cpu/m6502/m65c02.c b/src/emu/cpu/m6502/m65c02.c index e69de29bb2d..783505ea268 100644 --- a/src/emu/cpu/m6502/m65c02.c +++ b/src/emu/cpu/m6502/m65c02.c @@ -0,0 +1,61 @@ +/*************************************************************************** + + m65c02.c + + Mostek 6502, CMOS variant with some additional instructions (but + not the bitwise ones) + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "m65c02.h" + +const device_type M65C02 = &device_creator; + +m65c02_device::m65c02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, M65C02, "M65C02", tag, owner, clock) +{ +} + +m65c02_device::m65c02_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, type, name, tag, owner, clock) +{ +} + +offs_t m65c02_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); +} + +#include "cpu/m6502/m65c02.inc" diff --git a/src/emu/cpu/m6502/m65c02.h b/src/emu/cpu/m6502/m65c02.h index e69de29bb2d..479578ff745 100644 --- a/src/emu/cpu/m6502/m65c02.h +++ b/src/emu/cpu/m6502/m65c02.h @@ -0,0 +1,105 @@ +/*************************************************************************** + + m65c02.h + + Mostek 6502, CMOS variant with some additional instructions (but + not the bitwise ones) + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M65C02_H__ +#define __M65C02_H__ + +#include "m6502.h" + +class m65c02_device : public m6502_device { +public: + m65c02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + m65c02_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + +protected: +#define O(o) void o ## _full(); void o ## _partial() + + // 65c02 opcodes + O(adc_c_aba); O(adc_c_abx); O(adc_c_aby); O(adc_c_idx); O(adc_c_idy); O(adc_c_imm); O(adc_c_zpg); O(adc_c_zpi); O(adc_c_zpx); + O(and_zpi); + O(asl_c_abx); + O(bbr_zpb); + O(bbs_zpb); + O(bit_abx); O(bit_imm); O(bit_zpx); + O(bra_rel); + O(brk_c_imp); + O(cmp_zpi); + O(dec_acc); + O(eor_zpi); + O(inc_acc); + O(jmp_c_ind); O(jmp_iax); + O(lda_zpi); + O(lsr_c_abx); + O(nop_c_aba); O(nop_c_abx); O(nop_c_imp); + O(ora_zpi); + O(phx_imp); + O(phy_imp); + O(plx_imp); + O(ply_imp); + O(rmb_bzp); + O(rol_c_abx); + O(ror_c_abx); + O(sbc_c_aba); O(sbc_c_abx); O(sbc_c_aby); O(sbc_c_idx); O(sbc_c_idy); O(sbc_c_imm); O(sbc_c_zpg); O(sbc_c_zpi); O(sbc_c_zpx); + O(smb_bzp); + O(stp_imp); + O(sta_zpi); + O(stz_aba); O(stz_abx); O(stz_zpg); O(stz_zpx); + O(trb_aba); O(trb_zpg); + O(tsb_aba); O(tsb_zpg); + O(wai_imp); + +#undef O +}; + +enum { + M65C02_IRQ_LINE = m6502_device::IRQ_LINE, + M65C02_NMI_LINE = m6502_device::NMI_LINE, + M65C02_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type M65C02; + +#endif diff --git a/src/emu/cpu/m6502/m65ce02.c b/src/emu/cpu/m6502/m65ce02.c index 082e17ba6e3..581396b1b3b 100644 --- a/src/emu/cpu/m6502/m65ce02.c +++ b/src/emu/cpu/m6502/m65ce02.c @@ -1,364 +1,127 @@ -/***************************************************************************** - * - * m65ce02.c - * Portable 65ce02 emulator V1.0beta3 - * - * Copyright Peter Trauner, all rights reserved - * documentation preliminary databook - * documentation by michael steil mist@c64.org - * available at ftp://ftp.funet.fi/pub/cbm/c65 - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ -/* 4. February 2000 PeT fixed relative word operand */ -/* 4. February 2000 PeT jsr (absolut) jsr (absolut,x) inw dew */ -/* 17.February 2000 PeT phw */ -/* 16.March 2000 PeT fixed some instructions accordingly to databook */ -/* 7. May 2000 PeT splittet into m65ce02 and m4510 */ +/*************************************************************************** -/* + m65ce02.c -* neg is now simple 2er komplement negation with set of N and Z + 6502 with Z register and some more stuff -* phw push low order byte, push high order byte! +**************************************************************************** -* tys txs not interruptable, not implemented + Copyright Olivier Galibert + All rights reserved. -*/ + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ #include "emu.h" -#include "debugger.h" #include "m65ce02.h" -#include "mincce02.h" -#include "opsce02.h" +const device_type M65CE02 = &device_creator; -#define M6502_NMI_VEC 0xfffa -#define M6502_RST_VEC 0xfffc -#define M6502_IRQ_VEC 0xfffe -#define M65CE02_RST_VEC M6502_RST_VEC -#define M65CE02_IRQ_VEC M6502_IRQ_VEC -#define M65CE02_NMI_VEC M6502_NMI_VEC - -#define VERBOSE 0 - -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) - -struct m65ce02_Regs { - void (*const *insn)(m65ce02_Regs *); /* pointer to the function pointer table */ - PAIR ppc; /* previous program counter */ - PAIR pc; /* program counter */ - PAIR sp; /* stack pointer (always 100 - 1FF) */ - PAIR zp; /* zero page address */ - /* contains B register zp.b.h */ - PAIR ea; /* effective address */ - UINT8 a; /* Accumulator */ - UINT8 x; /* X index register */ - UINT8 y; /* Y index register */ - UINT8 z; /* Z index register */ - UINT8 p; /* Processor status */ - UINT8 pending_irq; /* nonzero if an IRQ is pending */ - UINT8 after_cli; /* pending IRQ and last insn cleared I */ - UINT8 nmi_state; - UINT8 irq_state; - int icount; - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *space; - direct_read_data *direct; - devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ - devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ -}; - -INLINE m65ce02_Regs *get_safe_token(device_t *device) +m65ce02_device::m65ce02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m65c02_device(mconfig, M65CE02, "M65CE02", tag, owner, clock) { - assert(device != NULL); - assert(device->type() == M65CE02); - return (m65ce02_Regs *)downcast(device)->token(); } -/*************************************************************** - * include the opcode macros, functions and tables - ***************************************************************/ - -#include "t65ce02.c" - -static CPU_INIT( m65ce02 ) +m65ce02_device::m65ce02_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : + m65c02_device(mconfig, type, name, tag, owner, clock) { - m65ce02_Regs *cpustate = get_safe_token(device); - const m6502_interface *intf = (const m6502_interface *)device->static_config(); +} - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->space = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->space->direct(); +offs_t m65ce02_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); +} - if ( intf ) - { - cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); - cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); - } +void m65ce02_device::init() +{ + m65c02_device::init(); + state_add(M65CE02_Z, "Z", Z); + state_add(M65CE02_B, "B", B).callimport().formatstr("%2s"); + save_item(NAME(B)); + save_item(NAME(Z)); + save_item(NAME(TMP3)); + Z = 0x00; + B = 0x0000; + TMP3 = 0x0000; +} + +void m65ce02_device::device_start() +{ + if(direct_disabled) + mintf = new mi_default_nd; else - { - devcb_read8 nullrcb = DEVCB_NULL; - devcb_write8 nullwcb = DEVCB_NULL; + mintf = new mi_default_normal; - cpustate->rdmem_id.resolve(nullrcb, *device); - cpustate->wrmem_id.resolve(nullwcb, *device); + init(); +} + +void m65ce02_device::device_reset() +{ + m65c02_device::device_reset(); + Z = 0x00; + B = 0x0000; +} + +void m65ce02_device::state_import(const device_state_entry &entry) +{ + switch(entry.index()) { + case STATE_GENFLAGS: + case M6502_P: + P = P | F_B; + break; + case M65CE02_B: + B <<= 8; + break; } } -static CPU_RESET( m65ce02 ) +void m65ce02_device::state_export(const device_state_entry &entry) { - m65ce02_Regs *cpustate = get_safe_token(device); - - cpustate->insn = insn65ce02; - - /* wipe out the rest of the m65ce02 structure */ - /* read the reset vector into PC */ - /* reset z index and b bank */ - PCL = RDMEM(M65CE02_RST_VEC); - PCH = RDMEM(M65CE02_RST_VEC+1); - - /* after reset in 6502 compatibility mode */ - cpustate->sp.d = 0x01ff; /* high byte descriped in databook */ - cpustate->z = 0; - B = 0; - cpustate->p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */ - cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ - cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ - cpustate->irq_callback = NULL; } -static CPU_EXIT( m65ce02 ) +void m65ce02_device::state_string_export(const device_state_entry &entry, astring &string) { - /* nothing to do yet */ -} - -INLINE void m65ce02_take_irq(m65ce02_Regs *cpustate) -{ - if( !(P & F_I) ) - { - EAD = M65CE02_IRQ_VEC; - cpustate->icount -= 7; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P = (P & ~F_D) | F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M65ce02 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD)); - /* call back the cpuintrf to let it clear the line */ - if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); - } - cpustate->pending_irq = 0; -} - -static CPU_EXECUTE( m65ce02 ) -{ - m65ce02_Regs *cpustate = get_safe_token(device); - - do - { - UINT8 op; - PPC = PCD; - - debugger_instruction_hook(device, PCD); - - /* if an irq is pending, take it now */ - if( cpustate->pending_irq ) - m65ce02_take_irq(cpustate); - - op = RDOP(); - (*insn65ce02[op])(cpustate); - - /* check if the I flag was just reset (interrupts enabled) */ - if( cpustate->after_cli ) - { - LOG(("M65ce02 '%s' after_cli was >0", cpustate->device->tag())); - cpustate->after_cli = 0; - if (cpustate->irq_state != CLEAR_LINE) - { - LOG((": irq line is asserted: set pending IRQ\n")); - cpustate->pending_irq = 1; - } - else - { - LOG((": irq line is clear\n")); - } - } - else - if( cpustate->pending_irq ) - m65ce02_take_irq(cpustate); - - } while (cpustate->icount > 0); -} - -static void m65ce02_set_irq_line(m65ce02_Regs *cpustate, int irqline, int state) -{ - if (irqline == INPUT_LINE_NMI) - { - if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; - if( state != CLEAR_LINE ) - { - LOG(("M65ce02 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag())); - EAD = M65CE02_NMI_VEC; - cpustate->icount -= 7; - PUSH(PCH); - PUSH(PCL); - PUSH(P & ~F_B); - P = (P & ~F_D) | F_I; /* knock out D and set I flag */ - PCL = RDMEM(EAD); - PCH = RDMEM(EAD+1); - LOG(("M65ce02 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD)); - } - } - else - { - cpustate->irq_state = state; - if( state != CLEAR_LINE ) - { - LOG(("M65ce02 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag())); - cpustate->pending_irq = 1; - } + switch(entry.index()) { + case STATE_GENFLAGS: + case M6502_P: + string.printf("%c%c%c%c%c%c%c", + P & F_N ? 'N' : '.', + P & F_V ? 'V' : '.', + P & F_E ? 'E' : '.', + P & F_D ? 'D' : '.', + P & F_I ? 'I' : '.', + P & F_Z ? 'Z' : '.', + P & F_C ? 'C' : '.'); + break; + case M65CE02_B: + string.printf("%02x", B >> 8); + break; } } -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( m65ce02 ) -{ - m65ce02_Regs *cpustate = get_safe_token(device); - - switch( state ) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M65CE02_IRQ_STATE: m65ce02_set_irq_line( cpustate, M65CE02_IRQ_LINE, info->i ); break; - case CPUINFO_INT_INPUT_STATE + M65CE02_NMI_STATE: m65ce02_set_irq_line( cpustate, INPUT_LINE_NMI, info->i ); break; - - case CPUINFO_INT_PC: PCW = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_PC: cpustate->pc.w.l = info->i; break; - case CPUINFO_INT_SP: cpustate->sp.b.l = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_S: cpustate->sp.w.l = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_P: cpustate->p = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_A: cpustate->a = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_X: cpustate->x = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_Y: cpustate->y = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_Z: cpustate->z = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_B: cpustate->zp.b.h = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_EA: cpustate->ea.w.l = info->i; break; - case CPUINFO_INT_REGISTER + M65CE02_ZP: cpustate->zp.b.l = info->i; break; - } -} - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( m65ce02 ) -{ - m65ce02_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch( state ) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m65ce02_Regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 10; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 16; break; - case CPUINFO_INT_PAGE_SHIFT_PROGRAM: info->i = 13; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE+M65CE02_NMI_STATE: info->i = cpustate->nmi_state; break; - case CPUINFO_INT_INPUT_STATE+M65CE02_IRQ_STATE: info->i = cpustate->irq_state; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc.w.l; break; - - case CPUINFO_INT_PC: info->i = PCD; break; - case CPUINFO_INT_REGISTER+M65CE02_PC: info->i = cpustate->pc.w.l; break; - case CPUINFO_INT_SP: info->i = cpustate->sp.b.l; break; - case CPUINFO_INT_REGISTER+M65CE02_S: info->i = cpustate->sp.w.l; break; - case CPUINFO_INT_REGISTER+M65CE02_P: info->i = cpustate->p; break; - case CPUINFO_INT_REGISTER+M65CE02_A: info->i = cpustate->a; break; - case CPUINFO_INT_REGISTER+M65CE02_X: info->i = cpustate->x; break; - case CPUINFO_INT_REGISTER+M65CE02_Y: info->i = cpustate->y; break; - case CPUINFO_INT_REGISTER+M65CE02_Z: info->i = cpustate->z; break; - case CPUINFO_INT_REGISTER+M65CE02_B: info->i = cpustate->zp.b.h; break; - case CPUINFO_INT_REGISTER+M65CE02_EA: info->i = cpustate->ea.w.l; break; - case CPUINFO_INT_REGISTER+M65CE02_ZP: info->i = cpustate->zp.w.l; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m65ce02); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m65ce02); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m65ce02); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m65ce02); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m65ce02); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m65ce02); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M65CE02"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s,"CBM Semiconductor Group CSG 65CE02"); break; - case CPUINFO_STR_VERSION: strcpy(info->s,"1.0beta"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s,__FILE__); - case CPUINFO_STR_CREDITS: - strcpy(info->s, "Copyright Juergen Buchmueller\n" - "Copyright Peter Trauner\n" - "all rights reserved."); break; - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - cpustate->p & 0x80 ? 'N':'.', - cpustate->p & 0x40 ? 'V':'.', - cpustate->p & 0x20 ? 'E':'.', - cpustate->p & 0x10 ? 'B':'.', - cpustate->p & 0x08 ? 'D':'.', - cpustate->p & 0x04 ? 'I':'.', - cpustate->p & 0x02 ? 'Z':'.', - cpustate->p & 0x01 ? 'C':'.'); - break; - - case CPUINFO_STR_REGISTER + M65CE02_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break; - case CPUINFO_STR_REGISTER + M65CE02_S: sprintf(info->s, "S:%02X", cpustate->sp.b.l); break; - case CPUINFO_STR_REGISTER + M65CE02_P: sprintf(info->s, "P:%02X", cpustate->p); break; - case CPUINFO_STR_REGISTER + M65CE02_A: sprintf(info->s, "A:%02X", cpustate->a); break; - case CPUINFO_STR_REGISTER + M65CE02_X: sprintf(info->s, "X:%02X", cpustate->x); break; - case CPUINFO_STR_REGISTER + M65CE02_Y: sprintf(info->s, "Y:%02X", cpustate->y); break; - case CPUINFO_STR_REGISTER + M65CE02_Z: sprintf(info->s, "Z:%02X", cpustate->z); break; - case CPUINFO_STR_REGISTER + M65CE02_B: sprintf(info->s, "B:%02X", cpustate->zp.b.h); break; - case CPUINFO_STR_REGISTER + M65CE02_EA: sprintf(info->s, "EA:%04X", cpustate->ea.w.l); break; - case CPUINFO_STR_REGISTER + M65CE02_ZP: sprintf(info->s, "ZP:%03X", cpustate->zp.w.l); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(M65CE02, m65ce02); +#include "cpu/m6502/m65ce02.inc" diff --git a/src/emu/cpu/m6502/m65ce02.h b/src/emu/cpu/m6502/m65ce02.h index 2a556f560ff..5d8e4391c03 100644 --- a/src/emu/cpu/m6502/m65ce02.h +++ b/src/emu/cpu/m6502/m65ce02.h @@ -1,42 +1,182 @@ -/***************************************************************************** - * - * m65ce02.c - * Portable 65ce02 emulator V1.0beta - * - * Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ +/*************************************************************************** -#pragma once + m65ce02.h + + 6502 with Z register and some more stuff + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ #ifndef __M65CE02_H__ #define __M65CE02_H__ -#include "m6502.h" +#include "m65c02.h" -enum -{ - M65CE02_PC=1, M65CE02_S, M65CE02_P, M65CE02_A, M65CE02_X, M65CE02_Y, - M65CE02_Z, M65CE02_B, M65CE02_EA, M65CE02_ZP, - M65CE02_NMI_STATE, M65CE02_IRQ_STATE +class m65ce02_device : public m65c02_device { +public: + m65ce02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + m65ce02_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + +protected: + UINT16 TMP3; /* temporary internal values */ + UINT8 Z; /* Z index register */ + UINT16 B; /* Zero page base address (always xx00) */ + + virtual void init(); + virtual void device_start(); + virtual void device_reset(); + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + virtual void state_string_export(const device_state_entry &entry, astring &string); + + inline void dec_SP_ce() { if(P & F_E) SP = set_l(SP, SP-1); else SP--; } + inline void inc_SP_ce() { if(P & F_E) SP = set_l(SP, SP+1); else SP++; } + +#define O(o) void o ## _full(); void o ## _partial() + + // 65ce02 opcodes + O(adc_ce_aba); O(adc_ce_abx); O(adc_ce_aby); O(adc_ce_idx); O(adc_ce_idy); O(adc_idz); O(adc_ce_imm); O(adc_ce_zpg); O(adc_ce_zpx); + O(and_ce_abx); O(and_ce_aby); O(and_ce_idx); O(and_ce_idy); O(and_idz); O(and_ce_zpg); O(and_ce_zpx); + O(asl_ce_aba); O(asl_ce_abx); O(asl_ce_acc); O(asl_ce_zpg); O(asl_ce_zpx); + O(asr_acc); O(asr_zpg); O(asr_zpx); + O(asw_aba); + O(aug_iw3); + O(bbr_ce_zpb); + O(bbs_ce_zpb); + O(bcc_ce_rel); O(bcc_rw2); + O(bcs_ce_rel); O(bcs_rw2); + O(beq_ce_rel); O(beq_rw2); + O(bit_ce_abx); O(bit_ce_imm); O(bit_ce_zpg); O(bit_ce_zpx); + O(bmi_ce_rel); O(bmi_rw2); + O(bne_ce_rel); O(bne_rw2); + O(bpl_ce_rel); O(bpl_rw2); + O(bra_ce_rel); O(bra_rw2); + O(brk_ce_imp); + O(bsr_rw2); + O(bvc_ce_rel); O(bvc_rw2); + O(bvs_ce_rel); O(bvs_rw2); + O(clc_ce_imp); + O(cld_ce_imp); + O(cle_imp); + O(cli_ce_imp); + O(clv_ce_imp); + O(cmp_ce_abx); O(cmp_ce_aby); O(cmp_ce_idx); O(cmp_ce_idy); O(cmp_idz); O(cmp_ce_zpg); O(cmp_ce_zpx); + O(cpx_ce_zpg); + O(cpy_ce_zpg); + O(cpz_aba); O(cpz_imm); O(cpz_zpg); + O(dec_ce_aba); O(dec_ce_abx); O(dec_ce_acc); O(dec_ce_zpg); O(dec_ce_zpx); + O(dew_zpg); + O(dex_ce_imp); + O(dey_ce_imp); + O(dez_imp); + O(eor_ce_abx); O(eor_ce_aby); O(eor_ce_idx); O(eor_ce_idy); O(eor_idz); O(eor_ce_zpg); O(eor_ce_zpx); + O(inc_ce_aba); O(inc_ce_abx); O(inc_ce_acc); O(inc_ce_zpg); O(inc_ce_zpx); + O(inw_zpg); + O(inx_ce_imp); + O(iny_ce_imp); + O(inz_imp); + O(jmp_ce_iax); O(jmp_ce_ind); + O(jsr_ce_adr); O(jsr_ind); O(jsr_iax); + O(lda_ce_abx); O(lda_ce_aby); O(lda_ce_idx); O(lda_ce_idy); O(lda_idz); O(lda_isy); O(lda_ce_zpg); O(lda_ce_zpx); + O(ldx_ce_aby); O(ldx_ce_zpg); O(ldx_ce_zpy); + O(ldy_ce_abx); O(ldy_ce_zpg); O(ldy_ce_zpx); + O(ldz_aba); O(ldz_abx); O(ldz_imm); + O(lsr_ce_aba); O(lsr_ce_abx); O(lsr_ce_acc); O(lsr_ce_zpg); O(lsr_ce_zpx); + O(neg_acc); + O(ora_ce_abx); O(ora_ce_aby); O(ora_ce_idx); O(ora_ce_idy); O(ora_idz); O(ora_ce_zpg); O(ora_ce_zpx); + O(pha_ce_imp); + O(php_ce_imp); + O(phw_aba); O(phw_iw2); + O(phx_ce_imp); + O(phy_ce_imp); + O(phz_imp); + O(pla_ce_imp); + O(plp_ce_imp); + O(plx_ce_imp); + O(ply_ce_imp); + O(plz_imp); + O(rmb_ce_bzp); + O(rol_ce_aba); O(rol_ce_abx); O(rol_ce_acc); O(rol_ce_zpg); O(rol_ce_zpx); + O(ror_ce_aba); O(ror_ce_abx); O(ror_ce_acc); O(ror_ce_zpg); O(ror_ce_zpx); + O(row_aba); + O(rti_ce_imp); + O(rtn_imm); + O(rts_ce_imp); + O(sbc_ce_aba); O(sbc_ce_abx); O(sbc_ce_aby); O(sbc_ce_idx); O(sbc_ce_idy); O(sbc_idz); O(sbc_ce_imm); O(sbc_ce_zpg); O(sbc_ce_zpx); + O(sec_ce_imp); + O(sed_ce_imp); + O(see_imp); + O(sei_ce_imp); + O(smb_ce_bzp); + O(sta_ce_abx); O(sta_ce_aby); O(sta_ce_idx); O(sta_ce_idy); O(sta_idz); O(sta_isy); O(sta_ce_zpg); O(sta_ce_zpx); + O(stx_aby); O(stx_ce_zpg); O(stx_ce_zpy); + O(sty_abx); O(sty_ce_zpg); O(sty_ce_zpx); + O(stz_ce_aba); O(stz_ce_abx); O(stz_ce_zpg); O(stz_ce_zpx); + O(tab_imp); + O(tax_ce_imp); + O(tay_ce_imp); + O(taz_imp); + O(tba_imp); + O(trb_ce_aba); O(trb_ce_zpg); + O(tsb_ce_aba); O(tsb_ce_zpg); + O(tsx_ce_imp); + O(tsy_imp); + O(txa_ce_imp); + O(txs_ce_imp); + O(tys_imp); + O(tya_ce_imp); + O(tza_imp); + +#undef O }; -#define M65CE02_IRQ_LINE M6502_IRQ_LINE +enum { + M65CE02_IRQ_LINE = m6502_device::IRQ_LINE, + M65CE02_NMI_LINE = m6502_device::NMI_LINE, +}; -DECLARE_LEGACY_CPU_DEVICE(M65CE02, m65ce02); -extern CPU_DISASSEMBLE( m65ce02 ); +enum { + M65CE02_Z = M6502_IR+1, + M65CE02_B +}; -#endif /* __M65CE02_H__ */ +extern const device_type M65CE02; + +#endif diff --git a/src/emu/cpu/m6502/m65sc02.c b/src/emu/cpu/m6502/m65sc02.c index e69de29bb2d..a537885a22c 100644 --- a/src/emu/cpu/m6502/m65sc02.c +++ b/src/emu/cpu/m6502/m65sc02.c @@ -0,0 +1,48 @@ +/*************************************************************************** + + m65sc02.c + + Rockwell-class 65c02 with internal static registers, making clock stoppable? + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "m65sc02.h" + +const device_type M65SC02 = &device_creator; + +m65sc02_device::m65sc02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + r65c02_device(mconfig, M65SC02, "M65SC02", tag, owner, clock) +{ +} diff --git a/src/emu/cpu/m6502/m65sc02.h b/src/emu/cpu/m6502/m65sc02.h index e69de29bb2d..5b37cc9cca9 100644 --- a/src/emu/cpu/m6502/m65sc02.h +++ b/src/emu/cpu/m6502/m65sc02.h @@ -0,0 +1,58 @@ +/*************************************************************************** + + m65sc02.h + + Rockwell-class 65c02 with internal static registers, making clock stoppable? + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M65SC02_H__ +#define __M65SC02_H__ + +#include "r65c02.h" + +class m65sc02_device : public r65c02_device { +public: + m65sc02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +enum { + M65SC02_IRQ_LINE = m6502_device::IRQ_LINE, + M65SC02_NMI_LINE = m6502_device::NMI_LINE, + M65SC02_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type M65SC02; + +#endif diff --git a/src/emu/cpu/m6502/m7501.c b/src/emu/cpu/m6502/m7501.c index e69de29bb2d..3f8c000c640 100644 --- a/src/emu/cpu/m6502/m7501.c +++ b/src/emu/cpu/m6502/m7501.c @@ -0,0 +1,48 @@ +/*************************************************************************** + + m7501.c + + 6510 derivative, essentially identical. Also known as the 8501. + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "m7501.h" + +const device_type M7501 = &device_creator; + +m7501_device::m7501_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6510_device(mconfig, M7501, "M7501", tag, owner, clock) +{ +} diff --git a/src/emu/cpu/m6502/m7501.h b/src/emu/cpu/m6502/m7501.h index e69de29bb2d..c75dba10de5 100644 --- a/src/emu/cpu/m6502/m7501.h +++ b/src/emu/cpu/m6502/m7501.h @@ -0,0 +1,63 @@ +/*************************************************************************** + + m7501.h + + 6510 derivative, essentially identical. Also known as the 8501. + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M7501_H__ +#define __M7501_H__ + +#include "m6510.h" + +#define MCFG_M7501_PORT_CALLBACKS(_read, _write) \ + downcast(device)->set_callbacks(DEVCB2_##_read, DEVCB2_##_write); + +#define MCFG_M7501_PORT_PULLS(_up, _down) \ + downcast(device)->set_pulls(_up, _down); + +class m7501_device : public m6510_device { +public: + m7501_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +enum { + M7501_IRQ_LINE = m6502_device::IRQ_LINE, + M7501_NMI_LINE = m6502_device::NMI_LINE, +}; + +extern const device_type M7501; + +#endif diff --git a/src/emu/cpu/m6502/m8502.c b/src/emu/cpu/m6502/m8502.c index e69de29bb2d..cb7dadd2b7b 100644 --- a/src/emu/cpu/m6502/m8502.c +++ b/src/emu/cpu/m6502/m8502.c @@ -0,0 +1,48 @@ +/*************************************************************************** + + m8502.c + + 6510 derivative, capable of running at 2MHz. + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "m8502.h" + +const device_type M8502 = &device_creator; + +m8502_device::m8502_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6510_device(mconfig, M8502, "M8502", tag, owner, clock) +{ +} diff --git a/src/emu/cpu/m6502/m8502.h b/src/emu/cpu/m6502/m8502.h index e69de29bb2d..cbd10093da8 100644 --- a/src/emu/cpu/m6502/m8502.h +++ b/src/emu/cpu/m6502/m8502.h @@ -0,0 +1,63 @@ +/*************************************************************************** + + m8502.h + + 6510 derivative, capable of running at 2MHz. + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __M8502_H__ +#define __M8502_H__ + +#include "m6510.h" + +#define MCFG_M8502_PORT_CALLBACKS(_read, _write) \ + downcast(device)->set_callbacks(DEVCB2_##_read, DEVCB2_##_write); + +#define MCFG_M8502_PORT_PULLS(_up, _down) \ + downcast(device)->set_pulls(_up, _down); + +class m8502_device : public m6510_device { +public: + m8502_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +enum { + M8502_IRQ_LINE = m6502_device::IRQ_LINE, + M8502_NMI_LINE = m6502_device::NMI_LINE, +}; + +extern const device_type M8502; + +#endif diff --git a/src/emu/cpu/m6502/minc4510.h b/src/emu/cpu/m6502/minc4510.h deleted file mode 100644 index 26b06fba9c9..00000000000 --- a/src/emu/cpu/m6502/minc4510.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************** - * - * minc4510.h - * Base macros for 4510 CPU files - * - *****************************************************************************/ - - -/* 4510 flags */ -#define F_C 0x01 -#define F_Z 0x02 -#define F_I 0x04 -#define F_D 0x08 -#define F_B 0x10 -#define F_E 0x20 -#define F_V 0x40 -#define F_N 0x80 - -/* some shortcuts for improved readability */ -#define A cpustate->a -#define X cpustate->x -#define Y cpustate->y -#define P cpustate->p -#define Z cpustate->z -#define B cpustate->zp.b.h -#define SW cpustate->sp.w.l -#define SPL cpustate->sp.b.l -#define SPH cpustate->sp.b.h -#define SPD cpustate->sp.d - -#define NZ cpustate->nz - -#define EAL cpustate->ea.b.l -#define EAH cpustate->ea.b.h -#define EAW cpustate->ea.w.l -#define EAD cpustate->ea.d - -#define ZPL cpustate->zp.b.l -#define ZPH cpustate->zp.b.h -#define ZPW cpustate->zp.w.l -#define ZPD cpustate->zp.d - -#define PCL cpustate->pc.b.l -#define PCH cpustate->pc.b.h -#define PCW cpustate->pc.w.l -#define PCD cpustate->pc.d - -#define PPC cpustate->ppc.d - -#define IRQ_STATE cpustate->irq_state -#define AFTER_CLI cpustate->after_cli - -#define M4510_MEM(addr) (cpustate->mem[(addr)>>13]+(addr)) - -#define PEEK_OP() cpustate->direct->read_decrypted_byte(M4510_MEM(PCW)) - -#define RDMEM(addr) cpustate->space->read_byte(M4510_MEM(addr)); cpustate->icount -= 1 -#define WRMEM(addr,data) cpustate->space->write_byte(M4510_MEM(addr),data); cpustate->icount -= 1 - -/*************************************************************** - * RDOP read an opcode - ***************************************************************/ -#undef RDOP -#define RDOP() m4510_cpu_readop(cpustate); cpustate->icount -= 1 - -/*************************************************************** - * RDOPARG read an opcode argument - ***************************************************************/ -#undef RDOPARG -#define RDOPARG() m4510_cpu_readop_arg(cpustate); cpustate->icount -= 1 diff --git a/src/emu/cpu/m6502/mincce02.h b/src/emu/cpu/m6502/mincce02.h deleted file mode 100644 index a54d02fec9e..00000000000 --- a/src/emu/cpu/m6502/mincce02.h +++ /dev/null @@ -1,69 +0,0 @@ -/***************************************************************************** - * - * mincce02.h - * Base macros for 65ce02 CPU files - * - *****************************************************************************/ - - -/* 65ce02 flags */ -#define F_C 0x01 -#define F_Z 0x02 -#define F_I 0x04 -#define F_D 0x08 -#define F_B 0x10 -#define F_E 0x20 -#define F_V 0x40 -#define F_N 0x80 - -/* some shortcuts for improved readability */ -#define A cpustate->a -#define X cpustate->x -#define Y cpustate->y -#define P cpustate->p -#define Z cpustate->z -#define B cpustate->zp.b.h -#define SW cpustate->sp.w.l -#define SPL cpustate->sp.b.l -#define SPH cpustate->sp.b.h -#define SPD cpustate->sp.d - -#define NZ cpustate->nz - -#define EAL cpustate->ea.b.l -#define EAH cpustate->ea.b.h -#define EAW cpustate->ea.w.l -#define EAD cpustate->ea.d - -#define ZPL cpustate->zp.b.l -#define ZPH cpustate->zp.b.h -#define ZPW cpustate->zp.w.l -#define ZPD cpustate->zp.d - -#define PCL cpustate->pc.b.l -#define PCH cpustate->pc.b.h -#define PCW cpustate->pc.w.l -#define PCD cpustate->pc.d - -#define PPC cpustate->ppc.d - -#define RDMEM_ID(a) cpustate->rdmem_id(*cpustate->space, a) -#define WRMEM_ID(a,d) cpustate->wrmem_id(*cpustate->space, a, d) - -#define IRQ_STATE cpustate->irq_state -#define AFTER_CLI cpustate->after_cli - -/*************************************************************** - * RDOP read an opcode - ***************************************************************/ -#define RDOP() cpustate->direct->read_decrypted_byte(PCW++); cpustate->icount -= 1 - -/*************************************************************** - * RDOPARG read an opcode argument - ***************************************************************/ -#define RDOPARG() cpustate->direct->read_raw_byte(PCW++); cpustate->icount -= 1 - -#define PEEK_OP() cpustate->direct->read_decrypted_byte(PCW) - -#define RDMEM(addr) cpustate->space->read_byte(addr); cpustate->icount -= 1 -#define WRMEM(addr,data) cpustate->space->write_byte(addr,data); cpustate->icount -= 1 diff --git a/src/emu/cpu/m6502/n2a03.c b/src/emu/cpu/m6502/n2a03.c index e69de29bb2d..34c922d4194 100644 --- a/src/emu/cpu/m6502/n2a03.c +++ b/src/emu/cpu/m6502/n2a03.c @@ -0,0 +1,105 @@ +/*************************************************************************** + + m6502.c + + 6502, NES variant + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "n2a03.h" + +const device_type N2A03 = &device_creator; + +n2a03_device::n2a03_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m6502_device(mconfig, N2A03, "N2A03", tag, owner, clock) +{ +} + +offs_t n2a03_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); +} + +void n2a03_device::device_start() +{ + if(direct_disabled) + mintf = new mi_2a03_nd; + else + mintf = new mi_2a03_normal; + + init(); +} + +UINT8 n2a03_device::mi_2a03_normal::read(UINT16 adr) +{ + return program->read_byte(adr); +} + +UINT8 n2a03_device::mi_2a03_normal::read_direct(UINT16 adr) +{ + return direct->read_raw_byte(adr); +} + +UINT8 n2a03_device::mi_2a03_normal::read_decrypted(UINT16 adr) +{ + return direct->read_decrypted_byte(adr); +} + +void n2a03_device::mi_2a03_normal::write(UINT16 adr, UINT8 val) +{ + program->write_byte(adr, val); +} + +UINT8 n2a03_device::mi_2a03_nd::read(UINT16 adr) +{ + return program->read_byte(adr); +} + +UINT8 n2a03_device::mi_2a03_nd::read_direct(UINT16 adr) +{ + return program->read_byte(adr); +} + +UINT8 n2a03_device::mi_2a03_nd::read_decrypted(UINT16 adr) +{ + return program->read_byte(adr); +} + +void n2a03_device::mi_2a03_nd::write(UINT16 adr, UINT8 val) +{ + program->write_byte(adr, val); +} + +#include "cpu/m6502/n2a03.inc" diff --git a/src/emu/cpu/m6502/n2a03.h b/src/emu/cpu/m6502/n2a03.h index e69de29bb2d..6c5a2c515b5 100644 --- a/src/emu/cpu/m6502/n2a03.h +++ b/src/emu/cpu/m6502/n2a03.h @@ -0,0 +1,96 @@ +/*************************************************************************** + + n2a03.h + + 6502, NES variant + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __N2A03_H__ +#define __N2A03_H__ + +#include "m6502.h" + +class n2a03_device : public m6502_device { +public: + n2a03_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); + +protected: + class mi_2a03_normal : public memory_interface { + public: + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + }; + + class mi_2a03_nd : public memory_interface { + public: + virtual UINT8 read(UINT16 adr); + virtual UINT8 read_direct(UINT16 adr); + virtual UINT8 read_decrypted(UINT16 adr); + virtual void write(UINT16 adr, UINT8 val); + }; + + virtual void device_start(); + +#define O(o) void o ## _full(); void o ## _partial() + + // n2a03 opcodes - same as 6502 with D disabled + O(adc_nd_aba); O(adc_nd_abx); O(adc_nd_aby); O(adc_nd_idx); O(adc_nd_idy); O(adc_nd_imm); O(adc_nd_zpg); O(adc_nd_zpx); + O(arr_nd_imm); + O(isb_nd_aba); O(isb_nd_abx); O(isb_nd_aby); O(isb_nd_idx); O(isb_nd_idy); O(isb_nd_zpg); O(isb_nd_zpx); + O(rra_nd_aba); O(rra_nd_abx); O(rra_nd_aby); O(rra_nd_idx); O(rra_nd_idy); O(rra_nd_zpg); O(rra_nd_zpx); + O(sbc_nd_aba); O(sbc_nd_abx); O(sbc_nd_aby); O(sbc_nd_idx); O(sbc_nd_idy); O(sbc_nd_imm); O(sbc_nd_zpg); O(sbc_nd_zpx); + +#undef O +}; + +#define N2A03_DEFAULTCLOCK (21477272.724 / 12) + +enum { + N2A03_IRQ_LINE = m6502_device::IRQ_LINE, + N2A03_NMI_LINE = m6502_device::NMI_LINE, + N2A03_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type N2A03; + +#endif diff --git a/src/emu/cpu/m6502/odeco16.lst b/src/emu/cpu/m6502/odeco16.lst index e69de29bb2d..e6035e751bf 100644 --- a/src/emu/cpu/m6502/odeco16.lst +++ b/src/emu/cpu/m6502/odeco16.lst @@ -0,0 +1,65 @@ +# deco 16 opcodes +ill_non + logerror("%s: Unimplemented instruction %02x\n", tag(), inst_state); + prefetch(); + +u0B_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OP0B %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +u13_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OP13 %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +u23_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OP23 %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +u3F_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OPBB %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +u4B_zpg + TMP2 = read_pc(); + A = io->read_byte(1); + prefetch(); + +u87_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OP87 %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +u8F_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OP8F (BANK) %02x (%04x)\n", tag(), NPC, TMP2); + io->write_byte(0, TMP2); + prefetch(); + +uA3_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OPA3 %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +uBB_zpg + TMP2 = read_pc(); + if(DECO16_VERBOSE) + logerror("%s: OPBB %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); + +vbl_zpg + TMP2 = read_pc(); + A = io->read_byte(0); + if(DECO16_VERBOSE) + logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2); + prefetch(); diff --git a/src/emu/cpu/m6502/om4510.lst b/src/emu/cpu/m6502/om4510.lst index e69de29bb2d..4728dd68786 100644 --- a/src/emu/cpu/m6502/om4510.lst +++ b/src/emu/cpu/m6502/om4510.lst @@ -0,0 +1,12 @@ +# 4510 opcodes + +eom_imp + inhibit_interrupts = false; // before or after prefetch? + prefetch(); + +map_imp + inhibit_interrupts = true; + map_offset[0] = (A<<8) | ((X & 0xf) << 16); + map_offset[1] = (Y<<8) | ((Z & 0xf) << 16); + map_enable = ((X & 0xf0) >> 4) | (Z & 0xf0); + prefetch(); diff --git a/src/emu/cpu/m6502/om6502.lst b/src/emu/cpu/m6502/om6502.lst index e69de29bb2d..5c3295324a0 100644 --- a/src/emu/cpu/m6502/om6502.lst +++ b/src/emu/cpu/m6502/om6502.lst @@ -0,0 +1,1962 @@ +# NMOS 6502 opcodes +# Verified with visual6502 +# documented opcodes + +adc_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_adc(TMP); + prefetch(); + +adc_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_adc(TMP); + prefetch(); + +adc_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_adc(TMP); + prefetch(); + +adc_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_adc(read(TMP)); + prefetch(); + +adc_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_adc(read(TMP+Y)); + prefetch(); + +adc_imm + TMP = read_pc(); + do_adc(TMP); + prefetch(); + +adc_zpg + TMP = read_pc(); + TMP = read(TMP); + do_adc(TMP); + prefetch(); + +adc_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_adc(TMP); + prefetch(); + +and_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A &= read(TMP); + set_nz(A); + prefetch(); + +and_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + A &= read(TMP); + set_nz(A); + prefetch(); + +and_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + A &= read(TMP); + set_nz(A); + prefetch(); + +and_imm + A &= read_pc(); + set_nz(A); + prefetch(); + +and_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A &= read(TMP); + set_nz(A); + prefetch(); + +and_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + A &= read(TMP+Y); + set_nz(A); + prefetch(); + +and_zpg + TMP = read_pc(); + A &= read(TMP); + set_nz(A); + prefetch(); + +and_zpx + TMP = read_pc(); + read(TMP); + A &= read(UINT8(TMP+X)); + set_nz(A); + prefetch(); + +asl_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_acc + read_pc_noinc(); + A = do_asl(A); + prefetch(); + +asl_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +bcc_rel + TMP = read_pc(); + if(!(P & F_C)) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +bcs_rel + TMP = read_pc(); + if(P & F_C) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +beq_rel + TMP = read_pc(); + if(P & F_Z) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +bit_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + do_bit(read(TMP)); + prefetch(); + +bit_zpg + TMP = read_pc(); + do_bit(read(TMP)); + prefetch(); + +bmi_rel + TMP = read_pc(); + if(P & F_N) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +bne_rel + TMP = read_pc(); + if(!(P & F_Z)) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +bpl_rel + TMP = read_pc(); + if(!(P & F_N)) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +brk_imp + // The 6502 bug when a nmi occurs in a brk is reproduced (case !irq_taken && nmi_state) + if(irq_taken) { + read_pc_noinc(); + } else { + read_pc(); + } + write(SP, PC >> 8); + dec_SP(); + write(SP, PC); + dec_SP(); + write(SP, irq_taken ? P & ~F_B : P); + dec_SP(); + if(nmi_state) { + PC = read_direct(0xfffa); + PC = set_h(PC, read_direct(0xfffb)); + nmi_state = false; + } else { + PC = read_direct(0xfffe); + PC = set_h(PC, read_direct(0xffff)); + } + irq_taken = false; + P |= F_I; // Do *not* move after the prefetch + prefetch(); + inst_state = -1; + +bvc_rel + TMP = read_pc(); + if(!(P & F_V)) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +bvs_rel + TMP = read_pc(); + if(P & F_V) { + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + } + prefetch(); + +clc_imp + read_pc_noinc(); + P &= ~F_C; + prefetch(); + +cld_imp + read_pc_noinc(); + P &= ~F_D; + prefetch(); + +cli_imp + read_pc_noinc(); + prefetch(); + P &= ~F_I; // Do *not* move it before the prefetch + +clv_imp + read_pc_noinc(); + P &= ~F_V; + prefetch(); + +cmp_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_cmp(A, read(TMP)); + prefetch(); + +cmp_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_cmp(A, read(TMP+Y)); + prefetch(); + +cmp_imm + TMP = read_pc(); + do_cmp(A, TMP); + prefetch(); + +cmp_zpg + TMP = read_pc(); + TMP = read(TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_cmp(A, TMP); + prefetch(); + +cpx_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_cmp(X, TMP); + prefetch(); + +cpx_imm + TMP = read_pc(); + do_cmp(X, TMP); + prefetch(); + +cpx_zpg + TMP = read_pc(); + TMP = read(TMP); + do_cmp(X, TMP); + prefetch(); + +cpy_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_cmp(Y, TMP); + prefetch(); + +cpy_imm + TMP = read_pc(); + do_cmp(Y, TMP); + prefetch(); + +cpy_zpg + TMP = read_pc(); + TMP = read(TMP); + do_cmp(Y, TMP); + prefetch(); + +dec_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dex_imp + read_pc_noinc(); + X--; + set_nz(X); + prefetch(); + +dey_imp + read_pc_noinc(); + Y--; + set_nz(Y); + prefetch(); + +eor_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + A ^= read(TMP+Y); + set_nz(A); + prefetch(); + +eor_imm + A ^= read_pc(); + set_nz(A); + prefetch(); + +eor_zpg + TMP = read_pc(); + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_zpx + TMP = read_pc(); + read(TMP); + A ^= read(UINT8(TMP+X)); + set_nz(A); + prefetch(); + +inc_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inx_imp + read_pc_noinc(); + X++; + set_nz(X); + prefetch(); + +iny_imp + read_pc_noinc(); + Y++; + set_nz(Y); + prefetch(); + +jmp_adr + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + PC = TMP; + prefetch(); + +jmp_ind + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + PC = read(TMP); + PC = set_h(PC, read(set_l(TMP, TMP+1))); + prefetch(); + +jsr_adr + TMP = read_pc(); + read(SP); + write(SP, PC>>8); + dec_SP(); + write(SP, PC); + dec_SP(); + TMP = set_h(TMP, read_pc()); + PC = TMP; + prefetch(); + +lda_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A = read(TMP); + set_nz(A); + prefetch(); + +lda_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + A = read(TMP + X); + set_nz(A); + prefetch(); + +lda_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + A = read(TMP + Y); + set_nz(A); + prefetch(); + +lda_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A = read(TMP); + set_nz(A); + prefetch(); + +lda_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + A = read(TMP+Y); + set_nz(A); + prefetch(); + +lda_imm + A = read_pc(); + set_nz(A); + prefetch(); + +lda_zpg + TMP = read_pc(); + A = read(TMP); + set_nz(A); + prefetch(); + +lda_zpx + TMP = read_pc(); + read(TMP); + A = read(UINT8(TMP+X)); + set_nz(A); + prefetch(); + +ldx_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + X = read(TMP); + set_nz(X); + prefetch(); + +ldx_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + X = read(TMP + Y); + set_nz(X); + prefetch(); + +ldx_imm + X = read_pc(); + set_nz(X); + prefetch(); + +ldx_zpg + TMP = read_pc(); + X = read(TMP); + set_nz(X); + prefetch(); + +ldx_zpy + TMP = read_pc(); + read(TMP); + X = read(UINT8(TMP+Y)); + set_nz(X); + prefetch(); + +ldy_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + Y = read(TMP); + set_nz(Y); + prefetch(); + +ldy_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + Y = read(TMP); + set_nz(Y); + prefetch(); + +ldy_imm + Y = read_pc(); + set_nz(Y); + prefetch(); + +ldy_zpg + TMP = read_pc(); + Y = read(TMP); + set_nz(Y); + prefetch(); + +ldy_zpx + TMP = read_pc(); + read(TMP); + Y = read(UINT8(TMP+X)); + set_nz(Y); + prefetch(); + +lsr_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_acc + read_pc_noinc(); + A = do_lsr(A); + prefetch(); + +lsr_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +nop_imp + read_pc_noinc(); + prefetch(); + +ora_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_imm + A |= read_pc(); + set_nz(A); + prefetch(); + +ora_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + A |= read(TMP+Y); + set_nz(A); + prefetch(); + +ora_zpg + TMP = read_pc(); + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_zpx + TMP = read_pc(); + read(TMP); + A |= read(UINT8(TMP+X)); + set_nz(A); + prefetch(); + +pha_imp + read_pc_noinc(); + write(SP, A); + dec_SP(); + prefetch(); + +php_imp + read_pc_noinc(); + write(SP, P); + dec_SP(); + prefetch(); + +pla_imp + read_pc_noinc(); + read(SP); + inc_SP(); + A = read(SP); + set_nz(A); + prefetch(); + +plp_imp + read_pc_noinc(); + read(SP); + inc_SP(); + TMP = read(SP) | (F_B|F_E); + prefetch(); + P = TMP; // Do *not* move it before the prefetch + +rol_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_acc + read_pc_noinc(); + A = do_rol(A); + prefetch(); + +rol_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_acc + read_pc_noinc(); + A = do_ror(A); + prefetch(); + +ror_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +rti_imp + read_pc_noinc(); + read(SP); + inc_SP(); + P = read(SP) | (F_B|F_E); + inc_SP(); + PC = read(SP); + inc_SP(); + PC = set_h(PC, read(SP)); + prefetch(); + +rts_imp + read_pc_noinc(); + read(SP); + inc_SP(); + PC = read(SP); + inc_SP(); + PC = set_h(PC, read(SP)); + read_pc(); + prefetch(); + +sbc_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_sbc(TMP); + prefetch(); + +sbc_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_sbc(TMP); + prefetch(); + +sbc_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_sbc(TMP); + prefetch(); + +sbc_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_sbc(read(TMP)); + prefetch(); + +sbc_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_sbc(read(TMP+Y)); + prefetch(); + +sbc_imm + TMP = read_pc(); + do_sbc(TMP); + prefetch(); + +sbc_zpg + TMP = read_pc(); + TMP = read(TMP); + do_sbc(TMP); + prefetch(); + +sbc_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_sbc(TMP); + prefetch(); + +sec_imp + read_pc_noinc(); + P |= F_C; + prefetch(); + +sed_imp + read_pc_noinc(); + P |= F_D; + prefetch(); + +sei_imp + read_pc_noinc(); + prefetch(); + P |= F_I; // Do *not* move it before the prefetch + +sta_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP, A); + prefetch(); + +sta_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + write(TMP+X, A); + prefetch(); + +sta_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + write(TMP+Y, A); + prefetch(); + +sta_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + write(TMP, A); + prefetch(); + +sta_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + write(TMP+Y, A); + prefetch(); + +sta_zpg + TMP = read_pc(); + write(TMP, A); + prefetch(); + +sta_zpx + TMP = read_pc(); + read(TMP); + write(UINT8(TMP+X), A); + prefetch(); + +stx_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP, X); + prefetch(); + +stx_zpg + TMP = read_pc(); + write(TMP, X); + prefetch(); + +stx_zpy + TMP = read_pc(); + read(TMP); + write(UINT8(TMP+Y), X); + prefetch(); + +sty_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP, Y); + prefetch(); + +sty_zpg + TMP = read_pc(); + write(TMP, Y); + prefetch(); + +sty_zpx + TMP = read_pc(); + read(TMP); + write(UINT8(TMP+X), Y); + prefetch(); + +tax_imp + read_pc_noinc(); + X = A; + set_nz(X); + prefetch(); + +tay_imp + read_pc_noinc(); + Y = A; + set_nz(Y); + prefetch(); + +tsx_imp + read_pc_noinc(); + X = SP; + set_nz(X); + prefetch(); + +txa_imp + read_pc_noinc(); + A = X; + set_nz(A); + prefetch(); + +txs_imp + read_pc_noinc(); + SP = set_l(SP, X); + prefetch(); + +tya_imp + read_pc_noinc(); + A = Y; + set_nz(A); + prefetch(); + +# exceptions +reset + PC = read_direct(0xfffc); + PC = set_h(PC, read_direct(0xfffd)); + prefetch(); + inst_state = -1; + + +# undocumented reliable instructions +dcp_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +dcp_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +dcp_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +dcp_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +dcp_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +dcp_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +dcp_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2--; + write(TMP, TMP2); + do_cmp(A, TMP2); + prefetch(); + +isb_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +isb_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +isb_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +isb_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +isb_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +isb_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +isb_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc(TMP2); + prefetch(); + +lax_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A = X = read(TMP); + set_nz(A); + prefetch(); + +lax_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + A = X = read(TMP); + set_nz(A); + prefetch(); + +lax_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A = X = read(TMP); + set_nz(A); + prefetch(); + +lax_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + A = X = read(TMP+Y); + set_nz(A); + prefetch(); + +lax_zpg + TMP = read_pc(); + A = X = read(TMP); + set_nz(A); + prefetch(); + +lax_zpy + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+Y); + A = X = read(TMP); + set_nz(A); + prefetch(); + +rla_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rla_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rla_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rla_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rla_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rla_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rla_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + A &= TMP2; + set_nz(A); + prefetch(); + +rra_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +rra_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +rra_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +rra_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +rra_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +rra_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +rra_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc(TMP2); + prefetch(); + +sax_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = A & X; + write(TMP, TMP2); + prefetch(); + +sax_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = A & X; + write(TMP, TMP2); + prefetch(); + +sax_zpg + TMP = read_pc(); + TMP2 = A & X; + write(TMP, TMP2); + prefetch(); + +sax_zpy + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+Y); + TMP2 = A & X; + write(TMP, TMP2); + prefetch(); + +sbx_imm + TMP2 = read_pc(); + X &= A; + if(X < TMP2) + P &= ~F_C; + else + P |= F_C; + X -= TMP2; + set_nz(X); + prefetch(); + +sha_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP2 = A & X & ((TMP >> 8)+1); + if(page_changing(TMP, Y)) + TMP = set_h(TMP+Y, TMP2); + else + TMP += Y; + write(TMP, TMP2); + prefetch(); + +sha_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP2 = A & X & ((TMP >> 8)+1); + if(page_changing(TMP, Y)) + TMP = set_h(TMP+Y, TMP2); + else + TMP += Y; + write(TMP, TMP2); + prefetch(); + +shs_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + SP = set_l(SP, A & X); + TMP2 = A & X & ((TMP >> 8)+1); + if(page_changing(TMP, Y)) + TMP = set_h(TMP+Y, TMP2); + else + TMP += Y; + write(TMP, TMP2); + prefetch(); + +shx_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP2 = X & ((TMP >> 8)+1); + if(page_changing(TMP, Y)) + TMP = set_h(TMP+Y, TMP2); + else + TMP += Y; + write(TMP, TMP2); + prefetch(); + +shy_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP2 = Y & ((TMP >> 8)+1); + if(page_changing(TMP, X)) + TMP = set_h(TMP+X, TMP2); + else + TMP += X; + write(TMP, TMP2); + prefetch(); + +slo_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +slo_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +slo_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +slo_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +slo_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +slo_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +slo_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + A |= TMP2; + set_nz(A); + prefetch(); + +sre_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +sre_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +sre_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +sre_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +sre_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +sre_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +sre_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + A ^= TMP2; + set_nz(A); + prefetch(); + +# undocumented unreliable instructions +anc_imm + read_pc(); + set_nz(A); + if(A & 0x80) + P |= F_C; + else + P &= ~F_C; + prefetch(); + +ane_imm + TMP2 = read_pc(); + A &= TMP2 & X; + set_nz(A); + prefetch(); + +asr_imm + read_pc(); + A = do_lsr(A); + prefetch(); + +arr_imm + read_pc(); + do_arr(); + prefetch(); + +las_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP2 = read(TMP+Y); + A = TMP2 | 0x51; + X = 0xff; + set_nz(TMP2); + prefetch(); + +lxa_imm + TMP2 = read_pc(); + A = X = A & TMP2; + set_nz(A); + prefetch(); + +# nop variants +nop_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(TMP); + prefetch(); + +nop_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + read(TMP + X); + prefetch(); + +nop_imm + read_pc(); + prefetch(); + +nop_zpg + TMP = read_pc(); + read(TMP); + prefetch(); + +nop_zpx + TMP = read_pc(); + read(TMP); + read(UINT8(TMP+X)); + prefetch(); + +# system killers +kil_non + read_pc(); + read(0xffff); + read(0xfffe); + read(0xfffe); + for(;;) { + read(0xffff); + } diff --git a/src/emu/cpu/m6502/om6509.lst b/src/emu/cpu/m6502/om6509.lst index e69de29bb2d..f09d8f7d5f1 100644 --- a/src/emu/cpu/m6502/om6509.lst +++ b/src/emu/cpu/m6502/om6509.lst @@ -0,0 +1,20 @@ +# 6509 opcodes + +lda_9_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read_9(set_l(TMP, TMP+Y)); + } + A = read_9(TMP+Y); + set_nz(A); + prefetch(); + +sta_9_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read_9(set_l(TMP, TMP+Y)); + write_9(TMP+Y, A); + prefetch(); diff --git a/src/emu/cpu/m6502/om6510.lst b/src/emu/cpu/m6502/om6510.lst index e69de29bb2d..e08a5229111 100644 --- a/src/emu/cpu/m6502/om6510.lst +++ b/src/emu/cpu/m6502/om6510.lst @@ -0,0 +1,46 @@ +# 6510 undocumented instructions in a C64 context +anc_10_imm + TMP2 = read_pc(); + A &= TMP2; + set_nz(A); + if(A & 0x80) + P |= F_C; + else + P &= ~F_C; + prefetch(); + +ane_10_imm + TMP2 = read_pc(); + A = (A | 0xee) & TMP2 & X; + set_nz(A); + prefetch(); + +asr_10_imm + TMP2 = read_pc(); + A = do_lsr(A & TMP2); + set_nz(A); + prefetch(); + +arr_10_imm + TMP2 = read_pc(); + A &= TMP2; + do_arr(); + prefetch(); + +las_10_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP2 = read(TMP+Y); + A = X = TMP2 & SP; + SP = set_l(SP, A); + set_nz(A); + prefetch(); + +lxa_10_imm + TMP2 = read_pc(); + A = X = (A | 0xee) & TMP2; + set_nz(A); + prefetch(); diff --git a/src/emu/cpu/m6502/om65c02.lst b/src/emu/cpu/m6502/om65c02.lst index e69de29bb2d..8fef0da41fb 100644 --- a/src/emu/cpu/m6502/om65c02.lst +++ b/src/emu/cpu/m6502/om65c02.lst @@ -0,0 +1,581 @@ +# m65c02 opcodes + +adc_c_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_adc(read(TMP)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_adc(read(TMP+Y)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_imm + TMP = read_pc(); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_zpg + TMP = read_pc(); + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_adc(read(TMP)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +adc_c_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_adc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +and_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A &= read(TMP); + set_nz(A); + prefetch(); + +asl_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +bbr_zpb + // Access pattern uncertain + TMP = read_pc(); + TMP2 = read(TMP); + TMP = read_pc(); + read_pc_noinc(); + if(!(TMP2 & (1 << (inst_state & 7)))) { + PC += INT8(TMP); + } + prefetch(); + +bbs_zpb + // Access pattern uncertain + TMP = read_pc(); + TMP2 = read(TMP); + TMP = read_pc(); + read_pc_noinc(); + if(TMP2 & (1 << (inst_state & 7))) { + PC += INT8(TMP); + } + prefetch(); + +bit_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + do_bit(read(TMP)); + prefetch(); + +bit_imm + TMP = read_pc(); + if(A & TMP) + P &= ~F_Z; + else + P |= F_Z; + prefetch(); + +bit_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_bit(TMP); + prefetch(); + +bra_rel + TMP = read_pc(); + read_pc_noinc(); + if(page_changing(PC, INT8(TMP))) { + read_direct(set_l(PC, PC+INT8(TMP))); + } + PC += INT8(TMP); + prefetch(); + +brk_c_imp + if(irq_taken || nmi_state) { + read_pc_noinc(); + } else { + read_pc(); + } + write(SP, PC >> 8); + dec_SP(); + write(SP, PC); + dec_SP(); + write(SP, irq_taken || nmi_state ? P & ~F_B : P); + dec_SP(); + if(irq_taken && nmi_state) { + PC = read_direct(0xfffa); + PC = set_h(PC, read_direct(0xfffb)); + nmi_state = false; + } else { + PC = read_direct(0xfffe); + PC = set_h(PC, read_direct(0xffff)); + } + irq_taken = false; + P = (P | F_I) & ~F_D; // Do *not* move after the prefetch + prefetch(); + inst_state = -1; + +cmp_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_cmp(A, read(TMP)); + prefetch(); + +dec_acc + read_pc_noinc(); + A--; + set_nz(A); + prefetch(); + +eor_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A ^= read(TMP); + set_nz(A); + prefetch(); + +inc_acc + read_pc_noinc(); + A++; + set_nz(A); + prefetch(); + +jmp_iax + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +jmp_c_ind + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + PC = read(TMP); + read(set_l(TMP, TMP+1)); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +lda_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A = read(TMP); + set_nz(A); + prefetch(); + + +lsr_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +nop_c_imp + prefetch(); + +nop_c_aba + read_pc(); + read_pc(); + read_pc_noinc(); + read_pc_noinc(); + read_pc_noinc(); + read_pc_noinc(); + read_pc_noinc(); + prefetch(); + +nop_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + prefetch(); + +ora_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + A |= read(TMP); + set_nz(A); + prefetch(); + +phx_imp + read_pc_noinc(); + write(SP, X); + dec_SP(); + prefetch(); + +phy_imp + read_pc_noinc(); + write(SP, Y); + dec_SP(); + prefetch(); + +plx_imp + read_pc_noinc(); + read(SP); + inc_SP(); + X = read(SP); + set_nz(X); + prefetch(); + +ply_imp + read_pc_noinc(); + read(SP); + inc_SP(); + Y = read(SP); + set_nz(Y); + prefetch(); + +rmb_bzp + // Access pattern unknown but probable (built upon inc_zpg) + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 &= ~(1 << (inst_state & 7)); + write(TMP, TMP2); + prefetch(); + +rol_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + + +ror_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +sbc_c_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_sbc(read(TMP)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_sbc(read(TMP+Y)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_imm + TMP = read_pc(); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_zpg + TMP = read_pc(); + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_sbc(read(TMP)); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +sbc_c_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_sbc(TMP); + if(P & F_D) { + read_pc_noinc(); + set_nz(A); + } + prefetch(); + +smb_bzp + // Access pattern unknown but probable (built upon inc_zpg) + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 |= 1 << (inst_state & 7); + write(TMP, TMP2); + prefetch(); + +sta_zpi + TMP2 = read_pc(); + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + write(TMP, A); + prefetch(); + +stp_imp + for(;;) { + eat-all-cycles; + } + +stz_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP, 0x00); + prefetch(); + +stz_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + write(TMP+X, 0x00); + prefetch(); + +stz_zpg + TMP = read_pc(); + write(TMP, 0x00); + prefetch(); + +stz_zpx + TMP = read_pc(); + read(TMP); + write(UINT8(TMP+X), 0x00); + prefetch(); + +trb_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 &= ~A; + write(TMP, TMP2); + prefetch(); + +trb_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 &= ~A; + write(TMP, TMP2); + prefetch(); + +tsb_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 |= A; + write(TMP, TMP2); + prefetch(); + +tsb_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 |= A; + write(TMP, TMP2); + prefetch(); + +wai_imp + read_pc_noinc(); + read_pc_noinc(); + while(!nmi_state && !irq_state) { + eat-all-cycles; + } + prefetch(); diff --git a/src/emu/cpu/m6502/om65ce02.lst b/src/emu/cpu/m6502/om65ce02.lst index e69de29bb2d..2c59ffb01dc 100644 --- a/src/emu/cpu/m6502/om65ce02.lst +++ b/src/emu/cpu/m6502/om65ce02.lst @@ -0,0 +1,1532 @@ +# 65ce02 opcodes, a lot only remove dummy read/write cycles, some are new, some use the B register + +adc_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += Y; + TMP = read(TMP); + do_adc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_adc(read(TMP)); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_adc(read(TMP+Y)); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_adc(read(TMP+Z)); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_imm + TMP = read_pc(); + do_adc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_zpg + TMP = read_pc(); + TMP = read(B|TMP); + do_adc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +adc_ce_zpx + TMP = read_pc(); + TMP = read(B|UINT8(TMP+X)); + do_adc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +and_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + A &= read(TMP); + set_nz(A); + prefetch(); + +and_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += Y; + A &= read(TMP); + set_nz(A); + prefetch(); + +and_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A &= read(TMP); + set_nz(A); + prefetch(); + +and_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A &= read(TMP+Y); + set_nz(A); + prefetch(); + +and_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A &= read(TMP+Z); + set_nz(A); + prefetch(); + +and_ce_zpg + TMP = read_pc(); + A &= read(B|TMP); + set_nz(A); + prefetch(); + +and_ce_zpx + TMP = read_pc(); + A &= read(B|UINT8(TMP+X)); + set_nz(A); + prefetch(); + +asl_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP2 = read(TMP); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_ce_acc + A = do_asl(A); + prefetch(); + +asl_ce_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asl_ce_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2 = do_asl(TMP2); + write(TMP, TMP2); + prefetch(); + +asr_acc + A = do_asr(A); + prefetch(); + +asr_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2 = do_asr(TMP2); + write(TMP, TMP2); + prefetch(); + +asr_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2 = do_asr(TMP2); + write(TMP, TMP2); + prefetch(); + +asw_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP3 = read(TMP); + TMP3 = set_h(TMP3, read(TMP+1)); + P &= ~(F_C|F_N|F_Z); + if(TMP3 & 0x8000) + P |= F_C; + TMP3 <<= 1; + if(!TMP3) + P |= F_Z; + else if(TMP3 & 0x8000) + P |= F_N; + write(TMP, TMP3); + write(TMP, TMP3 >> 8); + prefetch(); + +aug_iw3 + read_pc(); + read_pc(); + read_pc(); + prefetch(); + +bbr_ce_zpb + // Access pattern uncertain + TMP = read_pc(); + TMP2 = read(TMP); + TMP = read_pc(); + if(!(TMP2 & (1 << (inst_state & 7)))) + PC += INT8(TMP); + prefetch(); + +bbs_ce_zpb + // Access pattern uncertain + TMP = read_pc(); + TMP2 = read(TMP); + TMP = read_pc(); + if(TMP2 & (1 << (inst_state & 7))) + PC += INT8(TMP); + prefetch(); + +bcc_ce_rel + TMP = read_pc(); + if(!(P & F_C)) + PC += INT8(TMP); + prefetch(); + +bcc_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(!(P & F_C)) + PC += TMP; + prefetch(); + +bcs_ce_rel + TMP = read_pc(); + if(P & F_C) + PC += INT8(TMP); + prefetch(); + +bcs_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(P & F_C) + PC += TMP; + prefetch(); + +beq_ce_rel + TMP = read_pc(); + if(P & F_Z) + PC += INT8(TMP); + prefetch(); + +beq_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(P & F_Z) + PC += TMP; + prefetch(); + +bit_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + do_bit(read(TMP)); + prefetch(); + +bit_ce_imm + TMP = read_pc(); + do_bit(TMP); + prefetch(); + +bit_ce_zpg + TMP = B|read_pc(); + do_bit(read(TMP)); + prefetch(); + +bit_ce_zpx + TMP = read_pc(); + TMP = read(B|UINT8(TMP+X)); + do_bit(TMP); + prefetch(); + +bmi_ce_rel + TMP = read_pc(); + if(P & F_N) + PC += INT8(TMP); + prefetch(); + +bmi_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(P & F_N) + PC += TMP; + prefetch(); + +bne_ce_rel + TMP = read_pc(); + if(!(P & F_Z)) + PC += INT8(TMP); + prefetch(); + +bne_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(!(P & F_Z)) + PC += TMP; + prefetch(); + +bpl_ce_rel + TMP = read_pc(); + if(!(P & F_N)) + PC += INT8(TMP); + prefetch(); + +bpl_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(!(P & F_N)) + PC += TMP; + prefetch(); + +bra_ce_rel + TMP = read_pc(); + PC += INT8(TMP); + prefetch(); + +bra_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + PC += TMP; + prefetch(); + +brk_ce_imp + if(irq_taken) { + read_pc_noinc(); + } else { + read_pc(); + } + write(SP, PC >> 8); + dec_SP_ce(); + write(SP, PC); + dec_SP_ce(); + write(SP, irq_taken || nmi_state ? P & ~F_B : P); + dec_SP_ce(); + if(nmi_state) { + PC = read_direct(0xfffa); + PC = set_h(PC, read_direct(0xfffb)); + nmi_state = false; + } else { + PC = read_direct(0xfffe); + PC = set_h(PC, read_direct(0xffff)); + } + irq_taken = false; + P = (P | F_I) & ~F_D; // Do *not* move after the prefetch + prefetch(); + inst_state = -1; + +bsr_rw2 + TMP = read_pc(); + write(SP, PC>>8); + dec_SP_ce(); + write(SP, PC); + dec_SP_ce(); + TMP = set_h(TMP, read_pc()); + PC += TMP; + prefetch(); + +bvc_ce_rel + TMP = read_pc(); + if(!(P & F_V)) + PC += INT8(TMP); + prefetch(); + +bvc_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(!(P & F_V)) + PC += TMP; + prefetch(); + +bvs_ce_rel + TMP = read_pc(); + if(P & F_V) + PC += INT8(TMP); + prefetch(); + +bvs_rw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(P & F_V) + PC += TMP; + prefetch(); + +clc_ce_imp + P &= ~F_C; + prefetch(); + +cld_ce_imp + P &= ~F_D; + prefetch(); + +cle_imp + read_pc_noinc(); + P &= ~F_E; + prefetch(); + +cli_ce_imp + prefetch(); + P &= ~F_I; // Do *not* move it before the prefetch + +clv_ce_imp + P &= ~F_V; + prefetch(); + +cmp_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP = read(TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += Y; + TMP = read(TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_cmp(A, read(TMP)); + prefetch(); + +cmp_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_cmp(A, read(TMP+Y)); + prefetch(); + +cmp_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_cmp(A, read(TMP+Z)); + prefetch(); + +cmp_ce_zpg + TMP = read_pc(); + TMP = read(B|TMP); + do_cmp(A, TMP); + prefetch(); + +cmp_ce_zpx + TMP = read_pc(); + read(TMP); + TMP = read(B|UINT8(TMP+X)); + do_cmp(A, TMP); + prefetch(); + +cpx_ce_zpg + TMP = read_pc(); + TMP = read(B|TMP); + do_cmp(X, TMP); + prefetch(); + +cpy_ce_zpg + TMP = read_pc(); + TMP = read(B|TMP); + do_cmp(Y, TMP); + prefetch(); + +cpz_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_cmp(Z, TMP); + prefetch(); + +cpz_imm + TMP = read_pc(); + do_cmp(Z, TMP); + prefetch(); + +cpz_zpg + TMP = read_pc(); + TMP = read(B|TMP); + do_cmp(Z, TMP); + prefetch(); + +dec_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP2 = read(TMP); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_ce_acc + A--; + set_nz(A); + prefetch(); + +dec_ce_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dec_ce_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2--; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +dew_zpg + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + P &= ~(F_N|F_Z); + TMP++; + if(!TMP) + P |= F_Z; + else if(TMP & 0x8000) + P |= F_N; + TMP2++; + write(B|TMP2, TMP); + TMP2++; + write(B|TMP2, TMP >> 8); + prefetch(); + +dex_ce_imp + X--; + set_nz(X); + prefetch(); + +dey_ce_imp + Y--; + set_nz(Y); + prefetch(); + +dez_imp + Z--; + set_nz(Z); + prefetch(); + +eor_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += Y; + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A ^= read(TMP); + set_nz(A); + prefetch(); + +eor_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A ^= read(TMP+Y); + set_nz(A); + prefetch(); + +eor_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A ^= read(TMP+Z); + set_nz(A); + prefetch(); + +eor_ce_zpg + TMP = read_pc(); + A ^= read(B|TMP); + set_nz(A); + prefetch(); + +eor_ce_zpx + TMP = read_pc(); + A ^= read(B|UINT8(TMP+X)); + set_nz(A); + prefetch(); + +inc_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP2 = read(TMP); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_ce_acc + A++; + set_nz(A); + prefetch(); + +inc_ce_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inc_ce_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2++; + set_nz(TMP2); + write(TMP, TMP2); + prefetch(); + +inw_zpg + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + P &= ~(F_N|F_Z); + TMP++; + if(!TMP) + P |= F_Z; + else if(TMP & 0x8000) + P |= F_N; + TMP2--; + write(B|TMP2, TMP); + TMP2++; + write(B|TMP2, TMP >> 8); + prefetch(); + +inx_ce_imp + X++; + set_nz(X); + prefetch(); + +iny_ce_imp + Y++; + set_nz(Y); + prefetch(); + +inz_imp + Z++; + set_nz(Z); + prefetch(); + +jmp_ce_iax + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +jmp_ce_ind + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +jsr_ce_adr + TMP = read_pc(); + write(SP, PC>>8); + dec_SP_ce(); + write(SP, PC); + dec_SP_ce(); + TMP = set_h(TMP, read_pc()); + PC = TMP; + prefetch(); + +jsr_iax + TMP = read_pc(); + write(SP, PC>>8); + dec_SP_ce(); + write(SP, PC); + dec_SP_ce(); + TMP = set_h(TMP, read_pc()); + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + PC += X; + prefetch(); + +jsr_ind + TMP = read_pc(); + write(SP, PC>>8); + dec_SP_ce(); + write(SP, PC); + dec_SP_ce(); + TMP = set_h(TMP, read_pc()); + PC = read(TMP); + PC = set_h(PC, read(TMP+1)); + prefetch(); + +lda_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A = read(TMP + X); + set_nz(A); + prefetch(); + +lda_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + A = read(TMP + Y); + set_nz(A); + prefetch(); + +lda_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A = read(TMP); + set_nz(A); + prefetch(); + +lda_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A = read(TMP+Y); + set_nz(A); + prefetch(); + +lda_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A = read(TMP+Z); + set_nz(A); + prefetch(); + +lda_isy + read_pc_noinc(); + TMP = read_pc(); + if(P & F_E) + TMP = set_l(SP, SP+TMP); + else + TMP = SP + TMP; + TMP2 = read(TMP); + TMP++; + TMP = TMP2 | (read(TMP) << 8); + A = read(TMP+Y); + set_nz(A); + prefetch(); + +lda_ce_zpg + TMP = read_pc(); + A = read(B|TMP); + set_nz(A); + prefetch(); + +lda_ce_zpx + TMP = read_pc(); + A = read(B|UINT8(TMP+X)); + set_nz(A); + prefetch(); + +ldx_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + X = read(TMP + Y); + set_nz(X); + prefetch(); + +ldx_ce_zpg + TMP = read_pc(); + X = read(B|TMP); + set_nz(X); + prefetch(); + +ldx_ce_zpy + TMP = read_pc(); + X = read(B|UINT8(TMP+Y)); + set_nz(X); + prefetch(); + +ldy_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + Y = read(TMP); + set_nz(Y); + prefetch(); + +ldy_ce_zpg + TMP = read_pc(); + Y = read(B|TMP); + set_nz(Y); + prefetch(); + +ldy_ce_zpx + TMP = read_pc(); + Y = read(B|UINT8(TMP+X)); + set_nz(Y); + prefetch(); + +ldz_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + Z = read(TMP); + set_nz(Z); + prefetch(); + +ldz_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + Z = read(TMP + X); + set_nz(Z); + prefetch(); + +ldz_imm + Z = read_pc(); + set_nz(Z); + prefetch(); + +lsr_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_ce_acc + A = do_lsr(A); + prefetch(); + +lsr_ce_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +lsr_ce_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2 = do_lsr(TMP2); + write(TMP, TMP2); + prefetch(); + +neg_acc + read_pc_noinc(); + A = -A; + set_nz(A); + prefetch(); + +ora_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += Y; + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A |= read(TMP); + set_nz(A); + prefetch(); + +ora_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A |= read(TMP+Y); + set_nz(A); + prefetch(); + +ora_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + A |= read(TMP+Z); + set_nz(A); + prefetch(); + +ora_ce_zpg + TMP = read_pc(); + A |= read(B|TMP); + set_nz(A); + prefetch(); + +ora_ce_zpx + TMP = read_pc(); + A |= read(B|UINT8(TMP+X)); + set_nz(A); + prefetch(); + +# push/pop instructions and rti/rtn/rts are not fully streamlined +pha_ce_imp + read_pc_noinc(); + write(SP, A); + dec_SP_ce(); + prefetch(); + +php_ce_imp + read_pc_noinc(); + write(SP, P); + dec_SP_ce(); + prefetch(); + +phw_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP3 = read(TMP); + TMP3 = set_h(TMP3, read(TMP+1)); + dec_SP_ce(); + write(SP, TMP3); + dec_SP_ce(); + write(SP, TMP3 >> 8); + prefetch(); + +phw_iw2 + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + dec_SP_ce(); + write(SP, TMP); + dec_SP_ce(); + write(SP, TMP >> 8); + prefetch(); + +phx_ce_imp + read_pc_noinc(); + write(SP, X); + dec_SP_ce(); + prefetch(); + +phy_ce_imp + read_pc_noinc(); + write(SP, Y); + dec_SP_ce(); + prefetch(); + +phz_imp + read_pc_noinc(); + write(SP, Z); + dec_SP_ce(); + prefetch(); + +pla_ce_imp + read_pc_noinc(); + inc_SP_ce(); + A = read(SP); + set_nz(A); + prefetch(); + +plp_ce_imp + read_pc_noinc(); + inc_SP_ce(); + TMP = read(SP) | F_B; + prefetch(); + P = TMP; // Do *not* move it before the prefetch + +plx_ce_imp + read_pc_noinc(); + inc_SP_ce(); + X = read(SP); + set_nz(X); + prefetch(); + +ply_ce_imp + read_pc_noinc(); + inc_SP_ce(); + Y = read(SP); + set_nz(Y); + prefetch(); + +plz_imp + read_pc_noinc(); + inc_SP_ce(); + Z = read(SP); + set_nz(Z); + prefetch(); + +rmb_ce_bzp + TMP = read_pc(); + TMP2 = read(TMP); + TMP2 &= ~(1 << (inst_state & 7)); + write(TMP, TMP2); + prefetch(); + +rol_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP2 = read(TMP); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_ce_acc + A = do_rol(A); + prefetch(); + +rol_ce_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +rol_ce_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2 = do_rol(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP2 = read(TMP); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_ce_acc + A = do_ror(A); + prefetch(); + +ror_ce_zpg + TMP = B|read_pc(); + TMP2 = read(TMP); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +ror_ce_zpx + TMP = read_pc(); + TMP = B|UINT8(TMP+X); + TMP2 = read(TMP); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + prefetch(); + +row_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP3 = read(TMP); + TMP3 = set_h(TMP3, read(TMP+1)); + TMP2 = P; + P &= ~(F_C|F_N|F_Z); + if(TMP3 & 0x8000) + P |= F_C; + TMP3 <<= 1; + if(TMP2 & F_C) + TMP3 |= 0x0001; + if(!TMP3) + P |= F_Z; + else if(TMP3 & 0x8000) + P |= F_N; + write(TMP, TMP3); + write(TMP, TMP3 >> 8); + prefetch(); + +rti_ce_imp + read_pc_noinc(); + inc_SP_ce(); + P = read(SP) | F_B; + inc_SP_ce(); + PC = read(SP); + inc_SP_ce(); + PC = set_h(PC, read(SP)); + prefetch(); + +rtn_imm + TMP = read_pc(); + if(P & F_E) + SP = set_l(SP, SP+TMP); + else + SP += TMP; + read_pc_noinc(); + read(SP); + inc_SP(); + PC = read(SP); + inc_SP(); + PC = set_h(PC, read(SP)); + read_pc(); + prefetch(); + +rts_ce_imp + inc_SP_ce(); + PC = read(SP); + inc_SP_ce(); + PC = set_h(PC, read(SP)); + read_pc(); + prefetch(); + +sbc_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += X; + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP += Y; + TMP = read(TMP); + do_sbc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_sbc(read(TMP)); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_sbc(read(TMP+Y)); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + do_sbc(read(TMP+Z)); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_imm + TMP = read_pc(); + do_sbc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_zpg + TMP = read_pc(); + TMP = read(B|TMP); + do_sbc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +sbc_ce_zpx + TMP = read_pc(); + read(TMP); + TMP = read(B|UINT8(TMP+X)); + do_sbc(TMP); + if(P & F_D) + set_nz(A); + prefetch(); + +sec_ce_imp + P |= F_C; + prefetch(); + +sed_ce_imp + P |= F_D; + prefetch(); + +see_imp + read_pc_noinc(); + P |= F_E; + prefetch(); + +sei_ce_imp + prefetch(); + P |= F_I; // Do *not* move it before the prefetch + +smb_ce_bzp + TMP = read_pc(); + TMP2 = read(TMP); + TMP2 |= 1 << (inst_state & 7); + write(TMP, TMP2); + prefetch(); + +sta_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP+X, A); + prefetch(); + +sta_ce_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP+Y, A); + prefetch(); + +sta_ce_idx + TMP2 = read_pc(); + TMP2 += X; + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + write(TMP, A); + prefetch(); + +sta_ce_idy + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + write(TMP+Y, A); + prefetch(); + +sta_idz + TMP2 = read_pc(); + TMP = read(B|TMP2); + TMP2++; + TMP = set_h(TMP, read(B|TMP2)); + write(TMP+Z, A); + prefetch(); + +sta_isy + read_pc_noinc(); + TMP = read_pc(); + if(P & F_E) + TMP = set_l(SP, SP+TMP); + else + TMP = SP + TMP; + TMP2 = read(TMP); + TMP++; + TMP = TMP2 | (read(TMP) << 8); + write(TMP+Y, A); + prefetch(); + +sta_ce_zpg + TMP = read_pc(); + write(B|TMP, A); + prefetch(); + +sta_ce_zpx + TMP = read_pc(); + write(B|UINT8(TMP+X), A); + prefetch(); + +stx_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP+Y, X); + prefetch(); + +stx_ce_zpg + TMP = read_pc(); + write(B|TMP, X); + prefetch(); + +stx_ce_zpy + TMP = read_pc(); + write(B|UINT8(TMP+Y), X); + prefetch(); + +sty_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP+X, Y); + prefetch(); + +sty_ce_zpg + TMP = read_pc(); + write(B|TMP, Y); + prefetch(); + +sty_ce_zpx + TMP = read_pc(); + write(B|UINT8(TMP+X), Y); + prefetch(); + +stz_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP, A); + prefetch(); + +stz_ce_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + write(TMP+X, A); + prefetch(); + +stz_ce_zpg + TMP = read_pc(); + write(B|TMP, Z); + prefetch(); + +stz_ce_zpx + TMP = read_pc(); + write(B|UINT8(TMP+X), Z); + prefetch(); + +tab_imp + B = A << 8; + prefetch(); + +tax_ce_imp + X = A; + set_nz(X); + prefetch(); + +tay_ce_imp + Y = A; + set_nz(Y); + prefetch(); + +taz_imp + Z = A; + set_nz(Z); + prefetch(); + +tba_imp + A = B >> 8; + set_nz(A); + prefetch(); + +trb_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 &= ~A; + write(TMP, TMP2); + prefetch(); + +trb_ce_zpg + TMP = read_pc(); + TMP2 = read(TMP); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 &= ~A; + write(TMP, TMP2); + prefetch(); + +tsb_ce_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 |= A; + write(TMP, TMP2); + prefetch(); + +tsb_ce_zpg + TMP = read_pc(); + TMP2 = read(TMP); + if(A & TMP2) + P &= ~F_Z; + else + P |= F_Z; + TMP2 |= A; + write(TMP, TMP2); + prefetch(); + +tsx_ce_imp + X = SP; + set_nz(X); + prefetch(); + +tsy_imp + Y = SP >> 8; + set_nz(Y); + prefetch(); + +txa_ce_imp + A = X; + set_nz(A); + prefetch(); + +txs_ce_imp + SP = set_l(SP, X); + prefetch_noirq(); + +tys_imp + SP = set_h(SP, Y); + prefetch(); + +tya_ce_imp + A = Y; + set_nz(A); + prefetch(); + +tza_imp + A = Z; + set_nz(A); + prefetch(); diff --git a/src/emu/cpu/m6502/on2a03.lst b/src/emu/cpu/m6502/on2a03.lst index e69de29bb2d..51231819376 100644 --- a/src/emu/cpu/m6502/on2a03.lst +++ b/src/emu/cpu/m6502/on2a03.lst @@ -0,0 +1,297 @@ +# n2a03 opcodes - same as 6502 but with d disabled +adc_nd_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_adc_nd(TMP); + prefetch(); + +adc_nd_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_adc_nd(TMP); + prefetch(); + +adc_nd_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_adc_nd(TMP); + prefetch(); + +adc_nd_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_adc_nd(read(TMP)); + prefetch(); + +adc_nd_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_adc_nd(read(TMP+Y)); + prefetch(); + +adc_nd_imm + TMP = read_pc(); + do_adc_nd(TMP); + prefetch(); + +adc_nd_zpg + TMP = read_pc(); + TMP = read(TMP); + do_adc_nd(TMP); + prefetch(); + +adc_nd_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_adc_nd(TMP); + prefetch(); + +arr_nd_imm + read_pc(); + do_arr_nd(); + prefetch(); + +rra_nd_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +rra_nd_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +rra_nd_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +rra_nd_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +rra_nd_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +rra_nd_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +rra_nd_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2 = do_ror(TMP2); + write(TMP, TMP2); + do_adc_nd(TMP2); + prefetch(); + +sbc_nd_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP = read(TMP); + do_sbc_nd(TMP); + prefetch(); + +sbc_nd_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, X)) { + read(set_l(TMP, TMP+X)); + } + TMP += X; + TMP = read(TMP); + do_sbc_nd(TMP); + prefetch(); + +sbc_nd_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + TMP += Y; + TMP = read(TMP); + do_sbc_nd(TMP); + prefetch(); + +sbc_nd_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + do_sbc_nd(read(TMP)); + prefetch(); + +sbc_nd_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + if(page_changing(TMP, Y)) { + read(set_l(TMP, TMP+Y)); + } + do_sbc_nd(read(TMP+Y)); + prefetch(); + +sbc_nd_imm + TMP = read_pc(); + do_sbc_nd(TMP); + prefetch(); + +sbc_nd_zpg + TMP = read_pc(); + TMP = read(TMP); + do_sbc_nd(TMP); + prefetch(); + +sbc_nd_zpx + TMP = read_pc(); + read(TMP); + TMP = read(UINT8(TMP+X)); + do_sbc_nd(TMP); + prefetch(); + +isb_nd_aba + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); + +isb_nd_abx + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+X)); + TMP += X; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); + +isb_nd_aby + TMP = read_pc(); + TMP = set_h(TMP, read_pc()); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); + +isb_nd_idx + TMP2 = read_pc(); + read(TMP2); + TMP2 += X; + TMP = read(TMP2 & 0xff); + TMP = set_h(TMP, read((TMP2+1) & 0xff)); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); + +isb_nd_idy + TMP2 = read_pc(); + TMP = read(TMP2); + TMP = set_h(TMP, read(TMP2+1)); + read(set_l(TMP, TMP+Y)); + TMP += Y; + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); + +isb_nd_zpg + TMP = read_pc(); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); + +isb_nd_zpx + TMP = read_pc(); + read(TMP); + TMP = UINT8(TMP+X); + TMP2 = read(TMP); + write(TMP, TMP2); + TMP2++; + write(TMP, TMP2); + do_sbc_nd(TMP2); + prefetch(); diff --git a/src/emu/cpu/m6502/ops02.h b/src/emu/cpu/m6502/ops02.h deleted file mode 100644 index 1dbbc21fea9..00000000000 --- a/src/emu/cpu/m6502/ops02.h +++ /dev/null @@ -1,808 +0,0 @@ -/***************************************************************************** - * - * ops02.h - * Addressing mode and opcode macros for 6502,65c02,65sc02,6510,n2a03 CPUs - * - * Copyright Juergen Buchmueller, all rights reserved. - * 65sc02 core Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - - -/* 6502 flags */ -#define F_C 0x01 -#define F_Z 0x02 -#define F_I 0x04 -#define F_D 0x08 -#define F_B 0x10 -#define F_T 0x20 -#define F_V 0x40 -#define F_N 0x80 - -/* some shortcuts for improved readability */ -#define A cpustate->a -#define X cpustate->x -#define Y cpustate->y -#define P cpustate->p -#define S cpustate->sp.b.l -#define SPD cpustate->sp.d - -#define NZ cpustate->nz - -#define SET_NZ(n) \ - if ((n) == 0) P = (P & ~F_N) | F_Z; else P = (P & ~(F_N | F_Z)) | ((n) & F_N) - -#define SET_Z(n) \ - if ((n) == 0) P |= F_Z; else P &= ~F_Z - -#define EAL cpustate->ea.b.l -#define EAH cpustate->ea.b.h -#define EAW cpustate->ea.w.l -#define EAD cpustate->ea.d - -#define ZPL cpustate->zp.b.l -#define ZPH cpustate->zp.b.h -#define ZPW cpustate->zp.w.l -#define ZPD cpustate->zp.d - -#define PCL cpustate->pc.b.l -#define PCH cpustate->pc.b.h -#define PCW cpustate->pc.w.l -#define PCD cpustate->pc.d - -#define PPC cpustate->ppc.d - -#define RDMEM_ID(a) (cpustate->rdmem_id.isnull() ? cpustate->space->read_byte(a) : cpustate->rdmem_id(a)) -#define WRMEM_ID(a,d) (cpustate->wrmem_id.isnull() ? cpustate->space->write_byte(a,d) : cpustate->wrmem_id(a,d)) - -/*************************************************************** - * RDOP read an opcode - ***************************************************************/ -#define RDOP() cpustate->direct->read_decrypted_byte(PCW++); cpustate->icount -= 1 -#define PEEKOP() cpustate->direct->read_decrypted_byte(PCW) - -/*************************************************************** - * RDOPARG read an opcode argument - ***************************************************************/ -#define RDOPARG() cpustate->direct->read_raw_byte(PCW++); cpustate->icount -= 1 - -/*************************************************************** - * RDMEM read memory - ***************************************************************/ -#define RDMEM(addr) cpustate->space->read_byte(addr); cpustate->icount -= 1 - -/*************************************************************** - * WRMEM write memory - ***************************************************************/ -#define WRMEM(addr,data) cpustate->space->write_byte(addr,data); cpustate->icount -= 1 - -/*************************************************************** - * BRA branch relative - * extra cycle if page boundary is crossed - ***************************************************************/ -#define BRA(cond) \ - { \ - INT8 tmp2 = RDOPARG(); \ - if (cond) \ - { \ - RDMEM(PCW); \ - EAW = PCW + (signed char)tmp2; \ - if ( EAH != PCH ) { \ - RDMEM( (PCH << 8 ) | EAL) ; \ - } \ - PCD = EAD; \ - } \ - } - -/*************************************************************** - * - * Helper macros to build the effective address - * - ***************************************************************/ - -/*************************************************************** - * EA = zero page address - ***************************************************************/ -#define EA_ZPG \ - ZPL = RDOPARG(); \ - EAD = ZPD - -/*************************************************************** - * EA = zero page address + X - ***************************************************************/ -#define EA_ZPX \ - ZPL = RDOPARG(); \ - RDMEM(ZPD); \ - ZPL = X + ZPL; \ - EAD = ZPD - -/*************************************************************** - * EA = zero page address + Y - ***************************************************************/ -#define EA_ZPY \ - ZPL = RDOPARG(); \ - RDMEM(ZPD); \ - ZPL = Y + ZPL; \ - EAD = ZPD - -/*************************************************************** - * EA = absolute address - ***************************************************************/ -#define EA_ABS \ - EAL = RDOPARG(); \ - EAH = RDOPARG() - -/*************************************************************** - * EA = absolute address + X - * one additional read if page boundary is crossed - ***************************************************************/ -#define EA_ABX_P \ - EA_ABS; \ - if ( EAL + X > 0xff ) { \ - RDMEM( ( EAH << 8 ) | ( ( EAL + X ) & 0xff ) ); \ - } \ - EAW += X; - -/*************************************************************** - * EA = absolute address + X - ***************************************************************/ -#define EA_ABX_NP \ - EA_ABS; \ - RDMEM( ( EAH << 8 ) | ( ( EAL + X ) & 0xff ) ); \ - EAW += X - -/*************************************************************** - * EA = absolute address + Y - * one additional read if page boundary is crossed - ***************************************************************/ -#define EA_ABY_P \ - EA_ABS; \ - if ( EAL + Y > 0xff ) { \ - RDMEM( ( EAH << 8 ) | ( ( EAL + Y ) & 0xff ) ); \ - } \ - EAW += Y; - -/*************************************************************** - * EA = absolute address + Y - ***************************************************************/ -#define EA_ABY_NP \ - EA_ABS; \ - RDMEM( ( EAH << 8 ) | ( ( EAL + Y ) & 0xff ) ); \ - EAW += Y - -/*************************************************************** - * EA = zero page + X indirect (pre indexed) - ***************************************************************/ -#define EA_IDX \ - ZPL = RDOPARG(); \ - RDMEM(ZPD); \ - ZPL = ZPL + X; \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD) - -/*************************************************************** - * EA = zero page indirect + Y (post indexed) - * subtract 1 cycle if page boundary is crossed - ***************************************************************/ -#define EA_IDY_P \ - ZPL = RDOPARG(); \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - if (EAL + Y > 0xff) { \ - RDMEM( ( EAH << 8 ) | ( ( EAL + Y ) & 0xff ) ); \ - } \ - EAW += Y; - -/*************************************************************** - * EA = zero page indirect + Y - ***************************************************************/ -#define EA_IDY_NP \ - ZPL = RDOPARG(); \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - RDMEM( ( EAH << 8 ) | ( ( EAL + Y ) & 0xff ) ); \ - EAW += Y - -/*************************************************************** - * EA = zero page indirect (65c02 pre indexed w/o X) - ***************************************************************/ -#define EA_ZPI \ - ZPL = RDOPARG(); \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD) - -/*************************************************************** - * EA = indirect (only used by JMP) - ***************************************************************/ -#define EA_IND \ - EA_ABS; \ - tmp = RDMEM(EAD); \ - EAL++; /* booby trap: stay in same page! ;-) */ \ - EAH = RDMEM(EAD); \ - EAL = tmp - - -/* read a value into tmp */ -/* Base number of cycles taken for each mode (including reading of opcode): - RD_IMM 2 - RD_DUM 2 - RD_ACC 0 - RD_ZPG/WR_ZPG 3 - RD_ZPX/WR_ZPX 4 - RD_ZPY/WR_ZPY 4 - RD_ABS/WR_ABS 4 - RD_ABX_P 4/5 - RD_ABX_NP/WR_ABX_NP 5 - RD_ABY_P 4/5 - RD_ABY_NP/WR_ABY_NP 5 - RD_IDX/WR_IDX 6 - RD_IDY_P 5/6 - RD_IDY_NP/WR_IDY_NP 6 - RD_ZPI/WR_ZPI 5 - */ -#define RD_IMM tmp = RDOPARG() -#define RD_IMM_DISCARD RDOPARG() -#define RD_DUM RDMEM(PCW) -#define RD_ACC tmp = A -#define RD_ZPG EA_ZPG; tmp = RDMEM(EAD) -#define RD_ZPG_DISCARD EA_ZPG; RDMEM(EAD) -#define RD_ZPX EA_ZPX; tmp = RDMEM(EAD) -#define RD_ZPX_DISCARD EA_ZPX; RDMEM(EAD) -#define RD_ZPY EA_ZPY; tmp = RDMEM(EAD) -#define RD_ABS EA_ABS; tmp = RDMEM(EAD) -#define RD_ABS_DISCARD EA_ABS; RDMEM(EAD) -#define RD_ABX_P EA_ABX_P; tmp = RDMEM(EAD) -#define RD_ABX_P_DISCARD EA_ABX_P; RDMEM(EAD); -#define RD_ABX_NP EA_ABX_NP; tmp = RDMEM(EAD) -#define RD_ABY_P EA_ABY_P; tmp = RDMEM(EAD) -#define RD_ABY_NP EA_ABY_NP; tmp = RDMEM(EAD) -#define RD_IDX EA_IDX; tmp = RDMEM_ID(EAD); cpustate->icount -= 1 -#define RD_IDY_P EA_IDY_P; tmp = RDMEM_ID(EAD); cpustate->icount -= 1 -#define RD_IDY_NP EA_IDY_NP; tmp = RDMEM_ID(EAD); cpustate->icount -= 1 -#define RD_ZPI EA_ZPI; tmp = RDMEM(EAD) - -/* write a value from tmp */ -#define WR_ZPG EA_ZPG; WRMEM(EAD, tmp) -#define WR_ZPX EA_ZPX; WRMEM(EAD, tmp) -#define WR_ZPY EA_ZPY; WRMEM(EAD, tmp) -#define WR_ABS EA_ABS; WRMEM(EAD, tmp) -#define WR_ABX_NP EA_ABX_NP; WRMEM(EAD, tmp) -#define WR_ABY_NP EA_ABY_NP; WRMEM(EAD, tmp) -#define WR_IDX EA_IDX; WRMEM_ID(EAD, tmp); cpustate->icount -= 1 -#define WR_IDY_NP EA_IDY_NP; WRMEM_ID(EAD, tmp); cpustate->icount -= 1 -#define WR_ZPI EA_ZPI; WRMEM(EAD, tmp) - -/* dummy read from the last EA */ -#define RD_EA RDMEM(EAD) - -/* write back a value from tmp to the last EA */ -#define WB_ACC A = (UINT8)tmp; -#define WB_EA WRMEM(EAD, tmp) - -/*************************************************************** - *************************************************************** - * Macros to emulate the plain 6502 opcodes - *************************************************************** - ***************************************************************/ - -/*************************************************************** - * push a register onto the stack - ***************************************************************/ -#define PUSH(Rg) WRMEM(SPD, Rg); S-- - -/*************************************************************** - * pull a register from the stack - ***************************************************************/ -#define PULL(Rg) S++; Rg = RDMEM(SPD) - -/* 6502 ******************************************************** - * ADC Add with carry - ***************************************************************/ -#define ADC \ - if (P & F_D) { \ - int c = (P & F_C); \ - int lo = (A & 0x0f) + (tmp & 0x0f) + c; \ - int hi = (A & 0xf0) + (tmp & 0xf0); \ - P &= ~(F_V | F_C|F_N|F_Z); \ - if (!((lo+hi)&0xff)) P|=F_Z; \ - if (lo > 0x09) { \ - hi += 0x10; \ - lo += 0x06; \ - } \ - if (hi&0x80) P|=F_N; \ - if (~(A^tmp) & (A^hi) & F_N) \ - P |= F_V; \ - if (hi > 0x90) \ - hi += 0x60; \ - if (hi & 0xff00) \ - P |= F_C; \ - A = (lo & 0x0f) + (hi & 0xf0); \ - } else { \ - int c = (P & F_C); \ - int sum = A + tmp + c; \ - P &= ~(F_V | F_C); \ - if (~(A^tmp) & (A^sum) & F_N) \ - P |= F_V; \ - if (sum & 0xff00) \ - P |= F_C; \ - A = (UINT8) sum; \ - SET_NZ(A); \ - } - -/* 6502 ******************************************************** - * AND Logical and - ***************************************************************/ -#define AND \ - A = (UINT8)(A & tmp); \ - SET_NZ(A) - -/* 6502 ******************************************************** - * ASL Arithmetic shift left - ***************************************************************/ -#define ASL \ - P = (P & ~F_C) | ((tmp >> 7) & F_C); \ - tmp = (UINT8)(tmp << 1); \ - SET_NZ(tmp) - -/* 6502 ******************************************************** - * BCC Branch if carry clear - ***************************************************************/ -#define BCC BRA(!(P & F_C)) - -/* 6502 ******************************************************** - * BCS Branch if carry set - ***************************************************************/ -#define BCS BRA(P & F_C) - -/* 6502 ******************************************************** - * BEQ Branch if equal - ***************************************************************/ -#define BEQ BRA(P & F_Z) - -/* 6502 ******************************************************** - * BIT Bit test - ***************************************************************/ -#undef BIT -#define BIT \ - P &= ~(F_N|F_V|F_Z); \ - P |= tmp & (F_N|F_V); \ - if ((tmp & A) == 0) \ - P |= F_Z - -/* 6502 ******************************************************** - * BMI Branch if minus - ***************************************************************/ -#define BMI BRA(P & F_N) - -/* 6502 ******************************************************** - * BNE Branch if not equal - ***************************************************************/ -#define BNE BRA(!(P & F_Z)) - -/* 6502 ******************************************************** - * BPL Branch if plus - ***************************************************************/ -#define BPL BRA(!(P & F_N)) - -/* 6502 ******************************************************** - * BRK Break - * increment PC, push PC hi, PC lo, flags (with B bit set), - * set I flag, jump via IRQ vector - ***************************************************************/ -#define BRK \ - RDOPARG(); \ - PUSH(PCH); \ - PUSH(PCL); \ - PUSH(P | F_B); \ - P = (P | F_I); \ - PCL = RDMEM(M6502_IRQ_VEC); \ - PCH = RDMEM(M6502_IRQ_VEC+1) - -/* 6502 ******************************************************** - * BVC Branch if overflow clear - ***************************************************************/ -#define BVC BRA(!(P & F_V)) - -/* 6502 ******************************************************** - * BVS Branch if overflow set - ***************************************************************/ -#define BVS BRA(P & F_V) - -/* 6502 ******************************************************** - * CLC Clear carry flag - ***************************************************************/ -#define CLC \ - P &= ~F_C - -/* 6502 ******************************************************** - * CLD Clear decimal flag - ***************************************************************/ -#define CLD \ - P &= ~F_D - -/* 6502 ******************************************************** - * CLI Clear interrupt flag - ***************************************************************/ -#define CLI \ - if ((cpustate->irq_state != CLEAR_LINE) && (P & F_I)) { \ - /* kludge for now until IRQ rewrite: ignore if RTI follows */ \ - if (PEEKOP() != 0x40) \ - cpustate->after_cli = 1; \ - } \ - P &= ~F_I - -/* 6502 ******************************************************** - * CLV Clear overflow flag - ***************************************************************/ -#define CLV \ - P &= ~F_V - -/* 6502 ******************************************************** - * CMP Compare accumulator - ***************************************************************/ -#define CMP \ - P &= ~F_C; \ - if (A >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(A - tmp)) - -/* 6502 ******************************************************** - * CPX Compare index X - ***************************************************************/ -#define CPX \ - P &= ~F_C; \ - if (X >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(X - tmp)) - -/* 6502 ******************************************************** - * CPY Compare index Y - ***************************************************************/ -#define CPY \ - P &= ~F_C; \ - if (Y >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(Y - tmp)) - -/* 6502 ******************************************************** - * DEC Decrement memory - ***************************************************************/ -#define DEC \ - tmp = (UINT8)(tmp-1); \ - SET_NZ(tmp) - -/* 6502 ******************************************************** - * DEX Decrement index X - ***************************************************************/ -#define DEX \ - X = (UINT8)(X-1); \ - SET_NZ(X) - -/* 6502 ******************************************************** - * DEY Decrement index Y - ***************************************************************/ -#define DEY \ - Y = (UINT8)(Y-1); \ - SET_NZ(Y) - -/* 6502 ******************************************************** - * EOR Logical exclusive or - ***************************************************************/ -#define EOR \ - A = (UINT8)(A ^ tmp); \ - SET_NZ(A) - -/* 6502 ******************************************************** - * ILL Illegal opcode - ***************************************************************/ -#define ILL \ - logerror("M6502 illegal opcode %04x: %02x\n",(PCW-1)&0xffff, cpustate->direct->read_decrypted_byte((PCW-1)&0xffff)) - -/* 6502 ******************************************************** - * INC Increment memory - ***************************************************************/ -#define INC \ - tmp = (UINT8)(tmp+1); \ - SET_NZ(tmp) - -/* 6502 ******************************************************** - * INX Increment index X - ***************************************************************/ -#define INX \ - X = (UINT8)(X+1); \ - SET_NZ(X) - -/* 6502 ******************************************************** - * INY Increment index Y - ***************************************************************/ -#define INY \ - Y = (UINT8)(Y+1); \ - SET_NZ(Y) - -/* 6502 ******************************************************** - * JMP Jump to address - * set PC to the effective address - ***************************************************************/ -#define JMP \ - if( EAD == PPC && !cpustate->pending_irq && !cpustate->after_cli ) \ - if( cpustate->icount > 0 ) cpustate->icount = 0; \ - PCD = EAD - -/* 6502 ******************************************************** - * JSR Jump to subroutine - * decrement PC (sic!) push PC hi, push PC lo and set - * PC to the effective address - ***************************************************************/ -#define JSR \ - EAL = RDOPARG(); \ - RDMEM(SPD); \ - PUSH(PCH); \ - PUSH(PCL); \ - EAH = RDOPARG(); \ - PCD = EAD - -/* 6502 ******************************************************** - * LDA Load accumulator - ***************************************************************/ -#define LDA \ - A = (UINT8)tmp; \ - SET_NZ(A) - -/* 6502 ******************************************************** - * LDX Load index X - ***************************************************************/ -#define LDX \ - X = (UINT8)tmp; \ - SET_NZ(X) - -/* 6502 ******************************************************** - * LDY Load index Y - ***************************************************************/ -#define LDY \ - Y = (UINT8)tmp; \ - SET_NZ(Y) - -/* 6502 ******************************************************** - * LSR Logic shift right - * 0 -> [7][6][5][4][3][2][1][0] -> C - ***************************************************************/ -#define LSR \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)tmp >> 1; \ - SET_NZ(tmp) - -/* 6502 ******************************************************** - * NOP No operation - ***************************************************************/ -#define NOP - -/* 6502 ******************************************************** - * ORA Logical inclusive or - ***************************************************************/ -#define ORA \ - A = (UINT8)(A | tmp); \ - SET_NZ(A) - -/* 6502 ******************************************************** - * PHA Push accumulator - ***************************************************************/ -#define PHA \ - PUSH(A) - -/* 6502 ******************************************************** - * PHP Push processor status (flags) - ***************************************************************/ -#define PHP \ - PUSH(P) - -/* 6502 ******************************************************** - * PLA Pull accumulator - ***************************************************************/ -#define PLA \ - RDMEM(SPD); \ - PULL(A); \ - SET_NZ(A) - - -/* 6502 ******************************************************** - * PLP Pull processor status (flags) - ***************************************************************/ -#define PLP \ - RDMEM(SPD); \ - if ( P & F_I ) { \ - PULL(P); \ - if ((cpustate->irq_state != CLEAR_LINE) && !(P & F_I)) { \ - LOG(("M6502 '%s' PLP sets after_cli\n",cpustate->device->tag())); \ - cpustate->after_cli = 1; \ - } \ - } else { \ - PULL(P); \ - } \ - P |= (F_T|F_B); - -/* 6502 ******************************************************** - * ROL Rotate left - * new C <- [7][6][5][4][3][2][1][0] <- C - ***************************************************************/ -#define ROL \ - tmp = (tmp << 1) | (P & F_C); \ - P = (P & ~F_C) | ((tmp >> 8) & F_C); \ - tmp = (UINT8)tmp; \ - SET_NZ(tmp) - -/* 6502 ******************************************************** - * ROR Rotate right - * C -> [7][6][5][4][3][2][1][0] -> new C - ***************************************************************/ -#define ROR \ - tmp |= (P & F_C) << 8; \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)(tmp >> 1); \ - SET_NZ(tmp) - -/* 6502 ******************************************************** - * RTI Return from interrupt - * pull flags, pull PC lo, pull PC hi and increment PC - * PCW++; - ***************************************************************/ -#define RTI \ - RDOPARG(); \ - RDMEM(SPD); \ - PULL(P); \ - PULL(PCL); \ - PULL(PCH); \ - P |= F_T | F_B; \ - if( (cpustate->irq_state != CLEAR_LINE) && !(P & F_I) ) \ - { \ - LOG(("M6502 '%s' RTI sets after_cli\n",cpustate->device->tag())); \ - cpustate->after_cli = 1; \ - } - -/* 6502 ******************************************************** - * RTS Return from subroutine - * pull PC lo, PC hi and increment PC - ***************************************************************/ -#define RTS \ - RDOPARG(); \ - RDMEM(SPD); \ - PULL(PCL); \ - PULL(PCH); \ - RDMEM(PCW); PCW++ - -/* 6502 ******************************************************** - * SBC Subtract with carry - ***************************************************************/ -#define SBC \ - if (P & F_D) \ - { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - int lo = (A & 0x0f) - (tmp & 0x0f) - c; \ - int hi = (A & 0xf0) - (tmp & 0xf0); \ - if (lo & 0x10) \ - { \ - lo -= 6; \ - hi--; \ - } \ - P &= ~(F_V | F_C|F_Z|F_N); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( hi & 0x0100 ) \ - hi -= 0x60; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - if( !((A-tmp-c) & 0xff) ) \ - P |= F_Z; \ - if( (A-tmp-c) & 0x80 ) \ - P |= F_N; \ - A = (lo & 0x0f) | (hi & 0xf0); \ - } \ - else \ - { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - P &= ~(F_V | F_C); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - SET_NZ(A); \ - } - -/* 6502 ******************************************************** - * SEC Set carry flag - ***************************************************************/ -#if defined(SEC) -#undef SEC -#endif -#define SEC \ - P |= F_C - -/* 6502 ******************************************************** - * SED Set decimal flag - ***************************************************************/ -#define SED \ - P |= F_D - -/* 6502 ******************************************************** - * SEI Set interrupt flag - ***************************************************************/ -#define SEI \ - P |= F_I - -/* 6502 ******************************************************** - * STA Store accumulator - ***************************************************************/ -#define STA \ - tmp = A - -/* 6502 ******************************************************** - * STX Store index X - ***************************************************************/ -#define STX \ - tmp = X - -/* 6502 ******************************************************** - * STY Store index Y - ***************************************************************/ -#define STY \ - tmp = Y - -/* 6502 ******************************************************** - * TAX Transfer accumulator to index X - ***************************************************************/ -#define TAX \ - X = A; \ - SET_NZ(X) - -/* 6502 ******************************************************** - * TAY Transfer accumulator to index Y - ***************************************************************/ -#define TAY \ - Y = A; \ - SET_NZ(Y) - -/* 6502 ******************************************************** - * TSX Transfer stack LSB to index X - ***************************************************************/ -#define TSX \ - X = S; \ - SET_NZ(X) - -/* 6502 ******************************************************** - * TXA Transfer index X to accumulator - ***************************************************************/ -#define TXA \ - A = X; \ - SET_NZ(A) - -/* 6502 ******************************************************** - * TXS Transfer index X to stack LSB - * no flags changed (sic!) - ***************************************************************/ -#define TXS \ - S = X - -/* 6502 ******************************************************** - * TYA Transfer index Y to accumulator - ***************************************************************/ -#define TYA \ - A = Y; \ - SET_NZ(A) diff --git a/src/emu/cpu/m6502/ops09.h b/src/emu/cpu/m6502/ops09.h deleted file mode 100644 index b29e31155d6..00000000000 --- a/src/emu/cpu/m6502/ops09.h +++ /dev/null @@ -1,221 +0,0 @@ -/***************************************************************************** - * - * ops09.h - * - * Copyright Peter Trauner, all rights reserved. - * documentation by michael steil mist@c64.org - * available at ftp://ftp.funet.fi/pub/cbm/c65 - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - -#define ZPWH cpustate->zp.w.h - -#define EAWH cpustate->ea.w.h - -#define PBWH cpustate->pc_bank.w.h -#define PB cpustate->pc_bank.d - -#define IBWH cpustate->ind_bank.w.h -#define IB cpustate->ind_bank.d - -/*************************************************************** - * RDOP read an opcode - ***************************************************************/ -#undef RDOP -#define RDOP() cpustate->direct->read_decrypted_byte((PCW++)|PB); cpustate->icount -= 1 - -/*************************************************************** - * RDOPARG read an opcode argument - ***************************************************************/ -#undef RDOPARG -#define RDOPARG() cpustate->direct->read_raw_byte((PCW++)|PB); cpustate->icount -= 1 - -/*************************************************************** - * RDMEM read memory - ***************************************************************/ -#undef RDMEM -#define RDMEM(addr) cpustate->space->read_byte(addr); cpustate->icount -= 1 - -/*************************************************************** - * WRMEM write memory - ***************************************************************/ -#undef WRMEM -#define WRMEM(addr,data) cpustate->space->write_byte(addr,data); cpustate->icount -= 1 - -/*************************************************************** - * push a register onto the stack - ***************************************************************/ -#undef PUSH -#define PUSH(Rg) WRMEM(SPD|PB, Rg); S-- - -/*************************************************************** - * pull a register from the stack - ***************************************************************/ -#undef PULL -#define PULL(Rg) S++; Rg = RDMEM(SPD|PB) - - -/*************************************************************** - * EA = zero page address - ***************************************************************/ -#undef EA_ZPG -#define EA_ZPG \ - ZPL = RDOPARG(); \ - ZPWH = PBWH; \ - EAD = ZPD - -/*************************************************************** - * EA = zero page address + X - ***************************************************************/ -#undef EA_ZPX -#define EA_ZPX \ - ZPL = X + RDOPARG(); \ - ZPWH = PBWH; \ - EAD = ZPD - -/*************************************************************** - * EA = zero page address + Y - ***************************************************************/ -#undef EA_ZPY -#define EA_ZPY \ - ZPL = Y + RDOPARG(); \ - ZPWH = PBWH; \ - EAD = ZPD - -/*************************************************************** - * EA = absolute address - ***************************************************************/ -#undef EA_ABS -#define EA_ABS \ - EAL = RDOPARG(); \ - EAH = RDOPARG(); \ - EAWH = PBWH - -/*************************************************************** - * EA = zero page + X indirect (pre indexed) - ***************************************************************/ -#undef EA_IDX -#define EA_IDX \ - ZPL = X + RDOPARG(); \ - ZPWH=PBWH; \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - EAWH = PBWH - -/*************************************************************** - * EA = zero page indirect + Y (post indexed) - * subtract 1 cycle if page boundary is crossed - ***************************************************************/ -#undef EA_IDY -#define EA_IDY \ - ZPL = RDOPARG(); \ - ZPWH = PBWH; \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - EAWH = PBWH; \ - if (EAL + Y > 0xff) \ - cpustate->icount--; \ - EAW += Y - -/*************************************************************** - * EA = zero page indirect + Y (post indexed) - * subtract 1 cycle if page boundary is crossed - ***************************************************************/ -#undef EA_IDY_P -#define EA_IDY_P \ - ZPL = RDOPARG(); \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - EAWH = PBWH; \ - if (EAL + Y > 0xff) { \ - RDMEM( ( EAH << 8 ) | ( ( EAL + Y ) & 0xff ) ); \ - } \ - EAW += Y; - -/*************************************************************** - * EA = zero page indirect + Y (post indexed) - * subtract 1 cycle if page boundary is crossed - ***************************************************************/ -#define EA_IDY_6509 \ - ZPL = RDOPARG(); \ - ZPWH = PBWH; \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - EAWH = IBWH; \ - if (EAL + Y > 0xff) \ - cpustate->icount--; \ - EAW += Y - -/*************************************************************** - * EA = indirect (only used by JMP) - ***************************************************************/ -#undef EA_IND -#define EA_IND \ - EA_ABS; \ - tmp = RDMEM(EAD); \ - EAL++; /* booby trap: stay in same page! ;-) */ \ - EAH = RDMEM(EAD); \ - EAL = tmp; -/* EAWH = PBWH */ - -#define RD_IDY_6509 EA_IDY_6509; tmp = RDMEM(EAD) -#define WR_IDY_6509 EA_IDY_6509; WRMEM(EAD, tmp) - -/*************************************************************** - * BRA branch relative - * extra cycle if page boundary is crossed - ***************************************************************/ -#undef BRA -#define BRA(cond) \ - if (cond) \ - { \ - tmp = RDOPARG(); \ - EAW = PCW + (signed char)tmp; \ - cpustate->icount -= (PCH == EAH) ? 1 : 2; \ - PCD = EAD|PB; \ - } \ - else \ - { \ - PCW++; \ - cpustate->icount -= 1; \ - } - -/* 6502 ******************************************************** - * JSR Jump to subroutine - * decrement PC (sic!) push PC hi, push PC lo and set - * PC to the effective address - ***************************************************************/ -#undef JSR -#define JSR \ - EAL = RDOPARG(); \ - PUSH(PCH); \ - PUSH(PCL); \ - EAH = RDOPARG(); \ - EAWH = PBWH; \ - PCD = EAD - -/* 6510 ******************************************************** - * KIL Illegal opcode - * processor haltet, no hardware interrupt will help - * only reset - ***************************************************************/ -#undef KIL -#define KIL \ - PCW--; \ - logerror("M6509 KILL opcode %05x: %02x\n", PCD, cpustate->direct->read_decrypted_byte(PCD)) diff --git a/src/emu/cpu/m6502/ops4510.h b/src/emu/cpu/m6502/ops4510.h deleted file mode 100644 index 82792bb83ae..00000000000 --- a/src/emu/cpu/m6502/ops4510.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************** - * - * ops4510.h - * Addressing mode and opcode macros for 4510 CPU - * - * Copyright Peter Trauner, all rights reserved. - * documentation preliminary databook - * documentation by michael steil mist@c64.org - * available at ftp://ftp.funet.fi/pub/cbm/c65 - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - - -/* 65ce02 ******************************************************** - * TXS Transfer index X to stack LSB - * no flags changed (sic!) - * txs tys not interruptable - ***************************************************************/ -#undef TXS -#define TXS \ - SPL = X; \ - if (PEEK_OP() == 0x2b /*TYS*/ ) { \ - UINT8 op = RDOP(); \ - (*cpustate->insn[op])(cpustate); \ - } - -#undef NOP -#define NOP \ - cpustate->interrupt_inhibit = 0; - -/* c65 docu says transfer of axyz to the mapper register - so no readback!? */ -#define MAP \ - cpustate->interrupt_inhibit = 1; \ - cpustate->low=cpustate->a|(cpustate->x<<8); \ - cpustate->high=cpustate->y|(cpustate->z<<8); \ - cpustate->mem[0]=(cpustate->low&0x1000) ? (cpustate->low&0xfff)<<8:0; \ - cpustate->mem[1]=(cpustate->low&0x2000) ? (cpustate->low&0xfff)<<8:0; \ - cpustate->mem[2]=(cpustate->low&0x4000) ? (cpustate->low&0xfff)<<8:0; \ - cpustate->mem[3]=(cpustate->low&0x8000) ? (cpustate->low&0xfff)<<8:0; \ - cpustate->mem[4]=(cpustate->high&0x1000) ? (cpustate->high&0xfff)<<8:0; \ - cpustate->mem[5]=(cpustate->high&0x2000) ? (cpustate->high&0xfff)<<8:0; \ - cpustate->mem[6]=(cpustate->high&0x4000) ? (cpustate->high&0xfff)<<8:0; \ - cpustate->mem[7]=(cpustate->high&0x8000) ? (cpustate->high&0xfff)<<8:0; \ - cpustate->icount -= 3; \ - { \ - UINT8 op = RDOP(); \ - (*cpustate->insn[op])(cpustate); \ - } - -#undef RDMEM_ID -#undef WRMEM_ID -#define RDMEM_ID(a) (cpustate->rdmem_id.isnull() ? cpustate->space->read_byte(M4510_MEM(a)) : cpustate->rdmem_id(M4510_MEM(a))) -#define WRMEM_ID(a,d) (cpustate->wrmem_id.isnull() ? cpustate->space->write_byte(M4510_MEM(a),d) : cpustate->wrmem_id(M4510_MEM(a),d)) diff --git a/src/emu/cpu/m6502/opsc02.h b/src/emu/cpu/m6502/opsc02.h deleted file mode 100644 index affd6dfd72a..00000000000 --- a/src/emu/cpu/m6502/opsc02.h +++ /dev/null @@ -1,359 +0,0 @@ -/***************************************************************************** - * - * m6502ops.h - * Addressing mode and opcode macros for 6502,65c02,65sc02,6510,n2a03 CPUs - * - * Copyright Juergen Buchmueller, all rights reserved. - * 65sc02 core Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - - -/*************************************************************** - *************************************************************** - * Macros to emulate the 65C02 opcodes - *************************************************************** - ***************************************************************/ - -/* 65C02 ******************************************************* - * EA = absolute address + X - * one additional read if page boundary is crossed - ***************************************************************/ -#define EA_ABX_C02_P \ - EA_ABS; \ - if ( EAL + X > 0xff ) { \ - RDMEM( PCW - 1 ); \ - } \ - EAW += X; - -/* 65C02 ******************************************************* - * EA = absolute address + X - ***************************************************************/ -#define EA_ABX_C02_NP \ - EA_ABS; \ - RDMEM( PCW - 1 ); \ - EAW += X; - -/*************************************************************** - * EA = absolute address + Y - * one additional read if page boundary is crossed - ***************************************************************/ -#define EA_ABY_C02_P \ - EA_ABS; \ - if ( EAL + Y > 0xff ) { \ - RDMEM( PCW - 1 ); \ - } \ - EAW += Y; - -/* 65C02 ******************************************************* - * EA = absolute address + Y - ***************************************************************/ -#define EA_ABY_C02_NP \ - EA_ABS; \ - RDMEM( PCW - 1 ); \ - EAW += Y - -/* 65C02 ******************************************************* - * EA = zero page indirect + Y (post indexed) - * subtract 1 cycle if page boundary is crossed - ***************************************************************/ -#define EA_IDY_C02_P \ - ZPL = RDOPARG(); \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - if (EAL + Y > 0xff) { \ - RDMEM( PCW - 1 ); \ - } \ - EAW += Y; - -/* 65C02 ******************************************************* - * EA = zero page indirect + Y - ***************************************************************/ -#define EA_IDY_C02_NP \ - ZPL = RDOPARG(); \ - EAL = RDMEM(ZPD); \ - ZPL++; \ - EAH = RDMEM(ZPD); \ - RDMEM( PCW - 1 ); \ - EAW += Y - -/* 65C02 ******************************************************* - * EA = indirect (only used by JMP) - * correct overflow handling - ***************************************************************/ -#define EA_IND_C02 \ - EA_ABS; \ - tmp = RDMEM(EAD); \ - RDMEM(PCW-1); \ - EAD++; \ - EAH = RDMEM(EAD); \ - EAL = tmp - -/* 65C02 ******************************************************* - * EA = indirect plus x (only used by 65c02 JMP) - ***************************************************************/ -#define EA_IAX \ - EA_ABS; \ - RDMEM( PCW - 1 ); \ - if (EAL + X > 0xff) { \ - RDMEM( PCW - 1 ); \ - } \ - EAW += X; \ - tmp = RDMEM(EAD); \ - EAD++; \ - EAH = RDMEM(EAD); \ - EAL = tmp - -/* read a value into tmp */ -/* Base number of cycles taken for each mode (including reading of opcode): - RD_ABX_C02_P 4/5 - RD_ABX_C02_NP/WR_ABX_C02_NP 5 - RD_ABY_C02_P 4/5 - RD_IDY_C02_P 5/6 - WR_IDY_C02_NP 6 - */ -#define RD_ABX_C02_P EA_ABX_C02_P; tmp = RDMEM(EAD) -#define RD_ABX_C02_NP EA_ABX_C02_NP; tmp = RDMEM(EAD) -#define RD_ABX_C02_NP_DISCARD EA_ABX_C02_NP; RDMEM(EAD) -#define RD_ABY_C02_P EA_ABY_C02_P; tmp = RDMEM(EAD) -#define RD_IDY_C02_P EA_IDY_C02_P; tmp = RDMEM_ID(EAD); cpustate->icount -= 1 - -#define WR_ABX_C02_NP EA_ABX_C02_NP; WRMEM(EAD, tmp) -#define WR_ABY_C02_NP EA_ABY_C02_NP; WRMEM(EAD, tmp) -#define WR_IDY_C02_NP EA_IDY_C02_NP; WRMEM_ID(EAD, tmp); cpustate->icount -= 1 - - -/* 65C02******************************************************** - * BRA branch relative - * extra cycle if page boundary is crossed - ***************************************************************/ -#define BRA_C02(cond) \ - tmp = RDOPARG(); \ - if (cond) \ - { \ - RDMEM(PCW); \ - EAW = PCW + (signed char)tmp; \ - if ( EAH != PCH ) { \ - RDMEM( PCW - 1 ); \ - } \ - PCD = EAD; \ - } - -/* 65C02 ******************************************************** - * ADC Add with carry - * different setting of flags in decimal mode - ***************************************************************/ -#define ADC_C02 \ - if (P & F_D) \ - { \ - int c = (P & F_C); \ - int lo = (A & 0x0f) + (tmp & 0x0f) + c; \ - int hi = (A & 0xf0) + (tmp & 0xf0); \ - P &= ~(F_V | F_C); \ - if( lo > 0x09 ) \ - { \ - hi += 0x10; \ - lo += 0x06; \ - } \ - if( ~(A^tmp) & (A^hi) & F_N ) \ - P |= F_V; \ - if( hi > 0x90 ) \ - hi += 0x60; \ - if( hi & 0xff00 ) \ - P |= F_C; \ - A = (lo & 0x0f) + (hi & 0xf0); \ - RDMEM( PCW - 1 ); \ - } \ - else \ - { \ - int c = (P & F_C); \ - int sum = A + tmp + c; \ - P &= ~(F_V | F_C); \ - if( ~(A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( sum & 0xff00 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - } \ - SET_NZ(A) - -/* 65C02 ******************************************************** - * SBC Subtract with carry - * different setting of flags in decimal mode - ***************************************************************/ -#define SBC_C02 \ - if (P & F_D) \ - { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - int lo = (A & 0x0f) - (tmp & 0x0f) - c; \ - int hi = (A & 0xf0) - (tmp & 0xf0); \ - P &= ~(F_V | F_C); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( lo & 0xf0 ) \ - lo -= 6; \ - if( lo & 0x80 ) \ - hi -= 0x10; \ - if( hi & 0x0f00 ) \ - hi -= 0x60; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - A = (lo & 0x0f) + (hi & 0xf0); \ - RDMEM( PCW - 1 ); \ - } \ - else \ - { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - P &= ~(F_V | F_C); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - } \ - SET_NZ(A) - -/* 65C02 ******************************************************* - * BBR Branch if bit is reset - ***************************************************************/ -#define BBR(bit) \ - BRA(!(tmp & (1< 0x09 ) { \ - hi += 0x10; \ - lo += 0x06; \ - } \ - if( ~(A^tmp) & (A^hi) & F_N ) \ - P |= F_V; \ - if( hi > 0x90 ) \ - hi += 0x60; \ - if( hi & 0xff00 ) \ - P |= F_C; \ - A = (lo & 0x0f) + (hi & 0xf0); \ - } else { \ - int c = (P & F_C); \ - int sum = A + tmp + c; \ - P &= ~(F_V | F_C); \ - if( ~(A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( sum & 0xff00 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - } \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * AND Logical and - ***************************************************************/ -#define AND \ - A = (UINT8)(A & tmp); \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * ASL Arithmetic shift left - ***************************************************************/ -#define ASL \ - P = (P & ~F_C) | ((tmp >> 7) & F_C); \ - tmp = (UINT8)(tmp << 1); \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * ASR arithmetic (signed) shift right - * [7] -> [7][6][5][4][3][2][1][0] -> C - ***************************************************************/ -#define ASR_65CE02 \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (signed char)tmp >> 1; \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * ASW arithmetic shift left word - * [c] <- [15]..[6][5][4][3][2][1][0] - ***************************************************************/ -/* not sure about how 16 bit memory modifying is executed */ -#define ASW \ - tmp.w.l = tmp.w.l << 1; \ - P = (P & ~F_C) | (tmp.b.h2 & F_C); \ - SET_NZ_WORD(tmp); - - -/* 65ce02 ****************************************************** - * augment - ***************************************************************/ -#define AUG \ - t1=RDOPARG(); \ - t2=RDOPARG(); \ - t3=RDOPARG(); \ - logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", cpustate->device->pc(),t1,t2,t3); - -/* 65ce02 ****************************************************** - * BBR Branch if bit is reset - ***************************************************************/ -#define BBR(bit) \ - BRA(!(tmp & (1<= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(A - tmp)) - -/* 65ce02 ****************************************************** - * CPX Compare index X - ***************************************************************/ -#define CPX \ - P &= ~F_C; \ - if (X >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(X - tmp)) - -/* 65ce02 ****************************************************** - * CPY Compare index Y - ***************************************************************/ -#define CPY \ - P &= ~F_C; \ - if (Y >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(Y - tmp)) - -/* 65ce02 ****************************************************** - * CPZ Compare index Z - ***************************************************************/ -#define CPZ \ - P &= ~F_C; \ - if (Z >= tmp) \ - P |= F_C; \ - SET_NZ((UINT8)(Z - tmp)) - -/* 65ce02 ****************************************************** - * DEA Decrement accumulator - ***************************************************************/ -#define DEA \ - A = (UINT8)(A - 1); \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * DEC Decrement memory - ***************************************************************/ -#define DEC \ - tmp = (UINT8)(tmp-1); \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * DEW Decrement memory word - ***************************************************************/ -#define DEW \ - tmp.w.l -= 1; \ - SET_NZ_WORD(tmp) - -/* 65ce02 ****************************************************** - * DEX Decrement index X - ***************************************************************/ -#define DEX \ - X = (UINT8)(X-1); \ - SET_NZ(X) - -/* 65ce02 ****************************************************** - * DEY Decrement index Y - ***************************************************************/ -#define DEY \ - Y = (UINT8)(Y-1); \ - SET_NZ(Y) - -/* 65ce02 ****************************************************** - * DEZ Decrement index Z - ***************************************************************/ -#define DEZ \ - Z = (UINT8)(Z-1); \ - SET_NZ(Z) - -/* 65ce02 ****************************************************** - * EOR Logical exclusive or - ***************************************************************/ -#define EOR \ - A = (UINT8)(A ^ tmp); \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * INA Increment accumulator - ***************************************************************/ -#define INA \ - A = (UINT8)(A + 1); \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * INC Increment memory - ***************************************************************/ -#define INC \ - tmp = (UINT8)(tmp+1); \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * INW Increment memory word - ***************************************************************/ -#define INW \ - tmp.w.l += 1; \ - SET_NZ_WORD(tmp) - -/* 65ce02 ****************************************************** - * INX Increment index X - ***************************************************************/ -#define INX \ - X = (UINT8)(X+1); \ - SET_NZ(X) - -/* 65ce02 ****************************************************** - * INY Increment index Y - ***************************************************************/ -#define INY \ - Y = (UINT8)(Y+1); \ - SET_NZ(Y) - -/* 65ce02 ****************************************************** - * INZ Increment index Z - ***************************************************************/ -#define INZ \ - Z = (UINT8)(Z+1); \ - SET_NZ(Z) - -/* 65ce02 ****************************************************** - * JMP Jump to address - * set PC to the effective address - ***************************************************************/ -#define JMP \ - PCD = EAD; - -/* 65ce02 ****************************************************** - * JSR Jump to subroutine - * decrement PC (sic!) push PC hi, push PC lo and set - * PC to the effective address - ***************************************************************/ -#define JSR \ - EAL = RDOPARG(); \ - PUSH(PCH); \ - PUSH(PCL); \ - EAH = RDOPARG(); \ - PCD = EAD; - -/* 65ce02 ****************************************************** - * JSR Jump to subroutine - * decrement PC (sic!) push PC hi, push PC lo and set - * PC to the effective address - ***************************************************************/ -#define JSR_IND \ - EAL = RDOPARG(); \ - PUSH(PCH); \ - PUSH(PCL); \ - EAH = RDOPARG(); \ - PCL = RDMEM(EAD); \ - PCH = RDMEM(EAD+1); - -/* 65ce02 ****************************************************** - * JSR Jump to subroutine - * decrement PC (sic!) push PC hi, push PC lo and set - * PC to the effective address - ***************************************************************/ -#define JSR_INDX \ - EAL = RDOPARG()+X; \ - PUSH(PCH); \ - PUSH(PCL); \ - EAH = RDOPARG(); \ - PCL = RDMEM(EAD); \ - PCH = RDMEM(EAD+1); - -/* 65ce02 ****************************************************** - * LDA Load accumulator - ***************************************************************/ -#define LDA \ - A = (UINT8)tmp; \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * LDX Load index X - ***************************************************************/ -#define LDX \ - X = (UINT8)tmp; \ - SET_NZ(X) - -/* 65ce02 ****************************************************** - * LDY Load index Y - ***************************************************************/ -#define LDY \ - Y = (UINT8)tmp; \ - SET_NZ(Y) - -/* 65ce02 ****************************************************** - * LDZ Load index Z - ***************************************************************/ -#define LDZ \ - Z = (UINT8)tmp; \ - SET_NZ(Z) - -/* 65ce02 ****************************************************** - * LSR Logic shift right - * 0 -> [7][6][5][4][3][2][1][0] -> C - ***************************************************************/ -#define LSR \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)tmp >> 1; \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * NEG accu - * twos complement - ***************************************************************/ -#define NEG \ - A= (A^0xff)+1; \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * NOP No operation - ***************************************************************/ -#define NOP - -/* 65ce02 ****************************************************** - * ORA Logical inclusive or - ***************************************************************/ -#define ORA \ - A = (UINT8)(A | tmp); \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * PHA Push accumulator - ***************************************************************/ -#define PHA \ - PUSH(A) - -/* 65ce02 ****************************************************** - * PHP Push processor status (flags) - ***************************************************************/ -#define PHP \ - PUSH(P) - -/* 65ce02 ****************************************************** - * PHX Push index X - ***************************************************************/ -#define PHX \ - PUSH(X) - -/* 65ce02 ****************************************************** - * PHY Push index Y - ***************************************************************/ -#define PHY \ - PUSH(Y) - -/* 65ce02 ****************************************************** - * PHZ Push index z - ***************************************************************/ -#define PHZ \ - PUSH(Z) - -/* 65ce02 ****************************************************** - * PLA Pull accumulator - ***************************************************************/ -#define PLA \ - PULL(A); \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * PLP Pull processor status (flags) - ***************************************************************/ -#define PLP \ - if ( P & F_I ) { \ - UINT8 temp; \ - PULL(temp); \ - P=(P&F_E)|F_B|(temp&~F_E); \ - if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) { \ - LOG(("M65ce02 '%s' PLP sets after_cli\n", cpustate->device->tag())); \ - AFTER_CLI = 1; \ - } \ - } else { \ - UINT8 temp; \ - PULL(temp); \ - P=(P&F_E)|F_B|(temp&~F_E); \ - } - -/* 65ce02 ****************************************************** - * PLX Pull index X - ***************************************************************/ -#define PLX \ - PULL(X); \ - SET_NZ(X) - -/* 65ce02 ****************************************************** - * PLY Pull index Y - ***************************************************************/ -#define PLY \ - PULL(Y); \ - SET_NZ(Y) - -/* 65ce02 ****************************************************** - * PLZ Pull index Z - ***************************************************************/ -#define PLZ \ - PULL(Z); \ - SET_NZ(Z) - -/* 65ce02 ****************************************************** - * RMB Reset memory bit - ***************************************************************/ -#define RMB(bit) \ - tmp &= ~(1<> 8) & F_C); \ - tmp = (UINT8)tmp; \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * ROR Rotate right - * C -> [7][6][5][4][3][2][1][0] -> new C - ***************************************************************/ -#define ROR \ - tmp |= (P & F_C) << 8; \ - P = (P & ~F_C) | (tmp & F_C); \ - tmp = (UINT8)(tmp >> 1); \ - SET_NZ(tmp) - -/* 65ce02 ****************************************************** - * ROW rotate left word - * [c] <- [15]..[6][5][4][3][2][1][0] <- C - ***************************************************************/ -/* not sure about how 16 bit memory modifying is executed */ -#define ROW \ - tmp.d =(tmp.d << 1); \ - tmp.w.l |= (P & F_C); \ - P = (P & ~F_C) | (tmp.w.l & F_C); \ - SET_NZ_WORD(tmp); - - -/* 65ce02 ******************************************************** - * RTI Return from interrupt - * pull flags, pull PC lo, pull PC hi - ***************************************************************/ -#define RTI \ - RDMEM(SPD); \ - PULL(tmp); \ - P = (P&F_E)|F_B|(tmp&~F_E); \ - PULL(PCL); \ - PULL(PCH); \ - if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) \ - { \ - LOG(("M65ce02 '%s' RTI sets after_cli\n", cpustate->device->tag())); \ - AFTER_CLI = 1; \ - } - -/* 65ce02 ****************************************************** - * RTS Return from subroutine - * pull PC lo, PC hi and increment PC - ***************************************************************/ -#define RTS \ - PULL(PCL); \ - PULL(PCH); \ - RDMEM(PCW); PCW++; - -/* 65ce02 ****************************************************** - * RTS imm - * Is the stack adjustment done before or after the return actions? - * Exact order of the read instructions unknown - ***************************************************************/ -#define RTN \ - if (P&F_E) { \ - SPL+=tmp; \ - } else { \ - SW+=tmp; \ - } \ - RDMEM(PCW-1); \ - RDMEM(PCW-1); \ - RDMEM(SPD); \ - P = (P&F_E)|F_B|(tmp&~F_E); \ - PULL(PCL); \ - PULL(PCH); \ - if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) { \ - LOG(("M65ce02 '%s' RTI sets after_cli\n", cpustate->device->tag())); \ - AFTER_CLI = 1; \ - } - - -/* 65ce02 ******************************************************* - * SBC Subtract with carry - * correct setting of flags in decimal mode - ***************************************************************/ -#define SBC \ - if (P & F_D) { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - int lo = (A & 0x0f) - (tmp & 0x0f) - c; \ - int hi = (A & 0xf0) - (tmp & 0xf0); \ - P &= ~(F_V | F_C); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( lo & 0xf0 ) \ - lo -= 6; \ - if( lo & 0x80 ) \ - hi -= 0x10; \ - if( hi & 0x0f00 ) \ - hi -= 0x60; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - A = (lo & 0x0f) + (hi & 0xf0); \ - } else { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - P &= ~(F_V | F_C); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - } \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * SEC Set carry flag - ***************************************************************/ -#if defined(SEC) -#undef SEC -#endif -#define SEC \ - P |= F_C - -/* 65ce02 ****************************************************** - * SED Set decimal flag - ***************************************************************/ -#define SED \ - P |= F_D - -/* 65ce02 ****************************************************** - * see set disable extended stack flag - ***************************************************************/ -#define SEE \ - P&=~F_E - -/* 65ce02 ****************************************************** - * SEI Set interrupt flag - ***************************************************************/ -#define SEI \ - P |= F_I - -/* 65ce02 ****************************************************** - * SMB Set memory bit - ***************************************************************/ -#define SMB(bit) \ - tmp |= (1<insn[op])(cpustate); \ - } - - -/* 65ce02 ****************************************************** - * TYA Transfer index Y to accumulator - ***************************************************************/ -#define TYA \ - A = Y; \ - SET_NZ(A) - -/* 65ce02 ****************************************************** - * TYS Transfer index y to stack pointer - ***************************************************************/ -#define TYS \ - SPH = Y; - -/* 65ce02 ****************************************************** - * TZA Transfer index z to accumulator - ***************************************************************/ -#define TZA \ - A = Z; \ - SET_NZ(A) diff --git a/src/emu/cpu/m6502/opsn2a03.h b/src/emu/cpu/m6502/opsn2a03.h deleted file mode 100644 index 8632168fe32..00000000000 --- a/src/emu/cpu/m6502/opsn2a03.h +++ /dev/null @@ -1,38 +0,0 @@ -/*************************************************************** - *************************************************************** - * Macros to emulate the N2A03 opcodes - *************************************************************** - ***************************************************************/ - - -/* N2A03 ******************************************************* - * ADC Add with carry - no decimal mode - ***************************************************************/ -#define ADC_NES \ - { \ - int c = (P & F_C); \ - int sum = A + tmp + c; \ - P &= ~(F_V | F_C); \ - if( ~(A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( sum & 0xff00 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - } \ - SET_NZ(A) - -/* N2A03 ******************************************************* - * SBC Subtract with carry - no decimal mode - ***************************************************************/ -#define SBC_NES \ - { \ - int c = (P & F_C) ^ F_C; \ - int sum = A - tmp - c; \ - P &= ~(F_V | F_C); \ - if( (A^tmp) & (A^sum) & F_N ) \ - P |= F_V; \ - if( (sum & 0xff00) == 0 ) \ - P |= F_C; \ - A = (UINT8) sum; \ - } \ - SET_NZ(A) diff --git a/src/emu/cpu/m6502/r65c02.c b/src/emu/cpu/m6502/r65c02.c index e69de29bb2d..eab84ab56c1 100644 --- a/src/emu/cpu/m6502/r65c02.c +++ b/src/emu/cpu/m6502/r65c02.c @@ -0,0 +1,60 @@ +/*************************************************************************** + + r65c02.c + + Rockwell 65c02, CMOS variant with bitwise instructions + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#include "emu.h" +#include "r65c02.h" + +const device_type R65C02 = &device_creator; + +r65c02_device::r65c02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + m65c02_device(mconfig, R65C02, "R65C02", tag, owner, clock) +{ +} + +r65c02_device::r65c02_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : + m65c02_device(mconfig, type, name, tag, owner, clock) +{ +} + +offs_t r65c02_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + return disassemble_generic(buffer, pc, oprom, opram, options, disasm_entries); +} + +#include "cpu/m6502/r65c02.inc" diff --git a/src/emu/cpu/m6502/r65c02.h b/src/emu/cpu/m6502/r65c02.h index e69de29bb2d..07996fe9ea5 100644 --- a/src/emu/cpu/m6502/r65c02.h +++ b/src/emu/cpu/m6502/r65c02.h @@ -0,0 +1,65 @@ +/*************************************************************************** + + r65c02.h + + Rockwell 65c02, CMOS variant with bitwise instructions + +**************************************************************************** + + Copyright Olivier Galibert + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name 'MAME' nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR + IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +***************************************************************************/ + +#ifndef __R65C02_H__ +#define __R65C02_H__ + +#include "m65c02.h" + +class r65c02_device : public m65c02_device { +public: + r65c02_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + r65c02_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); + + static const disasm_entry disasm_entries[0x100]; + + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void do_exec_full(); + virtual void do_exec_partial(); +}; + +enum { + R65C02_IRQ_LINE = m6502_device::IRQ_LINE, + R65C02_NMI_LINE = m6502_device::NMI_LINE, + R65C02_SET_OVERFLOW = m6502_device::V_LINE, +}; + +extern const device_type R65C02; + +#endif diff --git a/src/emu/cpu/m6502/t6502.c b/src/emu/cpu/m6502/t6502.c deleted file mode 100644 index 0bd06e6754d..00000000000 --- a/src/emu/cpu/m6502/t6502.c +++ /dev/null @@ -1,360 +0,0 @@ -/***************************************************************************** - * - * tbl6502.c - * 6502 opcode functions and function pointer table - * - * Copyright Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - * 2003-05-26 Fixed PHP, PLP, PHA, PLA cycle counts. [SJ] - * 2004-04-30 Fixed STX (abs) cycle count. [SJ] - * - *****************************************************************************/ - -#undef OP -#define OP(nn) INLINE void m6502_##nn(m6502_Regs *cpustate) - -/***************************************************************************** - ***************************************************************************** - * - * plain vanilla 6502 opcodes - * - ***************************************************************************** - * op temp cycles rdmem opc wrmem ********************/ - -OP(00) { BRK; } /* 7 BRK */ -OP(20) { JSR; } /* 6 JSR */ -OP(40) { RTI; } /* 6 RTI */ -OP(60) { RTS; } /* 6 RTS */ -OP(80) { RDOPARG(); NOP; } /* 2 NOP IMM */ -OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */ -OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */ -OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */ - -OP(10) { BPL; } /* 2-4 BPL REL */ -OP(30) { BMI; } /* 2-4 BMI REL */ -OP(50) { BVC; } /* 2-4 BVC REL */ -OP(70) { BVS; } /* 2-4 BVS REL */ -OP(90) { BCC; } /* 2-4 BCC REL */ -OP(b0) { BCS; } /* 2-4 BCS REL */ -OP(d0) { BNE; } /* 2-4 BNE REL */ -OP(f0) { BEQ; } /* 2-4 BEQ REL */ - -OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */ -OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */ -OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */ -OP(61) { int tmp; RD_IDX; ADC; } /* 6 ADC IDX */ -OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */ -OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */ -OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */ -OP(e1) { int tmp; RD_IDX; SBC; } /* 6 SBC IDX */ - -OP(11) { int tmp; RD_IDY_P; ORA; } /* 5 ORA IDY page penalty */ -OP(31) { int tmp; RD_IDY_P; AND; } /* 5 AND IDY page penalty */ -OP(51) { int tmp; RD_IDY_P; EOR; } /* 5 EOR IDY page penalty */ -OP(71) { int tmp; RD_IDY_P; ADC; } /* 5 ADC IDY page penalty */ -OP(91) { int tmp; STA; WR_IDY_NP; } /* 6 STA IDY */ -OP(b1) { int tmp; RD_IDY_P; LDA; } /* 5 LDA IDY page penalty */ -OP(d1) { int tmp; RD_IDY_P; CMP; } /* 5 CMP IDY page penalty */ -OP(f1) { int tmp; RD_IDY_P; SBC; } /* 5 SBC IDY page penalty */ - -OP(02) { KIL; } /* 1 KIL */ -OP(22) { KIL; } /* 1 KIL */ -OP(42) { KIL; } /* 1 KIL */ -OP(62) { KIL; } /* 1 KIL */ -OP(82) { RDOPARG(); NOP; } /* 2 NOP IMM */ -OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */ -OP(c2) { RDOPARG(); NOP; } /* 2 NOP IMM */ -OP(e2) { RDOPARG(); NOP; } /* 2 NOP IMM */ - -OP(12) { KIL; } /* 1 KIL */ -OP(32) { KIL; } /* 1 KIL */ -OP(52) { KIL; } /* 1 KIL */ -OP(72) { KIL; } /* 1 KIL */ -OP(92) { KIL; } /* 1 KIL */ -OP(b2) { KIL; } /* 1 KIL */ -OP(d2) { KIL; } /* 1 KIL */ -OP(f2) { KIL; } /* 1 KIL */ - -OP(03) { int tmp; RD_IDX; WB_EA; SLO; WB_EA; } /* 7 SLO IDX */ -OP(23) { int tmp; RD_IDX; WB_EA; RLA; WB_EA; } /* 7 RLA IDX */ -OP(43) { int tmp; RD_IDX; WB_EA; SRE; WB_EA; } /* 7 SRE IDX */ -OP(63) { int tmp; RD_IDX; WB_EA; RRA; WB_EA; } /* 7 RRA IDX */ -OP(83) { int tmp; SAX; WR_IDX; } /* 6 SAX IDX */ -OP(a3) { int tmp; RD_IDX; LAX; } /* 6 LAX IDX */ -OP(c3) { int tmp; RD_IDX; WB_EA; DCP; WB_EA; } /* 7 DCP IDX */ -OP(e3) { int tmp; RD_IDX; WB_EA; ISB; WB_EA; } /* 7 ISB IDX */ - -OP(13) { int tmp; RD_IDY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO IDY */ -OP(33) { int tmp; RD_IDY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA IDY */ -OP(53) { int tmp; RD_IDY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE IDY */ -OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA IDY */ -OP(93) { int tmp; EA_IDY_NP; SAH; WB_EA; } /* 5 SAH IDY */ -OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */ -OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */ -OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */ - -OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */ -OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */ -OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */ -OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */ -OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */ - -OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */ -OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */ -OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ - -OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */ -OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */ -OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */ -OP(65) { int tmp; RD_ZPG; ADC; } /* 3 ADC ZPG */ -OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */ -OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */ -OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */ -OP(e5) { int tmp; RD_ZPG; SBC; } /* 3 SBC ZPG */ - -OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */ -OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */ -OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */ -OP(75) { int tmp; RD_ZPX; ADC; } /* 4 ADC ZPX */ -OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */ -OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */ -OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */ -OP(f5) { int tmp; RD_ZPX; SBC; } /* 4 SBC ZPX */ - -OP(06) { int tmp; RD_ZPG; WB_EA; ASL; WB_EA; } /* 5 ASL ZPG */ -OP(26) { int tmp; RD_ZPG; WB_EA; ROL; WB_EA; } /* 5 ROL ZPG */ -OP(46) { int tmp; RD_ZPG; WB_EA; LSR; WB_EA; } /* 5 LSR ZPG */ -OP(66) { int tmp; RD_ZPG; WB_EA; ROR; WB_EA; } /* 5 ROR ZPG */ -OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */ -OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */ -OP(c6) { int tmp; RD_ZPG; WB_EA; DEC; WB_EA; } /* 5 DEC ZPG */ -OP(e6) { int tmp; RD_ZPG; WB_EA; INC; WB_EA; } /* 5 INC ZPG */ - -OP(16) { int tmp; RD_ZPX; WB_EA; ASL; WB_EA; } /* 6 ASL ZPX */ -OP(36) { int tmp; RD_ZPX; WB_EA; ROL; WB_EA; } /* 6 ROL ZPX */ -OP(56) { int tmp; RD_ZPX; WB_EA; LSR; WB_EA; } /* 6 LSR ZPX */ -OP(76) { int tmp; RD_ZPX; WB_EA; ROR; WB_EA; } /* 6 ROR ZPX */ -OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */ -OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */ -OP(d6) { int tmp; RD_ZPX; WB_EA; DEC; WB_EA; } /* 6 DEC ZPX */ -OP(f6) { int tmp; RD_ZPX; WB_EA; INC; WB_EA; } /* 6 INC ZPX */ - -OP(07) { int tmp; RD_ZPG; WB_EA; SLO; WB_EA; } /* 5 SLO ZPG */ -OP(27) { int tmp; RD_ZPG; WB_EA; RLA; WB_EA; } /* 5 RLA ZPG */ -OP(47) { int tmp; RD_ZPG; WB_EA; SRE; WB_EA; } /* 5 SRE ZPG */ -OP(67) { int tmp; RD_ZPG; WB_EA; RRA; WB_EA; } /* 5 RRA ZPG */ -OP(87) { int tmp; SAX; WR_ZPG; } /* 3 SAX ZPG */ -OP(a7) { int tmp; RD_ZPG; LAX; } /* 3 LAX ZPG */ -OP(c7) { int tmp; RD_ZPG; WB_EA; DCP; WB_EA; } /* 5 DCP ZPG */ -OP(e7) { int tmp; RD_ZPG; WB_EA; ISB; WB_EA; } /* 5 ISB ZPG */ - -OP(17) { int tmp; RD_ZPX; WB_EA; SLO; WB_EA; } /* 6 SLO ZPX */ -OP(37) { int tmp; RD_ZPX; WB_EA; RLA; WB_EA; } /* 6 RLA ZPX */ -OP(57) { int tmp; RD_ZPX; WB_EA; SRE; WB_EA; } /* 6 SRE ZPX */ -OP(77) { int tmp; RD_ZPX; WB_EA; RRA; WB_EA; } /* 6 RRA ZPX */ -OP(97) { int tmp; SAX; WR_ZPY; } /* 4 SAX ZPY */ -OP(b7) { int tmp; RD_ZPY; LAX; } /* 4 LAX ZPY */ -OP(d7) { int tmp; RD_ZPX; WB_EA; DCP; WB_EA; } /* 6 DCP ZPX */ -OP(f7) { int tmp; RD_ZPX; WB_EA; ISB; WB_EA; } /* 6 ISB ZPX */ - -OP(08) { RD_DUM; PHP; } /* 3 PHP */ -OP(28) { RD_DUM; PLP; } /* 4 PLP */ -OP(48) { RD_DUM; PHA; } /* 3 PHA */ -OP(68) { RD_DUM; PLA; } /* 4 PLA */ -OP(88) { RD_DUM; DEY; } /* 2 DEY */ -OP(a8) { RD_DUM; TAY; } /* 2 TAY */ -OP(c8) { RD_DUM; INY; } /* 2 INY */ -OP(e8) { RD_DUM; INX; } /* 2 INX */ - -OP(18) { RD_DUM; CLC; } /* 2 CLC */ -OP(38) { RD_DUM; SEC; } /* 2 SEC */ -OP(58) { RD_DUM; CLI; } /* 2 CLI */ -OP(78) { RD_DUM; SEI; } /* 2 SEI */ -OP(98) { RD_DUM; TYA; } /* 2 TYA */ -OP(b8) { RD_DUM; CLV; } /* 2 CLV */ -OP(d8) { RD_DUM; CLD; } /* 2 CLD */ -OP(f8) { RD_DUM; SED; } /* 2 SED */ - -OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */ -OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */ -OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */ -OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */ -OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ -OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */ -OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */ -OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(19) { int tmp; RD_ABY_P; ORA; } /* 4 ORA ABY page penalty */ -OP(39) { int tmp; RD_ABY_P; AND; } /* 4 AND ABY page penalty */ -OP(59) { int tmp; RD_ABY_P; EOR; } /* 4 EOR ABY page penalty */ -OP(79) { int tmp; RD_ABY_P; ADC; } /* 4 ADC ABY page penalty */ -OP(99) { int tmp; STA; WR_ABY_NP; } /* 5 STA ABY */ -OP(b9) { int tmp; RD_ABY_P; LDA; } /* 4 LDA ABY page penalty */ -OP(d9) { int tmp; RD_ABY_P; CMP; } /* 4 CMP ABY page penalty */ -OP(f9) { int tmp; RD_ABY_P; SBC; } /* 4 SBC ABY page penalty */ - -OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */ -OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */ -OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */ -OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */ -OP(8a) { RD_DUM; TXA; } /* 2 TXA */ -OP(aa) { RD_DUM; TAX; } /* 2 TAX */ -OP(ca) { RD_DUM; DEX; } /* 2 DEX */ -OP(ea) { RD_DUM; NOP; } /* 2 NOP */ - -OP(1a) { RD_DUM; NOP; } /* 2 NOP */ -OP(3a) { RD_DUM; NOP; } /* 2 NOP */ -OP(5a) { RD_DUM; NOP; } /* 2 NOP */ -OP(7a) { RD_DUM; NOP; } /* 2 NOP */ -OP(9a) { RD_DUM; TXS; } /* 2 TXS */ -OP(ba) { RD_DUM; TSX; } /* 2 TSX */ -OP(da) { RD_DUM; NOP; } /* 2 NOP */ -OP(fa) { RD_DUM; NOP; } /* 2 NOP */ - -OP(0b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */ -OP(2b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */ -OP(4b) { int tmp; RD_IMM; ASR; WB_ACC; } /* 2 ASR IMM */ -OP(6b) { int tmp; RD_IMM; ARR; WB_ACC; } /* 2 ARR IMM */ -OP(8b) { int tmp; RD_IMM; AXA; } /* 2 AXA IMM */ -OP(ab) { int tmp; RD_IMM; OAL; } /* 2 OAL IMM */ -OP(cb) { int tmp; RD_IMM; ASX; } /* 2 ASX IMM */ -OP(eb) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(1b) { int tmp; RD_ABY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABY */ -OP(3b) { int tmp; RD_ABY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABY */ -OP(5b) { int tmp; RD_ABY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABY */ -OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABY */ -OP(9b) { int tmp; EA_ABY_NP; SSH; WB_EA; } /* 5 SSH ABY */ -OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */ -OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */ -OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */ - -OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */ -OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */ -OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */ -OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */ -OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */ -OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */ -OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */ -OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */ - -OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */ -OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */ -OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ - -OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */ -OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */ -OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */ -OP(6d) { int tmp; RD_ABS; ADC; } /* 4 ADC ABS */ -OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */ -OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */ -OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */ -OP(ed) { int tmp; RD_ABS; SBC; } /* 4 SBC ABS */ - -OP(1d) { int tmp; RD_ABX_P; ORA; } /* 4 ORA ABX page penalty */ -OP(3d) { int tmp; RD_ABX_P; AND; } /* 4 AND ABX page penalty */ -OP(5d) { int tmp; RD_ABX_P; EOR; } /* 4 EOR ABX page penalty */ -OP(7d) { int tmp; RD_ABX_P; ADC; } /* 4 ADC ABX page penalty */ -OP(9d) { int tmp; STA; WR_ABX_NP; } /* 5 STA ABX */ -OP(bd) { int tmp; RD_ABX_P; LDA; } /* 4 LDA ABX page penalty */ -OP(dd) { int tmp; RD_ABX_P; CMP; } /* 4 CMP ABX page penalty */ -OP(fd) { int tmp; RD_ABX_P; SBC; } /* 4 SBC ABX page penalty */ - -OP(0e) { int tmp; RD_ABS; WB_EA; ASL; WB_EA; } /* 6 ASL ABS */ -OP(2e) { int tmp; RD_ABS; WB_EA; ROL; WB_EA; } /* 6 ROL ABS */ -OP(4e) { int tmp; RD_ABS; WB_EA; LSR; WB_EA; } /* 6 LSR ABS */ -OP(6e) { int tmp; RD_ABS; WB_EA; ROR; WB_EA; } /* 6 ROR ABS */ -OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */ -OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */ -OP(ce) { int tmp; RD_ABS; WB_EA; DEC; WB_EA; } /* 6 DEC ABS */ -OP(ee) { int tmp; RD_ABS; WB_EA; INC; WB_EA; } /* 6 INC ABS */ - -OP(1e) { int tmp; RD_ABX_NP; WB_EA; ASL; WB_EA; } /* 7 ASL ABX */ -OP(3e) { int tmp; RD_ABX_NP; WB_EA; ROL; WB_EA; } /* 7 ROL ABX */ -OP(5e) { int tmp; RD_ABX_NP; WB_EA; LSR; WB_EA; } /* 7 LSR ABX */ -OP(7e) { int tmp; RD_ABX_NP; WB_EA; ROR; WB_EA; } /* 7 ROR ABX */ -OP(9e) { int tmp; EA_ABY_NP; SXH; WB_EA; } /* 5 SXH ABY */ -OP(be) { int tmp; RD_ABY_P; LDX; } /* 4 LDX ABY page penalty */ -OP(de) { int tmp; RD_ABX_NP; WB_EA; DEC; WB_EA; } /* 7 DEC ABX */ -OP(fe) { int tmp; RD_ABX_NP; WB_EA; INC; WB_EA; } /* 7 INC ABX */ - -OP(0f) { int tmp; RD_ABS; WB_EA; SLO; WB_EA; } /* 6 SLO ABS */ -OP(2f) { int tmp; RD_ABS; WB_EA; RLA; WB_EA; } /* 6 RLA ABS */ -OP(4f) { int tmp; RD_ABS; WB_EA; SRE; WB_EA; } /* 6 SRE ABS */ -OP(6f) { int tmp; RD_ABS; WB_EA; RRA; WB_EA; } /* 6 RRA ABS */ -OP(8f) { int tmp; SAX; WR_ABS; } /* 4 SAX ABS */ -OP(af) { int tmp; RD_ABS; LAX; } /* 4 LAX ABS */ -OP(cf) { int tmp; RD_ABS; WB_EA; DCP; WB_EA; } /* 6 DCP ABS */ -OP(ef) { int tmp; RD_ABS; WB_EA; ISB; WB_EA; } /* 6 ISB ABS */ - -OP(1f) { int tmp; RD_ABX_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABX */ -OP(3f) { int tmp; RD_ABX_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABX */ -OP(5f) { int tmp; RD_ABX_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABX */ -OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABX */ -OP(9f) { int tmp; EA_ABY_NP; SAH; WB_EA; } /* 5 SAH ABY */ -OP(bf) { int tmp; RD_ABY_P; LAX; } /* 4 LAX ABY page penalty */ -OP(df) { int tmp; RD_ABX_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABX */ -OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */ - -/* and here's the array of function pointers */ - -static void (*const insn6502[0x100])(m6502_Regs *cpustate) = { - m6502_00,m6502_01,m6502_02,m6502_03,m6502_04,m6502_05,m6502_06,m6502_07, - m6502_08,m6502_09,m6502_0a,m6502_0b,m6502_0c,m6502_0d,m6502_0e,m6502_0f, - m6502_10,m6502_11,m6502_12,m6502_13,m6502_14,m6502_15,m6502_16,m6502_17, - m6502_18,m6502_19,m6502_1a,m6502_1b,m6502_1c,m6502_1d,m6502_1e,m6502_1f, - m6502_20,m6502_21,m6502_22,m6502_23,m6502_24,m6502_25,m6502_26,m6502_27, - m6502_28,m6502_29,m6502_2a,m6502_2b,m6502_2c,m6502_2d,m6502_2e,m6502_2f, - m6502_30,m6502_31,m6502_32,m6502_33,m6502_34,m6502_35,m6502_36,m6502_37, - m6502_38,m6502_39,m6502_3a,m6502_3b,m6502_3c,m6502_3d,m6502_3e,m6502_3f, - m6502_40,m6502_41,m6502_42,m6502_43,m6502_44,m6502_45,m6502_46,m6502_47, - m6502_48,m6502_49,m6502_4a,m6502_4b,m6502_4c,m6502_4d,m6502_4e,m6502_4f, - m6502_50,m6502_51,m6502_52,m6502_53,m6502_54,m6502_55,m6502_56,m6502_57, - m6502_58,m6502_59,m6502_5a,m6502_5b,m6502_5c,m6502_5d,m6502_5e,m6502_5f, - m6502_60,m6502_61,m6502_62,m6502_63,m6502_64,m6502_65,m6502_66,m6502_67, - m6502_68,m6502_69,m6502_6a,m6502_6b,m6502_6c,m6502_6d,m6502_6e,m6502_6f, - m6502_70,m6502_71,m6502_72,m6502_73,m6502_74,m6502_75,m6502_76,m6502_77, - m6502_78,m6502_79,m6502_7a,m6502_7b,m6502_7c,m6502_7d,m6502_7e,m6502_7f, - m6502_80,m6502_81,m6502_82,m6502_83,m6502_84,m6502_85,m6502_86,m6502_87, - m6502_88,m6502_89,m6502_8a,m6502_8b,m6502_8c,m6502_8d,m6502_8e,m6502_8f, - m6502_90,m6502_91,m6502_92,m6502_93,m6502_94,m6502_95,m6502_96,m6502_97, - m6502_98,m6502_99,m6502_9a,m6502_9b,m6502_9c,m6502_9d,m6502_9e,m6502_9f, - m6502_a0,m6502_a1,m6502_a2,m6502_a3,m6502_a4,m6502_a5,m6502_a6,m6502_a7, - m6502_a8,m6502_a9,m6502_aa,m6502_ab,m6502_ac,m6502_ad,m6502_ae,m6502_af, - m6502_b0,m6502_b1,m6502_b2,m6502_b3,m6502_b4,m6502_b5,m6502_b6,m6502_b7, - m6502_b8,m6502_b9,m6502_ba,m6502_bb,m6502_bc,m6502_bd,m6502_be,m6502_bf, - m6502_c0,m6502_c1,m6502_c2,m6502_c3,m6502_c4,m6502_c5,m6502_c6,m6502_c7, - m6502_c8,m6502_c9,m6502_ca,m6502_cb,m6502_cc,m6502_cd,m6502_ce,m6502_cf, - m6502_d0,m6502_d1,m6502_d2,m6502_d3,m6502_d4,m6502_d5,m6502_d6,m6502_d7, - m6502_d8,m6502_d9,m6502_da,m6502_db,m6502_dc,m6502_dd,m6502_de,m6502_df, - m6502_e0,m6502_e1,m6502_e2,m6502_e3,m6502_e4,m6502_e5,m6502_e6,m6502_e7, - m6502_e8,m6502_e9,m6502_ea,m6502_eb,m6502_ec,m6502_ed,m6502_ee,m6502_ef, - m6502_f0,m6502_f1,m6502_f2,m6502_f3,m6502_f4,m6502_f5,m6502_f6,m6502_f7, - m6502_f8,m6502_f9,m6502_fa,m6502_fb,m6502_fc,m6502_fd,m6502_fe,m6502_ff -}; - diff --git a/src/emu/cpu/m6502/t6509.c b/src/emu/cpu/m6502/t6509.c deleted file mode 100644 index 9803a7f325a..00000000000 --- a/src/emu/cpu/m6502/t6509.c +++ /dev/null @@ -1,352 +0,0 @@ -/***************************************************************************** - * - * tbl6509.c - * 6509 opcode functions and function pointer table - * - * Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - * - Opcode information based on an Intel 386 '6510.asm' core - * written by R.F. van Ee (1993) - * - Cycle counts are guesswork :-) - * - *****************************************************************************/ - -#undef OP -#define OP(nn) INLINE void m6509_##nn(m6509_Regs *cpustate) - -OP(00) { BRK; } /* 7 BRK */ -OP(20) { JSR; } /* 6 JSR */ -OP(40) { RTI; } /* 6 RTI */ -OP(60) { RTS; } /* 6 RTS */ -OP(80) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ -OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */ -OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */ -OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */ - -OP(10) { int tmp; BPL; } /* 2-4 BPL REL */ -OP(30) { int tmp; BMI; } /* 2-4 BMI REL */ -OP(50) { int tmp; BVC; } /* 2-4 BVC REL */ -OP(70) { int tmp; BVS; } /* 2-4 BVS REL */ -OP(90) { int tmp; BCC; } /* 2-4 BCC REL */ -OP(b0) { int tmp; BCS; } /* 2-4 BCS REL */ -OP(d0) { int tmp; BNE; } /* 2-4 BNE REL */ -OP(f0) { int tmp; BEQ; } /* 2-4 BEQ REL */ - -OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */ -OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */ -OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */ -OP(61) { int tmp; RD_IDX; ADC; } /* 6 ADC IDX */ -OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */ -OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */ -OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */ -OP(e1) { int tmp; RD_IDX; SBC; } /* 6 SBC IDX */ - -OP(11) { int tmp; RD_IDY_P; ORA; } /* 5 ORA IDY page penalty */ -OP(31) { int tmp; RD_IDY_P; AND; } /* 5 AND IDY page penalty */ -OP(51) { int tmp; RD_IDY_P; EOR; } /* 5 EOR IDY page penalty */ -OP(71) { int tmp; RD_IDY_P; ADC; } /* 5 ADC IDY page penalty */ -OP(91) { int tmp; STA; WR_IDY_6509; } /* 6 STA IDY */ -OP(b1) { int tmp; RD_IDY_6509; LDA; } /* 5 LDA IDY page penalty */ -OP(d1) { int tmp; RD_IDY_P; CMP; } /* 5 CMP IDY page penalty */ -OP(f1) { int tmp; RD_IDY_P; SBC; } /* 5 SBC IDY page penalty */ - -OP(02) { KIL; } /* 1 KIL */ -OP(22) { KIL; } /* 1 KIL */ -OP(42) { KIL; } /* 1 KIL */ -OP(62) { KIL; } /* 1 KIL */ -OP(82) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ -OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */ -OP(c2) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ -OP(e2) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ - -OP(12) { KIL; } /* 1 KIL */ -OP(32) { KIL; } /* 1 KIL */ -OP(52) { KIL; } /* 1 KIL */ -OP(72) { KIL; } /* 1 KIL */ -OP(92) { KIL; } /* 1 KIL */ -OP(b2) { KIL; } /* 1 KIL */ -OP(d2) { KIL; } /* 1 KIL */ -OP(f2) { KIL; } /* 1 KIL */ - -OP(03) { int tmp; RD_IDX; WB_EA; SLO; WB_EA; } /* 7 SLO IDX */ -OP(23) { int tmp; RD_IDX; WB_EA; RLA; WB_EA; } /* 7 RLA IDX */ -OP(43) { int tmp; RD_IDX; WB_EA; SRE; WB_EA; } /* 7 SRE IDX */ -OP(63) { int tmp; RD_IDX; WB_EA; RRA; WB_EA; } /* 7 RRA IDX */ -OP(83) { int tmp; SAX; WR_IDX; } /* 6 SAX IDX */ -OP(a3) { int tmp; RD_IDX; LAX; } /* 6 LAX IDX */ -OP(c3) { int tmp; RD_IDX; WB_EA; DCP; WB_EA; } /* 7 DCP IDX */ -OP(e3) { int tmp; RD_IDX; WB_EA; ISB; WB_EA; } /* 7 ISB IDX */ - -OP(13) { int tmp; RD_IDY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO IDY */ -OP(33) { int tmp; RD_IDY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA IDY */ -OP(53) { int tmp; RD_IDY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE IDY */ -OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA IDY */ -OP(93) { int tmp; EA_IDY_NP; SAH; WB_EA; } /* 5 SAH IDY */ -OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */ -OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */ -OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */ - -OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */ -OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */ -OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */ -OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */ -OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */ - -OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */ -OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */ -OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ - -OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */ -OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */ -OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */ -OP(65) { int tmp; RD_ZPG; ADC; } /* 3 ADC ZPG */ -OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */ -OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */ -OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */ -OP(e5) { int tmp; RD_ZPG; SBC; } /* 3 SBC ZPG */ - -OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */ -OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */ -OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */ -OP(75) { int tmp; RD_ZPX; ADC; } /* 4 ADC ZPX */ -OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */ -OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */ -OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */ -OP(f5) { int tmp; RD_ZPX; SBC; } /* 4 SBC ZPX */ - -OP(06) { int tmp; RD_ZPG; WB_EA; ASL; WB_EA; } /* 5 ASL ZPG */ -OP(26) { int tmp; RD_ZPG; WB_EA; ROL; WB_EA; } /* 5 ROL ZPG */ -OP(46) { int tmp; RD_ZPG; WB_EA; LSR; WB_EA; } /* 5 LSR ZPG */ -OP(66) { int tmp; RD_ZPG; WB_EA; ROR; WB_EA; } /* 5 ROR ZPG */ -OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */ -OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */ -OP(c6) { int tmp; RD_ZPG; WB_EA; DEC; WB_EA; } /* 5 DEC ZPG */ -OP(e6) { int tmp; RD_ZPG; WB_EA; INC; WB_EA; } /* 5 INC ZPG */ - -OP(16) { int tmp; RD_ZPX; WB_EA; ASL; WB_EA; } /* 6 ASL ZPX */ -OP(36) { int tmp; RD_ZPX; WB_EA; ROL; WB_EA; } /* 6 ROL ZPX */ -OP(56) { int tmp; RD_ZPX; WB_EA; LSR; WB_EA; } /* 6 LSR ZPX */ -OP(76) { int tmp; RD_ZPX; WB_EA; ROR; WB_EA; } /* 6 ROR ZPX */ -OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */ -OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */ -OP(d6) { int tmp; RD_ZPX; WB_EA; DEC; WB_EA; } /* 6 DEC ZPX */ -OP(f6) { int tmp; RD_ZPX; WB_EA; INC; WB_EA; } /* 6 INC ZPX */ - -OP(07) { int tmp; RD_ZPG; WB_EA; SLO; WB_EA; } /* 5 SLO ZPG */ -OP(27) { int tmp; RD_ZPG; WB_EA; RLA; WB_EA; } /* 5 RLA ZPG */ -OP(47) { int tmp; RD_ZPG; WB_EA; SRE; WB_EA; } /* 5 SRE ZPG */ -OP(67) { int tmp; RD_ZPG; WB_EA; RRA; WB_EA; } /* 5 RRA ZPG */ -OP(87) { int tmp; SAX; WR_ZPG; } /* 3 SAX ZPG */ -OP(a7) { int tmp; RD_ZPG; LAX; } /* 3 LAX ZPG */ -OP(c7) { int tmp; RD_ZPG; WB_EA; DCP; WB_EA; } /* 5 DCP ZPG */ -OP(e7) { int tmp; RD_ZPG; WB_EA; ISB; WB_EA; } /* 5 ISB ZPG */ - -OP(17) { int tmp; RD_ZPX; WB_EA; SLO; WB_EA; } /* 6 SLO ZPX */ -OP(37) { int tmp; RD_ZPX; WB_EA; RLA; WB_EA; } /* 6 RLA ZPX */ -OP(57) { int tmp; RD_ZPX; WB_EA; SRE; WB_EA; } /* 6 SRE ZPX */ -OP(77) { int tmp; RD_ZPX; WB_EA; RRA; WB_EA; } /* 6 RRA ZPX */ -OP(97) { int tmp; SAX; WR_ZPY; } /* 4 SAX ZPY */ -OP(b7) { int tmp; RD_ZPY; LAX; } /* 4 LAX ZPY */ -OP(d7) { int tmp; RD_ZPX; WB_EA; DCP; WB_EA; } /* 6 DCP ZPX */ -OP(f7) { int tmp; RD_ZPX; WB_EA; ISB; WB_EA; } /* 6 ISB ZPX */ - -OP(08) { RD_DUM; PHP; } /* 3 PHP */ -OP(28) { RD_DUM; PLP; } /* 4 PLP */ -OP(48) { RD_DUM; PHA; } /* 3 PHA */ -OP(68) { RD_DUM; PLA; } /* 4 PLA */ -OP(88) { RD_DUM; DEY; } /* 2 DEY */ -OP(a8) { RD_DUM; TAY; } /* 2 TAY */ -OP(c8) { RD_DUM; INY; } /* 2 INY */ -OP(e8) { RD_DUM; INX; } /* 2 INX */ - -OP(18) { RD_DUM; CLC; } /* 2 CLC */ -OP(38) { RD_DUM; SEC; } /* 2 SEC */ -OP(58) { RD_DUM; CLI; } /* 2 CLI */ -OP(78) { RD_DUM; SEI; } /* 2 SEI */ -OP(98) { RD_DUM; TYA; } /* 2 TYA */ -OP(b8) { RD_DUM; CLV; } /* 2 CLV */ -OP(d8) { RD_DUM; CLD; } /* 2 CLD */ -OP(f8) { RD_DUM; SED; } /* 2 SED */ - -OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */ -OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */ -OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */ -OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */ -OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ -OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */ -OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */ -OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(19) { int tmp; RD_ABY_P; ORA; } /* 4 ORA ABY page penalty */ -OP(39) { int tmp; RD_ABY_P; AND; } /* 4 AND ABY page penalty */ -OP(59) { int tmp; RD_ABY_P; EOR; } /* 4 EOR ABY page penalty */ -OP(79) { int tmp; RD_ABY_P; ADC; } /* 4 ADC ABY page penalty */ -OP(99) { int tmp; STA; WR_ABY_NP; } /* 5 STA ABY */ -OP(b9) { int tmp; RD_ABY_P; LDA; } /* 4 LDA ABY page penalty */ -OP(d9) { int tmp; RD_ABY_P; CMP; } /* 4 CMP ABY page penalty */ -OP(f9) { int tmp; RD_ABY_P; SBC; } /* 4 SBC ABY page penalty */ - -OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */ -OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */ -OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */ -OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */ -OP(8a) { RD_DUM; TXA; } /* 2 TXA */ -OP(aa) { RD_DUM; TAX; } /* 2 TAX */ -OP(ca) { RD_DUM; DEX; } /* 2 DEX */ -OP(ea) { RD_DUM; NOP; } /* 2 NOP */ - -OP(1a) { RD_DUM; NOP; } /* 2 NOP */ -OP(3a) { RD_DUM; NOP; } /* 2 NOP */ -OP(5a) { RD_DUM; NOP; } /* 2 NOP */ -OP(7a) { RD_DUM; NOP; } /* 2 NOP */ -OP(9a) { RD_DUM; TXS; } /* 2 TXS */ -OP(ba) { RD_DUM; TSX; } /* 2 TSX */ -OP(da) { RD_DUM; NOP; } /* 2 NOP */ -OP(fa) { RD_DUM; NOP; } /* 2 NOP */ - -OP(0b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */ -OP(2b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */ -OP(4b) { int tmp; RD_IMM; ASR; WB_ACC; } /* 2 ASR IMM */ -OP(6b) { int tmp; RD_IMM; ARR; WB_ACC; } /* 2 ARR IMM */ -OP(8b) { int tmp; RD_IMM; AXA; } /* 2 AXA IMM */ -OP(ab) { int tmp; RD_IMM; OAL; } /* 2 OAL IMM */ -OP(cb) { int tmp; RD_IMM; ASX; } /* 2 ASX IMM */ -OP(eb) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(1b) { int tmp; RD_ABY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABY */ -OP(3b) { int tmp; RD_ABY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABY */ -OP(5b) { int tmp; RD_ABY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABY */ -OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABY */ -OP(9b) { int tmp; EA_ABY_NP; SSH; WB_EA; } /* 5 SSH ABY */ -OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */ -OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */ -OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */ - -OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */ -OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */ -OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */ -OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */ -OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */ -OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */ -OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */ -OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */ - -OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */ -OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */ -OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ - -OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */ -OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */ -OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */ -OP(6d) { int tmp; RD_ABS; ADC; } /* 4 ADC ABS */ -OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */ -OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */ -OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */ -OP(ed) { int tmp; RD_ABS; SBC; } /* 4 SBC ABS */ - -OP(1d) { int tmp; RD_ABX_P; ORA; } /* 4 ORA ABX page penalty */ -OP(3d) { int tmp; RD_ABX_P; AND; } /* 4 AND ABX page penalty */ -OP(5d) { int tmp; RD_ABX_P; EOR; } /* 4 EOR ABX page penalty */ -OP(7d) { int tmp; RD_ABX_P; ADC; } /* 4 ADC ABX page penalty */ -OP(9d) { int tmp; STA; WR_ABX_NP; } /* 5 STA ABX */ -OP(bd) { int tmp; RD_ABX_P; LDA; } /* 4 LDA ABX page penalty */ -OP(dd) { int tmp; RD_ABX_P; CMP; } /* 4 CMP ABX page penalty */ -OP(fd) { int tmp; RD_ABX_P; SBC; } /* 4 SBC ABX page penalty */ - -OP(0e) { int tmp; RD_ABS; WB_EA; ASL; WB_EA; } /* 6 ASL ABS */ -OP(2e) { int tmp; RD_ABS; WB_EA; ROL; WB_EA; } /* 6 ROL ABS */ -OP(4e) { int tmp; RD_ABS; WB_EA; LSR; WB_EA; } /* 6 LSR ABS */ -OP(6e) { int tmp; RD_ABS; WB_EA; ROR; WB_EA; } /* 6 ROR ABS */ -OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */ -OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */ -OP(ce) { int tmp; RD_ABS; WB_EA; DEC; WB_EA; } /* 6 DEC ABS */ -OP(ee) { int tmp; RD_ABS; WB_EA; INC; WB_EA; } /* 6 INC ABS */ - -OP(1e) { int tmp; RD_ABX_NP; WB_EA; ASL; WB_EA; } /* 7 ASL ABX */ -OP(3e) { int tmp; RD_ABX_NP; WB_EA; ROL; WB_EA; } /* 7 ROL ABX */ -OP(5e) { int tmp; RD_ABX_NP; WB_EA; LSR; WB_EA; } /* 7 LSR ABX */ -OP(7e) { int tmp; RD_ABX_NP; WB_EA; ROR; WB_EA; } /* 7 ROR ABX */ -OP(9e) { int tmp; EA_ABY_NP; SXH; WB_EA; } /* 5 SXH ABY */ -OP(be) { int tmp; RD_ABY_P; LDX; } /* 4 LDX ABY page penalty */ -OP(de) { int tmp; RD_ABX_NP; WB_EA; DEC; WB_EA; } /* 7 DEC ABX */ -OP(fe) { int tmp; RD_ABX_NP; WB_EA; INC; WB_EA; } /* 7 INC ABX */ - -OP(0f) { int tmp; RD_ABS; WB_EA; SLO; WB_EA; } /* 6 SLO ABS */ -OP(2f) { int tmp; RD_ABS; WB_EA; RLA; WB_EA; } /* 6 RLA ABS */ -OP(4f) { int tmp; RD_ABS; WB_EA; SRE; WB_EA; } /* 6 SRE ABS */ -OP(6f) { int tmp; RD_ABS; WB_EA; RRA; WB_EA; } /* 6 RRA ABS */ -OP(8f) { int tmp; SAX; WR_ABS; } /* 4 SAX ABS */ -OP(af) { int tmp; RD_ABS; LAX; } /* 4 LAX ABS */ -OP(cf) { int tmp; RD_ABS; WB_EA; DCP; WB_EA; } /* 6 DCP ABS */ -OP(ef) { int tmp; RD_ABS; WB_EA; ISB; WB_EA; } /* 6 ISB ABS */ - -OP(1f) { int tmp; RD_ABX_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABX */ -OP(3f) { int tmp; RD_ABX_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABX */ -OP(5f) { int tmp; RD_ABX_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABX */ -OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABX */ -OP(9f) { int tmp; EA_ABY_NP; SAH; WB_EA; } /* 5 SAH ABY */ -OP(bf) { int tmp; RD_ABY_P; LAX; } /* 4 LAX ABY page penalty */ -OP(df) { int tmp; RD_ABX_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABX */ -OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */ - -static void (*const insn6509[0x100])(m6509_Regs *) = { - m6509_00,m6509_01,m6509_02,m6509_03,m6509_04,m6509_05,m6509_06,m6509_07, - m6509_08,m6509_09,m6509_0a,m6509_0b,m6509_0c,m6509_0d,m6509_0e,m6509_0f, - m6509_10,m6509_11,m6509_12,m6509_13,m6509_14,m6509_15,m6509_16,m6509_17, - m6509_18,m6509_19,m6509_1a,m6509_1b,m6509_1c,m6509_1d,m6509_1e,m6509_1f, - m6509_20,m6509_21,m6509_22,m6509_23,m6509_24,m6509_25,m6509_26,m6509_27, - m6509_28,m6509_29,m6509_2a,m6509_2b,m6509_2c,m6509_2d,m6509_2e,m6509_2f, - m6509_30,m6509_31,m6509_32,m6509_33,m6509_34,m6509_35,m6509_36,m6509_37, - m6509_38,m6509_39,m6509_3a,m6509_3b,m6509_3c,m6509_3d,m6509_3e,m6509_3f, - m6509_40,m6509_41,m6509_42,m6509_43,m6509_44,m6509_45,m6509_46,m6509_47, - m6509_48,m6509_49,m6509_4a,m6509_4b,m6509_4c,m6509_4d,m6509_4e,m6509_4f, - m6509_50,m6509_51,m6509_52,m6509_53,m6509_54,m6509_55,m6509_56,m6509_57, - m6509_58,m6509_59,m6509_5a,m6509_5b,m6509_5c,m6509_5d,m6509_5e,m6509_5f, - m6509_60,m6509_61,m6509_62,m6509_63,m6509_64,m6509_65,m6509_66,m6509_67, - m6509_68,m6509_69,m6509_6a,m6509_6b,m6509_6c,m6509_6d,m6509_6e,m6509_6f, - m6509_70,m6509_71,m6509_72,m6509_73,m6509_74,m6509_75,m6509_76,m6509_77, - m6509_78,m6509_79,m6509_7a,m6509_7b,m6509_7c,m6509_7d,m6509_7e,m6509_7f, - m6509_80,m6509_81,m6509_82,m6509_83,m6509_84,m6509_85,m6509_86,m6509_87, - m6509_88,m6509_89,m6509_8a,m6509_8b,m6509_8c,m6509_8d,m6509_8e,m6509_8f, - m6509_90,m6509_91,m6509_92,m6509_93,m6509_94,m6509_95,m6509_96,m6509_97, - m6509_98,m6509_99,m6509_9a,m6509_9b,m6509_9c,m6509_9d,m6509_9e,m6509_9f, - m6509_a0,m6509_a1,m6509_a2,m6509_a3,m6509_a4,m6509_a5,m6509_a6,m6509_a7, - m6509_a8,m6509_a9,m6509_aa,m6509_ab,m6509_ac,m6509_ad,m6509_ae,m6509_af, - m6509_b0,m6509_b1,m6509_b2,m6509_b3,m6509_b4,m6509_b5,m6509_b6,m6509_b7, - m6509_b8,m6509_b9,m6509_ba,m6509_bb,m6509_bc,m6509_bd,m6509_be,m6509_bf, - m6509_c0,m6509_c1,m6509_c2,m6509_c3,m6509_c4,m6509_c5,m6509_c6,m6509_c7, - m6509_c8,m6509_c9,m6509_ca,m6509_cb,m6509_cc,m6509_cd,m6509_ce,m6509_cf, - m6509_d0,m6509_d1,m6509_d2,m6509_d3,m6509_d4,m6509_d5,m6509_d6,m6509_d7, - m6509_d8,m6509_d9,m6509_da,m6509_db,m6509_dc,m6509_dd,m6509_de,m6509_df, - m6509_e0,m6509_e1,m6509_e2,m6509_e3,m6509_e4,m6509_e5,m6509_e6,m6509_e7, - m6509_e8,m6509_e9,m6509_ea,m6509_eb,m6509_ec,m6509_ed,m6509_ee,m6509_ef, - m6509_f0,m6509_f1,m6509_f2,m6509_f3,m6509_f4,m6509_f5,m6509_f6,m6509_f7, - m6509_f8,m6509_f9,m6509_fa,m6509_fb,m6509_fc,m6509_fd,m6509_fe,m6509_ff -}; - - diff --git a/src/emu/cpu/m6502/t6510.c b/src/emu/cpu/m6502/t6510.c deleted file mode 100644 index e46ffeb8503..00000000000 --- a/src/emu/cpu/m6502/t6510.c +++ /dev/null @@ -1,361 +0,0 @@ -/***************************************************************************** - * - * tbl6510.c - * 6510 opcode functions and function pointer table - * - * Copyright Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - * - Opcode information based on an Intel 386 '6510.asm' core - * written by R.F. van Ee (1993) - * - Cycle counts are guesswork :-) - * - *****************************************************************************/ - -#undef OP -#define OP(nn) INLINE void m6510_##nn(m6502_Regs *cpustate) - -/***************************************************************************** - ***************************************************************************** - * - * plain vanilla 6502 opcodes - * - ***************************************************************************** - * op temp cycles rdmem opc wrmem ********************/ - -OP(00) { BRK; } /* 7 BRK */ -OP(20) { JSR; } /* 6 JSR */ -OP(40) { RTI; } /* 6 RTI */ -OP(60) { RTS; } /* 6 RTS */ -OP(80) { RDOPARG(); NOP; } /* 2 NOP IMM */ -OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */ -OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */ -OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */ - -OP(10) { BPL; } /* 2-4 BPL REL */ -OP(30) { BMI; } /* 2-4 BMI REL */ -OP(50) { BVC; } /* 2-4 BVC REL */ -OP(70) { BVS; } /* 2-4 BVS REL */ -OP(90) { BCC; } /* 2-4 BCC REL */ -OP(b0) { BCS; } /* 2-4 BCS REL */ -OP(d0) { BNE; } /* 2-4 BNE REL */ -OP(f0) { BEQ; } /* 2-4 BEQ REL */ - -OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */ -OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */ -OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */ -OP(61) { int tmp; RD_IDX; ADC; } /* 6 ADC IDX */ -OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */ -OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */ -OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */ -OP(e1) { int tmp; RD_IDX; SBC; } /* 6 SBC IDX */ - -OP(11) { int tmp; RD_IDY_P; ORA; } /* 5 ORA IDY page penalty */ -OP(31) { int tmp; RD_IDY_P; AND; } /* 5 AND IDY page penalty */ -OP(51) { int tmp; RD_IDY_P; EOR; } /* 5 EOR IDY page penalty */ -OP(71) { int tmp; RD_IDY_P; ADC; } /* 5 ADC IDY page penalty */ -OP(91) { int tmp; STA; WR_IDY_NP; } /* 6 STA IDY */ -OP(b1) { int tmp; RD_IDY_P; LDA; } /* 5 LDA IDY page penalty */ -OP(d1) { int tmp; RD_IDY_P; CMP; } /* 5 CMP IDY page penalty */ -OP(f1) { int tmp; RD_IDY_P; SBC; } /* 5 SBC IDY page penalty */ - -OP(02) { KIL; } /* 1 KIL */ -OP(22) { KIL; } /* 1 KIL */ -OP(42) { KIL; } /* 1 KIL */ -OP(62) { KIL; } /* 1 KIL */ -OP(82) { RDOPARG(); NOP; } /* 2 NOP IMM */ -OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */ -OP(c2) { RDOPARG(); NOP; } /* 2 NOP IMM */ -OP(e2) { RDOPARG(); NOP; } /* 2 NOP IMM */ - -OP(12) { KIL; } /* 1 KIL */ -OP(32) { KIL; } /* 1 KIL */ -OP(52) { KIL; } /* 1 KIL */ -OP(72) { KIL; } /* 1 KIL */ -OP(92) { KIL; } /* 1 KIL */ -OP(b2) { KIL; } /* 1 KIL */ -OP(d2) { KIL; } /* 1 KIL */ -OP(f2) { KIL; } /* 1 KIL */ - -OP(03) { int tmp; RD_IDX; WB_EA; SLO; WB_EA; } /* 7 SLO IDX */ -OP(23) { int tmp; RD_IDX; WB_EA; RLA; WB_EA; } /* 7 RLA IDX */ -OP(43) { int tmp; RD_IDX; WB_EA; SRE; WB_EA; } /* 7 SRE IDX */ -OP(63) { int tmp; RD_IDX; WB_EA; RRA; WB_EA; } /* 7 RRA IDX */ -OP(83) { int tmp; SAX; WR_IDX; } /* 6 SAX IDX */ -OP(a3) { int tmp; RD_IDX; LAX; } /* 6 LAX IDX */ -OP(c3) { int tmp; RD_IDX; WB_EA; DCP; WB_EA; } /* 7 DCP IDX */ -OP(e3) { int tmp; RD_IDX; WB_EA; ISB; WB_EA; } /* 7 ISB IDX */ - -OP(13) { int tmp; RD_IDY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO IDY */ -OP(33) { int tmp; RD_IDY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA IDY */ -OP(53) { int tmp; RD_IDY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE IDY */ -OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA IDY */ -OP(93) { int tmp; EA_IDY_NP; SAH; WB_EA; } /* 5 SAH IDY */ -OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */ -OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */ -OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */ - -OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */ -OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */ -OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */ -OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */ -OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */ -OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */ - -OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */ -OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */ -OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ -OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */ - -OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */ -OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */ -OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */ -OP(65) { int tmp; RD_ZPG; ADC; } /* 3 ADC ZPG */ -OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */ -OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */ -OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */ -OP(e5) { int tmp; RD_ZPG; SBC; } /* 3 SBC ZPG */ - -OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */ -OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */ -OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */ -OP(75) { int tmp; RD_ZPX; ADC; } /* 4 ADC ZPX */ -OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */ -OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */ -OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */ -OP(f5) { int tmp; RD_ZPX; SBC; } /* 4 SBC ZPX */ - -OP(06) { int tmp; RD_ZPG; WB_EA; ASL; WB_EA; } /* 5 ASL ZPG */ -OP(26) { int tmp; RD_ZPG; WB_EA; ROL; WB_EA; } /* 5 ROL ZPG */ -OP(46) { int tmp; RD_ZPG; WB_EA; LSR; WB_EA; } /* 5 LSR ZPG */ -OP(66) { int tmp; RD_ZPG; WB_EA; ROR; WB_EA; } /* 5 ROR ZPG */ -OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */ -OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */ -OP(c6) { int tmp; RD_ZPG; WB_EA; DEC; WB_EA; } /* 5 DEC ZPG */ -OP(e6) { int tmp; RD_ZPG; WB_EA; INC; WB_EA; } /* 5 INC ZPG */ - -OP(16) { int tmp; RD_ZPX; WB_EA; ASL; WB_EA; } /* 6 ASL ZPX */ -OP(36) { int tmp; RD_ZPX; WB_EA; ROL; WB_EA; } /* 6 ROL ZPX */ -OP(56) { int tmp; RD_ZPX; WB_EA; LSR; WB_EA; } /* 6 LSR ZPX */ -OP(76) { int tmp; RD_ZPX; WB_EA; ROR; WB_EA; } /* 6 ROR ZPX */ -OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */ -OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */ -OP(d6) { int tmp; RD_ZPX; WB_EA; DEC; WB_EA; } /* 6 DEC ZPX */ -OP(f6) { int tmp; RD_ZPX; WB_EA; INC; WB_EA; } /* 6 INC ZPX */ - -OP(07) { int tmp; RD_ZPG; WB_EA; SLO; WB_EA; } /* 5 SLO ZPG */ -OP(27) { int tmp; RD_ZPG; WB_EA; RLA; WB_EA; } /* 5 RLA ZPG */ -OP(47) { int tmp; RD_ZPG; WB_EA; SRE; WB_EA; } /* 5 SRE ZPG */ -OP(67) { int tmp; RD_ZPG; WB_EA; RRA; WB_EA; } /* 5 RRA ZPG */ -OP(87) { int tmp; SAX; WR_ZPG; } /* 3 SAX ZPG */ -OP(a7) { int tmp; RD_ZPG; LAX; } /* 3 LAX ZPG */ -OP(c7) { int tmp; RD_ZPG; WB_EA; DCP; WB_EA; } /* 5 DCP ZPG */ -OP(e7) { int tmp; RD_ZPG; WB_EA; ISB; WB_EA; } /* 5 ISB ZPG */ - -OP(17) { int tmp; RD_ZPX; WB_EA; SLO; WB_EA; } /* 6 SLO ZPX */ -OP(37) { int tmp; RD_ZPX; WB_EA; RLA; WB_EA; } /* 6 RLA ZPX */ -OP(57) { int tmp; RD_ZPX; WB_EA; SRE; WB_EA; } /* 6 SRE ZPX */ -OP(77) { int tmp; RD_ZPX; WB_EA; RRA; WB_EA; } /* 6 RRA ZPX */ -OP(97) { int tmp; SAX; WR_ZPY; } /* 4 SAX ZPY */ -OP(b7) { int tmp; RD_ZPY; LAX; } /* 4 LAX ZPY */ -OP(d7) { int tmp; RD_ZPX; WB_EA; DCP; WB_EA; } /* 6 DCP ZPX */ -OP(f7) { int tmp; RD_ZPX; WB_EA; ISB; WB_EA; } /* 6 ISB ZPX */ - -OP(08) { RD_DUM; PHP; } /* 3 PHP */ -OP(28) { RD_DUM; PLP; } /* 4 PLP */ -OP(48) { RD_DUM; PHA; } /* 3 PHA */ -OP(68) { RD_DUM; PLA; } /* 4 PLA */ -OP(88) { RD_DUM; DEY; } /* 2 DEY */ -OP(a8) { RD_DUM; TAY; } /* 2 TAY */ -OP(c8) { RD_DUM; INY; } /* 2 INY */ -OP(e8) { RD_DUM; INX; } /* 2 INX */ - -OP(18) { RD_DUM; CLC; } /* 2 CLC */ -OP(38) { RD_DUM; SEC; } /* 2 SEC */ -OP(58) { RD_DUM; CLI; } /* 2 CLI */ -OP(78) { RD_DUM; SEI; } /* 2 SEI */ -OP(98) { RD_DUM; TYA; } /* 2 TYA */ -OP(b8) { RD_DUM; CLV; } /* 2 CLV */ -OP(d8) { RD_DUM; CLD; } /* 2 CLD */ -OP(f8) { RD_DUM; SED; } /* 2 SED */ - -OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */ -OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */ -OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */ -OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */ -OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */ -OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */ -OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */ -OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(19) { int tmp; RD_ABY_P; ORA; } /* 4 ORA ABY page penalty */ -OP(39) { int tmp; RD_ABY_P; AND; } /* 4 AND ABY page penalty */ -OP(59) { int tmp; RD_ABY_P; EOR; } /* 4 EOR ABY page penalty */ -OP(79) { int tmp; RD_ABY_P; ADC; } /* 4 ADC ABY page penalty */ -OP(99) { int tmp; STA; WR_ABY_NP; } /* 5 STA ABY */ -OP(b9) { int tmp; RD_ABY_P; LDA; } /* 4 LDA ABY page penalty */ -OP(d9) { int tmp; RD_ABY_P; CMP; } /* 4 CMP ABY page penalty */ -OP(f9) { int tmp; RD_ABY_P; SBC; } /* 4 SBC ABY page penalty */ - -OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */ -OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */ -OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */ -OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */ -OP(8a) { RD_DUM; TXA; } /* 2 TXA */ -OP(aa) { RD_DUM; TAX; } /* 2 TAX */ -OP(ca) { RD_DUM; DEX; } /* 2 DEX */ -OP(ea) { RD_DUM; NOP; } /* 2 NOP */ - -OP(1a) { RD_DUM; NOP; } /* 2 NOP */ -OP(3a) { RD_DUM; NOP; } /* 2 NOP */ -OP(5a) { RD_DUM; NOP; } /* 2 NOP */ -OP(7a) { RD_DUM; NOP; } /* 2 NOP */ -OP(9a) { RD_DUM; TXS; } /* 2 TXS */ -OP(ba) { RD_DUM; TSX; } /* 2 TSX */ -OP(da) { RD_DUM; NOP; } /* 2 NOP */ -OP(fa) { RD_DUM; NOP; } /* 2 NOP */ - -OP(0b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */ -OP(2b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */ -OP(4b) { int tmp; RD_IMM; ASR; WB_ACC; } /* 2 ASR IMM */ -OP(6b) { int tmp; RD_IMM; ARR; WB_ACC; } /* 2 ARR IMM */ -OP(8b) { int tmp; RD_IMM; AXA; } /* 2 AXA IMM */ -OP(ab) { int tmp; RD_IMM; OAL_6510; } /* 2 OAL IMM */ -OP(cb) { int tmp; RD_IMM; ASX; } /* 2 ASX IMM */ -OP(eb) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(1b) { int tmp; RD_ABY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABY */ -OP(3b) { int tmp; RD_ABY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABY */ -OP(5b) { int tmp; RD_ABY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABY */ -OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABY */ -OP(9b) { int tmp; EA_ABY_NP; SSH; WB_EA; } /* 5 SSH ABY */ -OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */ -OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */ -OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */ - -OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */ -OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */ -OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */ -OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */ -OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */ -OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */ -OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */ -OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */ - -OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */ -OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */ -OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ -OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */ - -OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */ -OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */ -OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */ -OP(6d) { int tmp; RD_ABS; ADC; } /* 4 ADC ABS */ -OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */ -OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */ -OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */ -OP(ed) { int tmp; RD_ABS; SBC; } /* 4 SBC ABS */ - -OP(1d) { int tmp; RD_ABX_P; ORA; } /* 4 ORA ABX page penalty */ -OP(3d) { int tmp; RD_ABX_P; AND; } /* 4 AND ABX page penalty */ -OP(5d) { int tmp; RD_ABX_P; EOR; } /* 4 EOR ABX page penalty */ -OP(7d) { int tmp; RD_ABX_P; ADC; } /* 4 ADC ABX page penalty */ -OP(9d) { int tmp; STA; WR_ABX_NP; } /* 5 STA ABX */ -OP(bd) { int tmp; RD_ABX_P; LDA; } /* 4 LDA ABX page penalty */ -OP(dd) { int tmp; RD_ABX_P; CMP; } /* 4 CMP ABX page penalty */ -OP(fd) { int tmp; RD_ABX_P; SBC; } /* 4 SBC ABX page penalty */ - -OP(0e) { int tmp; RD_ABS; WB_EA; ASL; WB_EA; } /* 6 ASL ABS */ -OP(2e) { int tmp; RD_ABS; WB_EA; ROL; WB_EA; } /* 6 ROL ABS */ -OP(4e) { int tmp; RD_ABS; WB_EA; LSR; WB_EA; } /* 6 LSR ABS */ -OP(6e) { int tmp; RD_ABS; WB_EA; ROR; WB_EA; } /* 6 ROR ABS */ -OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */ -OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */ -OP(ce) { int tmp; RD_ABS; WB_EA; DEC; WB_EA; } /* 6 DEC ABS */ -OP(ee) { int tmp; RD_ABS; WB_EA; INC; WB_EA; } /* 6 INC ABS */ - -OP(1e) { int tmp; RD_ABX_NP; WB_EA; ASL; WB_EA; } /* 7 ASL ABX */ -OP(3e) { int tmp; RD_ABX_NP; WB_EA; ROL; WB_EA; } /* 7 ROL ABX */ -OP(5e) { int tmp; RD_ABX_NP; WB_EA; LSR; WB_EA; } /* 7 LSR ABX */ -OP(7e) { int tmp; RD_ABX_NP; WB_EA; ROR; WB_EA; } /* 7 ROR ABX */ -OP(9e) { int tmp; EA_ABY_NP; SXH; WB_EA; } /* 5 SXH ABY */ -OP(be) { int tmp; RD_ABY_P; LDX; } /* 4 LDX ABY page penalty */ -OP(de) { int tmp; RD_ABX_NP; WB_EA; DEC; WB_EA; } /* 7 DEC ABX */ -OP(fe) { int tmp; RD_ABX_NP; WB_EA; INC; WB_EA; } /* 7 INC ABX */ - -OP(0f) { int tmp; RD_ABS; WB_EA; SLO; WB_EA; } /* 6 SLO ABS */ -OP(2f) { int tmp; RD_ABS; WB_EA; RLA; WB_EA; } /* 6 RLA ABS */ -OP(4f) { int tmp; RD_ABS; WB_EA; SRE; WB_EA; } /* 6 SRE ABS */ -OP(6f) { int tmp; RD_ABS; WB_EA; RRA; WB_EA; } /* 6 RRA ABS */ -OP(8f) { int tmp; SAX; WR_ABS; } /* 4 SAX ABS */ -OP(af) { int tmp; RD_ABS; LAX; } /* 4 LAX ABS */ -OP(cf) { int tmp; RD_ABS; WB_EA; DCP; WB_EA; } /* 6 DCP ABS */ -OP(ef) { int tmp; RD_ABS; WB_EA; ISB; WB_EA; } /* 6 ISB ABS */ - -OP(1f) { int tmp; RD_ABX_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABX */ -OP(3f) { int tmp; RD_ABX_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABX */ -OP(5f) { int tmp; RD_ABX_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABX */ -OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABX */ -OP(9f) { int tmp; EA_ABY_NP; SAH; WB_EA; } /* 5 SAH ABY */ -OP(bf) { int tmp; RD_ABY_P; LAX; } /* 4 LAX ABY page penalty */ -OP(df) { int tmp; RD_ABX_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABX */ -OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */ - -/* and here's the array of function pointers */ - -static void (*const insn6510[0x100])(m6502_Regs *cpustate) = { - m6510_00,m6510_01,m6510_02,m6510_03,m6510_04,m6510_05,m6510_06,m6510_07, - m6510_08,m6510_09,m6510_0a,m6510_0b,m6510_0c,m6510_0d,m6510_0e,m6510_0f, - m6510_10,m6510_11,m6510_12,m6510_13,m6510_14,m6510_15,m6510_16,m6510_17, - m6510_18,m6510_19,m6510_1a,m6510_1b,m6510_1c,m6510_1d,m6510_1e,m6510_1f, - m6510_20,m6510_21,m6510_22,m6510_23,m6510_24,m6510_25,m6510_26,m6510_27, - m6510_28,m6510_29,m6510_2a,m6510_2b,m6510_2c,m6510_2d,m6510_2e,m6510_2f, - m6510_30,m6510_31,m6510_32,m6510_33,m6510_34,m6510_35,m6510_36,m6510_37, - m6510_38,m6510_39,m6510_3a,m6510_3b,m6510_3c,m6510_3d,m6510_3e,m6510_3f, - m6510_40,m6510_41,m6510_42,m6510_43,m6510_44,m6510_45,m6510_46,m6510_47, - m6510_48,m6510_49,m6510_4a,m6510_4b,m6510_4c,m6510_4d,m6510_4e,m6510_4f, - m6510_50,m6510_51,m6510_52,m6510_53,m6510_54,m6510_55,m6510_56,m6510_57, - m6510_58,m6510_59,m6510_5a,m6510_5b,m6510_5c,m6510_5d,m6510_5e,m6510_5f, - m6510_60,m6510_61,m6510_62,m6510_63,m6510_64,m6510_65,m6510_66,m6510_67, - m6510_68,m6510_69,m6510_6a,m6510_6b,m6510_6c,m6510_6d,m6510_6e,m6510_6f, - m6510_70,m6510_71,m6510_72,m6510_73,m6510_74,m6510_75,m6510_76,m6510_77, - m6510_78,m6510_79,m6510_7a,m6510_7b,m6510_7c,m6510_7d,m6510_7e,m6510_7f, - m6510_80,m6510_81,m6510_82,m6510_83,m6510_84,m6510_85,m6510_86,m6510_87, - m6510_88,m6510_89,m6510_8a,m6510_8b,m6510_8c,m6510_8d,m6510_8e,m6510_8f, - m6510_90,m6510_91,m6510_92,m6510_93,m6510_94,m6510_95,m6510_96,m6510_97, - m6510_98,m6510_99,m6510_9a,m6510_9b,m6510_9c,m6510_9d,m6510_9e,m6510_9f, - m6510_a0,m6510_a1,m6510_a2,m6510_a3,m6510_a4,m6510_a5,m6510_a6,m6510_a7, - m6510_a8,m6510_a9,m6510_aa,m6510_ab,m6510_ac,m6510_ad,m6510_ae,m6510_af, - m6510_b0,m6510_b1,m6510_b2,m6510_b3,m6510_b4,m6510_b5,m6510_b6,m6510_b7, - m6510_b8,m6510_b9,m6510_ba,m6510_bb,m6510_bc,m6510_bd,m6510_be,m6510_bf, - m6510_c0,m6510_c1,m6510_c2,m6510_c3,m6510_c4,m6510_c5,m6510_c6,m6510_c7, - m6510_c8,m6510_c9,m6510_ca,m6510_cb,m6510_cc,m6510_cd,m6510_ce,m6510_cf, - m6510_d0,m6510_d1,m6510_d2,m6510_d3,m6510_d4,m6510_d5,m6510_d6,m6510_d7, - m6510_d8,m6510_d9,m6510_da,m6510_db,m6510_dc,m6510_dd,m6510_de,m6510_df, - m6510_e0,m6510_e1,m6510_e2,m6510_e3,m6510_e4,m6510_e5,m6510_e6,m6510_e7, - m6510_e8,m6510_e9,m6510_ea,m6510_eb,m6510_ec,m6510_ed,m6510_ee,m6510_ef, - m6510_f0,m6510_f1,m6510_f2,m6510_f3,m6510_f4,m6510_f5,m6510_f6,m6510_f7, - m6510_f8,m6510_f9,m6510_fa,m6510_fb,m6510_fc,m6510_fd,m6510_fe,m6510_ff -}; - diff --git a/src/emu/cpu/m6502/t65c02.c b/src/emu/cpu/m6502/t65c02.c deleted file mode 100644 index 679c5c0f23e..00000000000 --- a/src/emu/cpu/m6502/t65c02.c +++ /dev/null @@ -1,410 +0,0 @@ -/***************************************************************************** - * - * tbl65c02.c - * 65c02 opcode functions and function pointer table - * - * Copyright Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - * Not sure about the timing of all the extra (undocumented) NOP instructions. - * Core may need to be split up into two 65c02 core. Not all versions supported - * the bit operation RMB/SMB/etc. - * - *****************************************************************************/ - -#undef OP -#define OP(nn) INLINE void m65c02_##nn(m6502_Regs *cpustate) - -/***************************************************************************** - ***************************************************************************** - * - * Implementations for 65C02 opcodes - * - * There are a few slight differences between Rockwell and WDC 65C02 CPUs. - * The absolute indexed addressing mode RMW instructions take 6 cycles on - * WDC 65C02 CPU but 7 cycles on a regular 6502 and a Rockwell 65C02 CPU. - * TODO: Implement STP and WAI for wdc65c02. - * - ***************************************************************************** - * op temp cycles rdmem opc wrmem ********************/ -OP(00) { BRK_C02; } /* 7 BRK */ -OP(20) { JSR; } /* 6 JSR */ -OP(40) { RTI; } /* 6 RTI */ -OP(60) { RTS; } /* 6 RTS */ -OP(80) { int tmp; BRA_C02( 1 ); } /* 3-4 BRA REL */ -OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */ -OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */ -OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */ - -OP(10) { int tmp; BRA_C02( ! ( P & F_N ) ); } /* 2-4 BPL REL */ -OP(30) { int tmp; BRA_C02( ( P & F_N ) ); } /* 2-4 BMI REL */ -OP(50) { int tmp; BRA_C02( ! ( P & F_V ) ); } /* 2-4 BVC REL */ -OP(70) { int tmp; BRA_C02( ( P & F_V ) ); } /* 2-4 BVS REL */ -OP(90) { int tmp; BRA_C02( ! ( P & F_C ) ); } /* 2-4 BCC REL */ -OP(b0) { int tmp; BRA_C02( ( P & F_C ) ); } /* 2-4 BCS REL */ -OP(d0) { int tmp; BRA_C02( ! ( P & F_Z ) ); } /* 2-4 BNE REL */ -OP(f0) { int tmp; BRA_C02( ( P & F_Z ) ); } /* 2-4 BEQ REL */ - -OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */ -OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */ -OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */ -OP(61) { int tmp; RD_IDX; ADC_C02; } /* 6/7 ADC IDX */ -OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */ -OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */ -OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */ -OP(e1) { int tmp; RD_IDX; SBC_C02; } /* 6/7 SBC IDX */ - -OP(11) { int tmp; RD_IDY_C02_P; ORA; } /* 5 ORA IDY page penalty */ -OP(31) { int tmp; RD_IDY_C02_P; AND; } /* 5 AND IDY page penalty */ -OP(51) { int tmp; RD_IDY_C02_P; EOR; } /* 5 EOR IDY page penalty */ -OP(71) { int tmp; RD_IDY_C02_P; ADC_C02; } /* 5/6 ADC IDY page penalty */ -OP(91) { int tmp; STA; WR_IDY_C02_NP; } /* 6 STA IDY */ -OP(b1) { int tmp; RD_IDY_C02_P; LDA; } /* 5 LDA IDY page penalty */ -OP(d1) { int tmp; RD_IDY_C02_P; CMP; } /* 5 CMP IDY page penalty */ -OP(f1) { int tmp; RD_IDY_C02_P; SBC_C02; } /* 5/6 SBC IDY page penalty */ - -OP(02) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ -OP(22) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ -OP(42) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ -OP(62) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ -OP(82) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ -OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */ -OP(c2) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ -OP(e2) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */ - -OP(12) { int tmp; RD_ZPI; ORA; } /* 5 ORA ZPI */ -OP(32) { int tmp; RD_ZPI; AND; } /* 5 AND ZPI */ -OP(52) { int tmp; RD_ZPI; EOR; } /* 5 EOR ZPI */ -OP(72) { int tmp; RD_ZPI; ADC_C02; } /* 5/6 ADC ZPI */ -OP(92) { int tmp; STA; WR_ZPI; } /* 5 STA ZPI */ -OP(b2) { int tmp; RD_ZPI; LDA; } /* 5 LDA ZPI */ -OP(d2) { int tmp; RD_ZPI; CMP; } /* 5 CMP ZPI */ -OP(f2) { int tmp; RD_ZPI; SBC_C02; } /* 5/6 SBC ZPI */ - -OP(03) { NOP; } /* 1 NOP not sure for rockwell */ -OP(23) { NOP; } /* 1 NOP not sure for rockwell */ -OP(43) { NOP; } /* 1 NOP not sure for rockwell */ -OP(63) { NOP; } /* 1 NOP not sure for rockwell */ -OP(83) { NOP; } /* 1 NOP not sure for rockwell */ -OP(a3) { NOP; } /* 1 NOP not sure for rockwell */ -OP(c3) { NOP; } /* 1 NOP not sure for rockwell */ -OP(e3) { NOP; } /* 1 NOP not sure for rockwell */ - -OP(13) { NOP; } /* 1 NOP not sure for rockwell */ -OP(33) { NOP; } /* 1 NOP not sure for rockwell */ -OP(53) { NOP; } /* 1 NOP not sure for rockwell */ -OP(73) { NOP; } /* 1 NOP not sure for rockwell */ -OP(93) { NOP; } /* 1 NOP not sure for rockwell */ -OP(b3) { NOP; } /* 1 NOP not sure for rockwell */ -OP(d3) { NOP; } /* 1 NOP not sure for rockwell */ -OP(f3) { NOP; } /* 1 NOP not sure for rockwell */ - -OP(04) { int tmp; RD_ZPG; RD_EA; TSB; WB_EA; } /* 5 TSB ZPG */ -OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */ -OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP not sure for rockwell */ -OP(64) { int tmp; STZ; WR_ZPG; } /* 3 STZ ZPG */ -OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */ -OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */ -OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */ -OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */ - -OP(14) { int tmp; RD_ZPG; RD_EA; TRB; WB_EA; } /* 5 TRB ZPG */ -OP(34) { int tmp; RD_ZPX; BIT; } /* 4 BIT ZPX */ -OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */ -OP(74) { int tmp; STZ; WR_ZPX; } /* 4 STZ ZPX */ -OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */ -OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */ -OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */ -OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */ - -OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */ -OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */ -OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */ -OP(65) { int tmp; RD_ZPG; ADC_C02; } /* 3/4 ADC ZPG */ -OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */ -OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */ -OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */ -OP(e5) { int tmp; RD_ZPG; SBC_C02; } /* 3/4 SBC ZPG */ - -OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */ -OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */ -OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */ -OP(75) { int tmp; RD_ZPX; ADC_C02; } /* 4/5 ADC ZPX */ -OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */ -OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */ -OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */ -OP(f5) { int tmp; RD_ZPX; SBC_C02; } /* 4/5 SBC ZPX */ - -OP(06) { int tmp; RD_ZPG, RD_EA; ASL; WB_EA; } /* 5 ASL ZPG */ -OP(26) { int tmp; RD_ZPG; RD_EA; ROL; WB_EA; } /* 5 ROL ZPG */ -OP(46) { int tmp; RD_ZPG; RD_EA; LSR; WB_EA; } /* 5 LSR ZPG */ -OP(66) { int tmp; RD_ZPG; RD_EA; ROR; WB_EA; } /* 5 ROR ZPG */ -OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */ -OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */ -OP(c6) { int tmp; RD_ZPG; RD_EA; DEC; WB_EA; } /* 5 DEC ZPG */ -OP(e6) { int tmp; RD_ZPG; RD_EA; INC; WB_EA; } /* 5 INC ZPG */ - -OP(16) { int tmp; RD_ZPX; RD_EA; ASL; WB_EA; } /* 6 ASL ZPX */ -OP(36) { int tmp; RD_ZPX; RD_EA; ROL; WB_EA; } /* 6 ROL ZPX */ -OP(56) { int tmp; RD_ZPX; RD_EA; LSR; WB_EA; } /* 6 LSR ZPX */ -OP(76) { int tmp; RD_ZPX; RD_EA; ROR; WB_EA; } /* 6 ROR ZPX */ -OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */ -OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */ -OP(d6) { int tmp; RD_ZPX; RD_EA; DEC; WB_EA; } /* 6 DEC ZPX */ -OP(f6) { int tmp; RD_ZPX; RD_EA; INC; WB_EA; } /* 6 INC ZPX */ - -OP(07) { int tmp; RD_ZPG; RD_EA; RMB(0);WB_EA; } /* 5 RMB0 ZPG */ -OP(27) { int tmp; RD_ZPG; RD_EA; RMB(2);WB_EA; } /* 5 RMB2 ZPG */ -OP(47) { int tmp; RD_ZPG; RD_EA; RMB(4);WB_EA; } /* 5 RMB4 ZPG */ -OP(67) { int tmp; RD_ZPG; RD_EA; RMB(6);WB_EA; } /* 5 RMB6 ZPG */ -OP(87) { int tmp; RD_ZPG; RD_EA; SMB(0);WB_EA; } /* 5 SMB0 ZPG */ -OP(a7) { int tmp; RD_ZPG; RD_EA; SMB(2);WB_EA; } /* 5 SMB2 ZPG */ -OP(c7) { int tmp; RD_ZPG; RD_EA; SMB(4);WB_EA; } /* 5 SMB4 ZPG */ -OP(e7) { int tmp; RD_ZPG; RD_EA; SMB(6);WB_EA; } /* 5 SMB6 ZPG */ - -OP(17) { int tmp; RD_ZPG; RD_EA; RMB(1);WB_EA; } /* 5 RMB1 ZPG */ -OP(37) { int tmp; RD_ZPG; RD_EA; RMB(3);WB_EA; } /* 5 RMB3 ZPG */ -OP(57) { int tmp; RD_ZPG; RD_EA; RMB(5);WB_EA; } /* 5 RMB5 ZPG */ -OP(77) { int tmp; RD_ZPG; RD_EA; RMB(7);WB_EA; } /* 5 RMB7 ZPG */ -OP(97) { int tmp; RD_ZPG; RD_EA; SMB(1);WB_EA; } /* 5 SMB1 ZPG */ -OP(b7) { int tmp; RD_ZPG; RD_EA; SMB(3);WB_EA; } /* 5 SMB3 ZPG */ -OP(d7) { int tmp; RD_ZPG; RD_EA; SMB(5);WB_EA; } /* 5 SMB5 ZPG */ -OP(f7) { int tmp; RD_ZPG; RD_EA; SMB(7);WB_EA; } /* 5 SMB7 ZPG */ - -OP(08) { RD_DUM; PHP; } /* 3 PHP */ -OP(28) { RD_DUM; PLP; } /* 4 PLP */ -OP(48) { RD_DUM; PHA; } /* 3 PHA */ -OP(68) { RD_DUM; PLA; } /* 4 PLA */ -OP(88) { RD_DUM; DEY; } /* 2 DEY */ -OP(a8) { RD_DUM; TAY; } /* 2 TAY */ -OP(c8) { RD_DUM; INY; } /* 2 INY */ -OP(e8) { RD_DUM; INX; } /* 2 INX */ - -OP(18) { RD_DUM; CLC; } /* 2 CLC */ -OP(38) { RD_DUM; SEC; } /* 2 SEC */ -OP(58) { RD_DUM; CLI; } /* 2 CLI */ -OP(78) { RD_DUM; SEI; } /* 2 SEI */ -OP(98) { RD_DUM; TYA; } /* 2 TYA */ -OP(b8) { RD_DUM; CLV; } /* 2 CLV */ -OP(d8) { RD_DUM; CLD; } /* 2 CLD */ -OP(f8) { RD_DUM; SED; } /* 2 SED */ - -OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */ -OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */ -OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */ -OP(69) { int tmp; RD_IMM; ADC_C02; } /* 2/3 ADC IMM */ -OP(89) { int tmp; RD_IMM; BIT_IMM_C02; } /* 2 BIT IMM */ -OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */ -OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */ -OP(e9) { int tmp; RD_IMM; SBC_C02; } /* 2/3 SBC IMM */ - -OP(19) { int tmp; RD_ABY_C02_P; ORA; } /* 4 ORA ABY page penalty */ -OP(39) { int tmp; RD_ABY_C02_P; AND; } /* 4 AND ABY page penalty */ -OP(59) { int tmp; RD_ABY_C02_P; EOR; } /* 4 EOR ABY page penalty */ -OP(79) { int tmp; RD_ABY_C02_P; ADC_C02; } /* 4/5 ADC ABY page penalty */ -OP(99) { int tmp; STA; WR_ABY_C02_NP; } /* 5 STA ABY */ -OP(b9) { int tmp; RD_ABY_C02_P; LDA; } /* 4 LDA ABY page penalty */ -OP(d9) { int tmp; RD_ABY_C02_P; CMP; } /* 4 CMP ABY page penalty */ -OP(f9) { int tmp; RD_ABY_C02_P; SBC_C02; } /* 4/5 SBC ABY page penalty */ - -OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */ -OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */ -OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */ -OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */ -OP(8a) { RD_DUM; TXA; } /* 2 TXA */ -OP(aa) { RD_DUM; TAX; } /* 2 TAX */ -OP(ca) { RD_DUM; DEX; } /* 2 DEX */ -OP(ea) { RD_DUM; NOP; } /* 2 NOP */ - -OP(1a) { RD_DUM;INA; } /* 2 INA */ -OP(3a) { RD_DUM;DEA; } /* 2 DEA */ -OP(5a) { RD_DUM;PHY; } /* 3 PHY */ -OP(7a) { RD_DUM;PLY; } /* 4 PLY */ -OP(9a) { RD_DUM; TXS; } /* 2 TXS */ -OP(ba) { RD_DUM; TSX; } /* 2 TSX */ -OP(da) { RD_DUM;PHX; } /* 3 PHX */ -OP(fa) { RD_DUM;PLX; } /* 4 PLX */ - -OP(0b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(2b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(4b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(6b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(8b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(ab) { NOP; } /* 1 NOP not sure for rockwell */ -OP(cb) { NOP; } /* 1 NOP not sure for rockwell */ -OP(eb) { NOP; } /* 1 NOP not sure for rockwell */ - -OP(1b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(3b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(5b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(7b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(9b) { NOP; } /* 1 NOP not sure for rockwell */ -OP(bb) { NOP; } /* 1 NOP not sure for rockwell */ -OP(db) { NOP; } /* 1 NOP not sure for rockwell */ -OP(fb) { NOP; } /* 1 NOP not sure for rockwell */ - -OP(0c) { int tmp; RD_ABS; RD_EA; TSB; WB_EA; } /* 6 TSB ABS */ -OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */ -OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */ -OP(6c) { int tmp; EA_IND_C02; JMP; } /* 6 JMP IND */ -OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */ -OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */ -OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */ -OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */ - -OP(1c) { int tmp; RD_ABS; RD_EA; TRB; WB_EA; } /* 6 TRB ABS */ -OP(3c) { int tmp; RD_ABX_C02_P; BIT; } /* 4 BIT ABX page penalty */ -OP(5c) { RD_ABX_C02_NP_DISCARD; RD_DUM; RD_DUM; RD_DUM; RD_DUM; } /* 8 NOP ABX not sure for rockwell. Page penalty not sure */ -OP(7c) { int tmp; EA_IAX; JMP; } /* 6 JMP IAX page penalty */ -OP(9c) { int tmp; STZ; WR_ABS; } /* 4 STZ ABS */ -OP(bc) { int tmp; RD_ABX_C02_P; LDY; } /* 4 LDY ABX page penalty */ -OP(dc) { RD_ABX_C02_NP_DISCARD; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */ -OP(fc) { RD_ABX_C02_NP_DISCARD; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */ - -OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */ -OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */ -OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */ -OP(6d) { int tmp; RD_ABS; ADC_C02; } /* 4/5 ADC ABS */ -OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */ -OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */ -OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */ -OP(ed) { int tmp; RD_ABS; SBC_C02; } /* 4/5 SBC ABS */ - -OP(1d) { int tmp; RD_ABX_C02_P; ORA; } /* 4 ORA ABX page penalty */ -OP(3d) { int tmp; RD_ABX_C02_P; AND; } /* 4 AND ABX page penalty */ -OP(5d) { int tmp; RD_ABX_C02_P; EOR; } /* 4 EOR ABX page penalty */ -OP(7d) { int tmp; RD_ABX_C02_P; ADC_C02; } /* 4/5 ADC ABX page penalty */ -OP(9d) { int tmp; STA; WR_ABX_C02_NP; } /* 5 STA ABX */ -OP(bd) { int tmp; RD_ABX_C02_P; LDA; } /* 4 LDA ABX page penalty */ -OP(dd) { int tmp; RD_ABX_C02_P; CMP; } /* 4 CMP ABX page penalty */ -OP(fd) { int tmp; RD_ABX_C02_P; SBC_C02; } /* 4/5 SBC ABX page penalty */ - -OP(0e) { int tmp; RD_ABS; RD_EA; ASL; WB_EA; } /* 6 ASL ABS */ -OP(2e) { int tmp; RD_ABS; RD_EA; ROL; WB_EA; } /* 6 ROL ABS */ -OP(4e) { int tmp; RD_ABS; RD_EA; LSR; WB_EA; } /* 6 LSR ABS */ -OP(6e) { int tmp; RD_ABS; RD_EA; ROR; WB_EA; } /* 6 ROR ABS */ -OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */ -OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */ -OP(ce) { int tmp; RD_ABS; RD_EA; DEC; WB_EA; } /* 6 DEC ABS */ -OP(ee) { int tmp; RD_ABS; RD_EA; INC; WB_EA; } /* 6 INC ABS */ - -OP(1e) { int tmp; RD_ABX_C02_NP; RD_EA; ASL; WB_EA; } /* 7 ASL ABX */ -OP(3e) { int tmp; RD_ABX_C02_NP; RD_EA; ROL; WB_EA; } /* 7 ROL ABX */ -OP(5e) { int tmp; RD_ABX_C02_NP; RD_EA; LSR; WB_EA; } /* 7 LSR ABX */ -OP(7e) { int tmp; RD_ABX_C02_NP; RD_EA; ROR; WB_EA; } /* 7 ROR ABX */ -OP(9e) { int tmp; STZ; WR_ABX_C02_NP; } /* 5 STZ ABX */ -OP(be) { int tmp; RD_ABY_C02_P; LDX; } /* 4 LDX ABY page penalty */ -OP(de) { int tmp; RD_ABX_C02_NP; RD_EA; DEC; WB_EA; } /* 7 DEC ABX */ -OP(fe) { int tmp; RD_ABX_C02_NP; RD_EA; INC; WB_EA; } /* 7 INC ABX */ - -OP(0f) { int tmp; RD_ZPG; BBR(0); } /* 5-7 BBR0 ZPG */ -OP(2f) { int tmp; RD_ZPG; BBR(2); } /* 5-7 BBR2 ZPG */ -OP(4f) { int tmp; RD_ZPG; BBR(4); } /* 5-7 BBR4 ZPG */ -OP(6f) { int tmp; RD_ZPG; BBR(6); } /* 5-7 BBR6 ZPG */ -OP(8f) { int tmp; RD_ZPG; BBS(0); } /* 5-7 BBS0 ZPG */ -OP(af) { int tmp; RD_ZPG; BBS(2); } /* 5-7 BBS2 ZPG */ -OP(cf) { int tmp; RD_ZPG; BBS(4); } /* 5-7 BBS4 ZPG */ -OP(ef) { int tmp; RD_ZPG; BBS(6); } /* 5-7 BBS6 ZPG */ - -OP(1f) { int tmp; RD_ZPG; BBR(1); } /* 5-7 BBR1 ZPG */ -OP(3f) { int tmp; RD_ZPG; BBR(3); } /* 5-7 BBR3 ZPG */ -OP(5f) { int tmp; RD_ZPG; BBR(5); } /* 5-7 BBR5 ZPG */ -OP(7f) { int tmp; RD_ZPG; BBR(7); } /* 5-7 BBR7 ZPG */ -OP(9f) { int tmp; RD_ZPG; BBS(1); } /* 5-7 BBS1 ZPG */ -OP(bf) { int tmp; RD_ZPG; BBS(3); } /* 5-7 BBS3 ZPG */ -OP(df) { int tmp; RD_ZPG; BBS(5); } /* 5-7 BBS5 ZPG */ -OP(ff) { int tmp; RD_ZPG; BBS(7); } /* 5-7 BBS7 ZPG */ - -static void (*const insn65c02[0x100])(m6502_Regs *cpustate) = { - m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07, - m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f, - m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17, - m65c02_18,m65c02_19,m65c02_1a,m65c02_1b,m65c02_1c,m65c02_1d,m65c02_1e,m65c02_1f, - m65c02_20,m65c02_21,m65c02_22,m65c02_23,m65c02_24,m65c02_25,m65c02_26,m65c02_27, - m65c02_28,m65c02_29,m65c02_2a,m65c02_2b,m65c02_2c,m65c02_2d,m65c02_2e,m65c02_2f, - m65c02_30,m65c02_31,m65c02_32,m65c02_33,m65c02_34,m65c02_35,m65c02_36,m65c02_37, - m65c02_38,m65c02_39,m65c02_3a,m65c02_3b,m65c02_3c,m65c02_3d,m65c02_3e,m65c02_3f, - m65c02_40,m65c02_41,m65c02_42,m65c02_43,m65c02_44,m65c02_45,m65c02_46,m65c02_47, - m65c02_48,m65c02_49,m65c02_4a,m65c02_4b,m65c02_4c,m65c02_4d,m65c02_4e,m65c02_4f, - m65c02_50,m65c02_51,m65c02_52,m65c02_53,m65c02_54,m65c02_55,m65c02_56,m65c02_57, - m65c02_58,m65c02_59,m65c02_5a,m65c02_5b,m65c02_5c,m65c02_5d,m65c02_5e,m65c02_5f, - m65c02_60,m65c02_61,m65c02_62,m65c02_63,m65c02_64,m65c02_65,m65c02_66,m65c02_67, - m65c02_68,m65c02_69,m65c02_6a,m65c02_6b,m65c02_6c,m65c02_6d,m65c02_6e,m65c02_6f, - m65c02_70,m65c02_71,m65c02_72,m65c02_73,m65c02_74,m65c02_75,m65c02_76,m65c02_77, - m65c02_78,m65c02_79,m65c02_7a,m65c02_7b,m65c02_7c,m65c02_7d,m65c02_7e,m65c02_7f, - m65c02_80,m65c02_81,m65c02_82,m65c02_83,m65c02_84,m65c02_85,m65c02_86,m65c02_87, - m65c02_88,m65c02_89,m65c02_8a,m65c02_8b,m65c02_8c,m65c02_8d,m65c02_8e,m65c02_8f, - m65c02_90,m65c02_91,m65c02_92,m65c02_93,m65c02_94,m65c02_95,m65c02_96,m65c02_97, - m65c02_98,m65c02_99,m65c02_9a,m65c02_9b,m65c02_9c,m65c02_9d,m65c02_9e,m65c02_9f, - m65c02_a0,m65c02_a1,m65c02_a2,m65c02_a3,m65c02_a4,m65c02_a5,m65c02_a6,m65c02_a7, - m65c02_a8,m65c02_a9,m65c02_aa,m65c02_ab,m65c02_ac,m65c02_ad,m65c02_ae,m65c02_af, - m65c02_b0,m65c02_b1,m65c02_b2,m65c02_b3,m65c02_b4,m65c02_b5,m65c02_b6,m65c02_b7, - m65c02_b8,m65c02_b9,m65c02_ba,m65c02_bb,m65c02_bc,m65c02_bd,m65c02_be,m65c02_bf, - m65c02_c0,m65c02_c1,m65c02_c2,m65c02_c3,m65c02_c4,m65c02_c5,m65c02_c6,m65c02_c7, - m65c02_c8,m65c02_c9,m65c02_ca,m65c02_cb,m65c02_cc,m65c02_cd,m65c02_ce,m65c02_cf, - m65c02_d0,m65c02_d1,m65c02_d2,m65c02_d3,m65c02_d4,m65c02_d5,m65c02_d6,m65c02_d7, - m65c02_d8,m65c02_d9,m65c02_da,m65c02_db,m65c02_dc,m65c02_dd,m65c02_de,m65c02_df, - m65c02_e0,m65c02_e1,m65c02_e2,m65c02_e3,m65c02_e4,m65c02_e5,m65c02_e6,m65c02_e7, - m65c02_e8,m65c02_e9,m65c02_ea,m65c02_eb,m65c02_ec,m65c02_ed,m65c02_ee,m65c02_ef, - m65c02_f0,m65c02_f1,m65c02_f2,m65c02_f3,m65c02_f4,m65c02_f5,m65c02_f6,m65c02_f7, - m65c02_f8,m65c02_f9,m65c02_fa,m65c02_fb,m65c02_fc,m65c02_fd,m65c02_fe,m65c02_ff -}; - -#ifdef WDC65C02 -OP(cb_wdc) { RD_DUM; RD_DUM; } /* 3 WAI, TODO: Implement HALT mode */ -OP(db_wdc) { RD_DUM; RD_DUM; } /* 3 STP, TODO: Implement STP mode */ -OP(1e_wdc) { int tmp; RD_ABX_P; RD_EA; ASL; WB_EA; } /* 6 ASL ABX page penalty */ -OP(3e_wdc) { int tmp; RD_ABX_P; RD_EA; ROL; WB_EA; } /* 6 ROL ABX page penalty */ -OP(5e_wdc) { int tmp; RD_ABX_P; RD_EA; LSR; WB_EA; } /* 6 LSR ABX page penalty */ -OP(7e_wdc) { int tmp; RD_ABX_P; RD_EA; ROR; WB_EA; } /* 6 ROR ABX page penalty */ -OP(de_wdc) { int tmp; RD_ABX_P; RD_EA; DEC; WB_EA; } /* 6 DEC ABX page penalty */ -OP(fe_wdc) { int tmp; RD_ABX_P; RD_EA; INC; WB_EA; } /* 6 INC ABX page penalty */ - -static void (*const insnwdc65c02[0x100])(m6502_Regs *cpustate) = { - m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07, - m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f, - m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17, - m65c02_18,m65c02_19,m65c02_1a,m65c02_1b,m65c02_1c,m65c02_1d,m65c02_1e_wdc,m65c02_1f, - m65c02_20,m65c02_21,m65c02_22,m65c02_23,m65c02_24,m65c02_25,m65c02_26,m65c02_27, - m65c02_28,m65c02_29,m65c02_2a,m65c02_2b,m65c02_2c,m65c02_2d,m65c02_2e,m65c02_2f, - m65c02_30,m65c02_31,m65c02_32,m65c02_33,m65c02_34,m65c02_35,m65c02_36,m65c02_37, - m65c02_38,m65c02_39,m65c02_3a,m65c02_3b,m65c02_3c,m65c02_3d,m65c02_3e_wdc,m65c02_3f, - m65c02_40,m65c02_41,m65c02_42,m65c02_43,m65c02_44,m65c02_45,m65c02_46,m65c02_47, - m65c02_48,m65c02_49,m65c02_4a,m65c02_4b,m65c02_4c,m65c02_4d,m65c02_4e,m65c02_4f, - m65c02_50,m65c02_51,m65c02_52,m65c02_53,m65c02_54,m65c02_55,m65c02_56,m65c02_57, - m65c02_58,m65c02_59,m65c02_5a,m65c02_5b,m65c02_5c,m65c02_5d,m65c02_5e_wdc,m65c02_5f, - m65c02_60,m65c02_61,m65c02_62,m65c02_63,m65c02_64,m65c02_65,m65c02_66,m65c02_67, - m65c02_68,m65c02_69,m65c02_6a,m65c02_6b,m65c02_6c,m65c02_6d,m65c02_6e,m65c02_6f, - m65c02_70,m65c02_71,m65c02_72,m65c02_73,m65c02_74,m65c02_75,m65c02_76,m65c02_77, - m65c02_78,m65c02_79,m65c02_7a,m65c02_7b,m65c02_7c,m65c02_7d,m65c02_7e_wdc,m65c02_7f, - m65c02_80,m65c02_81,m65c02_82,m65c02_83,m65c02_84,m65c02_85,m65c02_86,m65c02_87, - m65c02_88,m65c02_89,m65c02_8a,m65c02_8b,m65c02_8c,m65c02_8d,m65c02_8e,m65c02_8f, - m65c02_90,m65c02_91,m65c02_92,m65c02_93,m65c02_94,m65c02_95,m65c02_96,m65c02_97, - m65c02_98,m65c02_99,m65c02_9a,m65c02_9b,m65c02_9c,m65c02_9d,m65c02_9e,m65c02_9f, - m65c02_a0,m65c02_a1,m65c02_a2,m65c02_a3,m65c02_a4,m65c02_a5,m65c02_a6,m65c02_a7, - m65c02_a8,m65c02_a9,m65c02_aa,m65c02_ab,m65c02_ac,m65c02_ad,m65c02_ae,m65c02_af, - m65c02_b0,m65c02_b1,m65c02_b2,m65c02_b3,m65c02_b4,m65c02_b5,m65c02_b6,m65c02_b7, - m65c02_b8,m65c02_b9,m65c02_ba,m65c02_bb,m65c02_bc,m65c02_bd,m65c02_be,m65c02_bf, - m65c02_c0,m65c02_c1,m65c02_c2,m65c02_c3,m65c02_c4,m65c02_c5,m65c02_c6,m65c02_c7, - m65c02_c8,m65c02_c9,m65c02_ca,m65c02_cb_wdc,m65c02_cc,m65c02_cd,m65c02_ce,m65c02_cf, - m65c02_d0,m65c02_d1,m65c02_d2,m65c02_d3,m65c02_d4,m65c02_d5,m65c02_d6,m65c02_d7, - m65c02_d8,m65c02_d9,m65c02_da,m65c02_db_wdc,m65c02_dc,m65c02_dd,m65c02_de_wdc,m65c02_df, - m65c02_e0,m65c02_e1,m65c02_e2,m65c02_e3,m65c02_e4,m65c02_e5,m65c02_e6,m65c02_e7, - m65c02_e8,m65c02_e9,m65c02_ea,m65c02_eb,m65c02_ec,m65c02_ed,m65c02_ee,m65c02_ef, - m65c02_f0,m65c02_f1,m65c02_f2,m65c02_f3,m65c02_f4,m65c02_f5,m65c02_f6,m65c02_f7, - m65c02_f8,m65c02_f9,m65c02_fa,m65c02_fb,m65c02_fc,m65c02_fd,m65c02_fe_wdc,m65c02_ff -}; -#endif - - diff --git a/src/emu/cpu/m6502/t65ce02.c b/src/emu/cpu/m6502/t65ce02.c deleted file mode 100644 index 20f7f749182..00000000000 --- a/src/emu/cpu/m6502/t65ce02.c +++ /dev/null @@ -1,399 +0,0 @@ -/***************************************************************************** - * - * t65ce02.c - * 65ce02 opcode functions and function pointer table - * - * Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - -#undef OP -#ifdef M4510 -#define OP(nn) INLINE void m4510_##nn(m4510_Regs *cpustate) -#else -#define OP(nn) INLINE void m65ce02_##nn(m65ce02_Regs *cpustate) -#endif - -/***************************************************************************** - ***************************************************************************** - * - * overrides for 65CE02 opcodes - * - ***************************************************************************** - * op temp cycles rdmem opc wrmem ********************/ -OP(00) { BRK; } /* 7 BRK */ -OP(20) { JSR; } /* 5 JSR */ -OP(40) { int tmp; RTI; } /* 5 RTI */ -OP(60) { RTS; } /* 4 RTS */ -OP(80) { int tmp; BRA(1); } /* 2 BRA */ -OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */ -OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */ -OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */ - -OP(10) { int tmp; BRA( ! ( P & F_N ) ); } /* 2 BPL REL */ -OP(30) { int tmp; BRA( ( P & F_N ) ); } /* 2 BMI REL */ -OP(50) { int tmp; BRA( ! ( P & F_V ) ); } /* 2 BVC REL */ -OP(70) { int tmp; BRA( ( P & F_V ) ); } /* 2 BVS REL */ -OP(90) { int tmp; BRA( ! ( P & F_C ) ); } /* 2 BCC REL */ -OP(b0) { int tmp; BRA( ( P & F_C ) ); } /* 2 BCS REL */ -OP(d0) { int tmp; BRA( ! ( P & F_Z ) ); } /* 2 BNE REL */ -OP(f0) { int tmp; BRA( ( P & F_Z ) ); } /* 2 BEQ REL */ - -OP(01) { int tmp; RD_IDX; ORA; } /* 5 ORA IDX */ -OP(21) { int tmp; RD_IDX; AND; } /* 5 AND IDX */ -OP(41) { int tmp; RD_IDX; EOR; } /* 5 EOR IDX */ -OP(61) { int tmp; RD_IDX; ADC; } /* 5 ADC IDX */ -OP(81) { int tmp; STA; WR_IDX; } /* 5 STA IDX */ -OP(a1) { int tmp; RD_IDX; LDA; } /* 5 LDA IDX */ -OP(c1) { int tmp; RD_IDX; CMP; } /* 5 CMP IDX */ -OP(e1) { int tmp; RD_IDX; SBC; } /* 5 SBC IDX */ - -OP(11) { int tmp; RD_IDY; ORA; } /* 5 ORA IDY */ -OP(31) { int tmp; RD_IDY; AND; } /* 5 AND IDY */ -OP(51) { int tmp; RD_IDY; EOR; } /* 5 EOR IDY */ -OP(71) { int tmp; RD_IDY; ADC; } /* 5 ADC IDY */ -OP(91) { int tmp; STA; WR_IDY; } /* 5 STA IDY */ -OP(b1) { int tmp; RD_IDY; LDA; } /* 5 LDA IDY */ -OP(d1) { int tmp; RD_IDY; CMP; } /* 5 CMP IDY */ -OP(f1) { int tmp; RD_IDY; SBC; } /* 5 SBC IDY */ - -OP(02) { RD_DUM; CLE; } /* 2 CLE */ -OP(22) { JSR_IND; } /* 7 JSR IND */ -OP(42) { RD_DUM; NEG; } /* 2 NEG */ -OP(62) { int tmp; RD_IMM; RTN; } /* 7 RTN IMM */ -OP(82) { RD_INSY_DISCARD; } /* 6 STA INSY */ -OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */ -OP(c2) { int tmp; RD_IMM; CPZ; } /* 2 CPZ IMM */ -OP(e2) { int tmp; RD_INSY; LDA; } /* 6 LDA INSY */ - -OP(12) { int tmp; RD_IDZ; ORA; } /* 5 ORA IDZ */ -OP(32) { int tmp; RD_IDZ; AND; } /* 5 AND IDZ */ -OP(52) { int tmp; RD_IDZ; EOR; } /* 5 EOR IDZ */ -OP(72) { int tmp; RD_IDZ; ADC; } /* 5 ADC IDZ */ -OP(92) { RD_IDZ_DISCARD; } /* 5 STA IDZ */ -OP(b2) { int tmp; RD_IDZ; LDA; } /* 5 LDA IDZ */ -OP(d2) { int tmp; RD_IDZ; CMP; } /* 5 CMP IDZ */ -OP(f2) { int tmp; RD_IDZ; SBC; } /* 5 SBC IDZ */ - -OP(03) { RD_DUM; SEE; } /* 2 SEE */ -OP(23) { JSR_INDX; } /* 7 JSR INDX */ -OP(43) { int tmp; RD_DUM; RD_ACC; ASR_65CE02; WR_ACC; } /* 2 ASR A */ -OP(63) { BSR; } /* 5 BSR */ -OP(83) { BRA_WORD(1); } /* 3 BRA REL WORD */ -OP(a3) { int tmp; RD_IMM; LDZ; } /* 2 LDZ IMM */ -OP(c3) { PAIR tmp; RD_ZPG_WORD; DEW; WB_EA_WORD; } /* 6 DEW ABS */ -OP(e3) { PAIR tmp; RD_ZPG_WORD; INW; WB_EA_WORD; } /* 6 INW ABS */ - -OP(13) { BRA_WORD( ! ( P & F_N ) ); } /* 3 BPL REL WORD */ -OP(33) { BRA_WORD( ( P & F_N ) ); } /* 3 BMI REL WORD */ -OP(53) { BRA_WORD( ! ( P & F_V ) ); } /* 3 BVC REL WORD */ -OP(73) { BRA_WORD( ( P & F_V ) ); } /* 3 BVS REL WORD */ -OP(93) { BRA_WORD( ! ( P & F_C ) ); } /* 3 BCC REL WORD */ -OP(b3) { BRA_WORD( ( P & F_C ) ); } /* 3 BCS REL WORD */ -OP(d3) { BRA_WORD( ! ( P & F_Z ) ); } /* 3 BNE REL WORD */ -OP(f3) { BRA_WORD( ( P & F_Z ) ); } /* 3 BEQ REL WORD */ - -OP(04) { int tmp; RD_ZPG; TSB; WB_EA; } /* 4 TSB ZPG */ -OP(24) { int tmp; RD_ZPG; RD_DUM; BIT; } /* 4 BIT ZPG */ -OP(44) { int tmp; RD_ZPG; ASR_65CE02; WB_EA; } /* 4 ASR ZPG */ -OP(64) { int tmp; STZ_65CE02; WR_ZPG; } /* 3 STZ ZPG */ -OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */ -OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */ -OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */ -OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */ - -OP(14) { int tmp; RD_ZPG; TRB; WB_EA; } /* 4 TRB ZPG */ -OP(34) { int tmp; RD_ZPX; RD_DUM; BIT; } /* 4 BIT ZPX */ -OP(54) { int tmp; RD_ZPX; ASR_65CE02; WB_EA; } /* 4 ASR ZPX */ -OP(74) { int tmp; STZ_65CE02; WR_ZPX; } /* 3 STZ ZPX */ -OP(94) { int tmp; STY; WR_ZPX; } /* 3 STY ZPX */ -OP(b4) { int tmp; RD_ZPX; LDY; } /* 3 LDY ZPX */ -OP(d4) { int tmp; RD_ZPG; CPZ; } /* 3 CPZ ZPG */ -OP(f4) { PAIR tmp; RD_IMM_WORD; PUSH_WORD(tmp); } /* 5 PHW imm16 */ - -OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */ -OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */ -OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */ -OP(65) { int tmp; RD_ZPG; ADC; } /* 3 ADC ZPG */ -OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */ -OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */ -OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */ -OP(e5) { int tmp; RD_ZPG; SBC; } /* 3 SBC ZPG */ - -OP(15) { int tmp; RD_ZPX; ORA; } /* 3 ORA ZPX */ -OP(35) { int tmp; RD_ZPX; AND; } /* 3 AND ZPX */ -OP(55) { int tmp; RD_ZPX; EOR; } /* 3 EOR ZPX */ -OP(75) { int tmp; RD_ZPX; ADC; } /* 3 ADC ZPX */ -OP(95) { int tmp; STA; WR_ZPX; } /* 3 STA ZPX */ -OP(b5) { int tmp; RD_ZPX; LDA; } /* 3 LDA ZPX */ -OP(d5) { int tmp; RD_ZPX; CMP; } /* 3 CMP ZPX */ -OP(f5) { int tmp; RD_ZPX; SBC; } /* 3 SBC ZPX */ - -OP(06) { int tmp; RD_ZPG; ASL; WB_EA; } /* 4 ASL ZPG */ -OP(26) { int tmp; RD_ZPG; ROL; WB_EA; } /* 4 ROL ZPG */ -OP(46) { int tmp; RD_ZPG; LSR; WB_EA; } /* 4 LSR ZPG */ -OP(66) { int tmp; RD_ZPG; ROR; WB_EA; } /* 4 ROR ZPG */ -OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */ -OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */ -OP(c6) { int tmp; RD_ZPG; DEC; WB_EA; } /* 4 DEC ZPG */ -OP(e6) { int tmp; RD_ZPG; INC; WB_EA; } /* 4 INC ZPG */ - -OP(16) { int tmp; RD_ZPX; ASL; WB_EA; } /* 4 ASL ZPX */ -OP(36) { int tmp; RD_ZPX; ROL; WB_EA; } /* 4 ROL ZPX */ -OP(56) { int tmp; RD_ZPX; LSR; WB_EA; } /* 4 LSR ZPX */ -OP(76) { int tmp; RD_ZPX; ROR; WB_EA; } /* 4 ROR ZPX */ -OP(96) { int tmp; STX; WR_ZPY; } /* 3 STX ZPY */ -OP(b6) { int tmp; RD_ZPY; LDX; } /* 3 LDX ZPY */ -OP(d6) { int tmp; RD_ZPX; DEC; WB_EA; } /* 4 DEC ZPX */ -OP(f6) { int tmp; RD_ZPX; INC; WB_EA; } /* 4 INC ZPX */ - -OP(07) { int tmp; RD_ZPG; RMB(0); WB_EA; } /* 4 RMB0 ZPG */ -OP(27) { int tmp; RD_ZPG; RMB(2); WB_EA; } /* 4 RMB2 ZPG */ -OP(47) { int tmp; RD_ZPG; RMB(4); WB_EA; } /* 4 RMB4 ZPG */ -OP(67) { int tmp; RD_ZPG; RMB(6); WB_EA; } /* 4 RMB6 ZPG */ -OP(87) { int tmp; RD_ZPG; SMB(0); WB_EA; } /* 4 SMB0 ZPG */ -OP(a7) { int tmp; RD_ZPG; SMB(2); WB_EA; } /* 4 SMB2 ZPG */ -OP(c7) { int tmp; RD_ZPG; SMB(4); WB_EA; } /* 4 SMB4 ZPG */ -OP(e7) { int tmp; RD_ZPG; SMB(6); WB_EA; } /* 4 SMB6 ZPG */ - -OP(17) { int tmp; RD_ZPG; RMB(1); WB_EA; } /* 4 RMB1 ZPG */ -OP(37) { int tmp; RD_ZPG; RMB(3); WB_EA; } /* 4 RMB3 ZPG */ -OP(57) { int tmp; RD_ZPG; RMB(5); WB_EA; } /* 4 RMB5 ZPG */ -OP(77) { int tmp; RD_ZPG; RMB(7); WB_EA; } /* 4 RMB7 ZPG */ -OP(97) { int tmp; RD_ZPG; SMB(1); WB_EA; } /* 4 SMB1 ZPG */ -OP(b7) { int tmp; RD_ZPG; SMB(3); WB_EA; } /* 4 SMB3 ZPG */ -OP(d7) { int tmp; RD_ZPG; SMB(5); WB_EA; } /* 4 SMB5 ZPG */ -OP(f7) { int tmp; RD_ZPG; SMB(7); WB_EA; } /* 4 SMB7 ZPG */ - -OP(08) { RD_DUM; PHP; } /* 3 PHP */ -OP(28) { RD_DUM; PLP; } /* 3 PLP */ -OP(48) { RD_DUM; PHA; } /* 3 PHA */ -OP(68) { RD_DUM; PLA; } /* 3 PLA */ -OP(88) { DEY; } /* 1 DEY */ -OP(a8) { TAY; } /* 1 TAY */ -OP(c8) { INY; } /* 1 INY */ -OP(e8) { INX; } /* 1 INX */ - -OP(18) { CLC; } /* 1 CLC */ -OP(38) { SEC; } /* 1 SEC */ -OP(58) { CLI; } /* 1 CLI */ -OP(78) { RD_DUM; SEI; } /* 2 SEI */ -OP(98) { TYA; } /* 1 TYA */ -OP(b8) { CLV; } /* 1 CLV */ -OP(d8) { CLD; } /* 1 CLD */ -OP(f8) { SED; } /* 1 SED */ - -OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */ -OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */ -OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */ -OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */ -OP(89) { int tmp; RD_IMM; BIT; } /* 2 BIT IMM */ -OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */ -OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */ -OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */ - -OP(19) { int tmp; RD_ABY; ORA; } /* 4 ORA ABY */ -OP(39) { int tmp; RD_ABY; AND; } /* 4 AND ABY */ -OP(59) { int tmp; RD_ABY; EOR; } /* 4 EOR ABY */ -OP(79) { int tmp; RD_ABY; ADC; } /* 4 ADC ABY */ -OP(99) { int tmp; STA; WR_ABY; } /* 4 STA ABY */ -OP(b9) { int tmp; RD_ABY; LDA; } /* 4 LDA ABY */ -OP(d9) { int tmp; RD_ABY; CMP; } /* 4 CMP ABY */ -OP(f9) { int tmp; RD_ABY; SBC; } /* 4 SBC ABY */ - -OP(0a) { int tmp; RD_ACC; ASL; WR_ACC; } /* 1 ASL A */ -OP(2a) { int tmp; RD_ACC; ROL; WR_ACC; } /* 1 ROL A */ -OP(4a) { int tmp; RD_ACC; LSR; WR_ACC; } /* 1 LSR A */ -OP(6a) { int tmp; RD_ACC; ROR; WR_ACC; } /* 1 ROR A */ -OP(8a) { TXA; } /* 1 TXA */ -OP(aa) { TAX; } /* 1 TAX */ -OP(ca) { DEX; } /* 1 DEX */ -OP(ea) { NOP; } /* 1 NOP */ - -OP(1a) { INA; } /* 1 INA */ -OP(3a) { DEA; } /* 1 DEA */ -OP(5a) { RD_DUM; PHY; } /* 3 PHY */ -OP(7a) { RD_DUM; PLY; } /* 3 PLY */ -OP(9a) { TXS; } /* 1 TXS */ -OP(ba) { TSX; } /* 1 TSX */ -OP(da) { RD_DUM; PHX; } /* 3 PHX */ -OP(fa) { RD_DUM; PLX; } /* 3 PLX */ - -OP(0b) { TSY; } /* 1 TSY */ -OP(2b) { TYS; } /* 1 TYS */ -OP(4b) { TAZ; } /* 1 TAZ */ -OP(6b) { TZA; } /* 1 TZA */ -OP(8b) { int tmp; STY; WR_ABX; } /* 4 STY ABX */ -OP(ab) { int tmp; RD_ABS; LDZ; } /* 4 LDZ ABS */ -OP(cb) { PAIR tmp; tmp.d = 0; RD_ABS_WORD; ASW; WB_EA_WORD; } /* 7 ASW ABS */ -OP(eb) { PAIR tmp; RD_ABS_WORD; ROW; WB_EA_WORD; } /* 6/7? roW ABS */ - -OP(1b) { INZ; } /* 1 INZ */ -OP(3b) { DEZ; } /* 1 DEZ */ -OP(5b) { TAB; } /* 1 TAB */ -OP(7b) { TBA; } /* 1 TBA */ -OP(9b) { int tmp; STX; WR_ABY; } /* 4 STX ABY */ -OP(bb) { int tmp; RD_ABX; LDZ; } /* 4 LDZ ABX */ -OP(db) { RD_DUM; PHZ; } /* 3 PHZ */ -OP(fb) { RD_DUM; PLZ; } /* 3 PLZ */ - -OP(0c) { int tmp; RD_ABS; TSB; WB_EA; } /* 5 TSB ABS */ -OP(2c) { int tmp; RD_ABS; RD_DUM; BIT; } /* 5 BIT ABS */ -OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */ -OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */ -OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */ -OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */ -OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */ -OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */ - -OP(1c) { int tmp; RD_ABS; TRB; WB_EA; } /* 5 TRB ABS */ -OP(3c) { int tmp; RD_ABX; RD_DUM; BIT; } /* 5 BIT ABX */ -#ifdef M4510 -OP(5c) { MAP; } /* 4? MAP */ -#else -OP(5c) { int t1,t2,t3; AUG; } /* 4 AUGMENT/no operation */ -#endif -OP(7c) { int tmp; EA_IAX; JMP; } /* 5 JMP IAX */ -OP(9c) { int tmp; STZ_65CE02; WR_ABS; } /* 4 STZ ABS */ -OP(bc) { int tmp; RD_ABX; LDY; } /* 4 LDY ABX */ -OP(dc) { int tmp; RD_ABS; CPZ; } /* 4 CPZ ABS */ -OP(fc) { PAIR tmp; RD_ABS_WORD; PUSH_WORD(tmp); } /* 7 PHW ab */ - -OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */ -OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */ -OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */ -OP(6d) { int tmp; RD_ABS; ADC; } /* 4 ADC ABS */ -OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */ -OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */ -OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */ -OP(ed) { int tmp; RD_ABS; SBC; } /* 4 SBC ABS */ - -OP(1d) { int tmp; RD_ABX; ORA; } /* 4 ORA ABX */ -OP(3d) { int tmp; RD_ABX; AND; } /* 4 AND ABX */ -OP(5d) { int tmp; RD_ABX; EOR; } /* 4 EOR ABX */ -OP(7d) { int tmp; RD_ABX; ADC; } /* 4 ADC ABX */ -OP(9d) { int tmp; STA; WR_ABX; } /* 4 STA ABX */ -OP(bd) { int tmp; RD_ABX; LDA; } /* 4 LDA ABX */ -OP(dd) { int tmp; RD_ABX; CMP; } /* 4 CMP ABX */ -OP(fd) { int tmp; RD_ABX; SBC; } /* 4 SBC ABX */ - -OP(0e) { int tmp; RD_ABS; ASL; WB_EA; } /* 5 ASL ABS */ -OP(2e) { int tmp; RD_ABS; ROL; WB_EA; } /* 5 ROL ABS */ -OP(4e) { int tmp; RD_ABS; LSR; WB_EA; } /* 5 LSR ABS */ -OP(6e) { int tmp; RD_ABS; ROR; WB_EA; } /* 5 ROR ABS */ -OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */ -OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */ -OP(ce) { int tmp; RD_ABS; DEC; WB_EA; } /* 5 DEC ABS */ -OP(ee) { int tmp; RD_ABS; INC; WB_EA; } /* 5 INC ABS */ - -OP(1e) { int tmp; RD_ABX; ASL; WB_EA; } /* 5 ASL ABX */ -OP(3e) { int tmp; RD_ABX; ROL; WB_EA; } /* 5 ROL ABX */ -OP(5e) { int tmp; RD_ABX; LSR; WB_EA; } /* 5 LSR ABX */ -OP(7e) { int tmp; RD_ABX; ROR; WB_EA; } /* 5 ROR ABX */ -OP(9e) { int tmp; STZ_65CE02; WR_ABX; } /* 4 STZ ABX */ -OP(be) { int tmp; RD_ABY; LDX; } /* 4 LDX ABY */ -OP(de) { int tmp; RD_ABX; DEC; WB_EA; } /* 5 DEC ABX */ -OP(fe) { int tmp; RD_ABX; INC; WB_EA; } /* 5 INC ABX */ - -OP(0f) { int tmp; RD_ZPG; BBR(0); } /* 4 BBR0 ZPG */ -OP(2f) { int tmp; RD_ZPG; BBR(2); } /* 4 BBR2 ZPG */ -OP(4f) { int tmp; RD_ZPG; BBR(4); } /* 4 BBR4 ZPG */ -OP(6f) { int tmp; RD_ZPG; BBR(6); } /* 4 BBR6 ZPG */ -OP(8f) { int tmp; RD_ZPG; BBS(0); } /* 4 BBS0 ZPG */ -OP(af) { int tmp; RD_ZPG; BBS(2); } /* 4 BBS2 ZPG */ -OP(cf) { int tmp; RD_ZPG; BBS(4); } /* 4 BBS4 ZPG */ -OP(ef) { int tmp; RD_ZPG; BBS(6); } /* 4 BBS6 ZPG */ - -OP(1f) { int tmp; RD_ZPG; BBR(1); } /* 4 BBR1 ZPG */ -OP(3f) { int tmp; RD_ZPG; BBR(3); } /* 4 BBR3 ZPG */ -OP(5f) { int tmp; RD_ZPG; BBR(5); } /* 4 BBR5 ZPG */ -OP(7f) { int tmp; RD_ZPG; BBR(7); } /* 4 BBR7 ZPG */ -OP(9f) { int tmp; RD_ZPG; BBS(1); } /* 4 BBS1 ZPG */ -OP(bf) { int tmp; RD_ZPG; BBS(3); } /* 4 BBS3 ZPG */ -OP(df) { int tmp; RD_ZPG; BBS(5); } /* 4 BBS5 ZPG */ -OP(ff) { int tmp; RD_ZPG; BBS(7); } /* 4 BBS7 ZPG */ - -#ifdef M4510 -static void (*const insn4510[0x100])(m4510_Regs *) = { - m4510_00,m4510_01,m4510_02,m4510_03,m4510_04,m4510_05,m4510_06,m4510_07, - m4510_08,m4510_09,m4510_0a,m4510_0b,m4510_0c,m4510_0d,m4510_0e,m4510_0f, - m4510_10,m4510_11,m4510_12,m4510_13,m4510_14,m4510_15,m4510_16,m4510_17, - m4510_18,m4510_19,m4510_1a,m4510_1b,m4510_1c,m4510_1d,m4510_1e,m4510_1f, - m4510_20,m4510_21,m4510_22,m4510_23,m4510_24,m4510_25,m4510_26,m4510_27, - m4510_28,m4510_29,m4510_2a,m4510_2b,m4510_2c,m4510_2d,m4510_2e,m4510_2f, - m4510_30,m4510_31,m4510_32,m4510_33,m4510_34,m4510_35,m4510_36,m4510_37, - m4510_38,m4510_39,m4510_3a,m4510_3b,m4510_3c,m4510_3d,m4510_3e,m4510_3f, - m4510_40,m4510_41,m4510_42,m4510_43,m4510_44,m4510_45,m4510_46,m4510_47, - m4510_48,m4510_49,m4510_4a,m4510_4b,m4510_4c,m4510_4d,m4510_4e,m4510_4f, - m4510_50,m4510_51,m4510_52,m4510_53,m4510_54,m4510_55,m4510_56,m4510_57, - m4510_58,m4510_59,m4510_5a,m4510_5b,m4510_5c,m4510_5d,m4510_5e,m4510_5f, - m4510_60,m4510_61,m4510_62,m4510_63,m4510_64,m4510_65,m4510_66,m4510_67, - m4510_68,m4510_69,m4510_6a,m4510_6b,m4510_6c,m4510_6d,m4510_6e,m4510_6f, - m4510_70,m4510_71,m4510_72,m4510_73,m4510_74,m4510_75,m4510_76,m4510_77, - m4510_78,m4510_79,m4510_7a,m4510_7b,m4510_7c,m4510_7d,m4510_7e,m4510_7f, - m4510_80,m4510_81,m4510_82,m4510_83,m4510_84,m4510_85,m4510_86,m4510_87, - m4510_88,m4510_89,m4510_8a,m4510_8b,m4510_8c,m4510_8d,m4510_8e,m4510_8f, - m4510_90,m4510_91,m4510_92,m4510_93,m4510_94,m4510_95,m4510_96,m4510_97, - m4510_98,m4510_99,m4510_9a,m4510_9b,m4510_9c,m4510_9d,m4510_9e,m4510_9f, - m4510_a0,m4510_a1,m4510_a2,m4510_a3,m4510_a4,m4510_a5,m4510_a6,m4510_a7, - m4510_a8,m4510_a9,m4510_aa,m4510_ab,m4510_ac,m4510_ad,m4510_ae,m4510_af, - m4510_b0,m4510_b1,m4510_b2,m4510_b3,m4510_b4,m4510_b5,m4510_b6,m4510_b7, - m4510_b8,m4510_b9,m4510_ba,m4510_bb,m4510_bc,m4510_bd,m4510_be,m4510_bf, - m4510_c0,m4510_c1,m4510_c2,m4510_c3,m4510_c4,m4510_c5,m4510_c6,m4510_c7, - m4510_c8,m4510_c9,m4510_ca,m4510_cb,m4510_cc,m4510_cd,m4510_ce,m4510_cf, - m4510_d0,m4510_d1,m4510_d2,m4510_d3,m4510_d4,m4510_d5,m4510_d6,m4510_d7, - m4510_d8,m4510_d9,m4510_da,m4510_db,m4510_dc,m4510_dd,m4510_de,m4510_df, - m4510_e0,m4510_e1,m4510_e2,m4510_e3,m4510_e4,m4510_e5,m4510_e6,m4510_e7, - m4510_e8,m4510_e9,m4510_ea,m4510_eb,m4510_ec,m4510_ed,m4510_ee,m4510_ef, - m4510_f0,m4510_f1,m4510_f2,m4510_f3,m4510_f4,m4510_f5,m4510_f6,m4510_f7, - m4510_f8,m4510_f9,m4510_fa,m4510_fb,m4510_fc,m4510_fd,m4510_fe,m4510_ff -}; -#else -static void (*const insn65ce02[0x100])(m65ce02_Regs *) = { - m65ce02_00,m65ce02_01,m65ce02_02,m65ce02_03,m65ce02_04,m65ce02_05,m65ce02_06,m65ce02_07, - m65ce02_08,m65ce02_09,m65ce02_0a,m65ce02_0b,m65ce02_0c,m65ce02_0d,m65ce02_0e,m65ce02_0f, - m65ce02_10,m65ce02_11,m65ce02_12,m65ce02_13,m65ce02_14,m65ce02_15,m65ce02_16,m65ce02_17, - m65ce02_18,m65ce02_19,m65ce02_1a,m65ce02_1b,m65ce02_1c,m65ce02_1d,m65ce02_1e,m65ce02_1f, - m65ce02_20,m65ce02_21,m65ce02_22,m65ce02_23,m65ce02_24,m65ce02_25,m65ce02_26,m65ce02_27, - m65ce02_28,m65ce02_29,m65ce02_2a,m65ce02_2b,m65ce02_2c,m65ce02_2d,m65ce02_2e,m65ce02_2f, - m65ce02_30,m65ce02_31,m65ce02_32,m65ce02_33,m65ce02_34,m65ce02_35,m65ce02_36,m65ce02_37, - m65ce02_38,m65ce02_39,m65ce02_3a,m65ce02_3b,m65ce02_3c,m65ce02_3d,m65ce02_3e,m65ce02_3f, - m65ce02_40,m65ce02_41,m65ce02_42,m65ce02_43,m65ce02_44,m65ce02_45,m65ce02_46,m65ce02_47, - m65ce02_48,m65ce02_49,m65ce02_4a,m65ce02_4b,m65ce02_4c,m65ce02_4d,m65ce02_4e,m65ce02_4f, - m65ce02_50,m65ce02_51,m65ce02_52,m65ce02_53,m65ce02_54,m65ce02_55,m65ce02_56,m65ce02_57, - m65ce02_58,m65ce02_59,m65ce02_5a,m65ce02_5b,m65ce02_5c,m65ce02_5d,m65ce02_5e,m65ce02_5f, - m65ce02_60,m65ce02_61,m65ce02_62,m65ce02_63,m65ce02_64,m65ce02_65,m65ce02_66,m65ce02_67, - m65ce02_68,m65ce02_69,m65ce02_6a,m65ce02_6b,m65ce02_6c,m65ce02_6d,m65ce02_6e,m65ce02_6f, - m65ce02_70,m65ce02_71,m65ce02_72,m65ce02_73,m65ce02_74,m65ce02_75,m65ce02_76,m65ce02_77, - m65ce02_78,m65ce02_79,m65ce02_7a,m65ce02_7b,m65ce02_7c,m65ce02_7d,m65ce02_7e,m65ce02_7f, - m65ce02_80,m65ce02_81,m65ce02_82,m65ce02_83,m65ce02_84,m65ce02_85,m65ce02_86,m65ce02_87, - m65ce02_88,m65ce02_89,m65ce02_8a,m65ce02_8b,m65ce02_8c,m65ce02_8d,m65ce02_8e,m65ce02_8f, - m65ce02_90,m65ce02_91,m65ce02_92,m65ce02_93,m65ce02_94,m65ce02_95,m65ce02_96,m65ce02_97, - m65ce02_98,m65ce02_99,m65ce02_9a,m65ce02_9b,m65ce02_9c,m65ce02_9d,m65ce02_9e,m65ce02_9f, - m65ce02_a0,m65ce02_a1,m65ce02_a2,m65ce02_a3,m65ce02_a4,m65ce02_a5,m65ce02_a6,m65ce02_a7, - m65ce02_a8,m65ce02_a9,m65ce02_aa,m65ce02_ab,m65ce02_ac,m65ce02_ad,m65ce02_ae,m65ce02_af, - m65ce02_b0,m65ce02_b1,m65ce02_b2,m65ce02_b3,m65ce02_b4,m65ce02_b5,m65ce02_b6,m65ce02_b7, - m65ce02_b8,m65ce02_b9,m65ce02_ba,m65ce02_bb,m65ce02_bc,m65ce02_bd,m65ce02_be,m65ce02_bf, - m65ce02_c0,m65ce02_c1,m65ce02_c2,m65ce02_c3,m65ce02_c4,m65ce02_c5,m65ce02_c6,m65ce02_c7, - m65ce02_c8,m65ce02_c9,m65ce02_ca,m65ce02_cb,m65ce02_cc,m65ce02_cd,m65ce02_ce,m65ce02_cf, - m65ce02_d0,m65ce02_d1,m65ce02_d2,m65ce02_d3,m65ce02_d4,m65ce02_d5,m65ce02_d6,m65ce02_d7, - m65ce02_d8,m65ce02_d9,m65ce02_da,m65ce02_db,m65ce02_dc,m65ce02_dd,m65ce02_de,m65ce02_df, - m65ce02_e0,m65ce02_e1,m65ce02_e2,m65ce02_e3,m65ce02_e4,m65ce02_e5,m65ce02_e6,m65ce02_e7, - m65ce02_e8,m65ce02_e9,m65ce02_ea,m65ce02_eb,m65ce02_ec,m65ce02_ed,m65ce02_ee,m65ce02_ef, - m65ce02_f0,m65ce02_f1,m65ce02_f2,m65ce02_f3,m65ce02_f4,m65ce02_f5,m65ce02_f6,m65ce02_f7, - m65ce02_f8,m65ce02_f9,m65ce02_fa,m65ce02_fb,m65ce02_fc,m65ce02_fd,m65ce02_fe,m65ce02_ff -}; -#endif - diff --git a/src/emu/cpu/m6502/t65sc02.c b/src/emu/cpu/m6502/t65sc02.c deleted file mode 100644 index 5796cd38514..00000000000 --- a/src/emu/cpu/m6502/t65sc02.c +++ /dev/null @@ -1,80 +0,0 @@ -/***************************************************************************** - * - * tbl65sc02.c - * 65sc02 opcode functions and function pointer table - * - * Copyright Peter Trauner, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ -/* 4. February 2000 PeT fixed relative word operand */ - -/* opcode already in 65c02 - although docu says they were introduced with this cpu - - bbr - bbs - rmb - smb - trb - tsb -*/ - -#undef OP -#define OP(nn) INLINE void m65sc02_##nn(m6502_Regs *cpustate) - -/***************************************************************************** - ***************************************************************************** - * - * overrides for 65SC02 opcodes - * - ***************************************************************************** - * op temp cycles rdmem opc wrmem ********************/ -OP(63) { BSR; } /* 5? BSR */ - -static void (*const insn65sc02[0x100])(m6502_Regs *cpustate) = { - m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07, - m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f, - m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17, - m65c02_18,m65c02_19,m65c02_1a,m65c02_1b,m65c02_1c,m65c02_1d,m65c02_1e,m65c02_1f, - m65c02_20,m65c02_21,m65c02_22,m65c02_23,m65c02_24,m65c02_25,m65c02_26,m65c02_27, - m65c02_28,m65c02_29,m65c02_2a,m65c02_2b,m65c02_2c,m65c02_2d,m65c02_2e,m65c02_2f, - m65c02_30,m65c02_31,m65c02_32,m65c02_33,m65c02_34,m65c02_35,m65c02_36,m65c02_37, - m65c02_38,m65c02_39,m65c02_3a,m65c02_3b,m65c02_3c,m65c02_3d,m65c02_3e,m65c02_3f, - m65c02_40,m65c02_41,m65c02_42,m65c02_43,m65c02_44,m65c02_45,m65c02_46,m65c02_47, - m65c02_48,m65c02_49,m65c02_4a,m65c02_4b,m65c02_4c,m65c02_4d,m65c02_4e,m65c02_4f, - m65c02_50,m65c02_51,m65c02_52,m65c02_53,m65c02_54,m65c02_55,m65c02_56,m65c02_57, - m65c02_58,m65c02_59,m65c02_5a,m65c02_5b,m65c02_5c,m65c02_5d,m65c02_5e,m65c02_5f, - m65c02_60,m65c02_61,m65c02_62,m65c02_63,m65c02_64,m65c02_65,m65c02_66,m65c02_67, - m65c02_68,m65c02_69,m65c02_6a,m65c02_6b,m65c02_6c,m65c02_6d,m65c02_6e,m65c02_6f, - m65c02_70,m65c02_71,m65c02_72,m65c02_73,m65c02_74,m65c02_75,m65c02_76,m65c02_77, - m65c02_78,m65c02_79,m65c02_7a,m65c02_7b,m65c02_7c,m65c02_7d,m65c02_7e,m65c02_7f, - m65c02_80,m65c02_81,m65c02_82,m65c02_83,m65c02_84,m65c02_85,m65c02_86,m65c02_87, - m65c02_88,m65c02_89,m65c02_8a,m65c02_8b,m65c02_8c,m65c02_8d,m65c02_8e,m65c02_8f, - m65c02_90,m65c02_91,m65c02_92,m65c02_93,m65c02_94,m65c02_95,m65c02_96,m65c02_97, - m65c02_98,m65c02_99,m65c02_9a,m65c02_9b,m65c02_9c,m65c02_9d,m65c02_9e,m65c02_9f, - m65c02_a0,m65c02_a1,m65c02_a2,m65c02_a3,m65c02_a4,m65c02_a5,m65c02_a6,m65c02_a7, - m65c02_a8,m65c02_a9,m65c02_aa,m65c02_ab,m65c02_ac,m65c02_ad,m65c02_ae,m65c02_af, - m65c02_b0,m65c02_b1,m65c02_b2,m65c02_b3,m65c02_b4,m65c02_b5,m65c02_b6,m65c02_b7, - m65c02_b8,m65c02_b9,m65c02_ba,m65c02_bb,m65c02_bc,m65c02_bd,m65c02_be,m65c02_bf, - m65c02_c0,m65c02_c1,m65c02_c2,m65c02_c3,m65c02_c4,m65c02_c5,m65c02_c6,m65c02_c7, - m65c02_c8,m65c02_c9,m65c02_ca,m65c02_cb,m65c02_cc,m65c02_cd,m65c02_ce,m65c02_cf, - m65c02_d0,m65c02_d1,m65c02_d2,m65c02_d3,m65c02_d4,m65c02_d5,m65c02_d6,m65c02_d7, - m65c02_d8,m65c02_d9,m65c02_da,m65c02_db,m65c02_dc,m65c02_dd,m65c02_de,m65c02_df, - m65c02_e0,m65c02_e1,m65c02_e2,m65c02_e3,m65c02_e4,m65c02_e5,m65c02_e6,m65c02_e7, - m65c02_e8,m65c02_e9,m65c02_ea,m65c02_eb,m65c02_ec,m65c02_ed,m65c02_ee,m65c02_ef, - m65c02_f0,m65c02_f1,m65c02_f2,m65c02_f3,m65c02_f4,m65c02_f5,m65c02_f6,m65c02_f7, - m65c02_f8,m65c02_f9,m65c02_fa,m65c02_fb,m65c02_fc,m65c02_fd,m65c02_fe,m65c02_ff -}; - diff --git a/src/emu/cpu/m6502/tdeco16.c b/src/emu/cpu/m6502/tdeco16.c deleted file mode 100644 index f84b7489141..00000000000 --- a/src/emu/cpu/m6502/tdeco16.c +++ /dev/null @@ -1,428 +0,0 @@ -/***************************************************************************** - * Deco CPU16 instructions - still very work in progress! - * - *****************************************************************************/ - -#define DECO16_VERBOSE 0 - -#undef OP -#define OP(nn) INLINE void deco16_##nn(m6502_Regs *cpustate) - -#define DECO16_BRK \ - logerror("%04x: BRK\n",PCW); \ - RDOPARG(); \ - PUSH(PCH); \ - PUSH(PCL); \ - PUSH(P | F_B); \ - P = (P | F_I); \ - PCL = RDMEM(DECO16_IRQ_VEC+1); \ - PCH = RDMEM(DECO16_IRQ_VEC); - - -/***************************************************************************** - ***************************************************************************** - * - * overrides for 6502 opcodes - * - ***************************************************************************** - * op temp cycles rdmem opc wrmem ********************/ -OP(00) { DECO16_BRK; } /* 7 BRK */ -#define deco16_20 m6502_20 /* 6 JSR ABS */ -#define deco16_40 m6502_40 /* 6 RTI */ -#define deco16_60 m6502_60 /* 6 RTS */ -OP(80) { RD_DUM; ILL; } /* 2 ILL */ -#define deco16_a0 m6502_a0 /* 2 LDY IMM */ -#define deco16_c0 m6502_c0 /* 2 CPY IMM */ -#define deco16_e0 m6502_e0 /* 2 CPX IMM */ - -#define deco16_10 m6502_10 /* 2 BPL */ -#define deco16_30 m6502_30 /* 2 BMI */ -#define deco16_50 m6502_50 /* 2 BVC */ -#define deco16_70 m6502_70 /* 2 BVS */ -#define deco16_90 m6502_90 /* 2 BCC */ -#define deco16_b0 m6502_b0 /* 2 BCS */ -#define deco16_d0 m6502_d0 /* 2 BNE */ -#define deco16_f0 m6502_f0 /* 2 BEQ */ - -#define deco16_01 m6502_01 /* 6 ORA IDX */ -#define deco16_21 m6502_21 /* 6 AND IDX */ -#define deco16_41 m6502_41 /* 6 EOR IDX */ -#define deco16_61 m6502_61 /* 6 ADC IDX */ -#define deco16_81 m6502_81 /* 6 STA IDX */ -#define deco16_a1 m6502_a1 /* 6 LDA IDX */ -#define deco16_c1 m6502_c1 /* 6 CMP IDX */ -#define deco16_e1 m6502_e1 /* 6 SBC IDX */ - -#define deco16_11 m6502_11 /* 5 ORA IDY; */ -#define deco16_31 m6502_31 /* 5 AND IDY; */ -#define deco16_51 m6502_51 /* 5 EOR IDY; */ -#define deco16_71 m6502_71 /* 5 ADC IDY; */ -#define deco16_91 m6502_91 /* 6 STA IDY; */ -#define deco16_b1 m6502_b1 /* 5 LDA IDY; */ -#define deco16_d1 m6502_d1 /* 5 CMP IDY; */ -#define deco16_f1 m6502_f1 /* 5 SBC IDY; */ - -OP(02) { RD_DUM; ILL; } /* 2 ILL */ -OP(22) { RD_DUM; ILL; } /* 2 ILL */ -OP(42) { RD_DUM; ILL; } /* 2 ILL */ -OP(62) { RD_DUM; ILL; } /* 2 ILL */ -OP(82) { RD_DUM; ILL; } /* 2 ILL */ -#define deco16_a2 m6502_a2 /* 2 LDX IMM */ -OP(c2) { RD_DUM; ILL; } /* 2 ILL */ -OP(e2) { RD_DUM; ILL; } /* 2 ILL */ - -OP(12) { RD_DUM; ILL; } /* 2 ILL / 3 ora zpi ?? */ -OP(32) { RD_DUM; ILL; } /* 2 ILL / 3 and zpi ?? */ -OP(52) { RD_DUM; ILL; } /* 2 ILL / 3 eor zpi ?? */ -OP(72) { RD_DUM; ILL; } /* 2 ILL / 3 adc zpi ?? */ -OP(92) { RD_DUM; ILL; } /* 2 ILL / 3 sta zpi ?? */ -OP(b2) { RD_DUM; ILL; } /* 2 ILL / 3 lda zpi ?? */ -OP(d2) { RD_DUM; ILL; } /* 2 ILL / 3 cmp zpi ?? */ -OP(f2) { RD_DUM; ILL; } /* 2 ILL / 3 sbc zpi ?? */ - -OP(03) { RD_DUM; ILL; } /* 2 ILL */ -OP(23) { - int tmp; - - cpustate->icount -= 1; - RD_IMM; - - if (DECO16_VERBOSE) - logerror("%04x: OP23 %02x\n",PCW,tmp); -} -OP(43) { RD_DUM; ILL; } /* 2 ILL */ -OP(63) { - int tmp; - - cpustate->icount -= 1; - RD_IMM; - - if (DECO16_VERBOSE) - logerror("%04x: OP63 %02x\n",PCW,tmp); -} -OP(83) { RD_DUM; ILL; } /* 2 ILL */ -OP(a3) { - int tmp; - - cpustate->icount -= 1; - RD_IMM; - - if (DECO16_VERBOSE) - logerror("%04x: OPA3 %02x\n",PCW,tmp); -} -OP(c3) { RD_DUM; ILL; } /* 2 ILL */ -OP(e3) { RD_DUM; ILL; } /* 2 ILL */ - -OP(13) { int tmp; cpustate->icount -= 1; RD_IMM; - - if (DECO16_VERBOSE) - logerror("%04x: OP13 %02x\n",PCW,tmp); - -//bank select control? - - } /* */ -OP(33) { RD_DUM; ILL; } /* 2 ILL */ -OP(53) { RD_DUM; ILL; } /* 2 ILL */ -OP(73) { RD_DUM; ILL; } /* 2 ILL */ -OP(93) { RD_DUM; ILL; } /* 2 ILL */ -OP(b3) { RD_DUM; ILL; } /* 2 ILL */ -OP(d3) { RD_DUM; ILL; } /* 2 ILL */ -OP(f3) { RD_DUM; ILL; } /* 2 ILL */ - -OP(04) { RD_DUM; ILL; } /* 2 ILL / 3 tsb zpg ?? */ -#define deco16_24 m6502_24 /* 3 BIT ZPG */ -OP(44) { RD_DUM; ILL; } /* 2 ILL */ -OP(64) { RD_DUM; ILL; } /* 2 ILL / 3 stz zpg ?? */ -#define deco16_84 m6502_84 /* 3 STY ZPG */ -#define deco16_a4 m6502_a4 /* 3 LDY ZPG */ -#define deco16_c4 m6502_c4 /* 3 CPY ZPG */ -#define deco16_e4 m6502_e4 /* 3 CPX ZPG */ - -OP(14) { RD_DUM; ILL; } /* 2 ILL / 3 trb zpg ?? */ -OP(34) { RD_DUM; ILL; } /* 2 ILL / 4 bit zpx ?? */ -OP(54) { RD_DUM; ILL; } /* 2 ILL */ -OP(74) { RD_DUM; ILL; } /* 2 ILL / 4 stz zpx ?? */ -#define deco16_94 m6502_94 /* 4 sty zpx */ -#define deco16_b4 m6502_b4 /* 4 ldy zpx */ -OP(d4) { RD_DUM; ILL; } /* 2 ILL */ -OP(f4) { RD_DUM; ILL; } /* 2 ILL */ - -#define deco16_05 m6502_05 /* 3 ORA ZPG */ -#define deco16_25 m6502_25 /* 3 AND ZPG */ -#define deco16_45 m6502_45 /* 3 EOR ZPG */ -#define deco16_65 m6502_65 /* 3 ADC ZPG */ -#define deco16_85 m6502_85 /* 3 STA ZPG */ -#define deco16_a5 m6502_a5 /* 3 LDA ZPG */ -#define deco16_c5 m6502_c5 /* 3 CMP ZPG */ -#define deco16_e5 m6502_e5 /* 3 SBC ZPG */ - -#define deco16_15 m6502_15 /* 4 ORA ZPX */ -#define deco16_35 m6502_35 /* 4 AND ZPX */ -#define deco16_55 m6502_55 /* 4 EOR ZPX */ -#define deco16_75 m6502_75 /* 4 ADC ZPX */ -#define deco16_95 m6502_95 /* 4 STA ZPX */ -#define deco16_b5 m6502_b5 /* 4 LDA ZPX */ -#define deco16_d5 m6502_d5 /* 4 CMP ZPX */ -#define deco16_f5 m6502_f5 /* 4 SBC ZPX */ - -#define deco16_06 m6502_06 /* 5 ASL ZPG */ -#define deco16_26 m6502_26 /* 5 ROL ZPG */ -#define deco16_46 m6502_46 /* 5 LSR ZPG */ -#define deco16_66 m6502_66 /* 5 ROR ZPG */ -#define deco16_86 m6502_86 /* 3 STX ZPG */ -#define deco16_a6 m6502_a6 /* 3 LDX ZPG */ -#define deco16_c6 m6502_c6 /* 5 DEC ZPG */ -#define deco16_e6 m6502_e6 /* 5 INC ZPG */ - -#define deco16_16 m6502_16 /* 6 ASL ZPX */ -#define deco16_36 m6502_36 /* 6 ROL ZPX */ -#define deco16_56 m6502_56 /* 6 LSR ZPX */ -#define deco16_76 m6502_76 /* 6 ROR ZPX */ -#define deco16_96 m6502_96 /* 4 STX ZPY */ -#define deco16_b6 m6502_b6 /* 4 LDX ZPY */ -#define deco16_d6 m6502_d6 /* 6 DEC ZPX */ -#define deco16_f6 m6502_f6 /* 6 INC ZPX */ - -OP(07) { RD_DUM; ILL; } /* 2 ILL / 5 RMB0 ZPG ?? */ -OP(27) { RD_DUM; ILL; } /* 2 ILL / 5 RMB2 ZPG ?? */ -OP(47) { RD_DUM; ILL; } /* 2 ILL / 5 RMB4 ZPG ?? */ -OP(67) { - RD_IMM_DISCARD; - cpustate->a=cpustate->io->read_byte(0); - -// logerror("%04x: VBL (0x67)\n",PCW); - -// really - wait for status? - -} /* */ -OP(87) { int tmp; cpustate->icount -= 1; RD_IMM; - logerror("%04x: OP87 %02x\n",PCW,tmp); - -} /* */ -OP(a7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB2 ZPG ?? */ -OP(c7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB4 ZPG ?? */ -OP(e7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB6 ZPG ?? */ - -OP(17) { RD_DUM; ILL; } /* 2 ILL / 5 RMB1 ZPG ?? */ -OP(37) { RD_DUM; ILL; } /* 2 ILL / 5 RMB3 ZPG ?? */ -OP(57) { RD_DUM; ILL; } /* 2 ILL / 5 RMB5 ZPG ?? */ -OP(77) { RD_DUM; ILL; } /* 2 ILL / 5 RMB7 ZPG ?? */ -OP(97) { RD_DUM; ILL; } /* 2 ILL / 5 SMB1 ZPG ?? */ -OP(b7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB3 ZPG ?? */ -OP(d7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB5 ZPG ?? */ -OP(f7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB7 ZPG ?? */ - -#define deco16_08 m6502_08 /* 3 PHP */ -#define deco16_28 m6502_28 /* 4 PLP */ -#define deco16_48 m6502_48 /* 3 PHA */ -#define deco16_68 m6502_68 /* 4 PLA */ -#define deco16_88 m6502_88 /* 2 DEY */ -#define deco16_a8 m6502_a8 /* 2 TAY */ -#define deco16_c8 m6502_c8 /* 2 INY */ -#define deco16_e8 m6502_e8 /* 2 INX */ - -#define deco16_18 m6502_18 /* 2 CLC */ -#define deco16_38 m6502_38 /* 2 SEC */ -#define deco16_58 m6502_58 /* 2 CLI */ -#define deco16_78 m6502_78 /* 2 SEI */ -#define deco16_98 m6502_98 /* 2 TYA */ -#define deco16_b8 m6502_b8 /* 2 CLV */ -#define deco16_d8 m6502_d8 /* 2 CLD */ -#define deco16_f8 m6502_f8 /* 2 SED */ - -#define deco16_09 m6502_09 /* 2 ORA IMM */ -#define deco16_29 m6502_29 /* 2 AND IMM */ -#define deco16_49 m6502_49 /* 2 EOR IMM */ -#define deco16_69 m6502_69 /* 2 ADC IMM */ -#define deco16_89 m65c02_89 /* 2 BIT IMM */ -#define deco16_a9 m6502_a9 /* 2 LDA IMM */ -#define deco16_c9 m6502_c9 /* 2 CMP IMM */ -#define deco16_e9 m6502_e9 /* 2 SBC IMM */ - -#define deco16_19 m6502_19 /* 4 ORA ABY */ -#define deco16_39 m6502_39 /* 4 AND ABY */ -#define deco16_59 m6502_59 /* 4 EOR ABY */ -#define deco16_79 m6502_79 /* 4 ADC ABY */ -#define deco16_99 m6502_99 /* 5 STA ABY */ -#define deco16_b9 m6502_b9 /* 4 LDA ABY */ -#define deco16_d9 m6502_d9 /* 4 CMP ABY */ -#define deco16_f9 m6502_f9 /* 4 SBC ABY */ - -#define deco16_0a m6502_0a /* 2 ASL */ -#define deco16_2a m6502_2a /* 2 ROL */ -#define deco16_4a m6502_4a /* 2 LSR */ -#define deco16_6a m6502_6a /* 2 ROR */ -#define deco16_8a m6502_8a /* 2 TXA */ -#define deco16_aa m6502_aa /* 2 TAX */ -#define deco16_ca m6502_ca /* 2 DEX */ -#define deco16_ea m6502_ea /* 2 NOP */ - -#define deco16_1a m65c02_1a /* 2 INA */ -#define deco16_3a m65c02_3a /* 2 DEA */ -#define deco16_5a m65c02_5a /* 3 PHY */ -#define deco16_7a m65c02_7a /* 4 PLY */ -#define deco16_9a m6502_9a /* 2 TXS */ -#define deco16_ba m6502_ba /* 2 TSX */ -#define deco16_da m65c02_da /* 3 PHX */ -#define deco16_fa m65c02_fa /* 4 PLX */ - -OP(0b) { int tmp; cpustate->icount -= 1; RD_IMM; - logerror("%04x: OP0B %02x\n",PCW,tmp); - - } -OP(2b) { RD_DUM; ILL; } /* 2 ILL */ -OP(4b) { cpustate->icount -= 1; RD_IMM_DISCARD; - //logerror("%04x: OP4B %02x\n",PCW,tmp); - /* TODO: Maybe it's just read I/O 0 and do a logic AND with bit 1? */ - cpustate->a=cpustate->io->read_byte(1); - -//tilt?? - -//VBL on expr-raider -//VBL on boomrang (bit 2) - - } -OP(6b) { RD_DUM; ILL; } /* 2 ILL */ -OP(8b) { RD_DUM; ILL; } /* 2 ILL */ -OP(ab) { RD_DUM; ILL; } /* 2 ILL */ -OP(cb) { RD_DUM; ILL; } /* 2 ILL */ -OP(eb) { RD_DUM; ILL; } /* 2 ILL */ - -OP(1b) { RD_DUM; ILL; } /* 2 ILL */ -OP(3b) { RD_DUM; ILL; } /* 2 ILL */ -OP(5b) { RD_DUM; ILL; } /* 2 ILL */ -OP(7b) { RD_DUM; ILL; } /* 2 ILL */ -OP(9b) { RD_DUM; ILL; } /* 2 ILL */ -OP(bb) { - int tmp; - - cpustate->icount -= 1; - RD_IMM; - - if (DECO16_VERBOSE) - logerror("%04x: OPBB %02x\n",PCW,tmp); -} -OP(db) { RD_DUM; ILL; } /* 2 ILL */ -OP(fb) { RD_DUM; ILL; } /* 2 ILL */ - -#define deco16_0c m65c02_0c /* 4 TSB ABS */ -#define deco16_2c m6502_2c /* 4 BIT ABS */ -#define deco16_4c m6502_4c /* 3 JMP ABS */ -#define deco16_6c m65c02_6c /* 5 JMP IND */ -#define deco16_8c m6502_8c /* 4 STY ABS */ -#define deco16_ac m6502_ac /* 4 LDY ABS */ -#define deco16_cc m6502_cc /* 4 CPY ABS */ -#define deco16_ec m6502_ec /* 4 CPX ABS */ - -#define deco16_1c m65c02_1c /* 4 TRB ABS */ -#define deco16_3c m65c02_3c /* 4 BIT ABX */ -OP(5c) { RD_DUM; ILL; } /* 2 ILL */ -#define deco16_7c m65c02_7c /* 6 JMP IAX */ -#define deco16_9c m65c02_9c /* 4 STZ ABS */ -#define deco16_bc m65c02_bc /* 4 LDY ABX */ -OP(dc) { RD_DUM; ILL; } /* 2 ILL */ -OP(fc) { RD_DUM; ILL; } /* 2 ILL */ - -#define deco16_0d m6502_0d /* 4 ORA ABS */ -#define deco16_2d m6502_2d /* 4 AND ABS */ -#define deco16_4d m6502_4d /* 4 EOR ABS */ -#define deco16_6d m6502_6d /* 4 ADC ABS */ -#define deco16_8d m6502_8d /* 4 STA ABS */ -#define deco16_ad m6502_ad /* 4 LDA ABS */ -#define deco16_cd m6502_cd /* 4 CMP ABS */ -#define deco16_ed m6502_ed /* 4 SBC ABS */ - -#define deco16_1d m6502_1d /* 4 ORA ABX */ -#define deco16_3d m6502_3d /* 4 AND ABX */ -#define deco16_5d m6502_5d /* 4 EOR ABX */ -#define deco16_7d m6502_7d /* 4 ADC ABX */ -#define deco16_9d m6502_9d /* 5 STA ABX */ -#define deco16_bd m6502_bd /* 4 LDA ABX */ -#define deco16_dd m6502_dd /* 4 CMP ABX */ -#define deco16_fd m6502_fd /* 4 SBC ABX */ - -#define deco16_0e m6502_0e /* 6 ASL ABS */ -#define deco16_2e m6502_2e /* 6 ROL ABS */ -#define deco16_4e m6502_4e /* 6 LSR ABS */ -#define deco16_6e m6502_6e /* 6 ROR ABS */ -#define deco16_8e m6502_8e /* 4 STX ABS */ -#define deco16_ae m6502_ae /* 4 LDX ABS */ -#define deco16_ce m6502_ce /* 6 DEC ABS */ -#define deco16_ee m6502_ee /* 6 INC ABS */ - -#define deco16_1e m6502_1e /* 7 ASL ABX */ -#define deco16_3e m6502_3e /* 7 ROL ABX */ -#define deco16_5e m6502_5e /* 7 LSR ABX */ -#define deco16_7e m6502_7e /* 7 ROR ABX */ -#define deco16_9e m65c02_9e /* 5 STZ ABX */ -#define deco16_be m6502_be /* 4 LDX ABY */ -#define deco16_de m6502_de /* 7 DEC ABX */ -#define deco16_fe m6502_fe /* 7 INC ABX */ - -OP(0f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR0 ZPG ?? */ -OP(2f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR2 ZPG ?? */ -OP(4f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR4 ZPG ?? */ -OP(6f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR6 ZPG ?? */ -OP(8f) { int tmp; cpustate->icount -= 1; RD_IMM; - if (DECO16_VERBOSE) - logerror("%04x: BANK (8F) %02x\n",PCW,tmp); - - cpustate->io->write_byte(0,tmp); - - //swap bank in/out -} /* */ -OP(af) { RD_DUM; ILL; } /* 2 ILL / 5 BBS2 ZPG ?? */ -OP(cf) { RD_DUM; ILL; } /* 2 ILL / 5 BBS4 ZPG ?? */ -OP(ef) { RD_DUM; ILL; } /* 2 ILL / 5 BBS6 ZPG ?? */ - -OP(1f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR1 ZPG ?? */ -OP(3f) { - int tmp; - - cpustate->icount -= 1; - RD_IMM; - - if (DECO16_VERBOSE) - logerror("%04x: OP3F %02x\n",PCW,tmp); -} -OP(5f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR5 ZPG ?? */ -OP(7f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR7 ZPG ?? */ -OP(9f) { RD_DUM; ILL; } /* 2 ILL / 5 BBS1 ZPG ?? */ -OP(bf) { RD_DUM; ILL; } /* 2 ILL / 5 BBS3 ZPG ?? */ -OP(df) { RD_DUM; ILL; } /* 2 ILL / 5 BBS5 ZPG ?? */ -OP(ff) { RD_DUM; ILL; } /* 2 ILL / 5 BBS7 ZPG ?? */ - -static void (*const insndeco16[0x100])(m6502_Regs *cpustate) = { - deco16_00,deco16_01,deco16_02,deco16_03,deco16_04,deco16_05,deco16_06,deco16_07, - deco16_08,deco16_09,deco16_0a,deco16_0b,deco16_0c,deco16_0d,deco16_0e,deco16_0f, - deco16_10,deco16_11,deco16_12,deco16_13,deco16_14,deco16_15,deco16_16,deco16_17, - deco16_18,deco16_19,deco16_1a,deco16_1b,deco16_1c,deco16_1d,deco16_1e,deco16_1f, - deco16_20,deco16_21,deco16_22,deco16_23,deco16_24,deco16_25,deco16_26,deco16_27, - deco16_28,deco16_29,deco16_2a,deco16_2b,deco16_2c,deco16_2d,deco16_2e,deco16_2f, - deco16_30,deco16_31,deco16_32,deco16_33,deco16_34,deco16_35,deco16_36,deco16_37, - deco16_38,deco16_39,deco16_3a,deco16_3b,deco16_3c,deco16_3d,deco16_3e,deco16_3f, - deco16_40,deco16_41,deco16_42,deco16_43,deco16_44,deco16_45,deco16_46,deco16_47, - deco16_48,deco16_49,deco16_4a,deco16_4b,deco16_4c,deco16_4d,deco16_4e,deco16_4f, - deco16_50,deco16_51,deco16_52,deco16_53,deco16_54,deco16_55,deco16_56,deco16_57, - deco16_58,deco16_59,deco16_5a,deco16_5b,deco16_5c,deco16_5d,deco16_5e,deco16_5f, - deco16_60,deco16_61,deco16_62,deco16_63,deco16_64,deco16_65,deco16_66,deco16_67, - deco16_68,deco16_69,deco16_6a,deco16_6b,deco16_6c,deco16_6d,deco16_6e,deco16_6f, - deco16_70,deco16_71,deco16_72,deco16_73,deco16_74,deco16_75,deco16_76,deco16_77, - deco16_78,deco16_79,deco16_7a,deco16_7b,deco16_7c,deco16_7d,deco16_7e,deco16_7f, - deco16_80,deco16_81,deco16_82,deco16_83,deco16_84,deco16_85,deco16_86,deco16_87, - deco16_88,deco16_89,deco16_8a,deco16_8b,deco16_8c,deco16_8d,deco16_8e,deco16_8f, - deco16_90,deco16_91,deco16_92,deco16_93,deco16_94,deco16_95,deco16_96,deco16_97, - deco16_98,deco16_99,deco16_9a,deco16_9b,deco16_9c,deco16_9d,deco16_9e,deco16_9f, - deco16_a0,deco16_a1,deco16_a2,deco16_a3,deco16_a4,deco16_a5,deco16_a6,deco16_a7, - deco16_a8,deco16_a9,deco16_aa,deco16_ab,deco16_ac,deco16_ad,deco16_ae,deco16_af, - deco16_b0,deco16_b1,deco16_b2,deco16_b3,deco16_b4,deco16_b5,deco16_b6,deco16_b7, - deco16_b8,deco16_b9,deco16_ba,deco16_bb,deco16_bc,deco16_bd,deco16_be,deco16_bf, - deco16_c0,deco16_c1,deco16_c2,deco16_c3,deco16_c4,deco16_c5,deco16_c6,deco16_c7, - deco16_c8,deco16_c9,deco16_ca,deco16_cb,deco16_cc,deco16_cd,deco16_ce,deco16_cf, - deco16_d0,deco16_d1,deco16_d2,deco16_d3,deco16_d4,deco16_d5,deco16_d6,deco16_d7, - deco16_d8,deco16_d9,deco16_da,deco16_db,deco16_dc,deco16_dd,deco16_de,deco16_df, - deco16_e0,deco16_e1,deco16_e2,deco16_e3,deco16_e4,deco16_e5,deco16_e6,deco16_e7, - deco16_e8,deco16_e9,deco16_ea,deco16_eb,deco16_ec,deco16_ed,deco16_ee,deco16_ef, - deco16_f0,deco16_f1,deco16_f2,deco16_f3,deco16_f4,deco16_f5,deco16_f6,deco16_f7, - deco16_f8,deco16_f9,deco16_fa,deco16_fb,deco16_fc,deco16_fd,deco16_fe,deco16_ff -}; diff --git a/src/emu/cpu/m6502/tn2a03.c b/src/emu/cpu/m6502/tn2a03.c deleted file mode 100644 index 34d6f1d52ae..00000000000 --- a/src/emu/cpu/m6502/tn2a03.c +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************** - * - * tbl2a03.c - * 2a03 opcode functions and function pointer table - * - * The 2a03 is a 6502 CPU that does not support the decimal mode - * of the ADC and SBC instructions, so all opcodes except ADC/SBC - * are simply mapped to the m6502 ones. - * - * Copyright Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - -/* - based on the nmos 6502 - - b flag handling might be changed, - although only nmos series b-flag handling is quite sure -*/ - - -#undef OP -#define OP(nn) INLINE void n2a03_##nn(m6502_Regs *cpustate) - -/***************************************************************************** - ***************************************************************************** - * - * overrides for 2a03 opcodes - * - ***************************************************************************** - ********** insn temp cycles rdmem opc wrmem **********/ -OP(61) { int tmp; RD_IDX; ADC_NES; } /* 6 ADC IDX */ -OP(e1) { int tmp; RD_IDX; SBC_NES; } /* 6 SBC IDX */ -OP(71) { int tmp; RD_IDY_P; ADC_NES; } /* 5 ADC IDY page penalty */ -OP(f1) { int tmp; RD_IDY_P; SBC_NES; } /* 5 SBC IDY page penalty */ -OP(63) { int tmp; RD_IDX; WB_EA; RRA_NES; WB_EA; } /* 7 RRA IDX */ -OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA_NES; WB_EA; } /* 7 RRA IDY */ -OP(e3) { int tmp; RD_IDX; WB_EA; ISB_NES; WB_EA; } /* 7 ISB IDX */ -OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB_NES; WB_EA; } /* 7 ISB IDY */ -OP(65) { int tmp; RD_ZPG; ADC_NES; } /* 3 ADC ZPG */ -OP(e5) { int tmp; RD_ZPG; SBC_NES; } /* 3 SBC ZPG */ -OP(75) { int tmp; RD_ZPX; ADC_NES; } /* 4 ADC ZPX */ -OP(f5) { int tmp; RD_ZPX; SBC_NES; } /* 4 SBC ZPX */ -OP(67) { int tmp; RD_ZPG; WB_EA; RRA_NES; WB_EA; } /* 5 RRA ZPG */ -OP(77) { int tmp; RD_ZPX; WB_EA; RRA_NES; WB_EA; } /* 6 RRA ZPX */ -OP(e7) { int tmp; RD_ZPG; WB_EA; ISB_NES; WB_EA; } /* 5 ISB ZPG */ -OP(f7) { int tmp; RD_ZPX; WB_EA; ISB_NES; WB_EA; } /* 6 ISB ZPX */ -OP(69) { int tmp; RD_IMM; ADC_NES; } /* 2 ADC IMM */ -OP(e9) { int tmp; RD_IMM; SBC_NES; } /* 2 SBC IMM */ -OP(79) { int tmp; RD_ABY_P; ADC_NES; } /* 4 ADC ABY page penalty */ -OP(f9) { int tmp; RD_ABY_P; SBC_NES; } /* 4 SBC ABY page penalty */ -OP(6b) { int tmp; RD_IMM; ARR_NES; WB_ACC; } /* 2 ARR IMM */ -OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA_NES; WB_EA; } /* 7 RRA ABY */ -OP(ab) { int tmp; RD_IMM; OAL_NES; } /* 2 OAL IMM */ -OP(eb) { int tmp; RD_IMM; SBC_NES; } /* 2 SBC IMM */ -OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB_NES; WB_EA; } /* 7 ISB ABY */ -OP(9c) { int tmp; EA_ABX_NP; SYH_NES; WB_EA; } /* 5 SYH ABX */ -OP(6d) { int tmp; RD_ABS; ADC_NES; } /* 4 ADC ABS */ -OP(ed) { int tmp; RD_ABS; SBC_NES; } /* 4 SBC ABS */ -OP(7d) { int tmp; RD_ABX_P; ADC_NES; } /* 4 ADC ABX page penalty */ -OP(fd) { int tmp; RD_ABX_P; SBC_NES; } /* 4 SBC ABX page penalty */ -OP(9e) { int tmp; EA_ABY_NP; SXH_NES; WB_EA; } /* 5 SXH ABY */ -OP(6f) { int tmp; RD_ABS; WB_EA; RRA_NES; WB_EA; } /* 6 RRA ABS */ -OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA_NES; WB_EA; } /* 7 RRA ABX */ -OP(ef) { int tmp; RD_ABS; WB_EA; ISB_NES; WB_EA; } /* 6 ISB ABS */ -OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB_NES; WB_EA; } /* 7 ISB ABX */ - - -static void (*const insn2a03[0x100])(m6502_Regs *cpustate) = { - m6502_00,m6502_01,m6502_02,m6502_03,m6502_04,m6502_05,m6502_06,m6502_07, - m6502_08,m6502_09,m6502_0a,m6502_0b,m6502_0c,m6502_0d,m6502_0e,m6502_0f, - m6502_10,m6502_11,m6502_12,m6502_13,m6502_14,m6502_15,m6502_16,m6502_17, - m6502_18,m6502_19,m6502_1a,m6502_1b,m6502_1c,m6502_1d,m6502_1e,m6502_1f, - m6502_20,m6502_21,m6502_22,m6502_23,m6502_24,m6502_25,m6502_26,m6502_27, - m6502_28,m6502_29,m6502_2a,m6502_2b,m6502_2c,m6502_2d,m6502_2e,m6502_2f, - m6502_30,m6502_31,m6502_32,m6502_33,m6502_34,m6502_35,m6502_36,m6502_37, - m6502_38,m6502_39,m6502_3a,m6502_3b,m6502_3c,m6502_3d,m6502_3e,m6502_3f, - m6502_40,m6502_41,m6502_42,m6502_43,m6502_44,m6502_45,m6502_46,m6502_47, - m6502_48,m6502_49,m6502_4a,m6502_4b,m6502_4c,m6502_4d,m6502_4e,m6502_4f, - m6502_50,m6502_51,m6502_52,m6502_53,m6502_54,m6502_55,m6502_56,m6502_57, - m6502_58,m6502_59,m6502_5a,m6502_5b,m6502_5c,m6502_5d,m6502_5e,m6502_5f, - m6502_60,n2a03_61,m6502_62,n2a03_63,m6502_64,n2a03_65,m6502_66,n2a03_67, - m6502_68,n2a03_69,m6502_6a,n2a03_6b,m6502_6c,n2a03_6d,m6502_6e,n2a03_6f, - m6502_70,n2a03_71,m6502_72,n2a03_73,m6502_74,n2a03_75,m6502_76,n2a03_77, - m6502_78,n2a03_79,m6502_7a,n2a03_7b,m6502_7c,n2a03_7d,m6502_7e,n2a03_7f, - m6502_80,m6502_81,m6502_82,m6502_83,m6502_84,m6502_85,m6502_86,m6502_87, - m6502_88,m6502_89,m6502_8a,m6502_8b,m6502_8c,m6502_8d,m6502_8e,m6502_8f, - m6502_90,m6502_91,m6502_92,m6502_93,m6502_94,m6502_95,m6502_96,m6502_97, - m6502_98,m6502_99,m6502_9a,m6502_9b,n2a03_9c,m6502_9d,n2a03_9e,m6502_9f, - m6502_a0,m6502_a1,m6502_a2,m6502_a3,m6502_a4,m6502_a5,m6502_a6,m6502_a7, - m6502_a8,m6502_a9,m6502_aa,n2a03_ab,m6502_ac,m6502_ad,m6502_ae,m6502_af, - m6502_b0,m6502_b1,m6502_b2,m6502_b3,m6502_b4,m6502_b5,m6502_b6,m6502_b7, - m6502_b8,m6502_b9,m6502_ba,m6502_bb,m6502_bc,m6502_bd,m6502_be,m6502_bf, - m6502_c0,m6502_c1,m6502_c2,m6502_c3,m6502_c4,m6502_c5,m6502_c6,m6502_c7, - m6502_c8,m6502_c9,m6502_ca,m6502_cb,m6502_cc,m6502_cd,m6502_ce,m6502_cf, - m6502_d0,m6502_d1,m6502_d2,m6502_d3,m6502_d4,m6502_d5,m6502_d6,m6502_d7, - m6502_d8,m6502_d9,m6502_da,m6502_db,m6502_dc,m6502_dd,m6502_de,m6502_df, - m6502_e0,n2a03_e1,m6502_e2,n2a03_e3,m6502_e4,n2a03_e5,m6502_e6,n2a03_e7, - m6502_e8,n2a03_e9,m6502_ea,n2a03_eb,m6502_ec,n2a03_ed,m6502_ee,n2a03_ef, - m6502_f0,n2a03_f1,m6502_f2,n2a03_f3,m6502_f4,n2a03_f5,m6502_f6,n2a03_f7, - m6502_f8,n2a03_f9,m6502_fa,n2a03_fb,m6502_fc,n2a03_fd,m6502_fe,n2a03_ff -}; diff --git a/src/emu/sound/nes_apu.c b/src/emu/sound/nes_apu.c index a5875faf521..e40aad5e4fb 100644 --- a/src/emu/sound/nes_apu.c +++ b/src/emu/sound/nes_apu.c @@ -46,7 +46,7 @@ #include "emu.h" #include "nes_apu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "nes_defs.h" @@ -371,7 +371,7 @@ static int8 apu_dpcm(nesapu_state *info, dpcm_t *chan) if (chan->regs[0] & 0x80) /* IRQ Generator */ { chan->irq_occurred = TRUE; - n2a03_irq(&info->APU.dpcm.memory->device()); + downcast(info->APU.dpcm.memory->device()).set_input_line(N2A03_IRQ_LINE, ASSERT_LINE); } break; } @@ -520,8 +520,10 @@ INLINE void apu_regwrite(nesapu_state *info,int address, uint8 value) /* DMC */ case APU_WRE0: info->APU.dpcm.regs[0] = value; - if (0 == (value & 0x80)) + if (0 == (value & 0x80)) { + downcast(info->APU.dpcm.memory->device()).set_input_line(N2A03_IRQ_LINE, CLEAR_LINE); info->APU.dpcm.irq_occurred = FALSE; + } break; case APU_WRE1: /* 7-bit DAC */ diff --git a/src/mame/audio/dkong.c b/src/mame/audio/dkong.c index 4614e970d23..629f63a336f 100644 --- a/src/mame/audio/dkong.c +++ b/src/mame/audio/dkong.c @@ -1,6 +1,6 @@ #include "emu.h" #include "cpu/mcs48/mcs48.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "sound/nes_apu.h" #include "sound/discrete.h" #include "machine/latch8.h" diff --git a/src/mame/drivers/4roses.c b/src/mame/drivers/4roses.c index 94048bd85eb..4daaffdc4b5 100644 --- a/src/mame/drivers/4roses.c +++ b/src/mame/drivers/4roses.c @@ -173,7 +173,7 @@ #define MASTER_CLOCK XTAL_16MHz #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "video/mc6845.h" #include "sound/ay8910.h" #include "machine/nvram.h" diff --git a/src/mame/drivers/allied.c b/src/mame/drivers/allied.c index 96f27d980a5..953772f3f05 100644 --- a/src/mame/drivers/allied.c +++ b/src/mame/drivers/allied.c @@ -7,7 +7,7 @@ ***************************************************************************/ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6504.h" class allied_state : public driver_device { diff --git a/src/mame/drivers/alvg.c b/src/mame/drivers/alvg.c index 46693b3d17d..d6f27defee6 100644 --- a/src/mame/drivers/alvg.c +++ b/src/mame/drivers/alvg.c @@ -1,6 +1,6 @@ #include "emu.h" -#include "cpu/m6502/m65ce02.h" +#include "cpu/m6502/m65c02.h" class alvg_state : public driver_device { diff --git a/src/mame/drivers/bwing.c b/src/mame/drivers/bwing.c index 9efdc9a75ae..f56db4f4692 100644 --- a/src/mame/drivers/bwing.c +++ b/src/mame/drivers/bwing.c @@ -23,7 +23,7 @@ Known issues: #include "emu.h" #include "cpu/m6809/m6809.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/deco16.h" #include "sound/ay8910.h" #include "sound/dac.h" #include "includes/bwing.h" diff --git a/src/mame/drivers/calomega.c b/src/mame/drivers/calomega.c index 68e056fbb27..41ab83c6edc 100644 --- a/src/mame/drivers/calomega.c +++ b/src/mame/drivers/calomega.c @@ -645,6 +645,7 @@ #include "emu.h" #include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "video/mc6845.h" #include "machine/6821pia.h" #include "machine/6850acia.h" diff --git a/src/mame/drivers/cham24.c b/src/mame/drivers/cham24.c index 85efaff2fad..99f9fd9e612 100644 --- a/src/mame/drivers/cham24.c +++ b/src/mame/drivers/cham24.c @@ -55,7 +55,7 @@ Notes: */ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "sound/dac.h" #include "sound/nes_apu.h" #include "video/ppu2c0x.h" diff --git a/src/mame/drivers/cmmb.c b/src/mame/drivers/cmmb.c index fdd13760d8a..62f52e544e0 100644 --- a/src/mame/drivers/cmmb.c +++ b/src/mame/drivers/cmmb.c @@ -45,7 +45,7 @@ OSC @ 72.576MHz ***************************************************************************/ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65sc02.h" class cmmb_state : public driver_device diff --git a/src/mame/drivers/exprraid.c b/src/mame/drivers/exprraid.c index 51283da0a0a..cff7f9538cf 100644 --- a/src/mame/drivers/exprraid.c +++ b/src/mame/drivers/exprraid.c @@ -204,6 +204,7 @@ Stephh's notes (based on the games M6502 code and some tests) : ***************************************************************************/ #include "emu.h" +#include "cpu/m6502/deco16.h" #include "cpu/m6502/m6502.h" #include "cpu/m6809/m6809.h" #include "sound/2203intf.h" diff --git a/src/mame/drivers/famibox.c b/src/mame/drivers/famibox.c index 49b04dd2220..968d8f1705d 100644 --- a/src/mame/drivers/famibox.c +++ b/src/mame/drivers/famibox.c @@ -59,7 +59,7 @@ Notes/ToDo: #include "emu.h" #include "video/ppu2c0x.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "imagedev/cartslot.h" #include "sound/nes_apu.h" #include "sound/dac.h" diff --git a/src/mame/drivers/funworld.c b/src/mame/drivers/funworld.c index 0aaa730179f..91216784987 100644 --- a/src/mame/drivers/funworld.c +++ b/src/mame/drivers/funworld.c @@ -810,7 +810,8 @@ #define MASTER_CLOCK XTAL_16MHz #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" +#include "cpu/m6502/m65sc02.h" #include "video/mc6845.h" #include "machine/6821pia.h" #include "sound/ay8910.h" diff --git a/src/mame/drivers/gts3.c b/src/mame/drivers/gts3.c index 012ee26236f..55371afd56c 100644 --- a/src/mame/drivers/gts3.c +++ b/src/mame/drivers/gts3.c @@ -4,7 +4,7 @@ #include "emu.h" -#include "cpu/m6502/m65ce02.h" +#include "cpu/m6502/m65c02.h" class gts3_state : public driver_device { diff --git a/src/mame/drivers/liberate.c b/src/mame/drivers/liberate.c index 3e9d6c56e7c..37ef089d761 100644 --- a/src/mame/drivers/liberate.c +++ b/src/mame/drivers/liberate.c @@ -15,6 +15,7 @@ *******************************************************************************/ #include "emu.h" +#include "cpu/m6502/deco16.h" #include "cpu/m6502/m6502.h" #include "sound/ay8910.h" #include "includes/liberate.h" diff --git a/src/mame/drivers/multigam.c b/src/mame/drivers/multigam.c index 68d4da62963..ea66979a6d6 100644 --- a/src/mame/drivers/multigam.c +++ b/src/mame/drivers/multigam.c @@ -66,7 +66,7 @@ PCB Layout */ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "sound/dac.h" #include "sound/nes_apu.h" #include "video/ppu2c0x.h" diff --git a/src/mame/drivers/playch10.c b/src/mame/drivers/playch10.c index be389c160ef..e566fa967ca 100644 --- a/src/mame/drivers/playch10.c +++ b/src/mame/drivers/playch10.c @@ -290,7 +290,7 @@ Notes & Todo: ***************************************************************************/ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "video/ppu2c0x.h" #include "cpu/z80/z80.h" #include "machine/rp5h01.h" diff --git a/src/mame/drivers/punchout.c b/src/mame/drivers/punchout.c index 56121af00a4..cc2e33b6c5d 100644 --- a/src/mame/drivers/punchout.c +++ b/src/mame/drivers/punchout.c @@ -111,7 +111,7 @@ DIP locations verified for: #include "emu.h" #include "cpu/z80/z80.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "sound/vlm5030.h" #include "sound/nes_apu.h" #include "machine/nvram.h" diff --git a/src/mame/drivers/rgum.c b/src/mame/drivers/rgum.c index 5833d97f528..b049a5a4392 100644 --- a/src/mame/drivers/rgum.c +++ b/src/mame/drivers/rgum.c @@ -13,7 +13,7 @@ The ppi at 3000-3003 seems to be a dual port communication thing with the z80. #include "emu.h" #include "cpu/z80/z80.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "video/mc6845.h" #include "machine/i8255.h" #include "sound/ay8910.h" diff --git a/src/mame/drivers/seta.c b/src/mame/drivers/seta.c index 457ecacf156..73065d85ce8 100644 --- a/src/mame/drivers/seta.c +++ b/src/mame/drivers/seta.c @@ -1357,7 +1357,7 @@ Note: on screen copyright is (c)1998 Coinmaster. #include "emu.h" #include "cpu/z80/z80.h" #include "cpu/m68000/m68000.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "includes/seta.h" #include "machine/6821pia.h" #include "machine/6850acia.h" diff --git a/src/mame/drivers/snookr10.c b/src/mame/drivers/snookr10.c index 214577ca64e..83d884e3cfc 100644 --- a/src/mame/drivers/snookr10.c +++ b/src/mame/drivers/snookr10.c @@ -362,7 +362,7 @@ #define MASTER_CLOCK XTAL_16MHz #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65sc02.h" #include "sound/okim6295.h" #include "snookr10.lh" #include "includes/snookr10.h" diff --git a/src/mame/drivers/tceptor.c b/src/mame/drivers/tceptor.c index dc81ac1b853..3b59c901e55 100644 --- a/src/mame/drivers/tceptor.c +++ b/src/mame/drivers/tceptor.c @@ -7,7 +7,7 @@ */ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "cpu/m6809/m6809.h" #include "cpu/m6800/m6800.h" #include "cpu/m68000/m68000.h" diff --git a/src/mame/drivers/thedeep.c b/src/mame/drivers/thedeep.c index 5073116f50c..779cd9394a0 100644 --- a/src/mame/drivers/thedeep.c +++ b/src/mame/drivers/thedeep.c @@ -26,7 +26,7 @@ Notes: #include "emu.h" #include "cpu/z80/z80.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "cpu/mcs51/mcs51.h" #include "includes/thedeep.h" #include "sound/2203intf.h" diff --git a/src/mame/drivers/vsnes.c b/src/mame/drivers/vsnes.c index 0da552ffe53..53acf7dc1f8 100644 --- a/src/mame/drivers/vsnes.c +++ b/src/mame/drivers/vsnes.c @@ -138,7 +138,7 @@ Changes: ***************************************************************************/ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "rendlay.h" #include "video/ppu2c0x.h" #include "machine/rp5h01.h" diff --git a/src/mame/video/liberate.c b/src/mame/video/liberate.c index 8374dc00c71..0daa5b509ee 100644 --- a/src/mame/video/liberate.c +++ b/src/mame/video/liberate.c @@ -10,6 +10,7 @@ *******************************************************************************/ #include "emu.h" +#include "cpu/m6502/deco16.h" #include "cpu/m6502/m6502.h" #include "includes/liberate.h" diff --git a/src/mess/drivers/apple2.c b/src/mess/drivers/apple2.c index 0be7ae17609..5259f92a9ea 100644 --- a/src/mess/drivers/apple2.c +++ b/src/mess/drivers/apple2.c @@ -183,6 +183,7 @@ Apple 3.5 and Apple 5.25 drives - up to three devices #include "emu.h" #include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "cpu/z80/z80.h" #include "imagedev/flopdrv.h" #include "imagedev/cassette.h" diff --git a/src/mess/drivers/apple3.c b/src/mess/drivers/apple3.c index 32bc648c149..1175bf3fe68 100644 --- a/src/mess/drivers/apple3.c +++ b/src/mess/drivers/apple3.c @@ -34,6 +34,7 @@ ADDRESS_MAP_END /* the Apple /// does some weird tricks whereby it monitors the SYNC pin * on the CPU to check for indexed instructions and directs them to * different memory locations */ +#if 0 static const m6502_interface apple3_m6502_interface = { DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_read), /* read_indexed_func */ @@ -43,6 +44,7 @@ static const m6502_interface apple3_m6502_interface = 0x00, 0x00 }; +#endif static const floppy_interface apple3_floppy_interface = { @@ -70,7 +72,7 @@ static MACHINE_CONFIG_START( apple3, apple3_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", M6502, 2000000) /* 2 MHz */ MCFG_CPU_PROGRAM_MAP(apple3_map) - MCFG_CPU_CONFIG( apple3_m6502_interface ) +// MCFG_CPU_CONFIG( apple3_m6502_interface ) MCFG_CPU_PERIODIC_INT_DRIVER(apple3_state, apple3_interrupt, 192) MCFG_QUANTUM_TIME(attotime::from_hz(60)) diff --git a/src/mess/drivers/bbc.c b/src/mess/drivers/bbc.c index c5dc1c16142..2e2520dd97e 100644 --- a/src/mess/drivers/bbc.c +++ b/src/mess/drivers/bbc.c @@ -12,6 +12,7 @@ #include "emu.h" #include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65sc02.h" #include "machine/6522via.h" #include "machine/econet.h" #include "machine/e01.h" diff --git a/src/mess/drivers/c128.c b/src/mess/drivers/c128.c index 223c81223b5..d3b872d692e 100644 --- a/src/mess/drivers/c128.c +++ b/src/mess/drivers/c128.c @@ -1131,16 +1131,6 @@ WRITE8_MEMBER( c128_state::cpu_w ) m_cassette->motor_w(BIT(data, 5)); } -static M6510_INTERFACE( cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(c128_state, cpu_r), - DEVCB_DRIVER_MEMBER(c128_state, cpu_w), - 0x07, - 0x20 -}; - //------------------------------------------------- // CBM_IEC_INTERFACE( cbm_iec_intf ) @@ -1386,8 +1376,9 @@ static MACHINE_CONFIG_START( ntsc, c128_state ) MCFG_QUANTUM_PERFECT_CPU(Z80A_TAG) MCFG_CPU_ADD(M8502_TAG, M8502, VIC6567_CLOCK) + MCFG_M8502_PORT_CALLBACKS(READ8(c128_state, cpu_r), WRITE8(c128_state, cpu_w)) + MCFG_M8502_PORT_PULLS(0x07, 0x20) MCFG_CPU_PROGRAM_MAP(m8502_mem) - MCFG_CPU_CONFIG(cpu_intf) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, frame_interrupt) MCFG_QUANTUM_PERFECT_CPU(M8502_TAG) @@ -1491,8 +1482,9 @@ static MACHINE_CONFIG_START( pal, c128_state ) MCFG_QUANTUM_PERFECT_CPU(Z80A_TAG) MCFG_CPU_ADD(M8502_TAG, M8502, VIC6569_CLOCK) + MCFG_M8502_PORT_CALLBACKS(READ8(c128_state, cpu_r), WRITE8(c128_state, cpu_w)) + MCFG_M8502_PORT_PULLS(0x07, 0x20) MCFG_CPU_PROGRAM_MAP(m8502_mem) - MCFG_CPU_CONFIG(cpu_intf) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, frame_interrupt) MCFG_QUANTUM_PERFECT_CPU(M8502_TAG) diff --git a/src/mess/drivers/c64.c b/src/mess/drivers/c64.c index 39657f56837..314280561c2 100644 --- a/src/mess/drivers/c64.c +++ b/src/mess/drivers/c64.c @@ -713,17 +713,6 @@ WRITE8_MEMBER( c64_state::cpu_w ) m_cassette->motor_w(BIT(data, 5)); } -static M6510_INTERFACE( cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(c64_state, cpu_r), - DEVCB_DRIVER_MEMBER(c64_state, cpu_w), - 0x17, - 0x20 -}; - - //------------------------------------------------- // M6510_INTERFACE( sx64_cpu_intf ) //------------------------------------------------- @@ -767,17 +756,6 @@ WRITE8_MEMBER( sx64_state::cpu_w ) m_charen = BIT(data, 2); } -static M6510_INTERFACE( sx64_cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(sx64_state, cpu_r), - DEVCB_DRIVER_MEMBER(sx64_state, cpu_w), - 0x07, - 0x00 -}; - - //------------------------------------------------- // M6510_INTERFACE( c64gs_cpu_intf ) //------------------------------------------------- @@ -821,17 +799,6 @@ WRITE8_MEMBER( c64gs_state::cpu_w ) m_charen = BIT(data, 2); } -static M6510_INTERFACE( c64gs_cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(c64gs_state, cpu_r), - DEVCB_DRIVER_MEMBER(c64gs_state, cpu_w), - 0x07, - 0x00 -}; - - //------------------------------------------------- // PET_DATASSETTE_PORT_INTERFACE( datassette_intf ) //------------------------------------------------- @@ -1042,7 +1009,8 @@ static MACHINE_CONFIG_START( ntsc, c64_state ) // basic hardware MCFG_CPU_ADD(M6510_TAG, M6510, VIC6567_CLOCK) MCFG_CPU_PROGRAM_MAP(c64_mem) - MCFG_CPU_CONFIG(cpu_intf) + MCFG_M6510_PORT_CALLBACKS(READ8(c64_state, cpu_r), WRITE8(c64_state, cpu_w)) + MCFG_M6510_PORT_PULLS(0x17, 0xc8) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, c64_state, frame_interrupt) MCFG_QUANTUM_PERFECT_CPU(M6510_TAG) @@ -1101,7 +1069,8 @@ static MACHINE_CONFIG_START( ntsc_sx, sx64_state ) // basic hardware MCFG_CPU_MODIFY(M6510_TAG) - MCFG_CPU_CONFIG(sx64_cpu_intf) + MCFG_M6510_PORT_CALLBACKS(READ8(sx64_state, cpu_r), WRITE8(sx64_state, cpu_w)) + MCFG_M6510_PORT_PULLS(0x07, 0xc0) // devices MCFG_DEVICE_REMOVE("iec8") @@ -1141,7 +1110,8 @@ static MACHINE_CONFIG_START( pal, c64_state ) // basic hardware MCFG_CPU_ADD(M6510_TAG, M6510, VIC6569_CLOCK) MCFG_CPU_PROGRAM_MAP(c64_mem) - MCFG_CPU_CONFIG(cpu_intf) + MCFG_M6510_PORT_CALLBACKS(READ8(c64_state, cpu_r), WRITE8(c64_state, cpu_w)) + MCFG_M6510_PORT_PULLS(0x17, 0xc8) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, c64_state, frame_interrupt) MCFG_QUANTUM_PERFECT_CPU(M6510_TAG) @@ -1191,7 +1161,8 @@ static MACHINE_CONFIG_START( pal_sx, sx64_state ) // basic hardware MCFG_CPU_MODIFY(M6510_TAG) - MCFG_CPU_CONFIG(sx64_cpu_intf) + MCFG_M6510_PORT_CALLBACKS(READ8(sx64_state, cpu_r), WRITE8(sx64_state, cpu_w)) + MCFG_M6510_PORT_PULLS(0x07, 0xc0) // devices MCFG_DEVICE_REMOVE("iec8") @@ -1218,7 +1189,9 @@ static MACHINE_CONFIG_START( pal_gs, c64gs_state ) // basic hardware MCFG_CPU_ADD(M6510_TAG, M6510, VIC6569_CLOCK) MCFG_CPU_PROGRAM_MAP(c64_mem) - MCFG_CPU_CONFIG(c64gs_cpu_intf) + MCFG_M6510_PORT_CALLBACKS(READ8(c64gs_state, cpu_r), WRITE8(c64gs_state, cpu_w)) + MCFG_M6510_PORT_PULLS(0x07, 0xc0) + MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, c64_state, frame_interrupt) MCFG_QUANTUM_PERFECT_CPU(M6510_TAG) diff --git a/src/mess/drivers/clcd.c b/src/mess/drivers/clcd.c index 120d6e0c734..d4e1bb9fa17 100644 --- a/src/mess/drivers/clcd.c +++ b/src/mess/drivers/clcd.c @@ -10,7 +10,7 @@ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "machine/6522via.h" #include "machine/6551acia.h" #include "rendlay.h" @@ -253,7 +253,7 @@ static const via6522_interface via0_intf = DEVCB_NULL,//DEVCB_DRIVER_LINE_MEMBER(clcd_state, via0_ca2_w), // CASS MOTOR DEVCB_NULL, - DEVCB_CPU_INPUT_LINE("maincpu", M6502_IRQ_LINE) + DEVCB_CPU_INPUT_LINE("maincpu", M65C02_IRQ_LINE) }; static const via6522_interface via1_intf = diff --git a/src/mess/drivers/lisa.c b/src/mess/drivers/lisa.c index 7d8cf98c323..8814a0901e1 100644 --- a/src/mess/drivers/lisa.c +++ b/src/mess/drivers/lisa.c @@ -10,7 +10,7 @@ #include "emu.h" #include "cpu/m68000/m68000.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6504.h" #include "cpu/cop400/cop400.h" #include "includes/lisa.h" #include "devices/sonydriv.h" diff --git a/src/mess/drivers/lynx.c b/src/mess/drivers/lynx.c index 87680587fcb..64304b5252c 100644 --- a/src/mess/drivers/lynx.c +++ b/src/mess/drivers/lynx.c @@ -7,7 +7,7 @@ ******************************************************************************/ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65sc02.h" #include "includes/lynx.h" #include "imagedev/snapquik.h" diff --git a/src/mess/drivers/mephisto.c b/src/mess/drivers/mephisto.c index 0086de31144..a45113fcf22 100644 --- a/src/mess/drivers/mephisto.c +++ b/src/mess/drivers/mephisto.c @@ -61,7 +61,7 @@ Mephisto 4 Turbo Kit 18mhz - (mm4tk) #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "sound/beep.h" //#include "mephisto.lh" @@ -77,7 +77,7 @@ public: m_beep(*this, BEEPER_TAG) { } - required_device m_maincpu; + required_device m_maincpu; required_device m_beep; DECLARE_WRITE8_MEMBER(write_lcd); DECLARE_WRITE8_MEMBER(mephisto_NMI); @@ -351,8 +351,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(mephisto_state::update_nmi_r5) TIMER_DEVICE_CALLBACK_MEMBER(mephisto_state::update_irq)//only mm2 { - machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, ASSERT_LINE); - machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, CLEAR_LINE); + // That will not work + machine().device("maincpu")->execute().set_input_line(M65C02_IRQ_LINE, ASSERT_LINE); + machine().device("maincpu")->execute().set_input_line(M65C02_IRQ_LINE, CLEAR_LINE); beep_set_state(m_beep, m_led_status&64?1:0); } diff --git a/src/mess/drivers/mmodular.c b/src/mess/drivers/mmodular.c index 6786e97a5c8..f0eeb9a32b6 100644 --- a/src/mess/drivers/mmodular.c +++ b/src/mess/drivers/mmodular.c @@ -87,7 +87,7 @@ Bit 5+6 LED 1-8 enable #include "emu.h" #include "cpu/m68000/m68000.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "cpu/arm/arm.h" #include "sound/beep.h" //#include "machine/6551acia.h" @@ -813,9 +813,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(polgar_state::cause_nmi) TIMER_DEVICE_CALLBACK_MEMBER(polgar_state::cause_M6502_irq) { - machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, ASSERT_LINE); - machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, CLEAR_LINE); - + // That will not work + machine().device("maincpu")->execute().set_input_line(M65C02_IRQ_LINE, ASSERT_LINE); + machine().device("maincpu")->execute().set_input_line(M65C02_IRQ_LINE, CLEAR_LINE); } diff --git a/src/mess/drivers/nes.c b/src/mess/drivers/nes.c index edbec655ce3..420ca17b4bb 100644 --- a/src/mess/drivers/nes.c +++ b/src/mess/drivers/nes.c @@ -14,7 +14,7 @@ #include "video/ppu2c0x.h" #include "includes/nes.h" //#include "includes/nes_mmc.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/n2a03.h" #include "imagedev/cartslot.h" #include "sound/nes_apu.h" #include "imagedev/flopdrv.h" diff --git a/src/mess/drivers/plus4.c b/src/mess/drivers/plus4.c index 5e85aa4f4c3..f09c05d5f5e 100644 --- a/src/mess/drivers/plus4.c +++ b/src/mess/drivers/plus4.c @@ -542,26 +542,6 @@ WRITE8_MEMBER( plus4_state::cpu_w ) m_cassette->write(!BIT(data, 1)); } -static M6510_INTERFACE( cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(plus4_state, cpu_r), - DEVCB_DRIVER_MEMBER(plus4_state, cpu_w), - 0x00, - 0xc0 -}; - -static M6510_INTERFACE( c16_cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(plus4_state, c16_cpu_r), - DEVCB_DRIVER_MEMBER(plus4_state, cpu_w), - 0x00, - 0xc0 -}; - //------------------------------------------------- // ted7360_interface ted_intf //------------------------------------------------- @@ -911,7 +891,8 @@ static MACHINE_CONFIG_START( ntsc, plus4_state ) // basic machine hardware MCFG_CPU_ADD(MOS7501_TAG, M7501, XTAL_14_31818MHz/16) MCFG_CPU_PROGRAM_MAP(plus4_mem) - MCFG_CPU_CONFIG(cpu_intf) + MCFG_M7501_PORT_CALLBACKS(READ8(plus4_state, cpu_r), WRITE8(plus4_state, cpu_w)) + MCFG_M7501_PORT_PULLS(0x00, 0xc0) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, plus4_state, c16_frame_interrupt) MCFG_CPU_PERIODIC_INT_DRIVER(plus4_state, c16_raster_interrupt, TED7360_HRETRACERATE) MCFG_QUANTUM_TIME(attotime::from_hz(60)) @@ -950,7 +931,8 @@ static MACHINE_CONFIG_START( pal, plus4_state ) // basic machine hardware MCFG_CPU_ADD(MOS7501_TAG, M7501, XTAL_17_73447MHz/20) MCFG_CPU_PROGRAM_MAP(plus4_mem) - MCFG_CPU_CONFIG(cpu_intf) + MCFG_M7501_PORT_CALLBACKS(READ8(plus4_state, cpu_r), WRITE8(plus4_state, cpu_w)) + MCFG_M7501_PORT_PULLS(0x00, 0xc0) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, plus4_state, c16_frame_interrupt) MCFG_CPU_PERIODIC_INT_DRIVER(plus4_state, c16_raster_interrupt, TED7360_HRETRACERATE) MCFG_QUANTUM_TIME(attotime::from_hz(60)) @@ -987,7 +969,8 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( c16n, ntsc ) MCFG_CPU_MODIFY(MOS7501_TAG) - MCFG_CPU_CONFIG(c16_cpu_intf) + MCFG_M7501_PORT_CALLBACKS(READ8(plus4_state, c16_cpu_r), WRITE8(plus4_state, cpu_w)) + MCFG_M7501_PORT_PULLS(0x00, 0xc0) MCFG_DEVICE_REMOVE(MOS6551_TAG) MCFG_DEVICE_REMOVE(MOS6529_USER_TAG) @@ -1008,7 +991,8 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( c16p, pal ) MCFG_CPU_MODIFY(MOS7501_TAG) - MCFG_CPU_CONFIG(c16_cpu_intf) + MCFG_M7501_PORT_CALLBACKS(READ8(plus4_state, c16_cpu_r), WRITE8(plus4_state, cpu_w)) + MCFG_M7501_PORT_PULLS(0x00, 0xc0) MCFG_DEVICE_REMOVE(MOS6551_TAG) MCFG_DEVICE_REMOVE(MOS6529_USER_TAG) diff --git a/src/mess/drivers/sbc6510.c b/src/mess/drivers/sbc6510.c index 1e1bba7dc86..996e95b02fe 100644 --- a/src/mess/drivers/sbc6510.c +++ b/src/mess/drivers/sbc6510.c @@ -49,7 +49,7 @@ ToDo: ****************************************************************************/ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6510.h" #include "machine/6526cia.h" #include "sound/ay8910.h" #include "machine/terminal.h" @@ -198,16 +198,6 @@ void sbc6510_state::machine_reset() { } -static M6510_INTERFACE( sbc6510_m6510_interface ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_NULL, - DEVCB_NULL, - 0x00, - 0x00 -}; - READ8_MEMBER( sbc6510_state::psg_a_r ) { return 0xff; @@ -250,7 +240,7 @@ WRITE8_MEMBER( sbc6510_state::key_w ) const legacy_mos6526_interface cia_intf = { - DEVCB_CPU_INPUT_LINE("maincpu", M6502_IRQ_LINE), // irq + DEVCB_CPU_INPUT_LINE("maincpu", M6510_IRQ_LINE), // irq DEVCB_NULL, // pc (timer related) not connected DEVCB_NULL, // cnt (serial related) not connected DEVCB_NULL, // sp (serial related) not connected @@ -263,7 +253,6 @@ const legacy_mos6526_interface cia_intf = static MACHINE_CONFIG_START( sbc6510, sbc6510_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu",M6510, XTAL_1MHz) - MCFG_CPU_CONFIG( sbc6510_m6510_interface ) MCFG_CPU_PROGRAM_MAP(sbc6510_mem) diff --git a/src/mess/drivers/svision.c b/src/mess/drivers/svision.c index 51cfffbe875..19c8b330a04 100644 --- a/src/mess/drivers/svision.c +++ b/src/mess/drivers/svision.c @@ -6,7 +6,7 @@ #include #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "includes/svision.h" #include "imagedev/cartslot.h" @@ -61,7 +61,7 @@ void svision_irq(running_machine &machine) int irq = state->m_svision.timer_shot && (state->BANK & 2); irq = irq || (*state->m_dma_finished && (state->BANK & 4)); - machine.device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE); + machine.device("maincpu")->execute().set_input_line(M65C02_IRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE); } TIMER_CALLBACK_MEMBER(svision_state::svision_timer) diff --git a/src/mess/drivers/vic10.c b/src/mess/drivers/vic10.c index 681987cd3da..c9c012b94b7 100644 --- a/src/mess/drivers/vic10.c +++ b/src/mess/drivers/vic10.c @@ -409,17 +409,6 @@ WRITE8_MEMBER( vic10_state::cpu_w ) m_cassette->motor_w(BIT(data, 5)); } -static M6510_INTERFACE( cpu_intf ) -{ - DEVCB_NULL, - DEVCB_NULL, - DEVCB_DRIVER_MEMBER(vic10_state, cpu_r), - DEVCB_DRIVER_MEMBER(vic10_state, cpu_w), - 0x10, - 0x20 -}; - - //------------------------------------------------- // PET_DATASSETTE_PORT_INTERFACE( datassette_intf ) //------------------------------------------------- @@ -505,7 +494,8 @@ static MACHINE_CONFIG_START( vic10, vic10_state ) // basic hardware MCFG_CPU_ADD(M6510_TAG, M6510, VIC6566_CLOCK) MCFG_CPU_PROGRAM_MAP(vic10_mem) - MCFG_CPU_CONFIG(cpu_intf) + MCFG_M6510_PORT_CALLBACKS(READ8(vic10_state, cpu_r), WRITE8(vic10_state, cpu_w)) + MCFG_M6510_PORT_PULLS(0x10, 0x20) MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, vic10_state, vic10_frame_interrupt) MCFG_QUANTUM_PERFECT_CPU(M6510_TAG) diff --git a/src/mess/includes/c128.h b/src/mess/includes/c128.h index 67845e357af..62fded59947 100644 --- a/src/mess/includes/c128.h +++ b/src/mess/includes/c128.h @@ -6,6 +6,8 @@ #include "emu.h" #include "formats/cbm_snqk.h" #include "includes/cbm.h" +#include "cpu/m6502/m8502.h" +#include "machine/6526cia.h" #include "machine/c64exp.h" #include "machine/c64user.h" #include "machine/cbmiec.h" @@ -88,7 +90,7 @@ public: { } required_device m_maincpu; - required_device m_subcpu; + required_device m_subcpu; required_device m_mmu; required_device m_pla; required_device m_vdc; diff --git a/src/mess/includes/c64.h b/src/mess/includes/c64.h index 89704eea757..1122785c039 100644 --- a/src/mess/includes/c64.h +++ b/src/mess/includes/c64.h @@ -4,6 +4,7 @@ #define __C64__ #include "emu.h" +#include "cpu/m6502/m6510.h" #include "formats/cbm_snqk.h" #include "includes/cbm.h" #include "machine/c64exp.h" @@ -63,7 +64,7 @@ public: m_iec_srq(1) { } - required_device m_maincpu; + required_device m_maincpu; required_device m_pla; required_device m_vic; required_device m_sid; diff --git a/src/mess/includes/plus4.h b/src/mess/includes/plus4.h index 966b00b8ce6..a162e7ccf4e 100644 --- a/src/mess/includes/plus4.h +++ b/src/mess/includes/plus4.h @@ -4,6 +4,7 @@ #define __PLUS4__ #include "emu.h" +#include "cpu/m6502/m7501.h" #include "formats/cbm_snqk.h" #include "includes/cbm.h" #include "audio/t6721.h" @@ -52,7 +53,7 @@ public: m_exp_irq(CLEAR_LINE) { } - required_device m_maincpu; + required_device m_maincpu; required_device m_pla; required_device m_ted; optional_device m_acia; diff --git a/src/mess/includes/vic10.h b/src/mess/includes/vic10.h index ed6dfaa7beb..c45a52f2479 100644 --- a/src/mess/includes/vic10.h +++ b/src/mess/includes/vic10.h @@ -5,6 +5,7 @@ #include "emu.h" +#include "cpu/m6502/m6510.h" #include "includes/cbm.h" #include "machine/cbmipt.h" #include "machine/mos6526.h" @@ -44,7 +45,7 @@ public: m_exp_irq(CLEAR_LINE) { } - required_device m_maincpu; + required_device m_maincpu; required_device m_vic; required_device m_sid; required_device m_cia; diff --git a/src/mess/includes/vic20.h b/src/mess/includes/vic20.h index d4009b8c236..0e284e7c5ce 100644 --- a/src/mess/includes/vic20.h +++ b/src/mess/includes/vic20.h @@ -7,7 +7,7 @@ #include "emu.h" #include "includes/cbm.h" #include "formats/cbm_snqk.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6510.h" #include "imagedev/cartslot.h" #include "machine/6522via.h" #include "machine/cbmiec.h" @@ -48,7 +48,7 @@ public: m_color_ram(*this, "color_ram") { } - required_device m_maincpu; + required_device m_maincpu; required_device m_via0; required_device m_via1; required_device m_vic; diff --git a/src/mess/machine/c1541.h b/src/mess/machine/c1541.h index b47fdcd81be..6f5f0258b38 100644 --- a/src/mess/machine/c1541.h +++ b/src/mess/machine/c1541.h @@ -100,7 +100,7 @@ protected: inline void set_iec_data(); - required_device m_maincpu; + required_device m_maincpu; required_device m_via0; required_device m_via1; required_device m_ga; diff --git a/src/mess/machine/c1551.c b/src/mess/machine/c1551.c index c63a3399a5d..34aa8b93105 100644 --- a/src/mess/machine/c1551.c +++ b/src/mess/machine/c1551.c @@ -131,17 +131,6 @@ WRITE8_MEMBER( c1551_device::port_w ) m_ga->ds_w((data >> 5) & 0x03); } -static M6510_INTERFACE( cpu_intf ) -{ - DEVCB_NULL, // read_indexed_func - DEVCB_NULL, // write_indexed_func - DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, c1551_device, port_r), - DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, c1551_device, port_w), - 0x00, - 0x00 -}; - - //------------------------------------------------- // tpi6525_interface tpi0_intf //------------------------------------------------- @@ -408,7 +397,7 @@ static PLUS4_EXPANSION_INTERFACE( expansion_intf ) static MACHINE_CONFIG_FRAGMENT( c1551 ) MCFG_CPU_ADD(M6510T_TAG, M6510T, XTAL_16MHz/8) MCFG_CPU_PROGRAM_MAP(c1551_mem) - MCFG_CPU_CONFIG(cpu_intf) + MCFG_M6510T_PORT_CALLBACKS(READ8(c1551_device, port_r), WRITE8(c1551_device, port_w)) MCFG_QUANTUM_PERFECT_CPU(M6510T_TAG) MCFG_PLS100_ADD(PLA_TAG) diff --git a/src/mess/machine/c1551.h b/src/mess/machine/c1551.h index 7c8562c7171..89273113235 100644 --- a/src/mess/machine/c1551.h +++ b/src/mess/machine/c1551.h @@ -14,7 +14,7 @@ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6510t.h" #include "imagedev/flopdrv.h" #include "formats/d64_dsk.h" #include "formats/g64_dsk.h" @@ -84,7 +84,7 @@ protected: private: bool tpi1_selected(offs_t offset); - required_device m_maincpu; + required_device m_maincpu; required_device m_tpi0; required_device m_tpi1; required_device m_ga; diff --git a/src/mess/machine/c2040.h b/src/mess/machine/c2040.h index ed09107a62f..05aa396798f 100644 --- a/src/mess/machine/c2040.h +++ b/src/mess/machine/c2040.h @@ -15,6 +15,7 @@ #include "emu.h" #include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6504.h" #include "imagedev/flopdrv.h" #include "formats/d64_dsk.h" #include "formats/g64_dsk.h" @@ -97,8 +98,8 @@ protected: inline void mpi_step_motor(int unit, int stp); inline void initialize(int drives); - required_device m_maincpu; - required_device m_fdccpu; + required_device m_maincpu; + required_device m_fdccpu; required_device m_riot0; required_device m_riot1; required_device m_miot; diff --git a/src/mess/machine/c64.c b/src/mess/machine/c64.c index 42d5d4eff43..2f214417f37 100644 --- a/src/mess/machine/c64.c +++ b/src/mess/machine/c64.c @@ -15,7 +15,7 @@ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m6510.h" #include "cpu/z80/z80.h" #include "sound/sid6581.h" #include "machine/6526cia.h" @@ -159,7 +159,7 @@ static void c64_bankswitch( running_machine &machine, int reset ) legacy_c64_state *state = machine.driver_data(); int loram, hiram, charen; int ultimax_mode = 0; - int data = m6510_get_port(machine.device("maincpu")) & 0x07; + int data = machine.device("maincpu")->get_port() & 0x07; /* Are we in Ultimax mode? */ if (!state->m_game && state->m_exrom) diff --git a/src/mess/machine/c65.c b/src/mess/machine/c65.c index 4dd22cf8682..e3bbf3584c1 100644 --- a/src/mess/machine/c65.c +++ b/src/mess/machine/c65.c @@ -102,8 +102,8 @@ static void c65_irq( running_machine &machine, int level ) c65_state *state = machine.driver_data(); if (level != state->m_old_level) { - DBG_LOG(machine, 3, "mos6510", ("irq %s\n", level ? "start" : "end")); - machine.device("maincpu")->execute().set_input_line(M6510_IRQ_LINE, level); + DBG_LOG(machine, 3, "mos4510", ("irq %s\n", level ? "start" : "end")); + machine.device("maincpu")->execute().set_input_line(M4510_IRQ_LINE, level); state->m_old_level = level; } } @@ -837,7 +837,7 @@ void c65_bankswitch( running_machine &machine ) c65_state *state = machine.driver_data(); int data, loram, hiram, charen; - data = m4510_get_port(machine.device("maincpu")); + data = 0x00; // machine.device("maincpu")->get_port(); if (data == state->m_old_data) return; diff --git a/src/mess/machine/e01.h b/src/mess/machine/e01.h index ccb0101f630..4345db36330 100644 --- a/src/mess/machine/e01.h +++ b/src/mess/machine/e01.h @@ -13,7 +13,7 @@ #define __E01__ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "imagedev/flopdrv.h" #include "machine/6522via.h" #include "machine/ctronics.h" @@ -79,7 +79,7 @@ protected: // device_econet_interface overrides virtual void econet_clk(int state); - required_device m_maincpu; + required_device m_maincpu; required_device m_fdc; required_device m_adlc; required_device m_rtc; diff --git a/src/mess/machine/fd2000.h b/src/mess/machine/fd2000.h index 89738126739..54c5a91a03c 100644 --- a/src/mess/machine/fd2000.h +++ b/src/mess/machine/fd2000.h @@ -15,7 +15,7 @@ #define ADDRESS_MAP_MODERN #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "imagedev/flopdrv.h" #include "formats/mfi_dsk.h" #include "machine/6522via.h" @@ -62,7 +62,7 @@ protected: void cbm_iec_data(int state); void cbm_iec_reset(int state); - required_device m_maincpu; + required_device m_maincpu; }; diff --git a/src/mess/machine/isa_finalchs.c b/src/mess/machine/isa_finalchs.c index d17e09fb772..d57d057316a 100644 --- a/src/mess/machine/isa_finalchs.c +++ b/src/mess/machine/isa_finalchs.c @@ -9,7 +9,7 @@ #include "emu.h" #include "isa_finalchs.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" static UINT8 FCH_latch_data = 0; diff --git a/src/mess/machine/lynx.c b/src/mess/machine/lynx.c index c94d1b8ea53..ad922295d1a 100644 --- a/src/mess/machine/lynx.c +++ b/src/mess/machine/lynx.c @@ -4,7 +4,7 @@ #include "emu.h" #include "includes/lynx.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65sc02.h" #include "imagedev/cartslot.h" diff --git a/src/mess/machine/serialbox.h b/src/mess/machine/serialbox.h index 58c3c38ccc0..73cb684506f 100644 --- a/src/mess/machine/serialbox.h +++ b/src/mess/machine/serialbox.h @@ -14,7 +14,7 @@ #include "emu.h" -#include "cpu/m6502/m6502.h" +#include "cpu/m6502/m65c02.h" #include "machine/cbmiec.h" @@ -57,7 +57,7 @@ protected: void cbm_iec_reset(int state); private: - required_device m_maincpu; + required_device m_maincpu; }; diff --git a/src/tools/unidasm.c b/src/tools/unidasm.c index df9ec912e8f..2f78c8fc5dd 100644 --- a/src/tools/unidasm.c +++ b/src/tools/unidasm.c @@ -125,13 +125,6 @@ CPU_DISASSEMBLE( konami ); CPU_DISASSEMBLE( lh5801 ); CPU_DISASSEMBLE( lr35902 ); CPU_DISASSEMBLE( m37710_generic ); -CPU_DISASSEMBLE( m6502 ); -CPU_DISASSEMBLE( m65sc02 ); -CPU_DISASSEMBLE( m65c02 ); -CPU_DISASSEMBLE( m65ce02 ); -CPU_DISASSEMBLE( m6510 ); -CPU_DISASSEMBLE( deco16 ); -CPU_DISASSEMBLE( m4510 ); CPU_DISASSEMBLE( m6800 ); CPU_DISASSEMBLE( m6801 ); CPU_DISASSEMBLE( m6802 ); @@ -254,13 +247,6 @@ static const dasm_table_entry dasm_table[] = { "lh5801", _8bit, 0, CPU_DISASSEMBLE_NAME(lh5801) }, { "lr35902", _8bit, 0, CPU_DISASSEMBLE_NAME(lr35902) }, { "m37710", _8bit, 0, CPU_DISASSEMBLE_NAME(m37710_generic) }, - { "m6502", _8bit, 0, CPU_DISASSEMBLE_NAME(m6502) }, - { "m65sc02", _8bit, 0, CPU_DISASSEMBLE_NAME(m65sc02) }, - { "m65c02", _8bit, 0, CPU_DISASSEMBLE_NAME(m65c02) }, - { "m65ce02", _8bit, 0, CPU_DISASSEMBLE_NAME(m65ce02) }, - { "m6510", _8bit, 0, CPU_DISASSEMBLE_NAME(m6510) }, - { "deco16", _8bit, 0, CPU_DISASSEMBLE_NAME(deco16) }, - { "m4510", _8bit, 0, CPU_DISASSEMBLE_NAME(m4510) }, { "m6800", _8bit, 0, CPU_DISASSEMBLE_NAME(m6800) }, { "m6801", _8bit, 0, CPU_DISASSEMBLE_NAME(m6801) }, { "m6802", _8bit, 0, CPU_DISASSEMBLE_NAME(m6802) },