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https://github.com/holub/mame
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hphybrid: fixed interrupt bug in 5061-3001
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fulivi
parent
d35eed3cd4
commit
fbb38f96b7
@ -1016,12 +1016,12 @@ void hp_hybrid_cpu_device::check_for_interrupts(void)
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m_pa_changed_func((UINT8)CURRENT_PA);
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// Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence
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// lasts for 32 cycles (6 are already accounted for in get_ea for one indirection)
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m_icount -= 26;
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// lasts for 32 cycles
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m_icount -= 32;
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// Do a double-indirect JSM IV,I instruction
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WM(AEC_CASE_C , ++m_reg_R , m_reg_P);
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m_reg_P = RM(get_ea(0xc008));
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m_reg_P = RM(AEC_CASE_I , RM(HP_REG_IV_ADDR));
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m_reg_I = fetch();
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}
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@ -1485,12 +1485,20 @@ UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr)
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bsc_reg = HP_REG_R37_ADDR;
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break;
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default:
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logerror("hphybrid: aec_case=%d\n" , aec_case);
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return 0;
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}
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case AEC_CASE_I:
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// Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware.
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// Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does:
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// top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35
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// (see pg 334 of patent).
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bsc_reg = top_half ? 0 : HP_REG_R35_ADDR;
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break;
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UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK;
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default:
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logerror("hphybrid: aec_case=%d\n" , aec_case);
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return 0;
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}
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UINT16 aec_reg = (bsc_reg != 0) ? (m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK) : 0;
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if (m_forced_bsc_25) {
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aec_reg = (aec_reg & 0xf) | 0x20;
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@ -90,82 +90,83 @@ public:
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template<class _Object> static devcb_base &set_pa_changed_func(device_t &device, _Object object) { return downcast<hp_hybrid_cpu_device &>(device).m_pa_changed_func.set_callback(object); }
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protected:
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hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth);
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hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth);
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const override { return 6; }
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virtual UINT32 execute_input_lines() const override { return 2; }
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virtual UINT32 execute_default_irq_vector() const override { return 0xffff; }
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virtual void execute_run() override;
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virtual void execute_set_input(int inputnum, int state) override;
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const override { return 6; }
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virtual UINT32 execute_input_lines() const override { return 2; }
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virtual UINT32 execute_default_irq_vector() const override { return 0xffff; }
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virtual void execute_run() override;
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virtual void execute_set_input(int inputnum, int state) override;
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UINT16 execute_one(UINT16 opcode);
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UINT16 execute_one_sub(UINT16 opcode);
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// Execute an instruction that doesn't belong to either BPC or IOC
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virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0;
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UINT16 execute_one(UINT16 opcode);
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UINT16 execute_one_sub(UINT16 opcode);
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// Execute an instruction that doesn't belong to either BPC or IOC
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virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0;
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
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// device_state_interface overrides
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void state_string_export(const device_state_entry &entry, std::string &str) override;
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// device_state_interface overrides
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void state_string_export(const device_state_entry &entry, std::string &str) override;
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const override { return 2; }
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virtual UINT32 disasm_max_opcode_bytes() const override { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override;
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const override { return 2; }
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virtual UINT32 disasm_max_opcode_bytes() const override { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override;
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// Different cases of memory access
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// See patent @ pg 361
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typedef enum {
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AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses
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AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses
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AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses
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AEC_CASE_D // DMA accesses
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} aec_cases_t;
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// Different cases of memory access
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// See patent @ pg 361
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typedef enum {
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AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses
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AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses
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AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses
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AEC_CASE_D, // DMA accesses
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AEC_CASE_I // Interrupt vector fetches
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} aec_cases_t;
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// do memory address extension
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virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0;
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// do memory address extension
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virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0;
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UINT16 remove_mae(UINT32 addr);
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UINT16 remove_mae(UINT32 addr);
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UINT16 RM(aec_cases_t aec_case , UINT16 addr);
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UINT16 RM(UINT32 addr);
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virtual UINT16 read_non_common_reg(UINT16 addr) = 0;
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UINT16 RM(aec_cases_t aec_case , UINT16 addr);
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UINT16 RM(UINT32 addr);
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virtual UINT16 read_non_common_reg(UINT16 addr) = 0;
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void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v);
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void WM(UINT32 addr , UINT16 v);
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virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0;
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void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v);
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void WM(UINT32 addr , UINT16 v);
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virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0;
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UINT16 fetch(void);
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UINT16 fetch(void);
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UINT16 get_skip_addr(UINT16 opcode , bool condition) const;
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UINT16 get_skip_addr(UINT16 opcode , bool condition) const;
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devcb_write8 m_pa_changed_func;
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devcb_write8 m_pa_changed_func;
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int m_icount;
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bool m_forced_bsc_25;
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int m_icount;
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bool m_forced_bsc_25;
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// State of processor
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UINT16 m_reg_A; // Register A
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UINT16 m_reg_B; // Register B
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UINT16 m_reg_P; // Register P
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UINT16 m_reg_R; // Register R
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UINT16 m_reg_C; // Register C
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UINT16 m_reg_D; // Register D
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UINT16 m_reg_IV; // Register IV
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UINT16 m_reg_W; // Register W
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UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long)
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UINT16 m_flags; // Flags
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UINT8 m_dmapa; // DMA peripheral address (4 bits)
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UINT16 m_dmama; // DMA address
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UINT16 m_dmac; // DMA counter
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UINT16 m_reg_I; // Instruction register
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UINT32 m_genpc; // Full PC
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// State of processor
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UINT16 m_reg_A; // Register A
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UINT16 m_reg_B; // Register B
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UINT16 m_reg_P; // Register P
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UINT16 m_reg_R; // Register R
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UINT16 m_reg_C; // Register C
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UINT16 m_reg_D; // Register D
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UINT16 m_reg_IV; // Register IV
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UINT16 m_reg_W; // Register W
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UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long)
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UINT16 m_flags; // Flags
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UINT8 m_dmapa; // DMA peripheral address (4 bits)
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UINT16 m_dmama; // DMA address
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UINT16 m_dmac; // DMA counter
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UINT16 m_reg_I; // Instruction register
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UINT32 m_genpc; // Full PC
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private:
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address_space_config m_program_config;
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