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hphybrid: fixed interrupt bug in 5061-3001

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fulivi 2015-12-31 15:58:29 +01:00
parent d35eed3cd4
commit fbb38f96b7
2 changed files with 77 additions and 68 deletions
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16
src/devices/cpu/hphybrid/hphybrid.cpp
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@ -1016,12 +1016,12 @@ void hp_hybrid_cpu_device::check_for_interrupts(void)
m_pa_changed_func((UINT8)CURRENT_PA); m_pa_changed_func((UINT8)CURRENT_PA);
// Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence // Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence
// lasts for 32 cycles (6 are already accounted for in get_ea for one indirection) // lasts for 32 cycles
m_icount -= 26; m_icount -= 32;
// Do a double-indirect JSM IV,I instruction // Do a double-indirect JSM IV,I instruction
WM(AEC_CASE_C , ++m_reg_R , m_reg_P); WM(AEC_CASE_C , ++m_reg_R , m_reg_P);
m_reg_P = RM(get_ea(0xc008)); m_reg_P = RM(AEC_CASE_I , RM(HP_REG_IV_ADDR));
m_reg_I = fetch(); m_reg_I = fetch();
} }
@ -1485,12 +1485,20 @@ UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr)
bsc_reg = HP_REG_R37_ADDR; bsc_reg = HP_REG_R37_ADDR;
break; break;
case AEC_CASE_I:
// Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware.
// Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does:
// top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35
// (see pg 334 of patent).
bsc_reg = top_half ? 0 : HP_REG_R35_ADDR;
break;
default: default:
logerror("hphybrid: aec_case=%d\n" , aec_case); logerror("hphybrid: aec_case=%d\n" , aec_case);
return 0; return 0;
} }
UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK; UINT16 aec_reg = (bsc_reg != 0) ? (m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK) : 0;
if (m_forced_bsc_25) { if (m_forced_bsc_25) {
aec_reg = (aec_reg & 0xf) | 0x20; aec_reg = (aec_reg & 0xf) | 0x20;

3
src/devices/cpu/hphybrid/hphybrid.h
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@ -125,7 +125,8 @@ protected:
AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses
AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses
AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses
AEC_CASE_D // DMA accesses AEC_CASE_D, // DMA accesses
AEC_CASE_I // Interrupt vector fetches
} aec_cases_t; } aec_cases_t;
// do memory address extension // do memory address extension