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hphybrid: fixed interrupt bug in 5061-3001
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@ -1016,12 +1016,12 @@ void hp_hybrid_cpu_device::check_for_interrupts(void)
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m_pa_changed_func((UINT8)CURRENT_PA);
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// Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence
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// lasts for 32 cycles (6 are already accounted for in get_ea for one indirection)
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m_icount -= 26;
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// lasts for 32 cycles
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m_icount -= 32;
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// Do a double-indirect JSM IV,I instruction
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WM(AEC_CASE_C , ++m_reg_R , m_reg_P);
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m_reg_P = RM(get_ea(0xc008));
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m_reg_P = RM(AEC_CASE_I , RM(HP_REG_IV_ADDR));
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m_reg_I = fetch();
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}
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@ -1485,12 +1485,20 @@ UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr)
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bsc_reg = HP_REG_R37_ADDR;
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break;
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case AEC_CASE_I:
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// Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware.
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// Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does:
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// top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35
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// (see pg 334 of patent).
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bsc_reg = top_half ? 0 : HP_REG_R35_ADDR;
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break;
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default:
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logerror("hphybrid: aec_case=%d\n" , aec_case);
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return 0;
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}
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UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK;
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UINT16 aec_reg = (bsc_reg != 0) ? (m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK) : 0;
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if (m_forced_bsc_25) {
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aec_reg = (aec_reg & 0xf) | 0x20;
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@ -125,7 +125,8 @@ protected:
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AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses
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AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses
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AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses
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AEC_CASE_D // DMA accesses
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AEC_CASE_D, // DMA accesses
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AEC_CASE_I // Interrupt vector fetches
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} aec_cases_t;
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// do memory address extension
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