From fc16e06975753157d44af9a8d55e74b372c23cb5 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Mon, 16 Jan 2017 21:30:29 +0100 Subject: [PATCH] hcd62121: several small cleanups (nw) --- scripts/src/cpu.lua | 1 - src/devices/cpu/hcd62121/hcd62121.cpp | 1318 +++++++++++++++++++---- src/devices/cpu/hcd62121/hcd62121.h | 104 +- src/devices/cpu/hcd62121/hcd62121_ops.h | 1022 ------------------ src/devices/cpu/hcd62121/hcd62121d.cpp | 539 +++++---- src/mame/drivers/cfx9850.cpp | 311 +++--- 6 files changed, 1646 insertions(+), 1649 deletions(-) delete mode 100644 src/devices/cpu/hcd62121/hcd62121_ops.h diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index 6f39b1b0fc9..7e6ddc85135 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -611,7 +611,6 @@ if (CPUS["HCD62121"]~=null) then files { MAME_DIR .. "src/devices/cpu/hcd62121/hcd62121.cpp", MAME_DIR .. "src/devices/cpu/hcd62121/hcd62121.h", - MAME_DIR .. "src/devices/cpu/hcd62121/hcd62121_ops.h", } end diff --git a/src/devices/cpu/hcd62121/hcd62121.cpp b/src/devices/cpu/hcd62121/hcd62121.cpp index 3c8e98149ea..59930adceec 100644 --- a/src/devices/cpu/hcd62121/hcd62121.cpp +++ b/src/devices/cpu/hcd62121/hcd62121.cpp @@ -10,6 +10,10 @@ CFX-9850 (and maybe some other things too). This CPU core is based on the information provided by Martin Poupe. Martin Poupe's site can be found at http://martin.poupe.org/casio/ +TODO: + - instruction timings + - unknown instructions + **********************************************************************/ #include "emu.h" @@ -19,11 +23,11 @@ Martin Poupe's site can be found at http://martin.poupe.org/casio/ /* From the battery check routine at 20:e874 it looks like bit 3 of the flag register should be the Zero flag. */ -#define _FLAG_Z 0x08 -#define _FLAG_C 0x02 -#define _FLAG_ZL 0x04 -#define _FLAG_CL 0x01 -#define _FLAG_ZH 0x10 +constexpr u8 FLAG_Z = 0x08; +constexpr u8 FLAG_C = 0x02; +constexpr u8 FLAG_ZL = 0x04; +constexpr u8 FLAG_CL = 0x01; +constexpr u8 FLAG_ZH = 0x10; const device_type HCD62121 = &device_creator; @@ -32,105 +36,105 @@ const device_type HCD62121 = &device_creator; hcd62121_cpu_device::hcd62121_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : cpu_device(mconfig, HCD62121, "Hitachi HCD62121", tag, owner, clock, "hcd62121", __FILE__) , m_program_config("program", ENDIANNESS_BIG, 8, 24, 0) - , m_io_config("io", ENDIANNESS_BIG, 8, 8, 0), m_prev_pc(0) - , m_sp(0) + , m_prev_pc(0) + , m_sp(0) , m_ip(0) , m_dsize(0) , m_cseg(0) , m_dseg(0) , m_sseg(0) , m_f(0) - , m_lar(0), m_program(nullptr), m_io(nullptr), m_icount(0) + , m_lar(0) + , m_program(nullptr) + , m_icount(0) + , m_kol_cb(*this) + , m_koh_cb(*this) + , m_ki_cb(*this) + , m_in0_cb(*this) { } -uint8_t hcd62121_cpu_device::read_op() +u8 hcd62121_cpu_device::read_op() { - uint8_t d = m_program->read_byte( ( m_cseg << 16 ) | m_ip ); + u8 d = m_program->read_byte( ( m_cseg << 16 ) | m_ip ); m_ip++; return d; } -uint8_t hcd62121_cpu_device::datasize( uint8_t op ) +u8 hcd62121_cpu_device::datasize(u8 op) { - switch( op & 0x03 ) + switch (op & 0x03) { case 0: return 1; case 1: return 2; case 2: - return ( m_dsize >> 4 ) + 1; + return (m_dsize >> 4) + 1; case 3: - return ( m_dsize & 0x0f ) + 1; + return (m_dsize & 0x0f) + 1; } return 1; } -void hcd62121_cpu_device::read_reg( int size, uint8_t op1 ) +void hcd62121_cpu_device::read_reg(int size, u8 op1) { - int i; - - if ( op1 & 0x80 ) + if (op1 & 0x80) { - for ( i = 0; i < size; i++ ) - m_temp1[i] = m_reg[ ( op1 - i ) & 0x7f ]; + for (int i = 0; i < size; i++) + m_temp1[i] = m_reg[(op1 - i) & 0x7f]; } else { - for ( i = 0; i < size; i++ ) - m_temp1[i] = m_reg[ ( op1 + i ) & 0x7f ]; + for (int i = 0; i < size; i++) + m_temp1[i] = m_reg[(op1 + i) & 0x7f]; } } -void hcd62121_cpu_device::write_reg( int size, uint8_t op1 ) +void hcd62121_cpu_device::write_reg(int size, u8 op1) { - int i; - - if ( op1 & 0x80 ) + if (op1 & 0x80) { - for ( i = 0; i < size; i++ ) - m_reg[ ( op1 - i ) & 0x7f ] = m_temp1[i]; + for (int i = 0; i < size; i++) + m_reg[(op1 - i) & 0x7f] = m_temp1[i]; } else { - for ( i = 0; i < size; i++ ) - m_reg[ ( op1 + i ) & 0x7f ] = m_temp1[i]; + for (int i = 0; i < size; i++) + m_reg[(op1 + i) & 0x7f] = m_temp1[i]; } } -void hcd62121_cpu_device::read_regreg( int size, uint8_t op1, uint8_t op2, bool op_is_logical ) +void hcd62121_cpu_device::read_regreg(int size, u8 op1, u8 op2, bool op_is_logical) { - int i; + for (int i = 0; i < size; i++) + m_temp1[i] = m_reg[(op1 + i) & 0x7f]; - for ( i = 0; i < size; i++ ) - m_temp1[i] = m_reg[ (op1 + i) & 0x7f]; - - if ( op1 & 0x80 ) + if (op1 & 0x80) { /* Second operand is an immediate value */ m_temp2[0] = op2; - for ( i = 1; i < size; i++ ) + for (int i = 1; i < size; i++) m_temp2[i] = op_is_logical ? op2 : 0; } else { /* Second operand is a register */ - for ( i = 0; i < size; i++ ) - m_temp2[i] = m_reg[ (op2 + i) & 0x7f ]; + for (int i = 0; i < size; i++) + m_temp2[i] = m_reg[(op2 + i) & 0x7f]; } - if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) ) + if (!(op1 & 0x80) && !(op2 & 0x80)) { /* We need to swap parameters */ - for ( i = 0; i < size; i++ ) + for (int i = 0; i < size; i++) { - uint8_t v = m_temp1[i]; + u8 v = m_temp1[i]; m_temp1[i] = m_temp2[i]; m_temp2[i] = v; } @@ -138,57 +142,52 @@ void hcd62121_cpu_device::read_regreg( int size, uint8_t op1, uint8_t op2, bool } -void hcd62121_cpu_device::write_regreg( int size, uint8_t op1, uint8_t op2 ) +void hcd62121_cpu_device::write_regreg(int size, u8 op1, u8 op2) { - int i; - - if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) ) + if ((op1 & 0x80) || (op2 & 0x80)) { /* store in reg1 */ - for ( i = 0; i < size; i++ ) - m_reg[ (op1 + i) & 0x7f] = m_temp1[i]; + for (int i = 0; i < size; i++) + m_reg[(op1 + i) & 0x7f] = m_temp1[i]; } else { /* store in reg2 */ - for ( i = 0; i < size; i++ ) - m_reg[ (op2 + i) & 0x7f] = m_temp1[i]; + for (int i = 0; i < size; i++) + m_reg[(op2 + i) & 0x7f] = m_temp1[i]; } } -void hcd62121_cpu_device::read_iregreg( int size, uint8_t op1, uint8_t op2 ) +void hcd62121_cpu_device::read_iregreg(int size, u8 op1, u8 op2) { - int i; - uint16_t ad; + u16 ad = m_reg[(0x40 | op1) & 0x7f ] | (m_reg[(0x40 | (op1 + 1)) & 0x7f] << 8); - ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); - - for ( i = 0; i < size; i++ ) + for (int i = 0; i < size; i++) { - m_temp1[i] = m_program->read_byte( ( m_dseg << 16 ) | ad ); - ad += ( op1 & 0x40 ) ? -1 : 1; + m_temp1[i] = m_program->read_byte((m_dseg << 16) | ad); + ad += (op1 & 0x40) ? -1 : 1; } m_lar = ad; - if ( op1 & 0x80 ) + if (op1 & 0x80) { m_temp2[0] = op2; - for ( i = 1; i < size; i++ ) + for (int i = 1; i < size; i++) m_temp2[i] = 0; } else { - for ( i = 0; i < size; i++ ) - m_temp2[i] = m_reg[ (op2 + i) & 0x7f ]; + for (int i = 0; i < size; i++) + m_temp2[i] = m_reg[(op2 + i) & 0x7f]; } - if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) ) + if (!(op1 & 0x80) && !(op2 & 0x80)) { /* We need to swap parameters */ - for ( i = 0; i < size; i++ ) + for (int i = 0; i < size; i++) { - uint8_t v = m_temp1[i]; + u8 v = m_temp1[i]; m_temp1[i] = m_temp2[i]; m_temp2[i] = v; } @@ -196,174 +195,170 @@ void hcd62121_cpu_device::read_iregreg( int size, uint8_t op1, uint8_t op2 ) } -void hcd62121_cpu_device::write_iregreg( int size, uint8_t op1, uint8_t op2 ) +void hcd62121_cpu_device::write_iregreg(int size, u8 op1, u8 op2) { - int i; - - if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) ) + if ((op1 & 0x80) || (op2 & 0x80)) { /* store in (reg1) */ - uint16_t ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); + u16 ad = m_reg[(0x40 | op1) & 0x7f] | (m_reg[(0x40 | (op1 + 1)) & 0x7f] << 8); - for ( i = 0; i < size; i++ ) + for (int i = 0; i < size; i++) { - m_program->write_byte( ( m_dseg << 16 ) | ad, m_temp1[i] ); - ad += ( op1 & 0x40 ) ? -1 : 1; + m_program->write_byte((m_dseg << 16) | ad, m_temp1[i]); + ad += (op1 & 0x40) ? -1 : 1; } m_lar = ad; } else { /* store in reg2 */ - for ( i = 0; i < size; i++ ) - m_reg[ (op2 + i) & 0x7f] = m_temp1[i]; + for (int i = 0; i < size; i++) + m_reg[(op2 + i) & 0x7f] = m_temp1[i]; } } -void hcd62121_cpu_device::write_iregreg2( int size, uint8_t op1, uint8_t op2 ) +void hcd62121_cpu_device::write_iregreg2(int size, u8 op1, u8 op2) { - int i; - - if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) ) + if ((op1 & 0x80) || (op2 & 0x80)) { /* store in reg2 */ - for ( i = 0; i < size; i++ ) - m_reg[ (op2 + i) & 0x7f] = m_temp2[i]; + for (int i = 0; i < size; i++) + m_reg[(op2 + i) & 0x7f] = m_temp2[i]; } else { /* store in (reg1) */ - uint16_t ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); + u16 ad = m_reg[(0x40 | op1) & 0x7f] | (m_reg[(0x40 | (op1 + 1)) & 0x7f] << 8); - for ( i = 0; i < size; i++ ) + for (int i = 0; i < size; i++) { - m_program->write_byte( ( m_dseg << 16 ) | ad, m_temp2[i] ); - ad += ( op1 & 0x40 ) ? -1 : 1; + m_program->write_byte((m_dseg << 16) | ad, m_temp2[i]); + ad += (op1 & 0x40) ? -1 : 1; } m_lar = ad; } } -int hcd62121_cpu_device::check_cond( uint8_t op ) +bool hcd62121_cpu_device::check_cond(u8 op) { - switch ( op & 0x07 ) + switch (op & 0x07) { case 0x00: /* ZH set */ - if ( m_f & _FLAG_ZH ) - return 1; - break; + return (m_f & FLAG_ZH); case 0x01: /* ZL set */ - if ( m_f & _FLAG_ZL ) - return 1; - break; + return (m_f & FLAG_ZL); case 0x02: /* C set */ - if ( m_f & _FLAG_C ) - return 1; - break; + return (m_f & FLAG_C); case 0x03: /* Z set */ - if ( m_f & _FLAG_Z ) - return 1; - break; + return (m_f & FLAG_Z); case 0x04: /* Z or C set */ - if ( m_f & ( _FLAG_Z | _FLAG_C ) ) - return 1; - break; + return (m_f & (FLAG_Z | FLAG_C)); case 0x05: /* CL set */ - if ( m_f & _FLAG_CL ) - return 1; - break; + return (m_f & FLAG_CL); case 0x06: /* C clear */ - if ( ! ( m_f & _FLAG_C ) ) - return 1; - break; + return (!(m_f & FLAG_C)); case 0x07: /* Z clear */ - if ( ! ( m_f & _FLAG_Z ) ) - return 1; - break; + return (!(m_f & FLAG_Z)); } - return 0; + return false; } void hcd62121_cpu_device::device_start() { m_program = &space(AS_PROGRAM); - m_io = &space(AS_IO); - save_item( NAME(m_prev_pc) ); - save_item( NAME(m_sp) ); - save_item( NAME(m_ip) ); - save_item( NAME(m_dsize) ); - save_item( NAME(m_cseg) ); - save_item( NAME(m_dseg) ); - save_item( NAME(m_sseg) ); - save_item( NAME(m_f) ); - save_item( NAME(m_lar) ); - save_item( NAME(m_reg) ); - save_item( NAME(m_temp1) ); - save_item( NAME(m_temp2) ); + m_kol_cb.resolve_safe(); + m_koh_cb.resolve_safe(); + m_ki_cb.resolve_safe(0); + m_in0_cb.resolve_safe(0); + + save_item(NAME(m_prev_pc)); + save_item(NAME(m_sp)); + save_item(NAME(m_ip)); + save_item(NAME(m_dsize)); + save_item(NAME(m_cseg)); + save_item(NAME(m_dseg)); + save_item(NAME(m_sseg)); + save_item(NAME(m_f)); + save_item(NAME(m_lar)); + save_item(NAME(m_reg)); + save_item(NAME(m_temp1)); + save_item(NAME(m_temp2)); // Register state for debugger - state_add( STATE_GENPC, "GENPC", m_ip ).callexport().formatstr("%8s"); - state_add( STATE_GENPCBASE,"CURPC", m_ip ).callexport().formatstr("%8s"); - state_add( STATE_GENFLAGS, "GENFLAGS", m_f ).callimport().callexport().formatstr("%12s").noshow(); + state_add(STATE_GENPC, "GENPC", m_rtemp).callexport().formatstr("%8s"); + state_add(STATE_GENPCBASE,"CURPC", m_rtemp).callexport().formatstr("%8s"); + state_add(STATE_GENFLAGS, "GENFLAGS", m_f ).callimport().callexport().formatstr("%12s").noshow(); - state_add( HCD62121_IP, "IP", m_ip ).callimport().callexport().formatstr("%04X"); - state_add( HCD62121_SP, "SP", m_sp ).callimport().callexport().formatstr("%04X"); - state_add( HCD62121_LAR, "LAR", m_lar ).callimport().callexport().formatstr("%04X"); - state_add( HCD62121_CS, "CS", m_cseg ).callimport().callexport().formatstr("%02X"); - state_add( HCD62121_DS, "DS", m_dseg ).callimport().callexport().formatstr("%02X"); - state_add( HCD62121_SS, "SS", m_sseg ).callimport().callexport().formatstr("%02X"); - state_add( HCD62121_DSIZE, "DSIZE", m_dsize ).callimport().callexport().formatstr("%02X"); - state_add( HCD62121_F, "F", m_f ).callimport().callexport().formatstr("%02X"); + state_add(HCD62121_IP, "IP", m_ip ).callimport().callexport().formatstr("%04X"); + state_add(HCD62121_SP, "SP", m_sp ).callimport().callexport().formatstr("%04X"); + state_add(HCD62121_LAR, "LAR", m_lar ).callimport().callexport().formatstr("%04X"); + state_add(HCD62121_CS, "CS", m_cseg ).callimport().callexport().formatstr("%02X"); + state_add(HCD62121_DS, "DS", m_dseg ).callimport().callexport().formatstr("%02X"); + state_add(HCD62121_SS, "SS", m_sseg ).callimport().callexport().formatstr("%02X"); + state_add(HCD62121_DSIZE, "DSIZE", m_dsize).callimport().callexport().formatstr("%02X"); + state_add(HCD62121_F, "F", m_f ).callimport().callexport().formatstr("%02X"); - state_add( HCD62121_R00, "R00", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R04, "R04", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R08, "R08", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R0C, "R0C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R10, "R10", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R14, "R14", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R18, "R18", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R1C, "R1C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R20, "R20", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R24, "R24", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R28, "R28", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R2C, "R2C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R30, "R30", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R34, "R34", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R38, "R38", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R3C, "R3C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R40, "R40", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R44, "R44", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R48, "R48", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R4C, "R4C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R50, "R50", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R54, "R54", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R58, "R58", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R5C, "R5C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R60, "R60", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R64, "R64", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R68, "R68", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R6C, "R6C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R70, "R70", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R74, "R74", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R78, "R78", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); - state_add( HCD62121_R7C, "R7C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R00, "R00", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R04, "R04", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R08, "R08", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R0C, "R0C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R10, "R10", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R14, "R14", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R18, "R18", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R1C, "R1C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R20, "R20", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R24, "R24", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R28, "R28", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R2C, "R2C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R30, "R30", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R34, "R34", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R38, "R38", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R3C, "R3C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R40, "R40", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R44, "R44", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R48, "R48", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R4C, "R4C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R50, "R50", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R54, "R54", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R58, "R58", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R5C, "R5C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R60, "R60", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R64, "R64", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R68, "R68", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R6C, "R6C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R70, "R70", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R74, "R74", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R78, "R78", m_reg[0x00]).callimport().callexport().formatstr("%8s"); + state_add(HCD62121_R7C, "R7C", m_reg[0x00]).callimport().callexport().formatstr("%8s"); m_icountptr = &m_icount; } +void hcd62121_cpu_device::state_export(const device_state_entry &entry) +{ + switch (entry.index()) + { + case STATE_GENPC: + case STATE_GENPCBASE: + m_rtemp = (m_cseg << 16) | m_ip; + break; + } +} + + void hcd62121_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) const { switch (entry.index()) @@ -375,11 +370,11 @@ void hcd62121_cpu_device::state_string_export(const device_state_entry &entry, s case STATE_GENFLAGS: str = string_format("%s-%s-%s-%c-%c", - m_f & _FLAG_ZH ? "ZH":"__", - m_f & _FLAG_CL ? "CL":"__", - m_f & _FLAG_ZL ? "ZL":"__", - m_f & _FLAG_C ? 'C':'_', - m_f & _FLAG_Z ? 'Z':'_' + m_f & FLAG_ZH ? "ZH":"__", + m_f & FLAG_CL ? "CL":"__", + m_f & FLAG_ZL ? "ZL":"__", + m_f & FLAG_C ? 'C':'_', + m_f & FLAG_Z ? 'Z':'_' ); break; @@ -495,38 +490,999 @@ void hcd62121_cpu_device::device_reset() m_f = 0; m_dsize = 0; - for(auto & elem : m_reg) + for (auto & elem : m_reg) { elem = 0; } } +inline void hcd62121_cpu_device::set_zero_flag(bool is_zero) +{ + if (is_zero) + m_f |= FLAG_Z; + else + m_f &= ~FLAG_Z; +} + + +inline void hcd62121_cpu_device::set_carry_flag(bool is_carry) +{ + if (is_carry) + m_f |= FLAG_C; + else + m_f &= ~FLAG_C; +} + + +inline void hcd62121_cpu_device::set_zl_flag(bool is_zl) +{ + if (is_zl) + m_f |= FLAG_ZL; + else + m_f &= ~FLAG_ZL; +} + + +inline void hcd62121_cpu_device::set_zh_flag(bool is_zh) +{ + if (is_zh) + m_f |= FLAG_ZH; + else + m_f &= ~FLAG_ZH; +} + + +inline void hcd62121_cpu_device::set_cl_flag(bool is_cl) +{ + if (is_cl) + m_f |= FLAG_CL; + else + m_f &= ~FLAG_CL; +} + + +inline void hcd62121_cpu_device::op_msk(int size) +{ + bool mskres = true; + + for (int i = 0; i < size; i++) + { + if ((m_temp1[i] & m_temp2[i]) != m_temp2[i]) + mskres = false; + } + + set_zero_flag(!mskres); +} + + +inline void hcd62121_cpu_device::op_imsk(int size) +{ + bool mskres = true; + bool set_zero = false; + + for (int i = 0; i < size; i++) + { + if ((m_temp1[i] & ~m_temp2[i]) != ~m_temp2[i]) + mskres = false; + if (m_temp1[i] | m_temp2[i]) + set_zero = true; + } + + set_zero_flag(set_zero); + set_carry_flag(!mskres); +} + + +inline void hcd62121_cpu_device::op_and(int size) +{ + bool is_zero = true; + + for (int i = 0; i < size; i++) + { + m_temp1[i] = m_temp1[i] & m_temp2[i]; + if (m_temp1[i]) + is_zero = false; + } + + set_zero_flag(is_zero); + set_zl_flag((m_temp1[0] & 0x0f) == 0); + set_zh_flag((m_temp1[0] & 0xf0) == 0); +} + + +inline void hcd62121_cpu_device::op_or(int size) +{ + bool is_zero = true; + + for (int i = 0; i < size; i++) + { + m_temp1[i] = m_temp1[i] | m_temp2[i]; + if (m_temp1[i]) + is_zero = false; + } + + set_zero_flag(is_zero); + set_zl_flag((m_temp1[0] & 0x0f) == 0); + set_zh_flag((m_temp1[0] & 0xf0) == 0); +} + + +inline void hcd62121_cpu_device::op_xor(int size) +{ + bool is_zero = true; + + for (int i = 0; i < size; i++) + { + m_temp1[i] = m_temp1[i] ^ m_temp2[i]; + if (m_temp1[i]) + is_zero = false; + } + + set_zero_flag(is_zero); + set_zl_flag((m_temp1[0] & 0x0f) == 0); + set_zh_flag((m_temp1[0] & 0xf0) == 0); +} + + +inline void hcd62121_cpu_device::op_add(int size) +{ + bool is_zero = true; + u8 carry = 0; + + set_cl_flag((m_temp1[0] & 0x0f) + (m_temp2[0] & 0x0f) > 15); + + for (int i = 0; i < size; i++) + { + u16 res = m_temp1[i] + m_temp2[i] + carry; + + m_temp1[i] = res & 0xff; + if (m_temp1[i]) + is_zero = false; + + carry = (res & 0xff00) ? 1 : 0; + } + + set_zero_flag(is_zero); + set_carry_flag(carry); + set_zl_flag((m_temp1[0] & 0x0f) == 0); + set_zh_flag((m_temp1[0] & 0xf0) == 0); +} + + +// BCD ADD +inline void hcd62121_cpu_device::op_addb(int size) +{ + bool is_zero = true; + u8 carry = 0; + + set_cl_flag((m_temp1[0] & 0x0f) + (m_temp2[0] & 0x0f) > 9); + + for (int i = 0; i < size; i++) + { + u16 res = (m_temp1[i] & 0x0f) + (m_temp2[i] & 0x0f) + carry; + + if (res > 9) + { + res += 6; + } + res += (m_temp1[i] & 0xf0) + (m_temp2[i] & 0xf0); + if (res > 0x9f) + { + res += 0x60; + } + m_temp1[i] = res & 0xff; + if (m_temp1[i]) + is_zero = false; + + carry = (res & 0xff00) ? 1 : 0; + } + + set_zero_flag(is_zero); + set_carry_flag(carry); + set_zl_flag((m_temp1[0] & 0x0f) == 0); + set_zh_flag((m_temp1[0] & 0xf0) == 0); +} + + +inline void hcd62121_cpu_device::op_sub(int size) +{ + bool is_zero = true; + u8 carry = 0; + + set_cl_flag((m_temp1[0] & 0x0f) < (m_temp2[0] & 0x0f)); + + for (int i = 0; i < size; i++) + { + u16 res = m_temp1[i] - m_temp2[i] - carry; + + m_temp1[i] = res & 0xff; + if (m_temp1[i]) + is_zero = false; + + carry = ( res & 0xff00 ) ? 1 : 0; + } + + set_zero_flag(is_zero); + set_carry_flag(carry); + set_zl_flag((m_temp1[0] & 0x0f) == 0); + set_zh_flag((m_temp1[0] & 0xf0) == 0); +} + + +inline void hcd62121_cpu_device::op_pushw(u16 source) +{ + m_program->write_byte(( m_sseg << 16) | m_sp, source & 0xff); + m_sp--; + m_program->write_byte(( m_sseg << 16) | m_sp, source >> 8); + m_sp--; +} + + +inline u16 hcd62121_cpu_device::op_popw() +{ + m_sp++; + u16 res = m_program->read_byte((m_sseg << 16) | m_sp) << 8; + m_sp++; + res |= m_program->read_byte((m_sseg << 16) | m_sp); + + return res; +} + + void hcd62121_cpu_device::execute_run() { do { - uint32_t pc = ( m_cseg << 16 ) | m_ip; - uint8_t op; + offs_t pc = (m_cseg << 16) | m_ip; debugger_instruction_hook(this, pc); m_prev_pc = pc; - op = read_op(); + u8 op = read_op(); + // actual instruction timings unknown m_icount -= 4; - switch ( op ) + switch (op) { -#include "hcd62121_ops.h" + case 0x04: /* mskb r1,r2 */ + case 0x05: /* mskw r1,r2 */ + case 0x06: /* mskq r1,r2 */ + case 0x07: /* mskt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_msk(size); + } + break; + + case 0x08: /* shb r1,4 */ + case 0x09: /* shw r1,4 */ + case 0x0A: /* shq r1,4 */ + case 0x0B: /* sht r1,4 */ + /* Shift is a nibble shift! */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 d1 = 0, d2 = 0; + + read_reg(size, reg1); + + for (int i = 0; i < size; i++) + { + if (reg1 & 0x80) + { + d1 = (m_temp1[i] & 0x0f) << 4; + m_temp1[i] = (m_temp1[i] >> 4) | d2; + } + else + { + d1 = (m_temp1[i] & 0xf0) >> 4; + m_temp1[i] = (m_temp1[i] << 4) | d2; + } + d2 = d1; + } + + write_reg(size, reg1); + } + break; + + case 0x0C: /* testb r1,r2 */ + case 0x0D: /* testw r1,r2 */ + case 0x0E: /* testq r1,r2 */ + case 0x0F: /* testt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_and(size); + } + break; + + case 0x10: /* xorb r1,r2 */ + case 0x11: /* xorw r1,r2 */ + case 0x12: /* xorq r1,r2 */ + case 0x13: /* xort r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_xor(size); + + write_regreg(size, reg1, reg2); + } + break; + + case 0x14: /* cmpb r1,r2 */ + case 0x15: /* cmpw r1,r2 */ + case 0x16: /* cmpq r1,r2 */ + case 0x17: /* cmpt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_sub(size); + } + break; + + case 0x18: /* movb r1,r2 */ + case 0x19: /* movw r1,r2 */ + case 0x1A: /* movq r1,r2 */ + case 0x1B: /* movt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + for (int i = 0; i < size; i++) + m_temp1[i] = m_temp2[i]; + + write_regreg(size, reg1, reg2); + } + break; + + case 0x1C: /* imskb r1,r2 */ + case 0x1D: /* imskw r1,r2 */ + case 0x1E: /* imskq r1,r2 */ + case 0x1F: /* imskt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_imsk(size); + } + break; + + case 0x20: /* shrb r1 */ + case 0x21: /* shrw r1 */ + case 0x22: /* shrq r1 */ + case 0x23: /* shrt r1 */ + /* Shift is a single shift! */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 d1 = 0, d2 = 0; + + read_reg(size, reg1); + + for (int i = 0; i < size; i++) + { + d1 = (m_temp1[i] & 0x01) << 7; + m_temp1[i] = (m_temp1[i] >> 1) | d2; + d2 = d1; + } + + write_reg(size, reg1); + } + break; + + case 0x24: /* orb r1,r2 */ + case 0x25: /* orw r1,r2 */ + case 0x26: /* orq r1,r2 */ + case 0x27: /* ort r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_or(size); + + write_regreg(size, reg1, reg2); + } + break; + + case 0x28: /* shlb r1 */ + case 0x29: /* shlw r1 */ + case 0x2A: /* shlq r1 */ + case 0x2B: /* shlt r1 */ + /* Shift is a single shift! */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 d1 = 0, d2 = 0; + + read_reg(size, reg1); + + for (int i = 0; i < size; i++) + { + d1 = (m_temp1[i] & 0x80) >> 7; + m_temp1[i] = (m_temp1[i] << 1) | d2; + d2 = d1; + } + + write_reg(size, reg1); + } + break; + + case 0x2C: /* andb r1,r2 */ + case 0x2D: /* andw r1,r2 */ + case 0x2E: /* andq r1,r2 */ + case 0x2F: /* andt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, true); + + op_and(size); + + write_regreg(size, reg1, reg2); + } + break; + + case 0x34: /* subb r1,r2 */ + case 0x35: /* subw r1,r2 */ + case 0x36: /* subq r1,r2 */ + case 0x37: /* subt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_sub(size); + + write_regreg(size, reg1, reg2); + } + break; + + case 0x38: /* adbb r1,r2 */ + case 0x39: /* adbw r1,r2 */ + case 0x3A: /* adbq r1,r2 */ + case 0x3B: /* adbt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_addb(size); + + write_regreg(size, reg1, reg2); + } + break; + + case 0x3C: /* addb r1,r2 */ + case 0x3D: /* addw r1,r2 */ + case 0x3E: /* addq r1,r2 */ + case 0x3F: /* addt r1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_regreg(size, reg1, reg2, false); + + op_add(size); + + write_regreg(size, reg1, reg2); + } + break; + + case 0x4C: /* testb ir1,r2 */ + case 0x4D: /* testw ir1,r2 */ + case 0x4E: /* testq ir1,r2 */ + case 0x4F: /* testt ir1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + op_and(size); + } + break; + + case 0x54: /* cmpb ir1,r2 */ + case 0x55: /* cmpw ir1,r2 */ + case 0x56: /* cmpq ir1,r2 */ + case 0x57: /* cmpt ir1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + op_sub(size); + } + break; + + case 0x58: /* movb ir1,r2 */ + case 0x59: /* movw ir1,r2 */ + case 0x5A: /* movq ir1,r2 */ + case 0x5B: /* movt ir1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + for (int i = 0; i < size; i++) + m_temp1[i] = m_temp2[i]; + + write_iregreg(size, reg1, reg2); + } + break; + + case 0x64: /* orb ir1,r2 */ + case 0x65: /* orb ir1,r2 */ + case 0x66: /* orb ir1,r2 */ + case 0x67: /* orb ir1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + op_or(size); + + write_iregreg(size, reg1, reg2); + } + break; + + case 0x6C: /* andb ir1,r2 */ + case 0x6D: /* andw ir1,r2 */ + case 0x6E: /* andq ir1,r2 */ + case 0x6F: /* andt ir1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + op_and(size); + + write_iregreg(size, reg1, reg2); + } + break; + + case 0x7C: /* addb ir1,r2 */ + case 0x7D: /* addw ir1,r2 */ + case 0x7E: /* addq ir1,r2 */ + case 0x7F: /* addt ir1,r2 */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + op_add(size); + + write_iregreg(size, reg1, reg2); + } + break; + + case 0x88: /* jump _a16 */ + m_ip = (read_op() << 8) | read_op(); + break; + + case 0x89: /* jumpf cs:a16 */ + { + u8 cs = read_op(); + u8 a1 = read_op(); + u8 a2 = read_op(); + + m_cseg = cs; + m_ip = (a1 << 8) | a2; + } + break; + + case 0x8A: /* call a16 */ + { + u8 a1 = read_op(); + u8 a2 = read_op(); + + op_pushw(m_ip); + + m_ip = (a1 << 8) | a2; + } + break; + + case 0x8C: /* unk_8C */ + case 0x8D: /* unk_8D */ + case 0x8E: /* unk_8E */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + break; + + case 0x90: /* retzh */ + case 0x91: /* retzl */ + case 0x92: /* retc */ + case 0x93: /* retz */ + case 0x94: /* retzc */ + case 0x95: /* retcl */ + case 0x96: /* retnc */ + case 0x97: /* retnz */ + if (check_cond(op)) + m_ip = op_popw(); + break; + + case 0x98: /* jump (r1) */ + { + u8 reg1 = read_op(); + u16 ad = m_reg[(reg1 | 0x40) & 0x7f] << 8; + + if (reg1 & 0x40) + ad |= m_reg[((reg1 - 1) | 0x40) & 0x7f]; + else + ad |= m_reg[((reg1 + 1) | 0x40) & 0x7f]; + + m_ip = ad; + } + break; + + case 0x9F: /* ret */ + m_ip = op_popw(); + break; + + case 0xA0: /* jmpzh a16 */ + case 0xA1: /* jmpzl a16 */ + case 0xA2: /* jmpc a16 */ + case 0xA3: /* jmpz a16 */ + case 0xA4: /* jmpzc a16 */ + case 0xA5: /* jmpcl a16 */ + case 0xA6: /* jmpnc a16 */ + case 0xA7: /* jmpnz a16 */ + { + u8 a1 = read_op(); + u8 a2 = read_op(); + + if (check_cond(op)) + m_ip = (a1 << 8) | a2; + } + break; + + case 0xA8: /* callzh a16 */ + case 0xA9: /* callzl a16 */ + case 0xAA: /* callc a16 */ + case 0xAB: /* callz a16 */ + case 0xAC: /* callzc a16 */ + case 0xAD: /* callcl a16 */ + case 0xAE: /* callnc a16 */ + case 0xAF: /* callnz a16 */ + { + u8 a1 = read_op(); + u8 a2 = read_op(); + + if (check_cond(op)) + { + op_pushw(m_ip); + + m_ip = (a1 << 8) | a2; + } + } + break; + + case 0xB1: /* unk_B1 reg/i8 */ + case 0xB3: /* unk_B3 reg/i8 */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + read_op(); + break; + + case 0xB4: /* out koh,reg */ + m_koh_cb(m_reg[read_op() & 0x7f]); + break; + + case 0xB5: /* out koh,i8 */ + m_koh_cb(read_op()); + break; + + case 0xB6: /* out kol,reg */ + m_kol_cb(m_reg[read_op() & 0x7f]); + break; + + case 0xB7: /* out kol,i8 */ + m_kol_cb(read_op()); + break; + + case 0xB9: /* unk_B9 reg/i8 */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + read_op(); + break; + + case 0xBB: /* jmpcl? a16 */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + { + u8 a1 = read_op(); + u8 a2 = read_op(); + + if (m_f & FLAG_CL) + m_ip = ( a1 << 8) | a2; + } + break; + + case 0xBF: /* jmpncl? a16 */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + { + u8 a1 = read_op(); + u8 a2 = read_op(); + + if (!(m_f & FLAG_CL)) + m_ip = (a1 << 8) | a2; + } + break; + + case 0xC0: /* movb reg,i8 */ + case 0xC1: /* movw reg,i16 */ + case 0xC2: /* movw reg,i64 */ + case 0xC3: /* movw reg,i80 */ + { + int size = datasize(op); + u8 reg = read_op(); + + for (int i = 0; i < size; i++) + { + m_reg[(reg + i) & 0x7f] = read_op(); + } + } + break; + + case 0xC4: /* movb (lar),r1 / r1,(lar) */ + case 0xC5: /* movw (lar),r1 / r1,(lar) */ + case 0xC6: /* movq (lar),r1 / r1,(lar) */ + case 0xC7: /* movt (lar),r1 / r1,(lar) */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + int pre_inc = 0; + int post_inc = 1; + + switch (reg1 & 0x60) + { + case 0x00: + pre_inc = 0; + post_inc = 1; + break; + case 0x20: + pre_inc = 1; + post_inc = 0; + break; + case 0x40: + pre_inc = 0; + post_inc = -1; + break; + case 0x60: + pre_inc = -1; + post_inc = 0; + break; + } + + if ((reg1 & 0x80) || (reg2 & 0x80)) + { + /* (lar) <- r1 */ + for (int i = 0; i < size; i++) + { + m_lar += pre_inc; + m_program->write_byte((m_dseg << 16) | m_lar, m_reg[(reg2 + i) & 0x7f]); + m_lar += post_inc; + } + } + else + { + /* r1 <- (lar) */ + for (int i = 0; i < size; i++) + { + m_lar += pre_inc; + m_reg[(reg2 + i) & 0x7f] = m_program->read_byte((m_dseg << 16) | m_lar); + m_lar += post_inc; + } + } + } + break; + + case 0xCC: /* swapb ir1,r2 */ + case 0xCD: /* swapw ir1,r2 */ + case 0xCE: /* swapq ir1,r2 */ + case 0xCF: /* swapt ir1,r2? */ + { + int size = datasize(op); + u8 reg1 = read_op(); + u8 reg2 = read_op(); + + read_iregreg(size, reg1, reg2); + + for (int i = 0; i < size; i++) + { + u8 d = m_temp1[i]; + m_temp1[i] = m_temp2[i]; + m_temp2[i] = d; + } + + write_iregreg(size, reg1, reg2); + write_iregreg2(size, reg1, reg2); + } + break; + + case 0xD0: /* movb cs,reg */ + m_cseg = m_reg[read_op() & 0x7f]; + break; + + case 0xD1: /* movb cs,i8 */ + m_cseg = read_op(); + break; + + case 0xD2: /* movb dsize,reg */ + m_dsize = m_reg[read_op() & 0x7f]; + break; + + case 0xD3: /* movb dsize,i8 */ + m_dsize = read_op(); + break; + + case 0xD4: /* movb ss,reg */ + m_sseg = m_reg[read_op() & 0x7f]; + break; + + case 0xD5: /* movb ss,i8 */ + m_sseg = read_op(); + break; + + case 0xD6: /* movw sp,reg */ + { + u8 reg1 = read_op(); + + m_sp = m_reg[reg1 & 0x7f] | (m_reg[(reg1 + 1) & 0x7f] << 8); + } + break; + + case 0xD7: /* movw sp,i16 */ + m_sp = read_op() << 8; + m_sp |= read_op(); + break; + + case 0xD8: /* movb f,reg */ + m_f = m_reg[read_op() & 0x7f]; + break; + + case 0xD9: /* movb f,i8 */ + m_f = read_op(); + break; + + case 0xDC: /* movb ds,reg */ + m_dseg = m_reg[read_op() & 0x7f]; + break; + + case 0xDD: /* movb ds,i8 */ + m_dseg = read_op(); + break; + + case 0xDE: /* movw lar,reg */ + { + u8 reg1 = read_op(); + + m_lar = m_reg[reg1 & 0x7f] | (m_reg[( reg1 + 1) & 0x7f] << 8); + } + break; + + case 0xE0: /* in0 reg */ + { + u8 reg1 = read_op(); + + m_reg[reg1 & 0x7f] = m_in0_cb(); + } + break; + + case 0xE1: /* unk_E1 reg/i8 (in?) */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + read_op(); + break; + + case 0xE2: /* in kb, reg */ + m_reg[read_op() & 0x7f] = m_ki_cb(); + break; + + case 0xE3: /* unk_e3 reg/i8 (in?) */ + case 0xE4: /* unk_e4 reg/i8 (in?) */ + case 0xE5: /* unk_e5 reg/i8 (in?) */ + case 0xE6: /* unk_e6 reg/i8 (in?) */ + case 0xE7: /* unk_e7 reg/i8 (in?) */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + read_op(); + break; + + case 0xE8: /* movw r1,lar */ + { + u8 reg1 = read_op(); + + m_reg[reg1 & 0x7f] = m_lar & 0xff; + m_reg[(reg1 + 1) & 0x7f] = m_lar >> 8; + } + break; + + case 0xEB: /* movw reg,ss */ + { + u8 reg1 = read_op(); + + m_reg[reg1 & 0x7f] = m_sp & 0xff; + m_reg[(reg1 + 1) & 0x7f] = m_sp >> 8; + } + break; + + case 0xEF: /* movb reg,ss */ + m_reg[read_op() & 0x7f] = m_sseg; + break; + + case 0xF0: /* unk_F0 reg/i8 (out?) */ + case 0xF1: /* unk_F1 reg/i8 (out?) */ + case 0xF2: /* unk_F2 reg/i8 (out?) */ + case 0xF3: /* unk_F3 reg/i8 (out?) */ + case 0xF4: /* unk_F4 reg/i8 (out?) */ + case 0xF5: /* unk_F5 reg/i8 (out?) */ + case 0xF6: /* unk_F6 reg/i8 (out?) */ + case 0xF7: /* unk_F7 reg/i8 (out?) */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + read_op(); + break; + + case 0xFC: /* unk_FC - disable interrupts?? */ + case 0xFD: /* unk_FD */ + case 0xFE: /* unk_FE */ + logerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); + break; + + case 0xFF: /* nop */ + break; + + default: + fatalerror("%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op); }; } while (m_icount > 0); } -offs_t hcd62121_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) +offs_t hcd62121_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const u8 *oprom, const u8 *opram, uint32_t options) { - extern CPU_DISASSEMBLE( hcd62121 ); + extern CPU_DISASSEMBLE(hcd62121); return CPU_DISASSEMBLE_NAME(hcd62121)(this, stream, pc, oprom, opram, options); } diff --git a/src/devices/cpu/hcd62121/hcd62121.h b/src/devices/cpu/hcd62121/hcd62121.h index af105c2a3a3..a7dd123f051 100644 --- a/src/devices/cpu/hcd62121/hcd62121.h +++ b/src/devices/cpu/hcd62121/hcd62121.h @@ -20,17 +20,10 @@ enum }; -/* I/O ports */ -enum -{ - /* Output ports */ - HCD62121_KOL=0x00, - HCD62121_KOH, - /* Input ports */ - HCD62121_KI, - /* Other I/O ports */ - HCD62121_IN0 -}; +#define MCFG_HCD62121_KOL_CB(_devcb) devcb = &hcd62121_cpu_device::set_kol_callback(*device, DEVCB_##_devcb); +#define MCFG_HCD62121_KOH_CB(_devcb) devcb = &hcd62121_cpu_device::set_koh_callback(*device, DEVCB_##_devcb); +#define MCFG_HCD62121_KI_CB(_devcb) devcb = &hcd62121_cpu_device::set_ki_callback(*device, DEVCB_##_devcb); +#define MCFG_HCD62121_IN0_CB(_devcb) devcb = &hcd62121_cpu_device::set_in0_callback(*device, DEVCB_##_devcb); class hcd62121_cpu_device : public cpu_device @@ -39,58 +32,85 @@ public: // construction/destruction hcd62121_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + template static devcb_base &set_kol_callback(device_t &device, _Object object) { return downcast(device).m_kol_cb.set_callback(object); } + template static devcb_base &set_koh_callback(device_t &device, _Object object) { return downcast(device).m_koh_cb.set_callback(object); } + template static devcb_base &set_ki_callback(device_t &device, _Object object) { return downcast(device).m_ki_cb.set_callback(object); } + template static devcb_base &set_in0_callback(device_t &device, _Object object) { return downcast(device).m_in0_cb.set_callback(object); } + protected: // device-level overrides virtual void device_start() override; virtual void device_reset() override; // device_execute_interface overrides - virtual uint32_t execute_min_cycles() const override { return 4; } - virtual uint32_t execute_max_cycles() const override { return 48; } - virtual uint32_t execute_input_lines() const override { return 2; } + virtual u32 execute_min_cycles() const override { return 4; } + virtual u32 execute_max_cycles() const override { return 48; } + virtual u32 execute_input_lines() const override { return 2; } virtual void execute_run() override; // device_memory_interface overrides - virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : nullptr ); } + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : nullptr; } // device_state_interface overrides + virtual void state_export(const device_state_entry &entry) override; virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; // device_disasm_interface overrides - virtual uint32_t disasm_min_opcode_bytes() const override { return 1; } - virtual uint32_t disasm_max_opcode_bytes() const override { return 18; } - virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override; + virtual u32 disasm_min_opcode_bytes() const override { return 1; } + virtual u32 disasm_max_opcode_bytes() const override { return 18; } + virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const u8 *oprom, const u8 *opram, u32 options) override; - uint8_t read_op(); - uint8_t datasize( uint8_t op ); - void read_reg( int size, uint8_t op1 ); - void write_reg( int size, uint8_t op1 ); - void read_regreg( int size, uint8_t op1, uint8_t op2, bool op_is_logical ); - void write_regreg( int size, uint8_t op1, uint8_t op2 ); - void read_iregreg( int size, uint8_t op1, uint8_t op2 ); - void write_iregreg( int size, uint8_t op1, uint8_t op2 ); - void write_iregreg2( int size, uint8_t op1, uint8_t op2 ); - int check_cond( uint8_t op ); +private: + u8 read_op(); + u8 datasize(u8 op); + void read_reg(int size, u8 op1); + void write_reg(int size, u8 op1); + void read_regreg(int size, u8 op1, u8 op2, bool op_is_logical); + void write_regreg(int size, u8 op1, u8 op2); + void read_iregreg(int size, u8 op1, u8 op2); + void write_iregreg(int size, u8 op1, u8 op2); + void write_iregreg2(int size, u8 op1, u8 op2); + bool check_cond(u8 op); + void set_zero_flag(bool is_zero); + void set_carry_flag(bool is_carry); + void set_zl_flag(bool is_zl); + void set_zh_flag(bool is_zh); + void set_cl_flag(bool is_cl); + void op_msk(int size); + void op_imsk(int size); + void op_and(int size); + void op_or(int size); + void op_xor(int size); + void op_add(int size); + void op_addb(int size); + void op_sub(int size); + void op_pushw(u16 source); + u16 op_popw(); address_space_config m_program_config; - address_space_config m_io_config; - uint32_t m_prev_pc; - uint16_t m_sp; - uint16_t m_ip; - uint8_t m_dsize; - uint8_t m_cseg; - uint8_t m_dseg; - uint8_t m_sseg; - uint8_t m_f; - uint16_t m_lar; - uint8_t m_reg[0x80]; - uint8_t m_temp1[0x10]; - uint8_t m_temp2[0x10]; + u32 m_prev_pc; + u16 m_sp; + u16 m_ip; + u8 m_dsize; + u8 m_cseg; + u8 m_dseg; + u8 m_sseg; + u8 m_f; + u16 m_lar; + u8 m_reg[0x80]; + u8 m_temp1[0x10]; + u8 m_temp2[0x10]; + u32 m_rtemp; address_space *m_program; - address_space *m_io; + int m_icount; + + devcb_write8 m_kol_cb; + devcb_write8 m_koh_cb; + devcb_read8 m_ki_cb; + devcb_read8 m_in0_cb; }; diff --git a/src/devices/cpu/hcd62121/hcd62121_ops.h b/src/devices/cpu/hcd62121/hcd62121_ops.h deleted file mode 100644 index 57c1f6b7d52..00000000000 --- a/src/devices/cpu/hcd62121/hcd62121_ops.h +++ /dev/null @@ -1,1022 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Wilbert Pol - -#define HCD62121_MSK \ - { \ - int i; \ - uint8_t mskres = 1; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - if ( ( m_temp1[i] & m_temp2[i] ) != m_temp2[i] ) \ - mskres = 0; \ - } \ - \ - if ( mskres ) \ - m_f &= ~_FLAG_Z; \ - else \ - m_f |= _FLAG_Z; \ - } - -#define HCD62121_IMSK \ - { \ - int i; \ - uint8_t mskres = 1; \ - uint8_t set_zero = 0; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - if ( ( m_temp1[i] & ~m_temp2[i] ) != ~m_temp2[i] ) \ - mskres = 0; \ - if ( m_temp1[i] | m_temp2[i] ) \ - set_zero = 1; \ - } \ - \ - if ( set_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( mskres ) \ - m_f &= ~_FLAG_C; \ - else \ - m_f |= _FLAG_C; \ - } - - -#define HCD62121_AND \ - { \ - int i; \ - uint8_t is_zero = 1; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - m_temp1[i] = m_temp1[i] & m_temp2[i]; \ - if ( m_temp1[i] ) \ - is_zero = 0; \ - } \ - \ - if ( is_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( m_temp1[0] & 0x0f ) \ - m_f &= ~_FLAG_ZL; \ - else \ - m_f |= _FLAG_ZL; \ - \ - if ( m_temp1[0] & 0xf0 ) \ - m_f &= ~_FLAG_ZH; \ - else \ - m_f |= _FLAG_ZH; \ - } - -#define HCD62121_OR \ - { \ - int i; \ - uint8_t is_zero = 1; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - m_temp1[i] = m_temp1[i] | m_temp2[i]; \ - if ( m_temp1[i] ) \ - is_zero = 0; \ - } \ - \ - if ( is_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( m_temp1[0] & 0x0f ) \ - m_f &= ~_FLAG_ZL; \ - else \ - m_f |= _FLAG_ZL; \ - \ - if ( m_temp1[0] & 0xf0 ) \ - m_f &= ~_FLAG_ZH; \ - else \ - m_f |= _FLAG_ZH; \ - } - -#define HCD62121_XOR \ - { \ - int i; \ - uint8_t is_zero = 1; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - m_temp1[i] = m_temp1[i] ^ m_temp2[i]; \ - if ( m_temp1[i] ) \ - is_zero = 0; \ - } \ - \ - if ( is_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( m_temp1[0] & 0x0f ) \ - m_f &= ~_FLAG_ZL; \ - else \ - m_f |= _FLAG_ZL; \ - \ - if ( m_temp1[0] & 0xf0 ) \ - m_f &= ~_FLAG_ZH; \ - else \ - m_f |= _FLAG_ZH; \ - } - -#define HCD62121_ADD \ - { \ - int i; \ - uint8_t is_zero = 1, carry = 0; \ - \ - if ( ( m_temp1[0] & 0x0f ) + ( m_temp2[0] & 0x0f ) > 15 ) \ - m_f |= _FLAG_CL; \ - else \ - m_f &= ~_FLAG_CL; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - uint16_t res = m_temp1[i] + m_temp2[i] + carry; \ - \ - m_temp1[i] = res & 0xff; \ - if ( m_temp1[i] ) \ - is_zero = 0; \ - \ - carry = ( res & 0xff00 ) ? 1 : 0; \ - } \ - \ - if ( is_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( carry ) \ - m_f |= _FLAG_C; \ - else \ - m_f &= ~_FLAG_C; \ - \ - if ( m_temp1[0] & 0x0f ) \ - m_f &= ~_FLAG_ZL; \ - else \ - m_f |= _FLAG_ZL; \ - \ - if ( m_temp1[0] & 0xf0 ) \ - m_f &= ~_FLAG_ZH; \ - else \ - m_f |= _FLAG_ZH; \ - } - -/* BCD ADD */ -#define HCD62121_ADDB \ - { \ - int i; \ - uint8_t is_zero = 1, carry = 0; \ - \ - if ( ( m_temp1[0] & 0x0f ) + ( m_temp2[0] & 0x0f ) > 9 ) \ - m_f |= _FLAG_CL; \ - else \ - m_f &= ~_FLAG_CL; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - uint16_t res = ( m_temp1[i] & 0x0f ) + ( m_temp2[i] & 0x0f ) + carry; \ - \ - if ( res > 9 ) \ - { \ - res += 6; \ - } \ - res += ( m_temp1[i] & 0xf0 ) + ( m_temp2[i] & 0xf0 ); \ - if ( res > 0x9f ) \ - { \ - res += 0x60; \ - } \ - m_temp1[i] = res & 0xff; \ - if ( m_temp1[i] ) \ - is_zero = 0; \ - \ - carry = ( res & 0xff00 ) ? 1 : 0; \ - } \ - \ - if ( is_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( carry ) \ - m_f |= _FLAG_C; \ - else \ - m_f &= ~_FLAG_C; \ - \ - if ( m_temp1[0] & 0x0f ) \ - m_f &= ~_FLAG_ZL; \ - else \ - m_f |= _FLAG_ZL; \ - \ - if ( m_temp1[0] & 0xf0 ) \ - m_f &= ~_FLAG_ZH; \ - else \ - m_f |= _FLAG_ZH; \ - } - -#define HCD62121_SUB \ - { \ - int i; \ - uint8_t is_zero = 1, carry = 0; \ - \ - if ( ( m_temp1[0] & 0x0f ) < ( m_temp2[0] & 0x0f ) ) \ - m_f |= _FLAG_CL; \ - else \ - m_f &= ~_FLAG_CL; \ - \ - for ( i = 0; i < size; i++ ) \ - { \ - uint16_t res = m_temp1[i] - m_temp2[i] - carry; \ - \ - m_temp1[i] = res & 0xff; \ - if ( m_temp1[i] ) \ - is_zero = 0; \ - \ - carry = ( res & 0xff00 ) ? 1 : 0; \ - } \ - \ - if ( is_zero ) \ - m_f |= _FLAG_Z; \ - else \ - m_f &= ~_FLAG_Z; \ - \ - if ( carry ) \ - m_f |= _FLAG_C; \ - else \ - m_f &= ~_FLAG_C; \ - \ - if ( m_temp1[0] & 0x0f ) \ - m_f &= ~_FLAG_ZL; \ - else \ - m_f |= _FLAG_ZL; \ - \ - if ( m_temp1[0] & 0xf0 ) \ - m_f &= ~_FLAG_ZH; \ - else \ - m_f |= _FLAG_ZH; \ - } - -#define HCD62121_PUSHW(source) \ - { \ - uint16_t address = source; \ - m_program->write_byte( ( m_sseg << 16 ) | m_sp, ( address ) & 0xff ); \ - m_sp--; \ - m_program->write_byte( ( m_sseg << 16 ) | m_sp, ( address ) >> 8 ); \ - m_sp--; \ - } - -#define HCD62121_POPW(dest) \ - { \ - uint16_t res; \ - m_sp++; \ - res = m_program->read_byte( ( m_sseg << 16 ) | m_sp ) << 8; \ - m_sp++; \ - res |= m_program->read_byte( ( m_sseg << 16 ) | m_sp ); \ - dest = res; \ - } - -case 0x04: /* mskb r1,r2 */ -case 0x05: /* mskw r1,r2 */ -case 0x06: /* mskq r1,r2 */ -case 0x07: /* mskt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_MSK; - } - break; - -case 0x08: /* shb r1,4 */ -case 0x09: /* shw r1,4 */ -case 0x0A: /* shq r1,4 */ -case 0x0B: /* sht r1,4 */ - /* Shift is a nibble shift! */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t d1 = 0, d2 = 0; - - read_reg( size, reg1 ); - - for ( i = 0; i < size; i++ ) - { - if ( reg1 & 0x80 ) - { - d1 = ( m_temp1[i] & 0x0f ) << 4; - m_temp1[i] = ( m_temp1[i] >> 4 ) | d2; - } - else - { - d1 = ( m_temp1[i] & 0xf0 ) >> 4; - m_temp1[i] = ( m_temp1[i] << 4 ) | d2; - } - d2 = d1; - } - - write_reg( size, reg1 ); - } - break; - -case 0x0C: /* testb r1,r2 */ -case 0x0D: /* testw r1,r2 */ -case 0x0E: /* testq r1,r2 */ -case 0x0F: /* testt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_AND; - } - break; - -case 0x10: /* xorb r1,r2 */ -case 0x11: /* xorw r1,r2 */ -case 0x12: /* xorq r1,r2 */ -case 0x13: /* xort r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_XOR; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x14: /* cmpb r1,r2 */ -case 0x15: /* cmpw r1,r2 */ -case 0x16: /* cmpq r1,r2 */ -case 0x17: /* cmpt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_SUB; - } - break; - -case 0x18: /* movb r1,r2 */ -case 0x19: /* movw r1,r2 */ -case 0x1A: /* movq r1,r2 */ -case 0x1B: /* movt r1,r2 */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - for ( i = 0; i < size; i++ ) - m_temp1[i] = m_temp2[i]; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x1C: /* imskb r1,r2 */ -case 0x1D: /* imskw r1,r2 */ -case 0x1E: /* imskq r1,r2 */ -case 0x1F: /* imskt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_IMSK; - } - break; - -case 0x20: /* shrb r1 */ -case 0x21: /* shrw r1 */ -case 0x22: /* shrq r1 */ -case 0x23: /* shrt r1 */ - /* Shift is a single shift! */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t d1 = 0, d2 = 0; - - read_reg( size, reg1 ); - - for ( i = 0; i < size; i++ ) - { - d1 = ( m_temp1[i] & 0x01 ) << 7; - m_temp1[i] = ( m_temp1[i] >> 1 ) | d2; - d2 = d1; - } - - write_reg( size, reg1 ); - } - break; - -case 0x24: /* orb r1,r2 */ -case 0x25: /* orw r1,r2 */ -case 0x26: /* orq r1,r2 */ -case 0x27: /* ort r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_OR; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x28: /* shlb r1 */ -case 0x29: /* shlw r1 */ -case 0x2A: /* shlq r1 */ -case 0x2B: /* shlt r1 */ - /* Shift is a single shift! */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t d1 = 0, d2 = 0; - - read_reg( size, reg1 ); - - for ( i = 0; i < size; i++ ) - { - d1 = ( m_temp1[i] & 0x80 ) >> 7; - m_temp1[i] = ( m_temp1[i] << 1 ) | d2; - d2 = d1; - } - - write_reg( size, reg1 ); - } - break; - -case 0x2C: /* andb r1,r2 */ -case 0x2D: /* andw r1,r2 */ -case 0x2E: /* andq r1,r2 */ -case 0x2F: /* andt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, true ); - - HCD62121_AND; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x34: /* subb r1,r2 */ -case 0x35: /* subw r1,r2 */ -case 0x36: /* subq r1,r2 */ -case 0x37: /* subt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_SUB; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x38: /* adbb r1,r2 */ -case 0x39: /* adbw r1,r2 */ -case 0x3A: /* adbq r1,r2 */ -case 0x3B: /* adbt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_ADDB; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x3C: /* addb r1,r2 */ -case 0x3D: /* addw r1,r2 */ -case 0x3E: /* addq r1,r2 */ -case 0x3F: /* addt r1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_regreg( size, reg1, reg2, false ); - - HCD62121_ADD; - - write_regreg( size, reg1, reg2 ); - } - break; - -case 0x4C: /* testb ir1,r2 */ -case 0x4D: /* testw ir1,r2 */ -case 0x4E: /* testq ir1,r2 */ -case 0x4F: /* testt ir1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - HCD62121_AND; - } - break; - -case 0x54: /* cmpb ir1,r2 */ -case 0x55: /* cmpw ir1,r2 */ -case 0x56: /* cmpq ir1,r2 */ -case 0x57: /* cmpt ir1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - HCD62121_SUB; - } - break; - -case 0x58: /* movb ir1,r2 */ -case 0x59: /* movw ir1,r2 */ -case 0x5A: /* movq ir1,r2 */ -case 0x5B: /* movt ir1,r2 */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - for ( i = 0; i < size; i++ ) - m_temp1[i] = m_temp2[i]; - - write_iregreg( size, reg1, reg2 ); - } - break; - -case 0x64: /* orb ir1,r2 */ -case 0x65: /* orb ir1,r2 */ -case 0x66: /* orb ir1,r2 */ -case 0x67: /* orb ir1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - HCD62121_OR; - - write_iregreg( size, reg1, reg2 ); - } - break; - -case 0x6C: /* andb ir1,r2 */ -case 0x6D: /* andw ir1,r2 */ -case 0x6E: /* andq ir1,r2 */ -case 0x6F: /* andt ir1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - HCD62121_AND; - - write_iregreg( size, reg1, reg2 ); - } - break; - -case 0x7C: /* addb ir1,r2 */ -case 0x7D: /* addw ir1,r2 */ -case 0x7E: /* addq ir1,r2 */ -case 0x7F: /* addt ir1,r2 */ - { - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - HCD62121_ADD; - - write_iregreg( size, reg1, reg2 ); - } - break; - -case 0x88: /* jump _a16 */ - m_ip = ( read_op() << 8 ) | read_op(); - break; - -case 0x89: /* jumpf cs:a16 */ - { - uint8_t cs = read_op(); - uint8_t a1 = read_op(); - uint8_t a2 = read_op(); - - m_cseg = cs; - m_ip = ( a1 << 8 ) | a2; - } - break; - -case 0x8A: /* call a16 */ - { - uint8_t a1 = read_op(); - uint8_t a2 = read_op(); - - HCD62121_PUSHW( m_ip ); - - m_ip = ( a1 << 8 ) | a2; - } - break; - -case 0x8C: /* unk_8C */ -case 0x8D: /* unk_8D */ -case 0x8E: /* unk_8E */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - break; - -case 0x90: /* retzh */ -case 0x91: /* retzl */ -case 0x92: /* retc */ -case 0x93: /* retz */ -case 0x94: /* retzc */ -case 0x95: /* retcl */ -case 0x96: /* retnc */ -case 0x97: /* retnz */ - if ( check_cond( op ) ) - HCD62121_POPW( m_ip ); - break; - -case 0x98: /* jump (r1) */ - { - uint8_t reg1 = read_op(); - uint16_t ad = m_reg[ ( reg1 | 0x40 ) & 0x7f ] << 8; - - if ( reg1 & 0x40 ) - ad |= m_reg[ ( ( reg1 - 1 ) | 0x40 ) & 0x7f ]; - else - ad |= m_reg[ ( ( reg1 + 1 ) | 0x40 ) & 0x7f ]; - - m_ip = ad; - } - break; - -case 0x9F: /* ret */ - HCD62121_POPW( m_ip ); - break; - -case 0xA0: /* jmpzh a16 */ -case 0xA1: /* jmpzl a16 */ -case 0xA2: /* jmpc a16 */ -case 0xA3: /* jmpz a16 */ -case 0xA4: /* jmpzc a16 */ -case 0xA5: /* jmpcl a16 */ -case 0xA6: /* jmpnc a16 */ -case 0xA7: /* jmpnz a16 */ - { - uint8_t a1 = read_op(); - uint8_t a2 = read_op(); - - if ( check_cond( op ) ) - m_ip = ( a1 << 8 ) | a2; - } - break; - -case 0xA8: /* callzh a16 */ -case 0xA9: /* callzl a16 */ -case 0xAA: /* callc a16 */ -case 0xAB: /* callz a16 */ -case 0xAC: /* callzc a16 */ -case 0xAD: /* callcl a16 */ -case 0xAE: /* callnc a16 */ -case 0xAF: /* callnz a16 */ - { - uint8_t a1 = read_op(); - uint8_t a2 = read_op(); - - if ( check_cond( op ) ) - { - HCD62121_PUSHW( m_ip ); - - m_ip = ( a1 << 8 ) | a2; - } - } - break; - -case 0xB1: /* unk_B1 reg/i8 */ -case 0xB3: /* unk_B3 reg/i8 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - read_op(); - break; - -case 0xB4: /* out koh,reg */ - m_io->write_byte( HCD62121_KOH, m_reg[ read_op() & 0x7f ] ); - break; - -case 0xB5: /* out koh,i8 */ - m_io->write_byte( HCD62121_KOH, read_op() ); - break; - -case 0xB6: /* out kol,reg */ - m_io->write_byte( HCD62121_KOL, m_reg[ read_op() & 0x7f ] ); - break; - -case 0xB7: /* out kol,i8 */ - m_io->write_byte( HCD62121_KOL, read_op() ); - break; - -case 0xB9: /* unk_B9 reg/i8 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - read_op(); - break; - -case 0xBB: /* jmpcl? a16 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - { - uint8_t a1 = read_op(); - uint8_t a2 = read_op(); - - if ( m_f & _FLAG_CL ) - m_ip = ( a1 << 8 ) | a2; - } - break; - -case 0xBF: /* jmpncl? a16 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - { - uint8_t a1 = read_op(); - uint8_t a2 = read_op(); - - if ( ! ( m_f & _FLAG_CL ) ) - m_ip = ( a1 << 8 ) | a2; - } - break; - -case 0xC0: /* movb reg,i8 */ -case 0xC1: /* movw reg,i16 */ -case 0xC2: /* movw reg,i64 */ -case 0xC3: /* movw reg,i80 */ - { - int i; - int size = datasize( op ); - uint8_t reg = read_op(); - - for( i = 0; i < size; i++ ) - { - m_reg[(reg + i) & 0x7f] = read_op(); - } - } - break; - -case 0xC4: /* movb (lar),r1 / r1,(lar) */ -case 0xC5: /* movw (lar),r1 / r1,(lar) */ -case 0xC6: /* movq (lar),r1 / r1,(lar) */ -case 0xC7: /* movt (lar),r1 / r1,(lar) */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - int pre_inc = 0; - int post_inc = 1; - - switch( reg1 & 0x60 ) - { - case 0x00: - pre_inc = 0; - post_inc = 1; - break; - case 0x20: - pre_inc = 1; - post_inc = 0; - break; - case 0x40: - pre_inc = 0; - post_inc = -1; - break; - case 0x60: - pre_inc = -1; - post_inc = 0; - break; - } - - if ( ( reg1 & 0x80 ) || ( reg2 & 0x80 ) ) - { - /* (lar) <- r1 */ - for ( i = 0; i < size; i++ ) - { - m_lar += pre_inc; - m_program->write_byte( ( m_dseg << 16 ) | m_lar, m_reg[ ( reg2 + i ) & 0x7f ] ); - m_lar += post_inc; - } - } - else - { - /* r1 <- (lar) */ - for ( i = 0; i < size; i++ ) - { - m_lar += pre_inc; - m_reg[ ( reg2 + i ) & 0x7f ] = m_program->read_byte( ( m_dseg << 16 ) | m_lar ); - m_lar += post_inc; - } - } - } - break; - -case 0xCC: /* swapb ir1,r2 */ -case 0xCD: /* swapw ir1,r2 */ -case 0xCE: /* swapq ir1,r2 */ -case 0xCF: /* swapt ir1,r2? */ - { - int i; - int size = datasize( op ); - uint8_t reg1 = read_op(); - uint8_t reg2 = read_op(); - - read_iregreg( size, reg1, reg2 ); - - for ( i = 0; i < size; i++ ) - { - uint8_t d = m_temp1[i]; - m_temp1[i] = m_temp2[i]; - m_temp2[i] = d; - } - - write_iregreg( size, reg1, reg2 ); - write_iregreg2( size, reg1, reg2 ); - } - break; - -case 0xD0: /* movb cs,reg */ - m_cseg = m_reg[ read_op() & 0x7f ]; - break; - -case 0xD1: /* movb cs,i8 */ - m_cseg = read_op(); - break; - -case 0xD2: /* movb dsize,reg */ - m_dsize = m_reg[ read_op() & 0x7f ]; - break; - -case 0xD3: /* movb dsize,i8 */ - m_dsize = read_op(); - break; - -case 0xD4: /* movb ss,reg */ - m_sseg = m_reg[ read_op() & 0x7f ]; - break; - -case 0xD5: /* movb ss,i8 */ - m_sseg = read_op(); - break; - -case 0xD6: /* movw sp,reg */ - { - uint8_t reg1 = read_op(); - - m_sp = m_reg[ reg1 & 0x7f ] | ( m_reg[ ( reg1 + 1 ) & 0x7f ] << 8 ); - } - break; - -case 0xD7: /* movw sp,i16 */ - m_sp = read_op() << 8; - m_sp |= read_op(); - break; - -case 0xD8: /* movb f,reg */ - m_f = m_reg[ read_op() & 0x7f ]; - break; - -case 0xD9: /* movb f,i8 */ - m_f = read_op(); - break; - -case 0xDC: /* movb ds,reg */ - m_dseg = m_reg[ read_op() & 0x7f ]; - break; - -case 0xDD: /* movb ds,i8 */ - m_dseg = read_op(); - break; - -case 0xDE: /* movw lar,reg */ - { - uint8_t reg1 = read_op(); - - m_lar = m_reg[ reg1 & 0x7f ] | ( m_reg[ ( reg1 + 1 ) & 0x7f ] << 8 ); - } - break; - -case 0xE0: /* in0 reg */ - { - uint8_t reg1 = read_op(); - - m_reg[ reg1 & 0x7f ] = m_io->read_byte( HCD62121_IN0 ); - } - break; - -case 0xE1: /* unk_E1 reg/i8 (in?) */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - read_op(); - break; - -case 0xE2: /* in kb, reg */ - m_reg[ read_op() & 0x7f ] = m_io->read_byte( HCD62121_KI ); - break; - -case 0xE3: /* unk_e3 reg/i8 (in?) */ -case 0xE4: /* unk_e4 reg/i8 (in?) */ -case 0xE5: /* unk_e5 reg/i8 (in?) */ -case 0xE6: /* unk_e6 reg/i8 (in?) */ -case 0xE7: /* unk_e7 reg/i8 (in?) */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - read_op(); - break; - -case 0xE8: /* movw r1,lar */ - { - uint8_t reg1 = read_op(); - - m_reg[ reg1 & 0x7f ] = m_lar & 0xff; - m_reg[ ( reg1 + 1 ) & 0x7f ] = m_lar >> 8; - } - break; - -case 0xEB: /* movw reg,ss */ - { - uint8_t reg1 = read_op(); - - m_reg[ reg1 & 0x7f ] = m_sp & 0xff; - m_reg[ ( reg1 + 1 ) & 0x7f ] = m_sp >> 8; - } - break; - -case 0xEF: /* movb reg,ss */ - m_reg[ read_op() & 0x7f ] = m_sseg; - break; - -case 0xF0: /* unk_F0 reg/i8 (out?) */ -case 0xF1: /* unk_F1 reg/i8 (out?) */ -case 0xF2: /* unk_F2 reg/i8 (out?) */ -case 0xF3: /* unk_F3 reg/i8 (out?) */ -case 0xF4: /* unk_F4 reg/i8 (out?) */ -case 0xF5: /* unk_F5 reg/i8 (out?) */ -case 0xF6: /* unk_F6 reg/i8 (out?) */ -case 0xF7: /* unk_F7 reg/i8 (out?) */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - read_op(); - break; - -case 0xFC: /* unk_FC */ -case 0xFD: /* unk_FD */ -case 0xFE: /* unk_FE */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); - break; - -case 0xFF: /* nop */ - break; - -default: - /*logerror*/fatalerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); diff --git a/src/devices/cpu/hcd62121/hcd62121d.cpp b/src/devices/cpu/hcd62121/hcd62121d.cpp index d355385f793..5c85f193224 100644 --- a/src/devices/cpu/hcd62121/hcd62121d.cpp +++ b/src/devices/cpu/hcd62121/hcd62121d.cpp @@ -2,139 +2,214 @@ // copyright-holders:Wilbert Pol #include "emu.h" -#include "debugger.h" -#include "hcd62121.h" - -#ifdef _MSC_VER -#undef _SP -#endif enum { - _REG=1, /* register */ - _REGREG, /* register1, register2, or register2, register1 or register1, imm byte */ - _IRG, /* register indirect */ - _IRGREG, /* 2 register indirect */ - _A16, /* 16bit address */ - _A24, /* seg:address */ - _F, /* flag register */ - _CS, /* cs register */ - _DS, /* ds register */ - _SS, /* ss register */ - _PC, /* program counter */ - _SP, /* stack pointer */ - _I8, /* immediate 8 bit value */ - _I16, /* immediate 16 bit value */ - _I64, /* immediate 64 bit value */ - _I80, /* immediate 80 bit value */ - _ILR, /* indirect last address register access */ - _LAR, /* last address register */ - _DSZ, /* dsize register? */ - _TIM, /* timing related register? */ - _KLO, /* KO1 - KO8 output lines */ - _KHI, /* KO9 - KO14(?) output lines */ - _KI, /* K input lines */ - _4 /* for nibble shifts */ + ARG_NONE=0, /* no argument or unknown */ + ARG_REG, /* register */ + ARG_REGREG, /* register1, register2, or register2, register1 or register1, imm byte */ + ARG_IRG, /* register indirect */ + ARG_IRGREG, /* 2 register indirect */ + ARG_A16, /* 16bit address */ + ARG_A24, /* seg:address */ + ARG_F, /* flag register */ + ARG_CS, /* cs register */ + ARG_DS, /* ds register */ + ARG_SS, /* ss register */ + ARG_PC, /* program counter */ + ARG_SP, /* stack pointer */ + ARG_I8, /* immediate 8 bit value */ + ARG_I16, /* immediate 16 bit value */ + ARG_I64, /* immediate 64 bit value */ + ARG_I80, /* immediate 80 bit value */ + ARG_ILR, /* indirect last address register access */ + ARG_LAR, /* last address register */ + ARG_DSZ, /* dsize register? */ + ARG_TIM, /* timing related register? */ + ARG_KLO, /* KO1 - KO8 output lines */ + ARG_KHI, /* KO9 - KO14(?) output lines */ + ARG_KI, /* K input lines */ + ARG_4 /* for nibble shifts */ }; struct hcd62121_dasm { const char *str; - uint8_t arg1; - uint8_t arg2; + u8 arg1; + u8 arg2; }; static const hcd62121_dasm hcd62121_ops[256] = { /* 0x00 */ - { "un00?", 0, 0 }, { "un01?", 0, 0 }, { "un02?", 0, 0 }, { "un03?", 0, 0 }, - { "mskb", _REGREG, 0 }, { "mskw", _REGREG, 0 }, { "mskq", _REGREG, 0 }, { "mskt", _REGREG, 0 }, - { "sh?b", _REG, _4 }, { "sh?w", _REG, _4 }, { "sh?q", _REG, _4 }, { "sh?t", _REG, _4 }, - { "tstb", _REGREG, 0 }, { "tstw", _REGREG, 0 }, { "tstq", _REGREG, 0 }, { "tstt", _REGREG, 0 }, - { "xorb", _REGREG, 0 }, { "xorw", _REGREG, 0 }, { "xorq", _REGREG, 0 }, { "xort", _REGREG, 0 }, - { "cmpb", _REGREG, 0 }, { "cmpw", _REGREG, 0 }, { "cmpq", _REGREG, 0 }, { "cmpt", _REGREG, 0 }, - { "movb", _REGREG, 0 }, { "movw", _REGREG, 0 }, { "movq", _REGREG, 0 }, { "movt", _REGREG, 0 }, - { "imskb", _REGREG, 0 }, { "imskw", _REGREG, 0 }, { "imskq", _REGREG, 0 }, { "imskt", _REGREG, 0 }, + { "un00?", ARG_NONE, ARG_NONE }, { "un01?", ARG_NONE, ARG_NONE }, + { "un02?", ARG_NONE, ARG_NONE }, { "un03?", ARG_NONE, ARG_NONE }, + { "mskb", ARG_REGREG, ARG_NONE }, { "mskw", ARG_REGREG, ARG_NONE }, + { "mskq", ARG_REGREG, ARG_NONE }, { "mskt", ARG_REGREG, ARG_NONE }, + { "sh?b", ARG_REG, ARG_4 }, { "sh?w", ARG_REG, ARG_4 }, + { "sh?q", ARG_REG, ARG_4 }, { "sh?t", ARG_REG, ARG_4 }, + { "tstb", ARG_REGREG, ARG_NONE }, { "tstw", ARG_REGREG, ARG_NONE }, + { "tstq", ARG_REGREG, ARG_NONE }, { "tstt", ARG_REGREG, ARG_NONE }, + + /* 0x10 */ + { "xorb", ARG_REGREG, ARG_NONE }, { "xorw", ARG_REGREG, ARG_NONE }, + { "xorq", ARG_REGREG, ARG_NONE }, { "xort", ARG_REGREG, ARG_NONE }, + { "cmpb", ARG_REGREG, ARG_NONE }, { "cmpw", ARG_REGREG, ARG_NONE }, + { "cmpq", ARG_REGREG, ARG_NONE }, { "cmpt", ARG_REGREG, ARG_NONE }, + { "movb", ARG_REGREG, ARG_NONE }, { "movw", ARG_REGREG, ARG_NONE }, + { "movq", ARG_REGREG, ARG_NONE }, { "movt", ARG_REGREG, ARG_NONE }, + { "imskb", ARG_REGREG, ARG_NONE }, { "imskw", ARG_REGREG, ARG_NONE }, + { "imskq", ARG_REGREG, ARG_NONE }, { "imskt", ARG_REGREG, ARG_NONE }, /* 0x20 */ - { "shrb", _REG, 0 }, { "shrw", _REG, 0 }, { "shrq", _REG, 0 }, { "shrt", _REG, 0 }, - { "orb", _REGREG, 0 }, { "orw", _REGREG, 0 }, { "orq", _REGREG, 0 }, { "ort", _REGREG, 0 }, - { "shlb", _REG, 0 }, { "shlw", _REG, 0 }, { "shlq", _REG, 0 }, { "shlt", _REG, 0 }, - { "andb", _REGREG, 0 }, { "andw", _REGREG, 0 }, { "andq", _REGREG, 0 }, { "andt", _REGREG, 0 }, - { "sbbb", _REGREG, 0 }, { "sbbw", _REGREG, 0 }, { "sbbq", _REGREG, 0 }, { "sbbt", _REGREG, 0 }, /* BCD SUB */ - { "subb", _REGREG, 0 }, { "subw", _REGREG, 0 }, { "subq", _REGREG, 0 }, { "subt", _REGREG, 0 }, - { "adbb", _REGREG, 0 }, { "adbw", _REGREG, 0 }, { "adbq", _REGREG, 0 }, { "adbt", _REGREG, 0 }, /* BCD ADD */ - { "addb", _REGREG, 0 }, { "addw", _REGREG, 0 }, { "addq", _REGREG, 0 }, { "addt", _REGREG, 0 }, + { "shrb", ARG_REG, ARG_NONE }, { "shrw", ARG_REG, ARG_NONE }, + { "shrq", ARG_REG, ARG_NONE }, { "shrt", ARG_REG, ARG_NONE }, + { "orb", ARG_REGREG, ARG_NONE }, { "orw", ARG_REGREG, ARG_NONE }, + { "orq", ARG_REGREG, ARG_NONE }, { "ort", ARG_REGREG, ARG_NONE }, + { "shlb", ARG_REG, ARG_NONE }, { "shlw", ARG_REG, ARG_NONE }, + { "shlq", ARG_REG, ARG_NONE }, { "shlt", ARG_REG, ARG_NONE }, + { "andb", ARG_REGREG, ARG_NONE }, { "andw", ARG_REGREG, ARG_NONE }, + { "andq", ARG_REGREG, ARG_NONE }, { "andt", ARG_REGREG, ARG_NONE }, + + /* 0x30 */ + { "sbbb", ARG_REGREG, ARG_NONE }, { "sbbw", ARG_REGREG, ARG_NONE }, /* BCD SUB */ + { "sbbq", ARG_REGREG, ARG_NONE }, { "sbbt", ARG_REGREG, ARG_NONE }, /* BCD SUB */ + { "subb", ARG_REGREG, ARG_NONE }, { "subw", ARG_REGREG, ARG_NONE }, + { "subq", ARG_REGREG, ARG_NONE }, { "subt", ARG_REGREG, ARG_NONE }, + { "adbb", ARG_REGREG, ARG_NONE }, { "adbw", ARG_REGREG, ARG_NONE }, /* BCD ADD */ + { "adbq", ARG_REGREG, ARG_NONE }, { "adbt", ARG_REGREG, ARG_NONE }, /* BCD ADD */ + { "addb", ARG_REGREG, ARG_NONE }, { "addw", ARG_REGREG, ARG_NONE }, + { "addq", ARG_REGREG, ARG_NONE }, { "addt", ARG_REGREG, ARG_NONE }, /* 0x40 */ - { "shrb?", _IRG, 0 }, { "shrw?", _IRG, 0 }, { "shrq?", _IRG, 0 }, { "shrt?", _IRG, 0 }, - { "mskb", _IRGREG, 0 }, { "mskw", _IRGREG, 0 }, { "mskq", _IRGREG, 0 }, { "mskt", _IRGREG, 0 }, - { "shrb", _IRG, 0 }, { "shrw", _IRG, 0 }, { "shrq", _IRG, 0 }, { "shrt", _IRG, 0 }, - { "tstb", _IRGREG, 0 }, { "tstw", _IRGREG, 0 }, { "tstq", _IRGREG, 0 }, { "tstt", _IRGREG, 0 }, - { "xorb", _IRGREG, 0 }, { "xorw", _IRGREG, 0 }, { "xorq", _IRGREG, 0 }, { "xort", _IRGREG, 0 }, - { "cmpb", _IRGREG, 0 }, { "cmpw", _IRGREG, 0 }, { "cmpq", _IRGREG, 0 }, { "cmpt", _IRGREG, 0 }, - { "movb", _IRGREG, 0 }, { "movw", _IRGREG, 0 }, { "movq", _IRGREG, 0 }, { "movt", _IRGREG, 0 }, - { "imskb", _IRGREG, 0 }, { "imskw", _IRGREG, 0 }, { "imskq", _IRGREG, 0 }, { "imskt", _IRGREG, 0 }, + { "shrb?", ARG_IRG, ARG_NONE }, { "shrw?", ARG_IRG, ARG_NONE }, + { "shrq?", ARG_IRG, ARG_NONE }, { "shrt?", ARG_IRG, ARG_NONE }, + { "mskb", ARG_IRGREG, ARG_NONE }, { "mskw", ARG_IRGREG, ARG_NONE }, + { "mskq", ARG_IRGREG, ARG_NONE }, { "mskt", ARG_IRGREG, ARG_NONE }, + { "shrb", ARG_IRG, ARG_NONE }, { "shrw", ARG_IRG, ARG_NONE }, + { "shrq", ARG_IRG, ARG_NONE }, { "shrt", ARG_IRG, ARG_NONE }, + { "tstb", ARG_IRGREG, ARG_NONE }, { "tstw", ARG_IRGREG, ARG_NONE }, + { "tstq", ARG_IRGREG, ARG_NONE }, { "tstt", ARG_IRGREG, ARG_NONE }, + + /* 0x50 */ + { "xorb", ARG_IRGREG, ARG_NONE }, { "xorw", ARG_IRGREG, ARG_NONE }, + { "xorq", ARG_IRGREG, ARG_NONE }, { "xort", ARG_IRGREG, ARG_NONE }, + { "cmpb", ARG_IRGREG, ARG_NONE }, { "cmpw", ARG_IRGREG, ARG_NONE }, + { "cmpq", ARG_IRGREG, ARG_NONE }, { "cmpt", ARG_IRGREG, ARG_NONE }, + { "movb", ARG_IRGREG, ARG_NONE }, { "movw", ARG_IRGREG, ARG_NONE }, + { "movq", ARG_IRGREG, ARG_NONE }, { "movt", ARG_IRGREG, ARG_NONE }, + { "imskb", ARG_IRGREG, ARG_NONE }, { "imskw", ARG_IRGREG, ARG_NONE }, + { "imskq", ARG_IRGREG, ARG_NONE }, { "imskt", ARG_IRGREG, ARG_NONE }, /* 0x60 */ - { "shrb", _IRG, 0 }, { "shrw", _IRG, 0 }, { "shrq", _IRG, 0 }, { "shrt", _IRG, 0 }, - { "orb", _IRGREG, 0 }, { "orw", _IRGREG, 0 }, { "orq", _IRGREG, 0 }, { "ort", _IRGREG, 0 }, - { "shlb", _IRG, 0 }, { "shlw", _IRG, 0 }, { "shlq", _IRG, 0 }, { "shlt", _IRG, 0 }, - { "andb", _IRGREG, 0 }, { "andw", _IRGREG, 0 }, { "andq", _IRGREG, 0 }, { "andt", _IRGREG, 0 }, - { "sbbb", _IRGREG, 0 }, { "sbbw", _IRGREG, 0 }, { "sbbq", _IRGREG, 0 }, { "sbbt", _IRGREG, 0 }, /* BCD SUB */ - { "subb", _IRGREG, 0 }, { "subw", _IRGREG, 0 }, { "subq", _IRGREG, 0 }, { "subt", _IRGREG, 0 }, - { "adbb", _IRGREG, 0 }, { "adbw", _IRGREG, 0 }, { "adbq", _IRGREG, 0 }, { "adbt", _IRGREG, 0 }, /* BCD ADD */ - { "addb", _IRGREG, 0 }, { "addw", _IRGREG, 0 }, { "addq", _IRGREG, 0 }, { "addt", _IRGREG, 0 }, + { "shrb", ARG_IRG, ARG_NONE }, { "shrw", ARG_IRG, ARG_NONE }, + { "shrq", ARG_IRG, ARG_NONE }, { "shrt", ARG_IRG, ARG_NONE }, + { "orb", ARG_IRGREG, ARG_NONE }, { "orw", ARG_IRGREG, ARG_NONE }, + { "orq", ARG_IRGREG, ARG_NONE }, { "ort", ARG_IRGREG, ARG_NONE }, + { "shlb", ARG_IRG, ARG_NONE }, { "shlw", ARG_IRG, ARG_NONE }, + { "shlq", ARG_IRG, ARG_NONE }, { "shlt", ARG_IRG, ARG_NONE }, + { "andb", ARG_IRGREG, ARG_NONE }, { "andw", ARG_IRGREG, ARG_NONE }, + { "andq", ARG_IRGREG, ARG_NONE }, { "andt", ARG_IRGREG, ARG_NONE }, + + /* 0x70 */ + { "sbbb", ARG_IRGREG, ARG_NONE }, { "sbbw", ARG_IRGREG, ARG_NONE }, /* BCD SUB */ + { "sbbq", ARG_IRGREG, ARG_NONE }, { "sbbt", ARG_IRGREG, ARG_NONE }, /* BCD SUB */ + { "subb", ARG_IRGREG, ARG_NONE }, { "subw", ARG_IRGREG, ARG_NONE }, + { "subq", ARG_IRGREG, ARG_NONE }, { "subt", ARG_IRGREG, ARG_NONE }, + { "adbb", ARG_IRGREG, ARG_NONE }, { "adbw", ARG_IRGREG, ARG_NONE }, /* BCD ADD */ + { "adbq", ARG_IRGREG, ARG_NONE }, { "adbt", ARG_IRGREG, ARG_NONE }, /* BCD ADD */ + { "addb", ARG_IRGREG, ARG_NONE }, { "addw", ARG_IRGREG, ARG_NONE }, + { "addq", ARG_IRGREG, ARG_NONE }, { "addt", ARG_IRGREG, ARG_NONE }, /* 0x80 */ - { "un80?", 0, 0 }, { "un81?", 0, 0 }, { "un82?", 0, 0 }, { "un83?", 0, 0 }, - { "un84?", 0, 0 }, { "un85?", 0, 0 }, { "un86?", 0, 0 }, { "un87?", 0, 0 }, - { "jump", _A16, 0 }, { "jump", _A24, 0 }, { "call", _A16, 0 }, { "un8b?", 0, 0 }, - { "un8C?", 0, 0 }, { "un8D?", 0, 0 }, { "un8E?", 0, 0 }, { "un8F?", 0, 0 }, - { "retzh", 0, 0 }, { "retzl", 0, 0 }, { "retc", 0, 0 }, { "retz", 0, 0 }, - { "retzc", 0, 0 }, { "retcl", 0, 0 }, { "retnc", 0, 0 }, { "retnz", 0, 0 }, - { "jump", _IRG, 0 }, { "un99?", 0, 0 }, { "un9A?", 0, 0 }, { "un9b?", 0, 0 }, - { "un9C?", 0, 0 }, { "un9D?", 0, 0 }, { "reti", 0, 0 }, { "ret", 0, 0 }, + { "un80?", ARG_NONE, ARG_NONE }, { "un81?", ARG_NONE, ARG_NONE }, + { "un82?", ARG_NONE, ARG_NONE }, { "un83?", ARG_NONE, ARG_NONE }, + { "un84?", ARG_NONE, ARG_NONE }, { "un85?", ARG_NONE, ARG_NONE }, + { "un86?", ARG_NONE, ARG_NONE }, { "un87?", ARG_NONE, ARG_NONE }, + { "jump", ARG_A16, ARG_NONE }, { "jump", ARG_A24, ARG_NONE }, + { "call", ARG_A16, ARG_NONE }, { "un8b?", ARG_NONE, ARG_NONE }, + { "un8C?", ARG_NONE, ARG_NONE }, { "un8D?", ARG_NONE, ARG_NONE }, + { "un8E?", ARG_NONE, ARG_NONE }, { "un8F?", ARG_NONE, ARG_NONE }, + + /* 0x90 */ + { "retzh", ARG_NONE, ARG_NONE }, { "retzl", ARG_NONE, ARG_NONE }, + { "retc", ARG_NONE, ARG_NONE }, { "retz", ARG_NONE, ARG_NONE }, + { "retzc", ARG_NONE, ARG_NONE }, { "retcl", ARG_NONE, ARG_NONE }, + { "retnc", ARG_NONE, ARG_NONE }, { "retnz", ARG_NONE, ARG_NONE }, + { "jump", ARG_IRG, ARG_NONE }, { "un99?", ARG_NONE, ARG_NONE }, + { "un9A?", ARG_NONE, ARG_NONE }, { "un9b?", ARG_NONE, ARG_NONE }, + { "un9C?", ARG_NONE, ARG_NONE }, { "un9D?", ARG_NONE, ARG_NONE }, + { "reti", ARG_NONE, ARG_NONE }, { "ret", ARG_NONE, ARG_NONE }, /* 0xa0 */ - { "jmpzh", _A16, 0 }, { "jmpzl", _A16, 0 }, { "jmpc", _A16, 0 }, { "jmpz", _A16, 0 }, - { "jmpzc", _A16, 0 }, { "jmpcl", _A16, 0 }, { "jmpnc", _A16, 0 }, { "jmpnz", _A16, 0 }, - { "callzh", _A16, 0 }, { "callzl", _A16, 0 }, { "callc", _A16, 0 }, { "callz", _A16, 0 }, - { "callzc", _A16, 0 }, { "callcl", _A16, 0 }, { "callnc", _A16, 0 }, { "callnz", _A16, 0 }, - { "unB0?", 0, 0 }, { "unB1?", _I8, 0 }, { "unB2?", 0, 0 }, { "unB3?", _I8, 0 }, - { "out", _KHI, _REG }, { "out", _KHI, _I8 }, { "out", _KLO, _REG }, { "out", _KLO, _I8 }, - { "unB8?", 0, 0 }, { "unB9?", _I8, 0 }, { "unBA?", 0, 0 }, { "jmpcl?", _A16, 0 }, - { "unBC?", 0, 0 }, { "unBD?", 0, 0 }, { "unBE?", 0, 0 }, { "jmpncl?", _A16, 0 }, + { "jmpzh", ARG_A16, ARG_NONE }, { "jmpzl", ARG_A16, ARG_NONE }, + { "jmpc", ARG_A16, ARG_NONE }, { "jmpz", ARG_A16, ARG_NONE }, + { "jmpzc", ARG_A16, ARG_NONE }, { "jmpcl", ARG_A16, ARG_NONE }, + { "jmpnc", ARG_A16, ARG_NONE }, { "jmpnz", ARG_A16, ARG_NONE }, + { "callzh", ARG_A16, ARG_NONE }, { "callzl", ARG_A16, ARG_NONE }, + { "callc", ARG_A16, ARG_NONE }, { "callz", ARG_A16, ARG_NONE }, + { "callzc", ARG_A16, ARG_NONE }, { "callcl", ARG_A16, ARG_NONE }, + { "callnc", ARG_A16, ARG_NONE }, { "callnz", ARG_A16, ARG_NONE }, + + /* 0xb0 */ + { "unB0?", ARG_NONE, ARG_NONE }, { "unB1?", ARG_I8, ARG_NONE }, + { "unB2?", ARG_NONE, ARG_NONE }, { "unB3?", ARG_I8, ARG_NONE }, + { "out", ARG_KHI, ARG_REG }, { "out", ARG_KHI, ARG_I8 }, + { "out", ARG_KLO, ARG_REG }, { "out", ARG_KLO, ARG_I8 }, + { "unB8?", ARG_NONE, ARG_NONE }, { "unB9?", ARG_I8, ARG_NONE }, + { "unBA?", ARG_NONE, ARG_NONE }, { "jmpcl?", ARG_A16, ARG_NONE }, + { "unBC?", ARG_NONE, ARG_NONE }, { "unBD?", ARG_NONE, ARG_NONE }, + { "unBE?", ARG_NONE, ARG_NONE }, { "jmpncl?", ARG_A16, ARG_NONE }, /* 0xc0 */ - { "movb", _REG, _I8 }, { "movw", _REG, _I16 }, { "movq", _REG, _I64 }, { "movt", _REG, _I80 }, - { "movb", _ILR, _ILR }, { "movw", _ILR, _ILR }, { "movq", _ILR, _ILR }, { "movt", _ILR, _ILR }, - { "unC8?", 0, 0 }, { "unC9?", 0, 0 }, { "unCA?", 0, 0 }, { "unCb?", 0, 0 }, - { "swapb", _IRGREG, 0 }, { "swapw", _IRGREG, 0 }, { "swapq", _IRGREG, 0 }, { "swapt", _IRGREG, 0 }, - { "movb", _CS, _REG }, { "movb", _CS, _I8 }, { "movb", _DSZ, _REG }, { "movb", _DSZ, _I8 }, - { "movb", _SS, _REG }, { "movb", _SS, _I8 }, { "movw", _SP, _REG }, { "movw", _SP, _I16 }, - { "movb", _F, _REG }, { "movb", _F, _I8 }, { "unDA?", 0, 0 }, { "unDb?", 0, 0 }, - { "movb", _DS, _REG }, { "movb", _DS, _I8 }, { "movw", _LAR, _REG }, { "movw?", _LAR, _I16 }, + { "movb", ARG_REG, ARG_I8 }, { "movw", ARG_REG, ARG_I16 }, + { "movq", ARG_REG, ARG_I64 }, { "movt", ARG_REG, ARG_I80 }, + { "movb", ARG_ILR, ARG_ILR }, { "movw", ARG_ILR, ARG_ILR }, + { "movq", ARG_ILR, ARG_ILR }, { "movt", ARG_ILR, ARG_ILR }, + { "unC8?", ARG_NONE, ARG_NONE }, { "unC9?", ARG_NONE, ARG_NONE }, + { "unCA?", ARG_NONE, ARG_NONE }, { "unCb?", ARG_NONE, ARG_NONE }, + { "swapb", ARG_IRGREG, ARG_NONE }, { "swapw", ARG_IRGREG, ARG_NONE }, + { "swapq", ARG_IRGREG, ARG_NONE }, { "swapt", ARG_IRGREG, ARG_NONE }, + + /* 0xd0 */ + { "movb", ARG_CS, ARG_REG }, { "movb", ARG_CS, ARG_I8 }, + { "movb", ARG_DSZ, ARG_REG }, { "movb", ARG_DSZ, ARG_I8 }, + { "movb", ARG_SS, ARG_REG }, { "movb", ARG_SS, ARG_I8 }, + { "movw", ARG_SP, ARG_REG }, { "movw", ARG_SP, ARG_I16 }, + { "movb", ARG_F, ARG_REG }, { "movb", ARG_F, ARG_I8 }, + { "unDA?", ARG_NONE, ARG_NONE }, { "unDb?", ARG_NONE, ARG_NONE }, + { "movb", ARG_DS, ARG_REG }, { "movb", ARG_DS, ARG_I8 }, + { "movw", ARG_LAR, ARG_REG }, { "movw?", ARG_LAR, ARG_I16 }, /* 0xe0 */ - { "in0", _REG, 0 }, { "unE1?", _I8, 0 }, { "in", _REG, _KI }, { "movb", _REG, _DSZ }, - { "movb", _REG, _F }, { "movb", _REG, _TIM }, { "unE6?", _I8, 0 }, { "unE7?", _I8, 0 }, - { "movw", _REG, _LAR }, { "movw?", _REG, _LAR }, { "movw", _REG, _PC }, { "movw", _REG, _SP }, - { "unEC?", 0, 0 }, { "movb", _REG, _DS }, { "movb", _REG, _CS }, { "movb", _REG, _SS }, - { "unF0?", _I8, 0 }, { "unF1?", _I8, 0 }, { "unF2?", _I8, 0 }, { "unF3?", _I8, 0 }, - { "unF4?", _I8, 0 }, { "unF5?", _I8, 0 }, { "unF6?", _I8, 0 }, { "unF7?", _I8, 0 }, - { "unF8?", 0, 0 }, { "unF9?", 0, 0 }, { "unFA?", 0, 0 }, { "unFb?", 0, 0 }, - { "unFC?", 0, 0 }, { "unFD?", 0, 0 }, { "unFE?", 0, 0 }, { "nop", 0, 0 } + { "in0", ARG_REG, ARG_NONE }, { "unE1?", ARG_I8, ARG_NONE }, + { "in", ARG_REG, ARG_KI }, { "movb", ARG_REG, ARG_DSZ }, + { "movb", ARG_REG, ARG_F }, { "movb", ARG_REG, ARG_TIM }, + { "unE6?", ARG_I8, ARG_NONE }, { "unE7?", ARG_I8, ARG_NONE }, + { "movw", ARG_REG, ARG_LAR }, { "movw?", ARG_REG, ARG_LAR }, + { "movw", ARG_REG, ARG_PC }, { "movw", ARG_REG, ARG_SP }, + { "unEC?", ARG_NONE, ARG_NONE }, { "movb", ARG_REG, ARG_DS }, + { "movb", ARG_REG, ARG_CS }, { "movb", ARG_REG, ARG_SS }, + + /* 0xf0 */ + { "unF0?", ARG_I8, ARG_NONE }, { "unF1?", ARG_I8, ARG_NONE }, + { "unF2?", ARG_I8, ARG_NONE }, { "unF3?", ARG_I8, ARG_NONE }, + { "unF4?", ARG_I8, ARG_NONE }, { "unF5?", ARG_I8, ARG_NONE }, + { "unF6?", ARG_I8, ARG_NONE }, { "unF7?", ARG_I8, ARG_NONE }, + { "unF8?", ARG_NONE, ARG_NONE }, { "unF9?", ARG_NONE, ARG_NONE }, + { "unFA?", ARG_NONE, ARG_NONE }, { "unFb?", ARG_NONE, ARG_NONE }, + { "unFC?", ARG_NONE, ARG_NONE }, { "unFD?", ARG_NONE, ARG_NONE }, + { "unFE?", ARG_NONE, ARG_NONE }, { "nop", ARG_NONE, ARG_NONE } }; CPU_DISASSEMBLE(hcd62121) { - uint8_t op; - uint8_t op1; - uint8_t op2; - int pos = 0; + u8 op; + u8 op1; + u8 op2; + u32 pos = 0; const hcd62121_dasm *inst; op = oprom[pos++]; @@ -142,213 +217,213 @@ CPU_DISASSEMBLE(hcd62121) inst = &hcd62121_ops[op]; /* Special case for nibble shift instruction */ - if ( inst->arg2 == _4 ) - util::stream_format(stream, "sh%c%c ", ( oprom[pos] & 0x80 ) ? 'l' : 'r', inst->str[3]); + if (inst->arg2 == ARG_4) + util::stream_format(stream, "sh%c%c ", (oprom[pos] & 0x80) ? 'l' : 'r', inst->str[3]); else util::stream_format(stream, "%-8s", inst->str); - switch( inst->arg1 ) + switch(inst->arg1) { - case _REGREG: + case ARG_REGREG: op1 = oprom[pos++]; op2 = oprom[pos++]; - if ( op1 & 0x80 ) + if (op1 & 0x80) { - util::stream_format( stream, "r%02x,0x%02x", op1 & 0x7f, op2 ); + util::stream_format(stream, "r%02x,0x%02x", op1 & 0x7f, op2); } else { - if ( op2 & 0x80 ) - util::stream_format( stream, "r%02x,r%02x", op1 & 0x7f, op2 & 0x7f ); + if (op2 & 0x80) + util::stream_format(stream, "r%02x,r%02x", op1 & 0x7f, op2 & 0x7f); else - util::stream_format( stream, "r%02x,r%02x", op2 & 0x7f, op1 & 0x7f ); + util::stream_format(stream, "r%02x,r%02x", op2 & 0x7f, op1 & 0x7f); } break; - case _REG: - util::stream_format( stream, "r%02x", oprom[pos++] & 0x7f ); + case ARG_REG: + util::stream_format(stream, "r%02x", oprom[pos++] & 0x7f); break; - case _IRGREG: + case ARG_IRGREG: /* bit 6 = direction. 0 - regular, 1 - reverse */ op1 = oprom[pos++]; op2 = oprom[pos++]; - if ( op1 & 0x80 ) + if (op1 & 0x80) { - util::stream_format( stream, "(r%02x),0x%02x", 0x40 | ( op1 & 0x3f ), op2 ); + util::stream_format(stream, "(r%02x),0x%02x", 0x40 | (op1 & 0x3f), op2); } else { - if ( op2 & 0x80 ) - util::stream_format( stream, "(r%02x%s),r%02x", 0x40 | ( op1 & 0x3f ), (op1 & 0x40) ? ".r" : "", op2 & 0x7f ); + if (op2 & 0x80) + util::stream_format(stream, "(r%02x%s),r%02x", 0x40 | (op1 & 0x3f), (op1 & 0x40) ? ".r" : "", op2 & 0x7f); else - util::stream_format( stream, "r%02x,(r%02x%s)", op2 & 0x7f, 0x40 | ( op1 & 0x3f ), (op1 & 0x40) ? ".r" : "" ); + util::stream_format(stream, "r%02x,(r%02x%s)", op2 & 0x7f, 0x40 | (op1 & 0x3f), (op1 & 0x40) ? ".r" : ""); } break; - case _IRG: + case ARG_IRG: /* bit 6 = direction. 0 - regular, 1 - reverse */ op1 = oprom[pos++]; - util::stream_format( stream, "(r%02x%s)", 0x40 | ( op1 & 0x3f ), (op1 & 0x40) ? ".r" : "" ); + util::stream_format(stream, "(r%02x%s)", 0x40 | (op1 & 0x3f), (op1 & 0x40) ? ".r" : ""); break; - case _F: - util::stream_format( stream, "F" ); + case ARG_F: + util::stream_format(stream, "F"); break; - case _CS: - util::stream_format( stream, "CS" ); + case ARG_CS: + util::stream_format(stream, "CS"); break; - case _DS: - util::stream_format( stream, "DS" ); + case ARG_DS: + util::stream_format(stream, "DS"); break; - case _SS: - util::stream_format( stream, "SS" ); + case ARG_SS: + util::stream_format(stream, "SS"); break; - case _PC: - util::stream_format( stream, "PC" ); + case ARG_PC: + util::stream_format(stream, "PC"); break; - case _SP: - util::stream_format( stream, "SP" ); + case ARG_SP: + util::stream_format(stream, "SP"); break; - case _I8: - util::stream_format( stream, "0x%02x", oprom[pos++] ); + case ARG_I8: + util::stream_format(stream, "0x%02x", oprom[pos++]); break; - case _I16: - case _A16: - util::stream_format( stream, "0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_I16: + case ARG_A16: + util::stream_format(stream, "0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _I64: - util::stream_format( stream, "0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_I64: + util::stream_format(stream, "0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _I80: - util::stream_format( stream, "0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_I80: + util::stream_format(stream, "0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _A24: - util::stream_format( stream, "0x%02x:", oprom[pos++] ); - util::stream_format( stream, "0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_A24: + util::stream_format(stream, "0x%02x:", oprom[pos++]); + util::stream_format(stream, "0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _ILR: + case ARG_ILR: op1 = oprom[pos++]; op2 = oprom[pos++]; - if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) ) + if ((op1 & 0x80) || (op2 & 0x80)) { /* (lar),reg */ - util::stream_format( stream, "(%slar%s),r%02x", (op1 & 0x20) ? ( (op1 & 0x40) ? "--" : "++" ) : "", (op1 & 0x20) ? "" : ( (op1 & 0x40) ? "--" : "++" ), op2 & 0x7f ); + util::stream_format(stream, "(%slar%s),r%02x", (op1 & 0x20) ? ((op1 & 0x40) ? "--" : "++") : "", (op1 & 0x20) ? "" : ((op1 & 0x40) ? "--" : "++"), op2 & 0x7f); } else { /* reg,(lar) */ - util::stream_format( stream, "r%02x,(%slar%s)", op2 & 0x7f, (op1 & 0x20) ? ( (op1 & 0x40) ? "--" : "++" ) : "", (op1 & 0x20) ? "" : ( (op1 & 0x40) ? "--" : "++" ) ); + util::stream_format(stream, "r%02x,(%slar%s)", op2 & 0x7f, (op1 & 0x20) ? ((op1 & 0x40) ? "--" : "++") : "", (op1 & 0x20) ? "" : ((op1 & 0x40) ? "--" : "++")); } break; - case _LAR: - util::stream_format( stream, "lar" ); + case ARG_LAR: + util::stream_format(stream, "lar"); break; - case _DSZ: - util::stream_format( stream, "dsize" ); + case ARG_DSZ: + util::stream_format(stream, "dsize"); break; - case _TIM: - util::stream_format( stream, "TIM?" ); + case ARG_TIM: + util::stream_format(stream, "TIM?"); break; - case _KLO: - util::stream_format( stream, "KOL" ); + case ARG_KLO: + util::stream_format(stream, "KOL"); break; - case _KHI: - util::stream_format( stream, "KOH" ); + case ARG_KHI: + util::stream_format(stream, "KOH"); break; default: break; } - switch( inst->arg2 ) + switch(inst->arg2) { - case _REG: - util::stream_format( stream, ",r%02x", oprom[pos++] & 0x7f ); + case ARG_REG: + util::stream_format(stream, ",r%02x", oprom[pos++] & 0x7f); break; - case _F: - util::stream_format( stream, ",F" ); + case ARG_F: + util::stream_format(stream, ",F"); break; - case _CS: - util::stream_format( stream, ",CS" ); + case ARG_CS: + util::stream_format(stream, ",CS"); break; - case _DS: - util::stream_format( stream, ",DS" ); + case ARG_DS: + util::stream_format(stream, ",DS"); break; - case _SS: - util::stream_format( stream, ",SS" ); + case ARG_SS: + util::stream_format(stream, ",SS"); break; - case _PC: - util::stream_format( stream, ",PC" ); + case ARG_PC: + util::stream_format(stream, ",PC"); break; - case _SP: - util::stream_format( stream, ",SP" ); + case ARG_SP: + util::stream_format(stream, ",SP"); break; - case _I8: - util::stream_format( stream, ",0x%02x", oprom[pos++] ); + case ARG_I8: + util::stream_format(stream, ",0x%02x", oprom[pos++]); break; - case _I16: - case _A16: - util::stream_format( stream, ",0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_I16: + case ARG_A16: + util::stream_format(stream, ",0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _I64: - util::stream_format( stream, ",0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_I64: + util::stream_format(stream, ",0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _I80: - util::stream_format( stream, ",0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_I80: + util::stream_format(stream, ",0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _A24: - util::stream_format( stream, ",0x%02x:", oprom[pos++] ); - util::stream_format( stream, "0x%02x", oprom[pos++] ); - util::stream_format( stream, "%02x", oprom[pos++] ); + case ARG_A24: + util::stream_format(stream, ",0x%02x:", oprom[pos++]); + util::stream_format(stream, "0x%02x", oprom[pos++]); + util::stream_format(stream, "%02x", oprom[pos++]); break; - case _ILR: - /* Implemented by _ILR section for arg1 */ + case ARG_ILR: + /* Implemented by ARG_ILR section for arg1 */ break; - case _LAR: - util::stream_format( stream, ",lar" ); + case ARG_LAR: + util::stream_format(stream, ",lar"); break; - case _DSZ: - util::stream_format( stream, ",dsize" ); + case ARG_DSZ: + util::stream_format(stream, ",dsize"); break; - case _TIM: - util::stream_format( stream, ",TIM?" ); + case ARG_TIM: + util::stream_format(stream, ",TIM?"); break; - case _KI: - util::stream_format( stream, ",KI" ); + case ARG_KI: + util::stream_format(stream, ",KI"); break; - case _4: - util::stream_format( stream, ",4" ); + case ARG_4: + util::stream_format(stream, ",4"); break; default: break; diff --git a/src/mame/drivers/cfx9850.cpp b/src/mame/drivers/cfx9850.cpp index a3a74af5640..5c120979a51 100644 --- a/src/mame/drivers/cfx9850.cpp +++ b/src/mame/drivers/cfx9850.cpp @@ -30,219 +30,185 @@ public: : driver_device(mconfig, type, tag), m_video_ram(*this, "video_ram"), m_display_ram(*this, "display_ram"), - m_ko1(*this, "KO1"), - m_ko2(*this, "KO2"), - m_ko3(*this, "KO3"), - m_ko4(*this, "KO4"), - m_ko5(*this, "KO5"), - m_ko6(*this, "KO6"), - m_ko7(*this, "KO7"), - m_ko8(*this, "KO8"), - m_ko9(*this, "KO9"), - m_ko10(*this, "KO10"), - m_ko11(*this, "KO11"), - m_ko12(*this, "KO12") , + m_ko_port(*this, "KO.%u", 0), m_maincpu(*this, "maincpu") { } - DECLARE_WRITE8_MEMBER(cfx9850_kol_w); - DECLARE_WRITE8_MEMBER(cfx9850_koh_w); - DECLARE_READ8_MEMBER(cfx9850_ki_r); - DECLARE_READ8_MEMBER(cfx9850_battery_level_r); - required_shared_ptr m_video_ram; - required_shared_ptr m_display_ram; - uint16_t m_ko; /* KO lines KO1 - KO14 */ + DECLARE_WRITE8_MEMBER(kol_w); + DECLARE_WRITE8_MEMBER(koh_w); + DECLARE_READ8_MEMBER(ki_r); + DECLARE_READ8_MEMBER(in0_r); + required_shared_ptr m_video_ram; + required_shared_ptr m_display_ram; + u16 m_ko; // KO lines KO1 - KO14 DECLARE_PALETTE_INIT(cfx9850); - uint32_t screen_update_cfx9850(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); + u32 screen_update_cfx9850(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); protected: - required_ioport m_ko1; - required_ioport m_ko2; - required_ioport m_ko3; - required_ioport m_ko4; - required_ioport m_ko5; - required_ioport m_ko6; - required_ioport m_ko7; - required_ioport m_ko8; - required_ioport m_ko9; - required_ioport m_ko10; - required_ioport m_ko11; - required_ioport m_ko12; + required_ioport_array<12> m_ko_port; required_device m_maincpu; }; -static ADDRESS_MAP_START( cfx9850, AS_PROGRAM, 8, cfx9850_state ) +static ADDRESS_MAP_START(cfx9850, AS_PROGRAM, 8, cfx9850_state) AM_RANGE( 0x000000, 0x007fff ) AM_ROM AM_RANGE( 0x080000, 0x0807ff ) AM_RAM AM_SHARE("video_ram") -// AM_RANGE( 0x100000, 0x10ffff ) /* some memory mapped i/o? */ -// AM_RANGE( 0x110000, 0x11ffff ) /* some memory mapped i/o? */ +// AM_RANGE( 0x100000, 0x10ffff ) // some memory mapped i/o? +// AM_RANGE( 0x110000, 0x11ffff ) // some memory mapped i/o? AM_RANGE( 0x200000, 0x27ffff ) AM_ROM AM_REGION( "bios", 0 ) AM_RANGE( 0x400000, 0x40ffff ) AM_RAM AM_RANGE( 0x600000, 0x6007ff ) AM_MIRROR(0xf800) AM_RAM AM_SHARE("display_ram") -// AM_RANGE( 0xe10000, 0xe1ffff ) /* some memory mapped i/o? */ +// AM_RANGE( 0xe10000, 0xe1ffff ) // some memory mapped i/o? ADDRESS_MAP_END -WRITE8_MEMBER( cfx9850_state::cfx9850_kol_w ) +WRITE8_MEMBER(cfx9850_state::kol_w) { - m_ko = ( m_ko & 0xff00 ) | data; + m_ko = (m_ko & 0xff00) | data; } -WRITE8_MEMBER( cfx9850_state::cfx9850_koh_w ) +WRITE8_MEMBER(cfx9850_state::koh_w) { - m_ko = ( m_ko & 0x00ff ) | ( data << 8 ); + m_ko = (m_ko & 0x00ff) | (data << 8); } -READ8_MEMBER( cfx9850_state::cfx9850_ki_r ) +READ8_MEMBER(cfx9850_state::ki_r) { - uint8_t data = 0; + u8 data = 0; - if ( m_ko & ( 1 << 0 ) ) data |= m_ko1->read(); - if ( m_ko & ( 1 << 1 ) ) data |= m_ko2->read(); - if ( m_ko & ( 1 << 2 ) ) data |= m_ko3->read(); - if ( m_ko & ( 1 << 3 ) ) data |= m_ko4->read(); - if ( m_ko & ( 1 << 4 ) ) data |= m_ko5->read(); - if ( m_ko & ( 1 << 5 ) ) data |= m_ko6->read(); - if ( m_ko & ( 1 << 6 ) ) data |= m_ko7->read(); - if ( m_ko & ( 1 << 7 ) ) data |= m_ko8->read(); - if ( m_ko & ( 1 << 8 ) ) data |= m_ko9->read(); - if ( m_ko & ( 1 << 9 ) ) data |= m_ko10->read(); - if ( m_ko & ( 1 << 10 ) ) data |= m_ko11->read(); - if ( m_ko & ( 1 << 11 ) ) data |= m_ko12->read(); + for (int i = 0; i < 12; i++) + { + if (BIT(m_ko, i)) + { + data |= m_ko_port[i]->read(); + } + } return data; } -READ8_MEMBER( cfx9850_state::cfx9850_battery_level_r ) +READ8_MEMBER(cfx9850_state::in0_r) { + // battery level return 0x30; } -static ADDRESS_MAP_START( cfx9850_io, AS_IO, 8, cfx9850_state ) - AM_RANGE( HCD62121_KOL, HCD62121_KOL ) AM_WRITE( cfx9850_kol_w ) - AM_RANGE( HCD62121_KOH, HCD62121_KOH ) AM_WRITE( cfx9850_koh_w ) - AM_RANGE( HCD62121_KI, HCD62121_KI ) AM_READ( cfx9850_ki_r ) - AM_RANGE( HCD62121_IN0, HCD62121_IN0 ) AM_READ( cfx9850_battery_level_r ) -ADDRESS_MAP_END +static INPUT_PORTS_START(cfx9850) + PORT_START("KO.0") + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("AC On/Off") PORT_CODE(KEYCODE_BACKSLASH) + PORT_BIT(0xfe, IP_ACTIVE_HIGH, IPT_UNUSED) + PORT_START("KO.1") + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXE Enter") PORT_CODE(KEYCODE_ENTER) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("(-) Ares") PORT_CODE(KEYCODE_MINUS) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXP Pi") PORT_CODE(KEYCODE_EQUALS) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(". SPACE") PORT_CODE(KEYCODE_SPACE) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("0 Z") PORT_CODE(KEYCODE_Z) + PORT_BIT(0x83, IP_ACTIVE_HIGH, IPT_UNUSED) -static INPUT_PORTS_START( cfx9850 ) - PORT_START( "KO1" ) - PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "AC On/Off" ) PORT_CODE(KEYCODE_BACKSLASH) - PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.2") + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("- ] Y") PORT_CODE(KEYCODE_Y) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("+ [ X") PORT_CODE(KEYCODE_X) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("3 W") PORT_CODE(KEYCODE_W) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("2 V") PORT_CODE(KEYCODE_V) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("1 U") PORT_CODE(KEYCODE_U) + PORT_BIT(0x83, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO2" ) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "EXE Enter" ) PORT_CODE(KEYCODE_ENTER) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "(-) Ares" ) PORT_CODE(KEYCODE_MINUS) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "EXP Pi" ) PORT_CODE(KEYCODE_EQUALS) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( ". SPACE" ) PORT_CODE(KEYCODE_SPACE) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "0 Z" ) PORT_CODE(KEYCODE_Z) - PORT_BIT( 0x83, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.3") + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("/ } T") PORT_CODE(KEYCODE_T) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("* { S") PORT_CODE(KEYCODE_S) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("6 R") PORT_CODE(KEYCODE_R) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("5 Q") PORT_CODE(KEYCODE_Q) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("4 P") PORT_CODE(KEYCODE_P) + PORT_BIT(0x83, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO3" ) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "- ] Y" ) PORT_CODE(KEYCODE_Y) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "+ [ X" ) PORT_CODE(KEYCODE_X) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "3 W" ) PORT_CODE(KEYCODE_W) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "2 V" ) PORT_CODE(KEYCODE_V) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "1 U" ) PORT_CODE(KEYCODE_U) - PORT_BIT( 0x83, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.4") + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("DEL DG") PORT_CODE(KEYCODE_BACKSPACE) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("9 O") PORT_CODE(KEYCODE_O) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("8 N") PORT_CODE(KEYCODE_N) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("7 M") PORT_CODE(KEYCODE_M) + PORT_BIT(0x87, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO4" ) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "/ } T" ) PORT_CODE(KEYCODE_T) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "* { S" ) PORT_CODE(KEYCODE_S) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "6 R" ) PORT_CODE(KEYCODE_R) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "5 Q" ) PORT_CODE(KEYCODE_Q) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "4 P" ) PORT_CODE(KEYCODE_P) - PORT_BIT( 0x83, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.5") + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TAB L") PORT_CODE(KEYCODE_L) + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(", K") PORT_CODE(KEYCODE_K) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(") x^-1 J") PORT_CODE(KEYCODE_J) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("( .. I") PORT_CODE(KEYCODE_I) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F<=>0 H") PORT_CODE(KEYCODE_H) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("a b/c G") PORT_CODE(KEYCODE_G) + PORT_BIT(0x81, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO5" ) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "DEL DG" ) PORT_CODE(KEYCODE_BACKSPACE) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "9 O" ) PORT_CODE(KEYCODE_O) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "8 N" ) PORT_CODE(KEYCODE_N) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "7 M" ) PORT_CODE(KEYCODE_M) - PORT_BIT( 0x87, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.6") + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("tan tan^-1 F") PORT_CODE(KEYCODE_F) + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("cos cas^-1 E") PORT_CODE(KEYCODE_E) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("sin sin^-1 D") PORT_CODE(KEYCODE_D) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ln e^x C") PORT_CODE(KEYCODE_C) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("log 10^x B") PORT_CODE(KEYCODE_B) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("x,d,t A") PORT_CODE(KEYCODE_A) + PORT_BIT(0x81, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO6" ) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "TAB L" ) PORT_CODE(KEYCODE_L) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( ", K" ) PORT_CODE(KEYCODE_K) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( ") x^-1 J" ) PORT_CODE(KEYCODE_J) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "( .. I" ) PORT_CODE(KEYCODE_I) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F<=>0 H" ) PORT_CODE(KEYCODE_H) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "a b/c G" ) PORT_CODE(KEYCODE_G) - PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.7") + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Right") PORT_CODE(KEYCODE_RIGHT) + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Down") PORT_CODE(KEYCODE_DOWN) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXIT QUIT") PORT_CODE(KEYCODE_STOP) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("/\\ .. ..") PORT_CODE(KEYCODE_COMMA) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("x^2 sqrt ..") PORT_CODE(KEYCODE_SLASH) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ALPHA ..-LOCK") PORT_CODE(KEYCODE_CAPSLOCK) + PORT_BIT(0x81, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO7" ) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "tan tan^-1 F" ) PORT_CODE(KEYCODE_F) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "cos cas^-1 E" ) PORT_CODE(KEYCODE_E) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "sin sin^-1 D" ) PORT_CODE(KEYCODE_D) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "ln e^x C" ) PORT_CODE(KEYCODE_C) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "log 10^x B" ) PORT_CODE(KEYCODE_B) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "x,d,t A" ) PORT_CODE(KEYCODE_A) - PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.8") + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Up") PORT_CODE(KEYCODE_UP) + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Left") PORT_CODE(KEYCODE_LEFT) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("MENU SET UP") PORT_CODE(KEYCODE_OPENBRACE) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("VARS PRGM") PORT_CODE(KEYCODE_CLOSEBRACE) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("OPTN") PORT_CODE(KEYCODE_LCONTROL) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("SHIFT") PORT_CODE(KEYCODE_LSHIFT) + PORT_BIT(0x81, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO8" ) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "Right" ) PORT_CODE(KEYCODE_RIGHT) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "Down" ) PORT_CODE(KEYCODE_DOWN) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "EXIT QUIT" ) PORT_CODE(KEYCODE_STOP) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "/\\ .. .." ) PORT_CODE(KEYCODE_COMMA) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "x^2 sqrt .." ) PORT_CODE(KEYCODE_SLASH) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "ALPHA ..-LOCK" ) PORT_CODE(KEYCODE_CAPSLOCK) - PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.9") + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F6 G<=>T") PORT_CODE(KEYCODE_F6) + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F5 G-Solv") PORT_CODE(KEYCODE_F5) + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F4 Sketch") PORT_CODE(KEYCODE_F4) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F3 V-Window") PORT_CODE(KEYCODE_F3) + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F2 Zoom") PORT_CODE(KEYCODE_F2) + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F1 Trace") PORT_CODE(KEYCODE_F1) + PORT_BIT(0x81, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO9" ) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "Up" ) PORT_CODE(KEYCODE_UP) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "Left" ) PORT_CODE(KEYCODE_LEFT) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "MENU SET UP" ) PORT_CODE(KEYCODE_OPENBRACE) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "VARS PRGM" ) PORT_CODE(KEYCODE_CLOSEBRACE) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "OPTN" ) PORT_CODE(KEYCODE_LCONTROL) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "SHIFT" ) PORT_CODE(KEYCODE_LSHIFT) - PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_UNUSED ) + // KO11 is not connected + PORT_START("KO.10") + PORT_BIT(0xff, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_START( "KO10" ) - PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F6 G<=>T" ) PORT_CODE(KEYCODE_F6) - PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F5 G-Solv" ) PORT_CODE(KEYCODE_F5) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F4 Sketch" ) PORT_CODE(KEYCODE_F4) - PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F3 V-Window" ) PORT_CODE(KEYCODE_F3) - PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F2 Zoom" ) PORT_CODE(KEYCODE_F2) - PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "F1 Trace" ) PORT_CODE(KEYCODE_F1) - PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_UNUSED ) - - /* KO11 is not connected */ - PORT_START( "KO11" ) - PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED ) - - PORT_START( "KO12" ) - PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME( "TEST" ) PORT_CODE(KEYCODE_TILDE) - PORT_BIT( 0xf7, IP_ACTIVE_HIGH, IPT_UNUSED ) + PORT_START("KO.11") + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TEST") PORT_CODE(KEYCODE_TILDE) + PORT_BIT(0xf7, IP_ACTIVE_HIGH, IPT_UNUSED) INPUT_PORTS_END PALETTE_INIT_MEMBER(cfx9850_state, cfx9850) { - palette.set_pen_color( 0, 0xff, 0xff, 0xff ); - palette.set_pen_color( 1, 0x00, 0x00, 0xff ); - palette.set_pen_color( 2, 0x00, 0xff, 0x00 ); - palette.set_pen_color( 3, 0xff, 0x00, 0x00 ); + palette.set_pen_color(0, 0xff, 0xff, 0xff); + palette.set_pen_color(1, 0x00, 0x00, 0xff); + palette.set_pen_color(2, 0x00, 0xff, 0x00); + palette.set_pen_color(3, 0xff, 0x00, 0x00); } -uint32_t cfx9850_state::screen_update_cfx9850(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) +u32 cfx9850_state::screen_update_cfx9850(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) { - uint16_t offset = 0; + u16 offset = 0; - for ( int i = 0; i < 16; i++ ) + for (int i = 0; i < 16; i++) { int x = 120 - i * 8; - for ( int j = 0; j < 64; j++ ) + for (int j = 0; j < 64; j++) { - uint8_t data1 = m_display_ram[ offset ]; - uint8_t data2 = m_display_ram[ offset + 0x400 ]; + u8 data1 = m_display_ram[offset]; + u8 data2 = m_display_ram[offset + 0x400]; - for ( int b = 0; b < 8; b++ ) + for (int b = 0; b < 8; b++) { bitmap.pix16(63-j, x+b) = ( data1 & 0x80 ) ? ( data2 & 0x80 ? 3 : 2 ) : ( data2 & 0x80 ? 1 : 0 ); data1 <<= 1; @@ -257,37 +223,40 @@ uint32_t cfx9850_state::screen_update_cfx9850(screen_device &screen, bitmap_ind1 } -static MACHINE_CONFIG_START( cfx9850, cfx9850_state ) - MCFG_CPU_ADD( "maincpu", HCD62121, 4300000 ) /* 4.3 MHz */ - MCFG_CPU_PROGRAM_MAP( cfx9850 ) - MCFG_CPU_IO_MAP( cfx9850_io ) +static MACHINE_CONFIG_START(cfx9850, cfx9850_state) + MCFG_CPU_ADD("maincpu", HCD62121, 4300000) /* 4.3 MHz */ + MCFG_CPU_PROGRAM_MAP(cfx9850) + MCFG_HCD62121_KOL_CB(WRITE8(cfx9850_state, kol_w)) + MCFG_HCD62121_KOH_CB(WRITE8(cfx9850_state, koh_w)) + MCFG_HCD62121_KI_CB(READ8(cfx9850_state, ki_r)) + MCFG_HCD62121_IN0_CB(READ8(cfx9850_state, in0_r)) - MCFG_SCREEN_ADD( "screen", LCD ) - MCFG_SCREEN_REFRESH_RATE( 60 ) - MCFG_SCREEN_SIZE( 128, 64 ) - MCFG_SCREEN_VISIBLE_AREA( 0, 127, 0, 63 ) + MCFG_SCREEN_ADD("screen", LCD) + MCFG_SCREEN_REFRESH_RATE(60) + MCFG_SCREEN_SIZE(128, 64) + MCFG_SCREEN_VISIBLE_AREA(0, 127, 0, 63) MCFG_SCREEN_UPDATE_DRIVER(cfx9850_state, screen_update_cfx9850) MCFG_SCREEN_PALETTE("palette") MCFG_DEFAULT_LAYOUT(layout_lcd) - /* TODO: It uses a color display, but I'm being lazy here. 3 colour lcd */ - MCFG_PALETTE_ADD( "palette", 4 ) + // TODO: Verify amount of colors and palette + MCFG_PALETTE_ADD("palette", 4) MCFG_PALETTE_INIT_OWNER(cfx9850_state, cfx9850) MACHINE_CONFIG_END -ROM_START( cfx9850 ) - ROM_REGION( 0x8000, "maincpu", 0 ) - ROM_LOAD( "hcd62121.bin", 0x0000, 0x8000, CRC(e72075f8) SHA1(f50d176e1c225dab69abfc67702c9dfb296b6a78) ) +ROM_START(cfx9850) + ROM_REGION(0x8000, "maincpu", 0) + ROM_LOAD("hcd62121.bin", 0x0000, 0x8000, CRC(e72075f8) SHA1(f50d176e1c225dab69abfc67702c9dfb296b6a78)) - ROM_REGION( 0x80000, "bios", 0 ) - /* No idea yet which rom is what version. */ - ROM_SYSTEM_BIOS( 0, "rom1", "rom1, version unknown" ) - ROMX_LOAD( "cfx9850.bin", 0x00000, 0x80000, CRC(6c9bd903) SHA1(d5b6677ab4e0d3f84e5769e89e8f3d101f98f848), ROM_BIOS(1) ) - ROM_SYSTEM_BIOS( 1, "rom2", "rom2, version unknown" ) - ROMX_LOAD( "cfx9850b.bin", 0x00000, 0x80000, CRC(cd3c497f) SHA1(1d1aa38205eec7aba3ed6bef7389767e38afe075), ROM_BIOS(2) ) + ROM_REGION(0x80000, "bios", 0) + // Unknown yet which rom is which version. + ROM_SYSTEM_BIOS(0, "rom1", "rom1, version unknown") + ROMX_LOAD("cfx9850.bin", 0x00000, 0x80000, CRC(6c9bd903) SHA1(d5b6677ab4e0d3f84e5769e89e8f3d101f98f848), ROM_BIOS(1)) + ROM_SYSTEM_BIOS(1, "rom2", "rom2, version unknown") + ROMX_LOAD("cfx9850b.bin", 0x00000, 0x80000, CRC(cd3c497f) SHA1(1d1aa38205eec7aba3ed6bef7389767e38afe075), ROM_BIOS(2)) ROM_END -COMP( 1996, cfx9850, 0, 0, cfx9850, cfx9850, driver_device, 0, "Casio", "CFX-9850G", MACHINE_NO_SOUND | MACHINE_NOT_WORKING ) +COMP(1996, cfx9850, 0, 0, cfx9850, cfx9850, driver_device, 0, "Casio", "CFX-9850G", MACHINE_NO_SOUND | MACHINE_NOT_WORKING)