From fc6ff102b1e622365109f4d2991b197c10bcbe09 Mon Sep 17 00:00:00 2001 From: Ryan Holtz Date: Sun, 30 Dec 2012 01:26:51 +0000 Subject: [PATCH] - m6805.c: Modernized M6805 CPU core. [MooglyGuy] --- src/emu/cpu/m6805/6805ops.c | 74 +- src/emu/cpu/m6805/m6805.c | 1586 ++++++++++++++++------------------- src/emu/cpu/m6805/m6805.h | 362 +++++++- src/emu/cpu/m6809/m6809.h | 4 +- 4 files changed, 1097 insertions(+), 929 deletions(-) diff --git a/src/emu/cpu/m6805/6805ops.c b/src/emu/cpu/m6805/6805ops.c index f32b2643349..a9058c5dd11 100644 --- a/src/emu/cpu/m6805/6805ops.c +++ b/src/emu/cpu/m6805/6805ops.c @@ -13,9 +13,10 @@ HNZC */ -#define OP_HANDLER(_name) INLINE void _name (m6805_Regs* cpustate) +#define OP_HANDLER(_name) void m6805_base_device::_name() +#define DERIVED_OP_HANDLER(_arch,_name) void _arch##_device::_name() -#define OP_HANDLER_BIT(_name) INLINE void _name (m6805_Regs* cpustate, UINT8 bit) +#define OP_HANDLER_BIT(_name) void m6805_base_device::_name(UINT8 bit) OP_HANDLER( illegal ) { @@ -158,27 +159,23 @@ OP_HANDLER( bms ) /* $2e BIL relative ---- */ OP_HANDLER( bil ) { - if(SUBTYPE==SUBTYPE_HD63705) - { - BRANCH( cpustate->nmi_state!=CLEAR_LINE ); - } - else - { - BRANCH( cpustate->irq_state[0]!=CLEAR_LINE ); - } + BRANCH(m_irq_state[0] != CLEAR_LINE); +} + +DERIVED_OP_HANDLER( hd63705, bil ) +{ + BRANCH(m_nmi_state != CLEAR_LINE); } /* $2f BIH relative ---- */ OP_HANDLER( bih ) { - if(SUBTYPE==SUBTYPE_HD63705) - { - BRANCH( cpustate->nmi_state==CLEAR_LINE ); - } - else - { - BRANCH( cpustate->irq_state[0]==CLEAR_LINE ); - } + BRANCH(m_irq_state[0] == CLEAR_LINE); +} + +DERIVED_OP_HANDLER( hd63705, bih ) +{ + BRANCH(m_nmi_state == CLEAR_LINE); } /* $30 NEG direct -*** */ @@ -789,17 +786,19 @@ OP_HANDLER( rti ) PULLBYTE(CC); PULLBYTE(A); PULLBYTE(X); - PULLWORD(pPC); + PULLWORD(m_pc); #if IRQ_LEVEL_DETECT - if( m6805.irq_state != CLEAR_LINE && (CC & IFLAG) == 0 ) - m6805.pending_interrupts |= M6805_INT_IRQ; + if( m_irq_state != CLEAR_LINE && (CC & IFLAG) == 0 ) + { + m_pending_interrupts |= M6805_INT_IRQ; + } #endif } /* $81 RTS inherent ---- */ OP_HANDLER( rts ) { - PULLWORD(pPC); + PULLWORD(m_pc); } /* $82 ILLEGAL */ @@ -807,14 +806,23 @@ OP_HANDLER( rts ) /* $83 SWI absolute indirect ---- */ OP_HANDLER( swi ) { - PUSHWORD(cpustate->pc); - PUSHBYTE(cpustate->x); - PUSHBYTE(cpustate->a); - PUSHBYTE(cpustate->cc); + PUSHWORD(m_pc); + PUSHBYTE(m_x); + PUSHBYTE(m_a); + PUSHBYTE(m_cc); SEI; - if(SUBTYPE==SUBTYPE_HD63705) RM16( cpustate, 0x1ffa, &pPC ); else RM16( cpustate, 0xfffc, &pPC ); + RM16(0xfffc, &m_pc); } +DERIVED_OP_HANDLER( hd63705, swi ) +{ + PUSHWORD(m_pc); + PUSHBYTE(m_x); + PUSHBYTE(m_a); + PUSHBYTE(m_cc); + SEI; + RM16(0x1ffa, &m_pc); +} /* $84 ILLEGAL */ /* $85 ILLEGAL */ @@ -1009,7 +1017,7 @@ OP_HANDLER( bsr ) { UINT8 t; IMMBYTE(t); - PUSHWORD(cpustate->pc); + PUSHWORD(m_pc); PC += SIGNED(t); } @@ -1157,7 +1165,7 @@ OP_HANDLER( jmp_di ) OP_HANDLER( jsr_di ) { DIRECT; - PUSHWORD(cpustate->pc); + PUSHWORD(m_pc); PC = EA; } @@ -1312,7 +1320,7 @@ OP_HANDLER( jmp_ex ) OP_HANDLER( jsr_ex ) { EXTENDED; - PUSHWORD(cpustate->pc); + PUSHWORD(m_pc); PC = EA; } @@ -1467,7 +1475,7 @@ OP_HANDLER( jmp_ix2 ) OP_HANDLER( jsr_ix2 ) { INDEXED2; - PUSHWORD(cpustate->pc); + PUSHWORD(m_pc); PC = EA; } @@ -1622,7 +1630,7 @@ OP_HANDLER( jmp_ix1 ) OP_HANDLER( jsr_ix1 ) { INDEXED1; - PUSHWORD(cpustate->pc); + PUSHWORD(m_pc); PC = EA; } @@ -1777,7 +1785,7 @@ OP_HANDLER( jmp_ix ) OP_HANDLER( jsr_ix ) { INDEXED; - PUSHWORD(cpustate->pc); + PUSHWORD(m_pc); PC = EA; } diff --git a/src/emu/cpu/m6805/m6805.c b/src/emu/cpu/m6805/m6805.c index b759981e145..c0ec5b6bfdb 100644 --- a/src/emu/cpu/m6805/m6805.c +++ b/src/emu/cpu/m6805/m6805.c @@ -36,92 +36,47 @@ #define IRQ_LEVEL_DETECT 0 -enum -{ - SUBTYPE_M6805, - SUBTYPE_M68705, - SUBTYPE_HD63705, - SUBTYPE_M68HC05EG -}; - -/* 6805 Registers */ -struct m6805_Regs -{ - /* Pre-pointerafied public globals */ - int iCount; - PAIR ea; /* effective address */ - - int subtype; /* Which sub-type is being emulated */ - UINT32 sp_mask; /* Stack pointer address mask */ - UINT32 sp_low; /* Stack pointer low water mark (or floor) */ - PAIR pc; /* Program counter */ - PAIR s; /* Stack pointer */ - UINT8 a; /* Accumulator */ - UINT8 x; /* Index register */ - UINT8 cc; /* Condition codes */ - - UINT16 pending_interrupts; /* MB */ - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *program; - direct_read_data *direct; - int irq_state[9]; /* KW Additional lines for HD63705 */ - int nmi_state; -}; - -INLINE m6805_Regs *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == M6805 || - device->type() == M68705 || - device->type() == HD63705 || - device->type() == M68HC05EG); - return (m6805_Regs *)downcast(device)->token(); -} - /****************************************************************************/ /* Read a byte from given memory location */ /****************************************************************************/ -#define M6805_RDMEM(Addr) ((unsigned)cpustate->program->read_byte(Addr)) +#define M6805_RDMEM(addr) ((unsigned)m_program->read_byte(addr)) /****************************************************************************/ /* Write a byte to given memory location */ /****************************************************************************/ -#define M6805_WRMEM(Addr,Value) (cpustate->program->write_byte(Addr,Value)) +#define M6805_WRMEM(addr, value) (m_program->write_byte(addr, value)) /****************************************************************************/ /* M6805_RDOP() is identical to M6805_RDMEM() except it is used for reading */ /* opcodes. In case of system with memory mapped I/O, this function can be */ /* used to greatly speed up emulation */ /****************************************************************************/ -#define M6805_RDOP(Addr) ((unsigned)cpustate->direct->read_decrypted_byte(Addr)) +#define M6805_RDOP(addr) ((unsigned)m_direct->read_decrypted_byte(addr)) /****************************************************************************/ /* M6805_RDOP_ARG() is identical to M6805_RDOP() but it's used for reading */ /* opcode arguments. This difference can be used to support systems that */ /* use different encoding mechanisms for opcodes and opcode arguments */ /****************************************************************************/ -#define M6805_RDOP_ARG(Addr) ((unsigned)cpustate->direct->read_raw_byte(Addr)) +#define M6805_RDOP_ARG(addr) ((unsigned)m_direct->read_raw_byte(addr)) -#define SUBTYPE cpustate->subtype /* CPU Type */ -#define SP_MASK cpustate->sp_mask /* stack pointer mask */ -#define SP_LOW cpustate->sp_low /* stack pointer low water mark */ -#define pPC cpustate->pc /* program counter PAIR */ -#define PC cpustate->pc.w.l /* program counter lower word */ -#define S cpustate->s.w.l /* stack pointer lower word */ -#define A cpustate->a /* accumulator */ -#define X cpustate->x /* index register */ -#define CC cpustate->cc /* condition codes */ +#define SP_MASK m_sp_mask /* stack pointer mask */ +#define SP_LOW m_sp_low /* stack pointer low water mark */ +#define PC m_pc.w.l /* program counter lower word */ +#define S m_s.w.l /* stack pointer lower word */ +#define A m_a /* accumulator */ +#define X m_x /* index register */ +#define CC m_cc /* condition codes */ -#define EAD cpustate->ea.d -#define EA cpustate->ea.w.l +#define EAD m_ea.d +#define EA m_ea.w.l /* DS -- THESE ARE RE-DEFINED IN m6805.h TO RAM, ROM or FUNCTIONS IN cpuintrf.c */ -#define RM(Addr) M6805_RDMEM(Addr) -#define WM(Addr,Value) M6805_WRMEM(Addr,Value) -#define M_RDOP(Addr) M6805_RDOP(Addr) -#define M_RDOP_ARG(Addr) M6805_RDOP_ARG(Addr) +#define RM(addr) M6805_RDMEM(addr) +#define WM(addr, value) M6805_WRMEM(addr, value) +#define M_RDOP(addr) M6805_RDOP(addr) +#define M_RDOP_ARG(addr) M6805_RDOP_ARG(addr) /* macros to tweak the PC and SP */ #define SP_INC if( ++S > SP_MASK) S = SP_LOW @@ -132,10 +87,10 @@ INLINE m6805_Regs *get_safe_token(device_t *device) #define IMMBYTE(b) {b = M_RDOP_ARG(PC++);} #define IMMWORD(w) {w.d = 0; w.b.h = M_RDOP_ARG(PC); w.b.l = M_RDOP_ARG(PC+1); PC+=2;} -#define PUSHBYTE(b) wr_s_handler_b(cpustate, &b) -#define PUSHWORD(w) wr_s_handler_w(cpustate, &w) -#define PULLBYTE(b) rd_s_handler_b(cpustate, &b) -#define PULLWORD(w) rd_s_handler_w(cpustate, &w) +#define PUSHBYTE(b) wr_s_handler_b(&b) +#define PUSHWORD(w) wr_s_handler_w(&w) +#define PULLBYTE(b) rd_s_handler_b(&b) +#define PULLWORD(w) rd_s_handler_w(&w) /* CC masks H INZC 7654 3210 */ @@ -158,88 +113,89 @@ INLINE m6805_Regs *get_safe_token(device_t *device) #define SET_H(a,b,r) CC|=((a^b^r)&0x10) #define SET_C8(a) CC|=((a&0x100)>>8) -static const UINT8 flags8i[256]= /* increment */ +const UINT8 m6805_base_device::m_flags8i[256]= /* increment */ { -0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 }; -static const UINT8 flags8d[256]= /* decrement */ + +const UINT8 m6805_base_device::m_flags8d[256]= /* decrement */ { -0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, -0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04, + 0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04 }; -#define SET_FLAGS8I(a) {CC|=flags8i[(a)&0xff];} -#define SET_FLAGS8D(a) {CC|=flags8d[(a)&0xff];} +#define SET_FLAGS8I(a) {CC |= m_flags8i[(a) & 0xff];} +#define SET_FLAGS8D(a) {CC |= m_flags8d[(a) & 0xff];} /* combos */ -#define SET_NZ8(a) {SET_N8(a);SET_Z(a);} -#define SET_FLAGS8(a,b,r) {SET_N8(r);SET_Z8(r);SET_C8(r);} +#define SET_NZ8(a) {SET_N8(a); SET_Z(a);} +#define SET_FLAGS8(a,b,r) {SET_N8(r); SET_Z8(r); SET_C8(r);} /* for treating an unsigned UINT8 as a signed INT16 */ -#define SIGNED(b) ((INT16)(b&0x80?b|0xff00:b)) +#define SIGNED(b) ((INT16)(b & 0x80 ? b | 0xff00 : b)) /* Macros for addressing modes */ -#define DIRECT EAD=0;IMMBYTE(cpustate->ea.b.l) -#define IMM8 EA=PC++ -#define EXTENDED IMMWORD(cpustate->ea) -#define INDEXED EA=X -#define INDEXED1 {EAD=0; IMMBYTE(cpustate->ea.b.l); EA+=X;} -#define INDEXED2 {IMMWORD(cpustate->ea); EA+=X;} +#define DIRECT EAD=0; IMMBYTE(m_ea.b.l) +#define IMM8 EA = PC++ +#define EXTENDED IMMWORD(m_ea) +#define INDEXED EA = X +#define INDEXED1 {EAD = 0; IMMBYTE(m_ea.b.l); EA += X;} +#define INDEXED2 {IMMWORD(m_ea); EA += X;} /* macros to set status flags */ #if defined(SEC) #undef SEC #endif -#define SEC CC|=CFLAG -#define CLC CC&=~CFLAG -#define SEZ CC|=ZFLAG -#define CLZ CC&=~ZFLAG -#define SEN CC|=NFLAG -#define CLN CC&=~NFLAG -#define SEH CC|=HFLAG -#define CLH CC&=~HFLAG -#define SEI CC|=IFLAG -#define CLI CC&=~IFLAG +#define SEC CC |= CFLAG +#define CLC CC &=~ CFLAG +#define SEZ CC |= ZFLAG +#define CLZ CC &=~ ZFLAG +#define SEN CC |= NFLAG +#define CLN CC &=~ NFLAG +#define SEH CC |= HFLAG +#define CLH CC &=~ HFLAG +#define SEI CC |= IFLAG +#define CLI CC &=~ IFLAG /* macros for convenience */ -#define DIRBYTE(b) {DIRECT;b=RM(EAD);} -#define EXTBYTE(b) {EXTENDED;b=RM(EAD);} -#define IDXBYTE(b) {INDEXED;b=RM(EAD);} -#define IDX1BYTE(b) {INDEXED1;b=RM(EAD);} -#define IDX2BYTE(b) {INDEXED2;b=RM(EAD);} +#define DIRBYTE(b) {DIRECT; b = RM(EAD);} +#define EXTBYTE(b) {EXTENDED; b = RM(EAD);} +#define IDXBYTE(b) {INDEXED; b = RM(EAD);} +#define IDX1BYTE(b) {INDEXED1; b = RM(EAD);} +#define IDX2BYTE(b) {INDEXED2; b = RM(EAD);} /* Macros for branch instructions */ -#define BRANCH(f) { UINT8 t; IMMBYTE(t); if(f) { PC+=SIGNED(t); if (t==0xfe) { /* speed up busy loops */ if(cpustate->iCount > 0) cpustate->iCount = 0; } } } +#define BRANCH(f) { UINT8 t; IMMBYTE(t); if(f) { PC += SIGNED(t); if (t == 0xfe) { /* speed up busy loops */ if(m_icount > 0) m_icount = 0; } } } /* what they say it is ... */ -static const unsigned char cycles1[] = +const UINT8 m6805_base_device::m_cycles1[] = { /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ /*0*/ 10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10, @@ -264,13 +220,13 @@ static const unsigned char cycles1[] = /* pre-clear a PAIR union; clearing h2 and h3 only might be faster? */ #define CLEAR_PAIR(p) p->d = 0 -INLINE void rd_s_handler_b( m6805_Regs *cpustate, UINT8 *b ) +void m6805_base_device::rd_s_handler_b(UINT8 *b) { SP_INC; *b = RM( S ); } -INLINE void rd_s_handler_w( m6805_Regs *cpustate, PAIR *p ) +void m6805_base_device::rd_s_handler_w(PAIR *p) { CLEAR_PAIR(p); SP_INC; @@ -279,13 +235,13 @@ INLINE void rd_s_handler_w( m6805_Regs *cpustate, PAIR *p ) p->b.l = RM( S ); } -INLINE void wr_s_handler_b( m6805_Regs *cpustate, UINT8 *b ) +void m6805_base_device::wr_s_handler_b(UINT8 *b) { WM( S, *b ); SP_DEC; } -INLINE void wr_s_handler_w( m6805_Regs *cpustate, PAIR *p ) +void m6805_base_device::wr_s_handler_w(PAIR *p) { WM( S, p->b.l ); SP_DEC; @@ -293,567 +249,678 @@ INLINE void wr_s_handler_w( m6805_Regs *cpustate, PAIR *p ) SP_DEC; } -INLINE void RM16( m6805_Regs *cpustate, UINT32 Addr, PAIR *p ) +void m6805_base_device::RM16(UINT32 addr, PAIR *p) { CLEAR_PAIR(p); - p->b.h = RM(Addr); - ++Addr; -// if( ++Addr > AMASK ) Addr = 0; - p->b.l = RM(Addr); + p->b.h = RM(addr); + ++addr; +// if( ++addr > AMASK ) addr = 0; + p->b.l = RM(addr); } -#ifdef UNUSED_FUNCTION -INLINE void WM16( m6805_Regs *cpustate, UINT32 Addr, PAIR *p ) -{ - WM( Addr, p->b.h ); - ++Addr; -// if( ++Addr > AMASK ) Addr = 0; - WM( Addr, p->b.l ); -} -#endif - - /* Generate interrupt - m68705 version */ -static void m68705_Interrupt( m6805_Regs *cpustate ) +void m68705_device::interrupt() { - if( (cpustate->pending_interrupts & ((1<pc); - PUSHBYTE(cpustate->x); - PUSHBYTE(cpustate->a); - PUSHBYTE(cpustate->cc); + PUSHWORD(m_pc); + PUSHBYTE(m_x); + PUSHBYTE(m_a); + PUSHBYTE(m_cc); SEI; - if (cpustate->irq_callback) - (*cpustate->irq_callback)(cpustate->device, 0); + standard_irq_callback(0); - if ((cpustate->pending_interrupts & (1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<iCount -= 11; + m_icount -= 11; + } +} + +void m6805_base_device::interrupt_vector() +{ + RM16(0xffff - 5, &m_pc); +} + +void m68hc05eg_device::interrupt_vector() +{ + if ((m_pending_interrupts & (1 << M68HC05EG_INT_IRQ)) != 0) + { + m_pending_interrupts &= ~(1 << M68HC05EG_INT_IRQ); + RM16(0x1ffa, &m_pc); + } + else if((m_pending_interrupts & (1 << M68HC05EG_INT_TIMER)) != 0) + { + m_pending_interrupts &= ~(1 << M68HC05EG_INT_TIMER); + RM16(0x1ff8, &m_pc); + } + else if((m_pending_interrupts & (1 << M68HC05EG_INT_CPI)) != 0) + { + m_pending_interrupts &= ~(1 << M68HC05EG_INT_CPI); + RM16(0x1ff6, &m_pc); + } +} + +void hd63705_device::interrupt_vector() +{ + /* Need to add emulation of other interrupt sources here KW-2/4/99 */ + /* This is just a quick patch for Namco System 2 operation */ + + if ((m_pending_interrupts & (1 << HD63705_INT_IRQ1)) != 0) + { + m_pending_interrupts &= ~(1 << HD63705_INT_IRQ1); + RM16(0x1ff8, &m_pc); + } + else if ((m_pending_interrupts & (1 << HD63705_INT_IRQ2)) != 0) + { + m_pending_interrupts &= ~(1 << HD63705_INT_IRQ2); + RM16(0x1fec, &m_pc); + } + else if ((m_pending_interrupts & (1 << HD63705_INT_ADCONV)) != 0) + { + m_pending_interrupts &= ~(1 << HD63705_INT_ADCONV); + RM16(0x1fea, &m_pc); + } + else if ((m_pending_interrupts & (1 << HD63705_INT_TIMER1)) != 0) + { + m_pending_interrupts &= ~(1 << HD63705_INT_TIMER1); + RM16(0x1ff6, &m_pc); + } + else if ((m_pending_interrupts & (1 << HD63705_INT_TIMER2)) != 0) + { + m_pending_interrupts &= ~(1 << HD63705_INT_TIMER2); + RM16(0x1ff4, &m_pc); + } + else if ((m_pending_interrupts & (1 << HD63705_INT_TIMER3)) != 0) + { + m_pending_interrupts &= ~(1<pending_interrupts & (1<pc); - PUSHBYTE(cpustate->x); - PUSHBYTE(cpustate->a); - PUSHBYTE(cpustate->cc); + PUSHWORD(m_pc); + PUSHBYTE(m_x); + PUSHBYTE(m_a); + PUSHBYTE(m_cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ - if (cpustate->irq_callback) - (*cpustate->irq_callback)(cpustate->device, 0); + standard_irq_callback(0); - RM16( cpustate, 0x1ffc, &pPC); - cpustate->pending_interrupts &= ~(1<iCount -= 11; + RM16(0x1ffc, &m_pc); + m_pending_interrupts &= ~(1 << HD63705_INT_NMI); + m_icount -= 11; } - else if( (cpustate->pending_interrupts & ((1<pc); - PUSHBYTE(cpustate->x); - PUSHBYTE(cpustate->a); - PUSHBYTE(cpustate->cc); - SEI; - /* no vectors supported, just do the callback to clear irq_state if needed */ - if (cpustate->irq_callback) - (*cpustate->irq_callback)(cpustate->device, 0); - - - if(SUBTYPE==SUBTYPE_HD63705) + if ((CC & IFLAG) == 0) { - /* Need to add emulation of other interrupt sources here KW-2/4/99 */ - /* This is just a quick patch for Namco System 2 operation */ + /* standard IRQ */ + PUSHWORD(m_pc); + PUSHBYTE(m_x); + PUSHBYTE(m_a); + PUSHBYTE(m_cc); + SEI; + /* no vectors supported, just do the callback to clear irq_state if needed */ + standard_irq_callback(0); - if((cpustate->pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts&(1<pending_interrupts &= ~(1<pending_interrupts &= ~(1<iCount -= 11; + m_icount -= 11; } } -static void state_register(m6805_Regs *cpustate, const char *type, legacy_cpu_device *device) + +//------------------------------------------------- +// m6809_base_device - constructor +//------------------------------------------------- + +m6805_base_device::m6805_base_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, const device_type type, const char *name, UINT32 addr_width) + : cpu_device(mconfig, type, name, tag, owner, clock), + m_program_config("program", ENDIANNESS_BIG, 8, addr_width) { - device->save_item(NAME(A)); - device->save_item(NAME(PC)); - device->save_item(NAME(S)); - device->save_item(NAME(X)); - device->save_item(NAME(CC)); - device->save_item(NAME(cpustate->pending_interrupts)); - device->save_item(NAME(cpustate->irq_state)); } -static CPU_INIT( m6805 ) +void m6805_base_device::device_start() { - m6805_Regs *cpustate = get_safe_token(device); + // register our state for the debugger + astring tempstr; + state_add(STATE_GENPC, "GENPC", m_pc.w.l).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_cc).callimport().callexport().formatstr("%8s").noshow(); + state_add(M6805_A, "A", m_a).mask(0xff); + state_add(M6805_PC, "PC", m_pc.w.l).mask(0xffff); + state_add(M6805_S, "S", m_s.w.l).mask(0xff); + state_add(M6805_X, "X", m_x).mask(0xff); + state_add(M6805_CC, "CC", m_cc).mask(0xff); - state_register(cpustate, "m6805", device); - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); + save_item(NAME(A)); + save_item(NAME(PC)); + save_item(NAME(S)); + save_item(NAME(X)); + save_item(NAME(CC)); + save_item(NAME(m_pending_interrupts)); + save_item(NAME(m_irq_state)); + + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + + // set our instruction counter + m_icountptr = &m_icount; + m_icount = 50000; } -static CPU_RESET( m6805 ) + +void m6805_base_device::device_reset() { - m6805_Regs *cpustate = get_safe_token(device); + m_ea.w.l = 0; + m_sp_mask = 0x07f; + m_sp_low = 0x060; + m_pc.w.l = 0; + m_s.w.l = SP_MASK; + m_a = 0; + m_x = 0; + m_cc = 0; + m_pending_interrupts = 0; - device_irq_acknowledge_callback save_irqcallback = cpustate->irq_callback; - memset(cpustate, 0, sizeof(*cpustate)); + memset(m_irq_state, 0, sizeof(int) * 9); + m_nmi_state = 0; - cpustate->iCount=50000; /* Used to be global */ - cpustate->irq_callback = save_irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); + m_icount = 50000; - /* Force CPU sub-type and relevant masks */ - cpustate->subtype = SUBTYPE_M6805; - SP_MASK = 0x07f; - SP_LOW = 0x060; - - /* Initial stack pointer */ - S = SP_MASK; + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); /* IRQ disabled */ SEI; - RM16( cpustate, 0xfffe, &pPC ); + + RM16(0xfffe, &m_pc); } -static CPU_EXIT( m6805 ) + +//------------------------------------------------- +// memory_space_config - return the configuration +// of the specified address space, or NULL if +// the space doesn't exist +//------------------------------------------------- + +const address_space_config *m6805_base_device::memory_space_config(address_spacenum spacenum) const { - /* nothing to do */ + if (spacenum == AS_PROGRAM) + { + return &m_program_config; + } + return NULL; } -static void set_irq_line( m6805_Regs *cpustate, int irqline, int state ) +//------------------------------------------------- +// state_string_export - export state as a string +// for the debugger +//------------------------------------------------- + +void m6805_base_device::state_string_export(const device_state_entry &entry, astring &string) +{ + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("%c%c%c%c%c%c%c%c", + (m_cc & 0x80) ? '?' : '.', + (m_cc & 0x40) ? '?' : '.', + (m_cc & 0x20) ? '?' : '.', + (m_cc & 0x10) ? 'H' : '.', + (m_cc & 0x08) ? 'I' : '.', + (m_cc & 0x04) ? 'N' : '.', + (m_cc & 0x02) ? 'Z' : '.', + (m_cc & 0x01) ? 'C' : '.'); + break; + } +} + + +//------------------------------------------------- +// disasm_min_opcode_bytes - return the length +// of the shortest instruction, in bytes +//------------------------------------------------- + +UINT32 m6805_base_device::disasm_min_opcode_bytes() const +{ + return 1; +} + + +//------------------------------------------------- +// disasm_max_opcode_bytes - return the length +// of the longest instruction, in bytes +//------------------------------------------------- + +UINT32 m6805_base_device::disasm_max_opcode_bytes() const +{ + return 3; +} + + +//------------------------------------------------- +// disasm_disassemble - call the disassembly +// helper function +//------------------------------------------------- + +offs_t m6805_base_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( m6805 ); + return cpu_disassemble_m6805(NULL, buffer, pc, oprom, opram, options); +} + + +void m6805_device::execute_set_input(int inputnum, int state) { /* Basic 6805 only has one IRQ line */ /* See HD63705 specific version */ - if (cpustate->irq_state[0] == state) return; + if (m_irq_state[0] != state) + { + m_irq_state[0] = state; - cpustate->irq_state[0] = state; - if (state != CLEAR_LINE) - cpustate->pending_interrupts |= 1<pending_interrupts != 0) + if (m_pending_interrupts != 0) { - if (SUBTYPE==SUBTYPE_M68705) - { - m68705_Interrupt(cpustate); - } - else - { - Interrupt(cpustate); - } + interrupt(); } - debugger_instruction_hook(device, PC); + debugger_instruction_hook(this, PC); ireg=M_RDOP(PC++); switch( ireg ) { - case 0x00: brset(cpustate, 0x01); break; - case 0x01: brclr(cpustate, 0x01); break; - case 0x02: brset(cpustate, 0x02); break; - case 0x03: brclr(cpustate, 0x02); break; - case 0x04: brset(cpustate, 0x04); break; - case 0x05: brclr(cpustate, 0x04); break; - case 0x06: brset(cpustate, 0x08); break; - case 0x07: brclr(cpustate, 0x08); break; - case 0x08: brset(cpustate, 0x10); break; - case 0x09: brclr(cpustate, 0x10); break; - case 0x0A: brset(cpustate, 0x20); break; - case 0x0B: brclr(cpustate, 0x20); break; - case 0x0C: brset(cpustate, 0x40); break; - case 0x0D: brclr(cpustate, 0x40); break; - case 0x0E: brset(cpustate, 0x80); break; - case 0x0F: brclr(cpustate, 0x80); break; - case 0x10: bset(cpustate, 0x01); break; - case 0x11: bclr(cpustate, 0x01); break; - case 0x12: bset(cpustate, 0x02); break; - case 0x13: bclr(cpustate, 0x02); break; - case 0x14: bset(cpustate, 0x04); break; - case 0x15: bclr(cpustate, 0x04); break; - case 0x16: bset(cpustate, 0x08); break; - case 0x17: bclr(cpustate, 0x08); break; - case 0x18: bset(cpustate, 0x10); break; - case 0x19: bclr(cpustate, 0x10); break; - case 0x1a: bset(cpustate, 0x20); break; - case 0x1b: bclr(cpustate, 0x20); break; - case 0x1c: bset(cpustate, 0x40); break; - case 0x1d: bclr(cpustate, 0x40); break; - case 0x1e: bset(cpustate, 0x80); break; - case 0x1f: bclr(cpustate, 0x80); break; - case 0x20: bra(cpustate); break; - case 0x21: brn(cpustate); break; - case 0x22: bhi(cpustate); break; - case 0x23: bls(cpustate); break; - case 0x24: bcc(cpustate); break; - case 0x25: bcs(cpustate); break; - case 0x26: bne(cpustate); break; - case 0x27: beq(cpustate); break; - case 0x28: bhcc(cpustate); break; - case 0x29: bhcs(cpustate); break; - case 0x2a: bpl(cpustate); break; - case 0x2b: bmi(cpustate); break; - case 0x2c: bmc(cpustate); break; - case 0x2d: bms(cpustate); break; - case 0x2e: bil(cpustate); break; - case 0x2f: bih(cpustate); break; - case 0x30: neg_di(cpustate); break; - case 0x31: illegal(cpustate); break; - case 0x32: illegal(cpustate); break; - case 0x33: com_di(cpustate); break; - case 0x34: lsr_di(cpustate); break; - case 0x35: illegal(cpustate); break; - case 0x36: ror_di(cpustate); break; - case 0x37: asr_di(cpustate); break; - case 0x38: lsl_di(cpustate); break; - case 0x39: rol_di(cpustate); break; - case 0x3a: dec_di(cpustate); break; - case 0x3b: illegal(cpustate); break; - case 0x3c: inc_di(cpustate); break; - case 0x3d: tst_di(cpustate); break; - case 0x3e: illegal(cpustate); break; - case 0x3f: clr_di(cpustate); break; - case 0x40: nega(cpustate); break; - case 0x41: illegal(cpustate); break; - case 0x42: illegal(cpustate); break; - case 0x43: coma(cpustate); break; - case 0x44: lsra(cpustate); break; - case 0x45: illegal(cpustate); break; - case 0x46: rora(cpustate); break; - case 0x47: asra(cpustate); break; - case 0x48: lsla(cpustate); break; - case 0x49: rola(cpustate); break; - case 0x4a: deca(cpustate); break; - case 0x4b: illegal(cpustate); break; - case 0x4c: inca(cpustate); break; - case 0x4d: tsta(cpustate); break; - case 0x4e: illegal(cpustate); break; - case 0x4f: clra(cpustate); break; - case 0x50: negx(cpustate); break; - case 0x51: illegal(cpustate); break; - case 0x52: illegal(cpustate); break; - case 0x53: comx(cpustate); break; - case 0x54: lsrx(cpustate); break; - case 0x55: illegal(cpustate); break; - case 0x56: rorx(cpustate); break; - case 0x57: asrx(cpustate); break; - case 0x58: aslx(cpustate); break; - case 0x59: rolx(cpustate); break; - case 0x5a: decx(cpustate); break; - case 0x5b: illegal(cpustate); break; - case 0x5c: incx(cpustate); break; - case 0x5d: tstx(cpustate); break; - case 0x5e: illegal(cpustate); break; - case 0x5f: clrx(cpustate); break; - case 0x60: neg_ix1(cpustate); break; - case 0x61: illegal(cpustate); break; - case 0x62: illegal(cpustate); break; - case 0x63: com_ix1(cpustate); break; - case 0x64: lsr_ix1(cpustate); break; - case 0x65: illegal(cpustate); break; - case 0x66: ror_ix1(cpustate); break; - case 0x67: asr_ix1(cpustate); break; - case 0x68: lsl_ix1(cpustate); break; - case 0x69: rol_ix1(cpustate); break; - case 0x6a: dec_ix1(cpustate); break; - case 0x6b: illegal(cpustate); break; - case 0x6c: inc_ix1(cpustate); break; - case 0x6d: tst_ix1(cpustate); break; - case 0x6e: illegal(cpustate); break; - case 0x6f: clr_ix1(cpustate); break; - case 0x70: neg_ix(cpustate); break; - case 0x71: illegal(cpustate); break; - case 0x72: illegal(cpustate); break; - case 0x73: com_ix(cpustate); break; - case 0x74: lsr_ix(cpustate); break; - case 0x75: illegal(cpustate); break; - case 0x76: ror_ix(cpustate); break; - case 0x77: asr_ix(cpustate); break; - case 0x78: lsl_ix(cpustate); break; - case 0x79: rol_ix(cpustate); break; - case 0x7a: dec_ix(cpustate); break; - case 0x7b: illegal(cpustate); break; - case 0x7c: inc_ix(cpustate); break; - case 0x7d: tst_ix(cpustate); break; - case 0x7e: illegal(cpustate); break; - case 0x7f: clr_ix(cpustate); break; - case 0x80: rti(cpustate); break; - case 0x81: rts(cpustate); break; - case 0x82: illegal(cpustate); break; - case 0x83: swi(cpustate); break; - case 0x84: illegal(cpustate); break; - case 0x85: illegal(cpustate); break; - case 0x86: illegal(cpustate); break; - case 0x87: illegal(cpustate); break; - case 0x88: illegal(cpustate); break; - case 0x89: illegal(cpustate); break; - case 0x8a: illegal(cpustate); break; - case 0x8b: illegal(cpustate); break; - case 0x8c: illegal(cpustate); break; - case 0x8d: illegal(cpustate); break; - case 0x8e: illegal(cpustate); break; - case 0x8f: illegal(cpustate); break; - case 0x90: illegal(cpustate); break; - case 0x91: illegal(cpustate); break; - case 0x92: illegal(cpustate); break; - case 0x93: illegal(cpustate); break; - case 0x94: illegal(cpustate); break; - case 0x95: illegal(cpustate); break; - case 0x96: illegal(cpustate); break; - case 0x97: tax(cpustate); break; + case 0x00: brset(0x01); break; + case 0x01: brclr(0x01); break; + case 0x02: brset(0x02); break; + case 0x03: brclr(0x02); break; + case 0x04: brset(0x04); break; + case 0x05: brclr(0x04); break; + case 0x06: brset(0x08); break; + case 0x07: brclr(0x08); break; + case 0x08: brset(0x10); break; + case 0x09: brclr(0x10); break; + case 0x0A: brset(0x20); break; + case 0x0B: brclr(0x20); break; + case 0x0C: brset(0x40); break; + case 0x0D: brclr(0x40); break; + case 0x0E: brset(0x80); break; + case 0x0F: brclr(0x80); break; + case 0x10: bset(0x01); break; + case 0x11: bclr(0x01); break; + case 0x12: bset(0x02); break; + case 0x13: bclr(0x02); break; + case 0x14: bset(0x04); break; + case 0x15: bclr(0x04); break; + case 0x16: bset(0x08); break; + case 0x17: bclr(0x08); break; + case 0x18: bset(0x10); break; + case 0x19: bclr(0x10); break; + case 0x1a: bset(0x20); break; + case 0x1b: bclr(0x20); break; + case 0x1c: bset(0x40); break; + case 0x1d: bclr(0x40); break; + case 0x1e: bset(0x80); break; + case 0x1f: bclr(0x80); break; + case 0x20: bra(); break; + case 0x21: brn(); break; + case 0x22: bhi(); break; + case 0x23: bls(); break; + case 0x24: bcc(); break; + case 0x25: bcs(); break; + case 0x26: bne(); break; + case 0x27: beq(); break; + case 0x28: bhcc(); break; + case 0x29: bhcs(); break; + case 0x2a: bpl(); break; + case 0x2b: bmi(); break; + case 0x2c: bmc(); break; + case 0x2d: bms(); break; + case 0x2e: bil(); break; + case 0x2f: bih(); break; + case 0x30: neg_di(); break; + case 0x31: illegal(); break; + case 0x32: illegal(); break; + case 0x33: com_di(); break; + case 0x34: lsr_di(); break; + case 0x35: illegal(); break; + case 0x36: ror_di(); break; + case 0x37: asr_di(); break; + case 0x38: lsl_di(); break; + case 0x39: rol_di(); break; + case 0x3a: dec_di(); break; + case 0x3b: illegal(); break; + case 0x3c: inc_di(); break; + case 0x3d: tst_di(); break; + case 0x3e: illegal(); break; + case 0x3f: clr_di(); break; + case 0x40: nega(); break; + case 0x41: illegal(); break; + case 0x42: illegal(); break; + case 0x43: coma(); break; + case 0x44: lsra(); break; + case 0x45: illegal(); break; + case 0x46: rora(); break; + case 0x47: asra(); break; + case 0x48: lsla(); break; + case 0x49: rola(); break; + case 0x4a: deca(); break; + case 0x4b: illegal(); break; + case 0x4c: inca(); break; + case 0x4d: tsta(); break; + case 0x4e: illegal(); break; + case 0x4f: clra(); break; + case 0x50: negx(); break; + case 0x51: illegal(); break; + case 0x52: illegal(); break; + case 0x53: comx(); break; + case 0x54: lsrx(); break; + case 0x55: illegal(); break; + case 0x56: rorx(); break; + case 0x57: asrx(); break; + case 0x58: aslx(); break; + case 0x59: rolx(); break; + case 0x5a: decx(); break; + case 0x5b: illegal(); break; + case 0x5c: incx(); break; + case 0x5d: tstx(); break; + case 0x5e: illegal(); break; + case 0x5f: clrx(); break; + case 0x60: neg_ix1(); break; + case 0x61: illegal(); break; + case 0x62: illegal(); break; + case 0x63: com_ix1(); break; + case 0x64: lsr_ix1(); break; + case 0x65: illegal(); break; + case 0x66: ror_ix1(); break; + case 0x67: asr_ix1(); break; + case 0x68: lsl_ix1(); break; + case 0x69: rol_ix1(); break; + case 0x6a: dec_ix1(); break; + case 0x6b: illegal(); break; + case 0x6c: inc_ix1(); break; + case 0x6d: tst_ix1(); break; + case 0x6e: illegal(); break; + case 0x6f: clr_ix1(); break; + case 0x70: neg_ix(); break; + case 0x71: illegal(); break; + case 0x72: illegal(); break; + case 0x73: com_ix(); break; + case 0x74: lsr_ix(); break; + case 0x75: illegal(); break; + case 0x76: ror_ix(); break; + case 0x77: asr_ix(); break; + case 0x78: lsl_ix(); break; + case 0x79: rol_ix(); break; + case 0x7a: dec_ix(); break; + case 0x7b: illegal(); break; + case 0x7c: inc_ix(); break; + case 0x7d: tst_ix(); break; + case 0x7e: illegal(); break; + case 0x7f: clr_ix(); break; + case 0x80: rti(); break; + case 0x81: rts(); break; + case 0x82: illegal(); break; + case 0x83: swi(); break; + case 0x84: illegal(); break; + case 0x85: illegal(); break; + case 0x86: illegal(); break; + case 0x87: illegal(); break; + case 0x88: illegal(); break; + case 0x89: illegal(); break; + case 0x8a: illegal(); break; + case 0x8b: illegal(); break; + case 0x8c: illegal(); break; + case 0x8d: illegal(); break; + case 0x8e: illegal(); break; + case 0x8f: illegal(); break; + case 0x90: illegal(); break; + case 0x91: illegal(); break; + case 0x92: illegal(); break; + case 0x93: illegal(); break; + case 0x94: illegal(); break; + case 0x95: illegal(); break; + case 0x96: illegal(); break; + case 0x97: tax(); break; case 0x98: CLC; break; case 0x99: SEC; break; #if IRQ_LEVEL_DETECT - case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts |= 1<iCount -= cycles1[ireg]; - } while( cpustate->iCount > 0 ); + m_icount -= m_cycles1[ireg]; + } while( m_icount > 0 ); } /**************************************************************************** * M68HC05EG section ****************************************************************************/ -static CPU_INIT( m68hc05eg ) +void m68hc05eg_device::device_reset() { - m6805_Regs *cpustate = get_safe_token(device); - state_register(cpustate, "m68hc05eg", device); - cpustate->irq_callback = irqcallback; - cpustate->device = device; + m6805_base_device::device_reset(); + + m_sp_mask = 0xff; + m_sp_low = 0xc0; + + RM16(0x1ffe, &m_pc); } -static CPU_RESET( m68hc05eg ) +void m68hc05eg_device::execute_set_input(int inputnum, int state) { - m6805_Regs *cpustate = get_safe_token(device); - CPU_RESET_CALL(m6805); - - /* Overide default 6805 type */ - cpustate->subtype = SUBTYPE_M68HC05EG; - SP_MASK = 0xff; - SP_LOW = 0xc0; - RM16( cpustate, 0x1ffe, &cpustate->pc ); -} - -static void m68hc05eg_set_irq_line(m6805_Regs *cpustate, int irqline, int state) -{ - if (cpustate->irq_state[irqline] != state) + if (m_irq_state[inputnum] != state) { - cpustate->irq_state[irqline] = state; + m_irq_state[inputnum] = state; if (state != CLEAR_LINE) { - cpustate->pending_interrupts |= 1<irq_callback = irqcallback; - cpustate->device = device; + m6805_base_device::device_reset(); + + RM16(0xfffe, &m_pc); } -static CPU_RESET( m68705 ) +void m68705_device::execute_set_input(int inputnum, int state) { - m6805_Regs *cpustate = get_safe_token(device); - CPU_RESET_CALL(m6805); + if (m_irq_state[inputnum] != state) + { + m_irq_state[inputnum] = state; - /* Overide default 6805 type */ - cpustate->subtype = SUBTYPE_M68705; - RM16( cpustate, 0xfffe, &cpustate->pc ); -} - -static void m68705_set_irq_line(m6805_Regs *cpustate, int irqline, int state) -{ - if (cpustate->irq_state[irqline] == state ) return; - cpustate->irq_state[irqline] = state; - if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<irq_callback = irqcallback; - cpustate->device = device; + m6805_base_device::device_reset(); + + m_sp_mask = 0x17f; + m_sp_low = 0x100; + m_s.w.l = SP_MASK; + + RM16(0x1ffe, &m_pc); } -static CPU_RESET( hd63705 ) +void hd63705_device::execute_set_input(int inputnum, int state) { - m6805_Regs *cpustate = get_safe_token(device); - CPU_RESET_CALL(m6805); - - /* Overide default 6805 types */ - cpustate->subtype = SUBTYPE_HD63705; - SP_MASK = 0x17f; - SP_LOW = 0x100; - RM16( cpustate, 0x1ffe, &cpustate->pc ); - S = 0x17f; -} - -static void hd63705_set_irq_line(m6805_Regs *cpustate, int irqline, int state) -{ - if (irqline == INPUT_LINE_NMI) + if (inputnum == INPUT_LINE_NMI) { - if (cpustate->nmi_state == state) return; + if (m_nmi_state != state) + { + m_nmi_state = state; - cpustate->nmi_state = state; - if (state != CLEAR_LINE) - cpustate->pending_interrupts |= 1<irq_state[irqline] == state) return; - cpustate->irq_state[irqline] = state; - if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<i); break; - - case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break; - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break; - case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break; - case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break; - } -} - - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( m6805 ) -{ - m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6805_Regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 2; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 10; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 12; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: info->i = cpustate->irq_state[M6805_IRQ_LINE]; break; - - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - case CPUINFO_INT_REGISTER + M6805_A: info->i = A; break; - case CPUINFO_INT_PC: info->i = PC; break; - case CPUINFO_INT_REGISTER + M6805_PC: info->i = PC; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + M6805_S: info->i = SP_ADJUST(S); break; - case CPUINFO_INT_REGISTER + M6805_X: info->i = X; break; - case CPUINFO_INT_REGISTER + M6805_CC: info->i = CC; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m6805); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m6805); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m6805); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(m6805); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m6805); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m6805);break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->iCount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M6805"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 6805"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "The MAME team."); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - cpustate->cc & 0x80 ? '?':'.', - cpustate->cc & 0x40 ? '?':'.', - cpustate->cc & 0x20 ? '?':'.', - cpustate->cc & 0x10 ? 'H':'.', - cpustate->cc & 0x08 ? 'I':'.', - cpustate->cc & 0x04 ? 'N':'.', - cpustate->cc & 0x02 ? 'Z':'.', - cpustate->cc & 0x01 ? 'C':'.'); - break; - - case CPUINFO_STR_REGISTER + M6805_A: sprintf(info->s, "A:%02X", cpustate->a); break; - case CPUINFO_STR_REGISTER + M6805_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break; - case CPUINFO_STR_REGISTER + M6805_S: sprintf(info->s, "S:%02X", cpustate->s.w.l); break; - case CPUINFO_STR_REGISTER + M6805_X: sprintf(info->s, "X:%02X", cpustate->x); break; - case CPUINFO_STR_REGISTER + M6805_CC: sprintf(info->s, "CC:%02X", cpustate->cc); break; - } -} - -/************************************************************************** - * CPU-specific set_info for 68HC05EG - **************************************************************************/ -static CPU_SET_INFO( m68hc05eg ) -{ - m6805_Regs *cpustate = get_safe_token(device); - - switch(state) - { - case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_IRQ: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_IRQ, info->i); break; - case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_TIMER: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_TIMER, info->i); break; - case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_CPI: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_CPI, info->i); break; - - default: CPU_SET_INFO_CALL(m6805); break; - } -} - -CPU_GET_INFO( m68hc05eg ) -{ - m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_IRQ: info->i = cpustate->irq_state[M68HC05EG_INT_IRQ]; break; - case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_TIMER: info->i = cpustate->irq_state[M68HC05EG_INT_TIMER]; break; - case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_CPI: info->i = cpustate->irq_state[M68HC05EG_INT_CPI]; break; - - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 13; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m68hc05eg); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68hc05eg); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m68hc05eg); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M68HC05EG"); break; - - default: CPU_GET_INFO_CALL(m6805); break; - } -} - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ -static CPU_SET_INFO( m68705 ) -{ - m6805_Regs *cpustate = get_safe_token(device); - - switch(state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M68705_INT_TIMER: m68705_set_irq_line(cpustate, M68705_INT_TIMER, info->i); break; - - default: CPU_SET_INFO_CALL(m6805); break; - } -} - -CPU_GET_INFO( m68705 ) -{ - m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + M68705_INT_TIMER: info->i = cpustate->irq_state[M68705_INT_TIMER]; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m68705); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68705); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m68705); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "M68705"); break; - - default: CPU_GET_INFO_CALL(m6805); break; - } -} - - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -static CPU_SET_INFO( hd63705 ) -{ - m6805_Regs *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ1: hd63705_set_irq_line(cpustate, HD63705_INT_IRQ1, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ2: hd63705_set_irq_line(cpustate, HD63705_INT_IRQ2, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER1: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER1, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER2: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER2, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER3: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER3, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_PCI: hd63705_set_irq_line(cpustate, HD63705_INT_PCI, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_SCI: hd63705_set_irq_line(cpustate, HD63705_INT_SCI, info->i); break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_ADCONV: hd63705_set_irq_line(cpustate, HD63705_INT_ADCONV, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: hd63705_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - - default: CPU_SET_INFO_CALL(m6805);break; - } -} - -CPU_GET_INFO( hd63705 ) -{ - m6805_Regs *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ1: info->i = cpustate->irq_state[HD63705_INT_IRQ1]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ2: info->i = cpustate->irq_state[HD63705_INT_IRQ2]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER1: info->i = cpustate->irq_state[HD63705_INT_TIMER1]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER2: info->i = cpustate->irq_state[HD63705_INT_TIMER2]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER3: info->i = cpustate->irq_state[HD63705_INT_TIMER3]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_PCI: info->i = cpustate->irq_state[HD63705_INT_PCI]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_SCI: info->i = cpustate->irq_state[HD63705_INT_SCI]; break; - case CPUINFO_INT_INPUT_STATE + HD63705_INT_ADCONV: info->i = cpustate->irq_state[HD63705_INT_ADCONV]; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->irq_state[HD63705_INT_NMI]; break; - - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hd63705); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hd63705); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hd63705); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "HD63705"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Keith Wilkins, Juergen Buchmueller"); break; - - default: CPU_GET_INFO_CALL(m6805); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(M6805, m6805); -DEFINE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg); -DEFINE_LEGACY_CPU_DEVICE(M68705, m68705); -DEFINE_LEGACY_CPU_DEVICE(HD63705, hd63705); +const device_type M6805 = &device_creator; +const device_type M68HC05EG = &device_creator; +const device_type M68705 = &device_creator; +const device_type HD63705 = &device_creator; diff --git a/src/emu/cpu/m6805/m6805.h b/src/emu/cpu/m6805/m6805.h index f4a195ec508..427f7561556 100644 --- a/src/emu/cpu/m6805/m6805.h +++ b/src/emu/cpu/m6805/m6805.h @@ -5,13 +5,363 @@ #ifndef __M6805_H__ #define __M6805_H__ +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class m6805_device; + +// device type definition +extern const device_type M6805; +extern const device_type M68HC05EG; +extern const device_type M68705; +extern const device_type HD63705; + +// ======================> m6805_base_device + +// Used by core CPU interface +class m6805_base_device : public cpu_device +{ +public: + // construction/destruction + m6805_base_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, const device_type type, const char *name, UINT32 addr_width); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const; + virtual UINT32 execute_max_cycles() const; + virtual UINT32 execute_input_lines() const; + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state) = 0; + virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const; + virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const; + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const; + virtual UINT32 disasm_max_opcode_bytes() const; + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + // device_state_interface overrides + virtual void state_string_export(const device_state_entry &entry, astring &string); + +private: + // opcode/condition tables + static const UINT8 m_flags8i[256]; + static const UINT8 m_flags8d[256]; + static const UINT8 m_cycles1[256]; + +protected: + void rd_s_handler_b(UINT8 *b); + void rd_s_handler_w(PAIR *p); + void wr_s_handler_b(UINT8 *b); + void wr_s_handler_w(PAIR *p); + void RM16(UINT32 addr, PAIR *p); + + void brset(UINT8 bit); + void brclr(UINT8 bit); + void bset(UINT8 bit); + void bclr(UINT8 bit); + + void bra(); + void brn(); + void bhi(); + void bls(); + void bcc(); + void bcs(); + void bne(); + void beq(); + void bhcc(); + void bhcs(); + void bpl(); + void bmi(); + void bmc(); + void bms(); + virtual void bil(); + virtual void bih(); + void bsr(); + + void neg_di(); + void com_di(); + void lsr_di(); + void ror_di(); + void asr_di(); + void lsl_di(); + void rol_di(); + void dec_di(); + void inc_di(); + void tst_di(); + void clr_di(); + + void nega(); + void coma(); + void lsra(); + void rora(); + void asra(); + void lsla(); + void rola(); + void deca(); + void inca(); + void tsta(); + void clra(); + + void negx(); + void comx(); + void lsrx(); + void rorx(); + void asrx(); + void aslx(); + void lslx(); + void rolx(); + void decx(); + void incx(); + void tstx(); + void clrx(); + + void neg_ix1(); + void com_ix1(); + void lsr_ix1(); + void ror_ix1(); + void asr_ix1(); + void lsl_ix1(); + void rol_ix1(); + void dec_ix1(); + void inc_ix1(); + void tst_ix1(); + void clr_ix1(); + + void neg_ix(); + void com_ix(); + void lsr_ix(); + void ror_ix(); + void asr_ix(); + void lsl_ix(); + void rol_ix(); + void dec_ix(); + void inc_ix(); + void tst_ix(); + void clr_ix(); + + void rti(); + void rts(); + virtual void swi(); + + void tax(); + void txa(); + + void rsp(); + void nop(); + + void suba_im(); + void cmpa_im(); + void sbca_im(); + void cpx_im(); + void anda_im(); + void bita_im(); + void lda_im(); + void eora_im(); + void adca_im(); + void ora_im(); + void adda_im(); + + void ldx_im(); + void suba_di(); + void cmpa_di(); + void sbca_di(); + void cpx_di(); + void anda_di(); + void bita_di(); + void lda_di(); + void sta_di(); + void eora_di(); + void adca_di(); + void ora_di(); + void adda_di(); + void jmp_di(); + void jsr_di(); + void ldx_di(); + void stx_di(); + void suba_ex(); + void cmpa_ex(); + void sbca_ex(); + void cpx_ex(); + void anda_ex(); + void bita_ex(); + void lda_ex(); + void sta_ex(); + void eora_ex(); + void adca_ex(); + void ora_ex(); + void adda_ex(); + void jmp_ex(); + void jsr_ex(); + void ldx_ex(); + void stx_ex(); + void suba_ix2(); + void cmpa_ix2(); + void sbca_ix2(); + void cpx_ix2(); + void anda_ix2(); + void bita_ix2(); + void lda_ix2(); + void sta_ix2(); + void eora_ix2(); + void adca_ix2(); + void ora_ix2(); + void adda_ix2(); + void jmp_ix2(); + void jsr_ix2(); + void ldx_ix2(); + void stx_ix2(); + void suba_ix1(); + void cmpa_ix1(); + void sbca_ix1(); + void cpx_ix1(); + void anda_ix1(); + void bita_ix1(); + void lda_ix1(); + void sta_ix1(); + void eora_ix1(); + void adca_ix1(); + void ora_ix1(); + void adda_ix1(); + void jmp_ix1(); + void jsr_ix1(); + void ldx_ix1(); + void stx_ix1(); + void suba_ix(); + void cmpa_ix(); + void sbca_ix(); + void cpx_ix(); + void anda_ix(); + void bita_ix(); + void lda_ix(); + void sta_ix(); + void eora_ix(); + void adca_ix(); + void ora_ix(); + void adda_ix(); + void jmp_ix(); + void jsr_ix(); + void ldx_ix(); + void stx_ix(); + + void illegal(); + + virtual void interrupt(); + virtual void interrupt_vector(); + + const char *m_tag; + + // address spaces + const address_space_config m_program_config; + + // CPU registers + PAIR m_ea; /* effective address */ + + UINT32 m_sp_mask; /* Stack pointer address mask */ + UINT32 m_sp_low; /* Stack pointer low water mark (or floor) */ + PAIR m_pc; /* Program counter */ + PAIR m_s; /* Stack pointer */ + UINT8 m_a; /* Accumulator */ + UINT8 m_x; /* Index register */ + UINT8 m_cc; /* Condition codes */ + + UINT16 m_pending_interrupts; /* MB */ + + int m_irq_state[9]; /* KW Additional lines for HD63705 */ + int m_nmi_state; + + // other internal states + int m_icount; + + // address spaces + address_space *m_program; + direct_read_data *m_direct; +}; + +// ======================> m6805_device + +class m6805_device : public m6805_base_device +{ +public: + // construction/destruction + m6805_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : m6805_base_device(mconfig, tag, owner, clock, M6805, "M6805", 12) { } + +protected: + virtual void execute_set_input(int inputnum, int state); +}; + +// ======================> m68hc05eg_device + +class m68hc05eg_device : public m6805_base_device +{ +public: + // construction/destruction + m68hc05eg_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : m6805_base_device(mconfig, tag, owner, clock, M68HC05EG, "M68HC05EG", 13) { } + +protected: + // device-level overrides + virtual void device_reset(); + + virtual void execute_set_input(int inputnum, int state); + + virtual void interrupt_vector(); +}; + +// ======================> m68705_device + +class m68705_device : public m6805_base_device +{ +public: + // construction/destruction + m68705_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : m6805_base_device(mconfig, tag, owner, clock, M68705, "M68705", 12) { } + +protected: + // device-level overrides + virtual void device_reset(); + + virtual void execute_set_input(int inputnum, int state); + + virtual void interrupt(); +}; + +// ======================> hd63705_device + +class hd63705_device : public m6805_base_device +{ +public: + // construction/destruction + hd63705_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : m6805_base_device(mconfig, tag, owner, clock, HD63705, "HD63705", 16) { } + +protected: + // device-level overrides + virtual void device_reset(); + + virtual void execute_set_input(int inputnum, int state); + + virtual void interrupt_vector(); + + // opcodes + virtual void bil(); + virtual void bih(); + virtual void swi(); +}; enum { M6805_PC=1, M6805_S, M6805_CC, M6805_A, M6805_X, M6805_IRQ_STATE }; #define M6805_IRQ_LINE 0 -DECLARE_LEGACY_CPU_DEVICE(M6805, m6805); - /**************************************************************************** * 68HC05EG section ****************************************************************************/ @@ -20,11 +370,10 @@ DECLARE_LEGACY_CPU_DEVICE(M6805, m6805); #define M68HC05EG_INT_TIMER (M6805_IRQ_LINE+1) #define M68HC05EG_INT_CPI (M6805_IRQ_LINE+2) -DECLARE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg); - /**************************************************************************** * 68705 section ****************************************************************************/ + #define M68705_A M6805_A #define M68705_PC M6805_PC #define M68705_S M6805_S @@ -36,11 +385,10 @@ DECLARE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg); #define M68705_IRQ_LINE M6805_IRQ_LINE #define M68705_INT_TIMER 0x01 -DECLARE_LEGACY_CPU_DEVICE(M68705, m68705); - /**************************************************************************** * HD63705 section ****************************************************************************/ + #define HD63705_A M6805_A #define HD63705_PC M6805_PC #define HD63705_S M6805_S @@ -63,8 +411,6 @@ DECLARE_LEGACY_CPU_DEVICE(M68705, m68705); #define HD63705_INT_ADCONV 0x07 #define HD63705_INT_NMI 0x08 -DECLARE_LEGACY_CPU_DEVICE(HD63705, hd63705); - CPU_DISASSEMBLE( m6805 ); #endif /* __M6805_H__ */ diff --git a/src/emu/cpu/m6809/m6809.h b/src/emu/cpu/m6809/m6809.h index c90005c7e67..62006dec1ad 100644 --- a/src/emu/cpu/m6809/m6809.h +++ b/src/emu/cpu/m6809/m6809.h @@ -30,7 +30,7 @@ struct m6809_config extern const device_type M6809; extern const device_type M6809E; -// ======================> m6809_device +// ======================> m6809_base_device // Used by core CPU interface class m6809_base_device : public cpu_device, @@ -114,8 +114,6 @@ protected: int m_extra_cycles; /* cycles used up by interrupts */ - device_irq_acknowledge_callback m_irq_callback; - PAIR m_ea; /* effective address */ // other internal states