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https://github.com/holub/mame
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-mc68328: Cleaned up register handlers and structure. [Ryan Holtz] (#8771)
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MooglyGuy
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File diff suppressed because it is too large
Load Diff
@ -132,198 +132,400 @@ protected:
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virtual void device_reset() override;
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private:
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struct mc68328_regs_t
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{
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// $(FF)FFF000
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uint8_t scr; // System Control Register
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uint8_t unused0[255];
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void scr_w(uint8_t data); // 0x000
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// $(FF)FFF100
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uint16_t grpbasea; // Chip Select Group A Base Register
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uint16_t grpbaseb; // Chip Select Group B Base Register
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uint16_t grpbasec; // Chip Select Group C Base Register
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uint16_t grpbased; // Chip Select Group D Base Register
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uint16_t grpmaska; // Chip Select Group A Mask Register
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uint16_t grpmaskb; // Chip Select Group B Mask Register
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uint16_t grpmaskc; // Chip Select Group C Mask Register
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uint16_t grpmaskd; // Chip Select Group D Mask Register
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uint32_t csa0; // Group A Chip Select 0 Register
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uint32_t csa1; // Group A Chip Select 1 Register
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uint32_t csa2; // Group A Chip Select 2 Register
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uint32_t csa3; // Group A Chip Select 3 Register
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uint32_t csb0; // Group B Chip Select 0 Register
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uint32_t csb1; // Group B Chip Select 1 Register
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uint32_t csb2; // Group B Chip Select 2 Register
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uint32_t csb3; // Group B Chip Select 3 Register
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uint32_t csc0; // Group C Chip Select 0 Register
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uint32_t csc1; // Group C Chip Select 1 Register
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uint32_t csc2; // Group C Chip Select 2 Register
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uint32_t csc3; // Group C Chip Select 3 Register
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uint32_t csd0; // Group D Chip Select 0 Register
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uint32_t csd1; // Group D Chip Select 1 Register
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uint32_t csd2; // Group D Chip Select 2 Register
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uint32_t csd3; // Group D Chip Select 3 Register
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uint8_t unused1[176];
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void grpbasea_w(uint16_t data); // 0x100
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void grpbaseb_w(uint16_t data); // 0x102
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void grpbasec_w(uint16_t data); // 0x104
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void grpbased_w(uint16_t data); // 0x106
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void grpmaska_w(uint16_t data); // 0x108
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void grpmaskb_w(uint16_t data); // 0x10a
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void grpmaskc_w(uint16_t data); // 0x10c
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void grpmaskd_w(uint16_t data); // 0x10e
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template<int ChipSelect> void csa_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x110, 0x114, 0x118, 0x11c
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template<int ChipSelect> void csa_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x112, 0x116, 0x11a, 0x11e
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template<int ChipSelect> void csb_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x120, 0x124, 0x128, 0x12c
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template<int ChipSelect> void csb_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x122, 0x126, 0x12a, 0x12e
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template<int ChipSelect> void csc_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x130, 0x134, 0x138, 0x13c
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template<int ChipSelect> void csc_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x132, 0x136, 0x13a, 0x13e
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template<int ChipSelect> void csd_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x140, 0x144, 0x148, 0x14c
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template<int ChipSelect> void csd_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x142, 0x146, 0x14a, 0x14e
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// $(FF)FFF200
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uint16_t pllcr; // PLL Control Register
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uint16_t pllfsr; // PLL Frequency Select Register
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uint8_t pad2[3];
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uint8_t pctlr; // Power Control Register
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uint8_t unused3[248];
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void pllcr_w(uint16_t data); // 0x200
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void pllfsr_w(uint16_t data); // 0x202
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void pctlr_w(uint8_t data); // 0x207
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void ivr_w(uint8_t data); // 0x300
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void icr_w(uint8_t data); // 0x302
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void imr_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x304
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void imr_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x306
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void iwr_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x308
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void iwr_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x30a
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void isr_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x30c
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void isr_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x30e
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void ipr_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x310
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void ipr_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0x312
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// $(FF)FFF300
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uint8_t ivr; // Interrupt Vector Register
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uint8_t unused4[1];
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uint16_t icr; // Interrupt Control Register
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uint32_t imr; // Interrupt Mask Register
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uint32_t iwr; // Interrupt Wakeup Enable Register
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uint32_t isr; // Interrupt Status Register
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uint32_t ipr; // Interrupt Pending Register
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uint8_t unused5[236];
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void padir_w(uint8_t data); // 0x400
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void padata_w(uint8_t data); // 0x401
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void pasel_w(uint8_t data); // 0x403
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void pbdir_w(uint8_t data); // 0x408
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void pbdata_w(uint8_t data); // 0x409
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void pbsel_w(uint8_t data); // 0x40b
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void pcdir_w(uint8_t data); // 0x410
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void pcdata_w(uint8_t data); // 0x411
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void pcsel_w(uint8_t data); // 0x413
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void pddir_w(uint8_t data); // 0x418
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void pddata_w(uint8_t data); // 0x419
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void pdpuen_w(uint8_t data); // 0x41a
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void pdpol_w(uint8_t data); // 0x41c
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void pdirqen_w(uint8_t data); // 0x41d
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void pdirqedge_w(uint8_t data); // 0x41f
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void pedir_w(uint8_t data); // 0x420
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void pedata_w(uint8_t data); // 0x421
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void pepuen_w(uint8_t data); // 0x422
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void pesel_w(uint8_t data); // 0x423
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void pfdir_w(uint8_t data); // 0x428
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void pfdata_w(uint8_t data); // 0x429
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void pfpuen_w(uint8_t data); // 0x42a
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void pfsel_w(uint8_t data); // 0x42b
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void pgdir_w(uint8_t data); // 0x430
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void pgdata_w(uint8_t data); // 0x431
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void pgpuen_w(uint8_t data); // 0x432
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void pgsel_w(uint8_t data); // 0x433
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void pjdir_w(uint8_t data); // 0x438
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void pjdata_w(uint8_t data); // 0x439
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void pjsel_w(uint8_t data); // 0x43b
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void pkdir_w(uint8_t data); // 0x440
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void pkdata_w(uint8_t data); // 0x441
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void pkpuen_w(uint8_t data); // 0x442
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void pksel_w(uint8_t data); // 0x443
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void pmdir_w(uint8_t data); // 0x448
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void pmdata_w(uint8_t data); // 0x449
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void pmpuen_w(uint8_t data); // 0x44a
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void pmsel_w(uint8_t data); // 0x44b
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// $(FF)FFF400
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uint8_t padir; // Port A Direction Register
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uint8_t padata; // Port A Data Register
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uint8_t unused6[1];
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uint8_t pasel; // Port A Select Register
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uint8_t unused7[4];
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void pwmc_w(uint16_t data); // 0x500
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void pwmp_w(uint16_t data); // 0x502
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void pwmw_w(uint16_t data); // 0x504
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void pwmcnt_w(uint16_t data); // 0x506
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uint8_t pbdir; // Port B Direction Register
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uint8_t pbdata; // Port B Data Register
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uint8_t unused8[1];
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uint8_t pbsel; // Port B Select Register
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uint8_t unused9[4];
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template <int Timer> void tctl_w(uint16_t data); // 0x600, 0x60c
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template <int Timer> void tprer_w(uint16_t data); // 0x602, 0x60e
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template <int Timer> void tcmp_w(uint16_t data); // 0x604, 0x610
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template <int Timer> void tcr_w(uint16_t data); // 0x606, 0x612
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template <int Timer> void tcn_w(uint16_t data); // 0x608, 0x614
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template <int Timer> void tstat_w(uint16_t data); // 0x60a, 0x616
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void wctlr_w(uint16_t data); // 0x618
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void wcmpr_w(uint16_t data); // 0x61a
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void wcn_w(uint16_t data); // 0x61c
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uint8_t pcdir; // Port C Direction Register
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uint8_t pcdata; // Port C Data Register
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uint8_t unused10[1];
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uint8_t pcsel; // Port C Select Register
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uint8_t unused11[4];
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void spisr_w(uint16_t data); // 0x700
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uint8_t pddir; // Port D Direction Register
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uint8_t pddata; // Port D Data Register
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uint8_t pdpuen; // Port D Pullup Enable Register
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uint8_t unused12[1];
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uint8_t pdpol; // Port D Polarity Register
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uint8_t pdirqen; // Port D IRQ Enable Register
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uint8_t pddataedge; // Port D Data Edge Level
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uint8_t pdirqedge; // Port D IRQ Edge Register
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void spimdata_w(uint16_t data); // 0x800
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void spimcont_w(uint16_t data); // 0x802
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uint8_t pedir; // Port E Direction Register
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uint8_t pedata; // Port E Data Register
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uint8_t pepuen; // Port E Pullup Enable Register
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uint8_t pesel; // Port E Select Register
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uint8_t unused14[4];
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void ustcnt_w(uint16_t data); // 0x900
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void ubaud_w(uint16_t data); // 0x902
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void urx_w(uint16_t data); // 0x904
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void utx_w(uint16_t data); // 0x906
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void umisc_w(uint16_t data); // 0x908
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uint8_t pfdir; // Port F Direction Register
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uint8_t pfdata; // Port F Data Register
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uint8_t pfpuen; // Port F Pullup Enable Register
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uint8_t pfsel; // Port F Select Register
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uint8_t unused15[4];
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void lssa_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xa00
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void lssa_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xa02
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void lvpw_w(uint8_t data); // 0xa05
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void lxmax_w(uint16_t data); // 0xa08
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void lymax_w(uint16_t data); // 0xa0a
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void lcxp_w(uint16_t data); // 0xa18
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void lcyp_w(uint16_t data); // 0xa1a
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void lcwch_w(uint16_t data); // 0xa1c
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void lblkc_w(uint8_t data); // 0xa1f
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void lpicf_w(uint8_t data); // 0xa20
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void lpolcf_w(uint8_t data); // 0xa21
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void lacdrc_w(uint8_t data); // 0xa23
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void lpxcd_w(uint8_t data); // 0xa25
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void lckcon_w(uint8_t data); // 0xa27
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void llbar_w(uint8_t data); // 0xa29
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void lotcr_w(uint8_t data); // 0xa2b
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void lposr_w(uint8_t data); // 0xa2d
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void lfrcm_w(uint8_t data); // 0xa31
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void lgpmr_w(uint8_t data); // 0xa32
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uint8_t pgdir; // Port G Direction Register
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uint8_t pgdata; // Port G Data Register
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uint8_t pgpuen; // Port G Pullup Enable Register
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uint8_t pgsel; // Port G Select Register
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uint8_t unused16[4];
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void hmsr_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb00
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void hmsr_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb02
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void alarm_msw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb04
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void alarm_lsw_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb06
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void rtcctl_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb0c
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void rtcisr_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb0e
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void rtcienr_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb10
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void stpwtch_w(offs_t offset, uint16_t data, uint16_t mem_mask); // 0xb12
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uint8_t pjdir; // Port J Direction Register
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uint8_t pjdata; // Port J Data Register
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uint8_t unused17[1];
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uint8_t pjsel; // Port J Select Register
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uint8_t unused18[4];
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uint8_t pkdir; // Port K Direction Register
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uint8_t pkdata; // Port K Data Register
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uint8_t pkpuen; // Port K Pullup Enable Register
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uint8_t pksel; // Port K Select Register
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uint8_t unused19[4];
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uint8_t scr_r(); // 0x000
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uint8_t pmdir; // Port M Direction Register
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uint8_t pmdata; // Port M Data Register
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uint8_t pmpuen; // Port M Pullup Enable Register
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uint8_t pmsel; // Port M Select Register
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uint8_t unused20[180];
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uint16_t grpbasea_r(); // 0x100
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uint16_t grpbaseb_r(); // 0x102
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uint16_t grpbasec_r(); // 0x104
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uint16_t grpbased_r(); // 0x106
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uint16_t grpmaska_r(); // 0x108
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uint16_t grpmaskb_r(); // 0x10a
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uint16_t grpmaskc_r(); // 0x10c
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uint16_t grpmaskd_r(); // 0x10e
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// $(FF)FFF500
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uint16_t pwmc; // PWM Control Register
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uint16_t pwmp; // PWM Period Register
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uint16_t pwmw; // PWM Width Register
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uint16_t pwmcnt; // PWN Counter
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uint8_t unused21[248];
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template<int ChipSelect> uint16_t csa_msw_r(); // 0x110, 0x114, 0x118, 0x11c
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template<int ChipSelect> uint16_t csa_lsw_r(); // 0x112, 0x116, 0x11a, 0x11e
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template<int ChipSelect> uint16_t csb_msw_r(); // 0x120, 0x124, 0x128, 0x12c
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template<int ChipSelect> uint16_t csb_lsw_r(); // 0x122, 0x126, 0x12a, 0x12e
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template<int ChipSelect> uint16_t csc_msw_r(); // 0x130, 0x134, 0x138, 0x13c
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template<int ChipSelect> uint16_t csc_lsw_r(); // 0x132, 0x136, 0x13a, 0x13e
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template<int ChipSelect> uint16_t csd_msw_r(); // 0x140, 0x144, 0x148, 0x14c
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template<int ChipSelect> uint16_t csd_lsw_r(); // 0x142, 0x146, 0x14a, 0x14e
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// $(FF)FFF600
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uint16_t tctl[2]; // Timer Control Register
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uint16_t tprer[2]; // Timer Prescaler Register
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uint16_t tcmp[2]; // Timer Compare Register
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uint16_t tcr[2]; // Timer Capture Register
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uint16_t tcn[2]; // Timer Counter
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uint16_t tstat[2]; // Timer Status
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uint16_t wctlr; // Watchdog Control Register
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uint16_t wcmpr; // Watchdog Compare Register
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uint16_t wcn; // Watchdog Counter
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uint8_t tclear[2]; // Timer Clearable Status
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uint8_t unused22[224];
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uint16_t pllcr_r(); // 0x200
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uint16_t pllfsr_r(); // 0x202
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uint8_t pctlr_r(); // 0x207
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// $(FF)FFF700
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uint16_t spisr; // SPIS Register
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uint8_t unused23[254];
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uint8_t ivr_r(); // 0x300
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uint16_t icr_r(); // 0x302
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uint16_t imr_msw_r(); // 0x304
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uint16_t imr_lsw_r(); // 0x306
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uint16_t iwr_msw_r(); // 0x308
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uint16_t iwr_lsw_r(); // 0x30a
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uint16_t isr_msw_r(); // 0x30c
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uint16_t isr_lsw_r(); // 0x30e
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uint16_t ipr_msw_r(); // 0x310
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uint16_t ipr_lsw_r(); // 0x312
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// $(FF)FFF800
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uint16_t spimdata; // SPIM Data Register
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uint16_t spimcont; // SPIM Control/Status Register
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uint8_t unused24[252];
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uint8_t padir_r(); // 0x400
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uint8_t padata_r(); // 0x401
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uint8_t pasel_r(); // 0x403
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uint8_t pbdir_r(); // 0x408
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uint8_t pbdata_r(); // 0x409
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uint8_t pbsel_r(); // 0x40b
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uint8_t pcdir_r(); // 0x410
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uint8_t pcdata_r(); // 0x411
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uint8_t pcsel_r(); // 0x413
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uint8_t pddir_r(); // 0x418
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uint8_t pddata_r(); // 0x419
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uint8_t pdpuen_r(); // 0x41a
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uint8_t pdpol_r(); // 0x41c
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uint8_t pdirqen_r(); // 0x41d
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uint8_t pdirqedge_r(); // 0x41f
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uint8_t pedir_r(); // 0x420
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uint8_t pedata_r(); // 0x421
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uint8_t pepuen_r(); // 0x422
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uint8_t pesel_r(); // 0x423
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uint8_t pfdir_r(); // 0x428
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uint8_t pfdata_r(); // 0x429
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uint8_t pfpuen_r(); // 0x42a
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uint8_t pfsel_r(); // 0x42b
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uint8_t pgdir_r(); // 0x430
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uint8_t pgdata_r(); // 0x431
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uint8_t pgpuen_r(); // 0x432
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uint8_t pgsel_r(); // 0x433
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uint8_t pjdir_r(); // 0x438
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uint8_t pjdata_r(); // 0x439
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uint8_t pjsel_r(); // 0x43b
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uint8_t pkdir_r(); // 0x440
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uint8_t pkdata_r(); // 0x441
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uint8_t pkpuen_r(); // 0x442
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||||
uint8_t pksel_r(); // 0x443
|
||||
uint8_t pmdata_r(); // 0x449
|
||||
uint8_t pmdir_r(); // 0x448
|
||||
uint8_t pmpuen_r(); // 0x44a
|
||||
uint8_t pmsel_r(); // 0x44b
|
||||
|
||||
// $(FF)FFF900
|
||||
uint16_t ustcnt; // UART Status/Control Register
|
||||
uint16_t ubaud; // UART Baud Control Register
|
||||
uint16_t urx; // UART RX Register
|
||||
uint16_t utx; // UART TX Register
|
||||
uint16_t umisc; // UART Misc Register
|
||||
uint8_t unused25[246];
|
||||
uint16_t pwmc_r(); // 0x500
|
||||
uint16_t pwmp_r(); // 0x502
|
||||
uint16_t pwmw_r(); // 0x504
|
||||
uint16_t pwmcnt_r(); // 0x506
|
||||
|
||||
// $(FF)FFFA00
|
||||
uint32_t lssa; // Screen Starting Address Register
|
||||
uint8_t unused26[1];
|
||||
uint8_t lvpw; // Virtual Page Width Register
|
||||
uint8_t unused27[2];
|
||||
uint16_t lxmax; // Screen Width Register
|
||||
uint16_t lymax; // Screen Height Register
|
||||
uint8_t unused28[12];
|
||||
uint16_t lcxp; // Cursor X Position
|
||||
uint16_t lcyp; // Cursor Y Position
|
||||
uint16_t lcwch; // Cursor Width & Height Register
|
||||
uint8_t unused29[1];
|
||||
uint8_t lblkc; // Blink Control Register
|
||||
uint8_t lpicf; // Panel Interface Config Register
|
||||
uint8_t lpolcf; // Polarity Config Register
|
||||
uint8_t unused30[1];
|
||||
uint8_t lacdrc; // ACD (M) Rate Control Register
|
||||
uint8_t unused31[1];
|
||||
uint8_t lpxcd; // Pixel Clock Divider Register
|
||||
uint8_t unused32[1];
|
||||
uint8_t lckcon; // Clocking Control Register
|
||||
uint8_t unused33[1];
|
||||
uint8_t llbar; // Last Buffer Address Register
|
||||
uint8_t unused34[1];
|
||||
uint8_t lotcr; // Octet Terminal Count Register
|
||||
uint8_t unused35[1];
|
||||
uint8_t lposr; // Panning Offset Register
|
||||
uint8_t unused36[3];
|
||||
uint8_t lfrcm; // Frame Rate Control Modulation Register
|
||||
uint16_t lgpmr; // Gray Palette Mapping Register
|
||||
uint8_t unused37[204];
|
||||
template <int Timer> uint16_t tctl_r(); // 0x600, 0x60c
|
||||
template <int Timer> uint16_t tprer_r(); // 0x602, 0x60e
|
||||
template <int Timer> uint16_t tcmp_r(); // 0x604, 0x610
|
||||
template <int Timer> uint16_t tcr_r(); // 0x606, 0x612
|
||||
template <int Timer> uint16_t tcn_r(); // 0x608, 0x614
|
||||
template <int Timer> uint16_t tstat_r(); // 0x60a, 0x616
|
||||
uint16_t wctlr_r(); // 0x618
|
||||
uint16_t wcmpr_r(); // 0x61a
|
||||
uint16_t wcn_r(); // 0x61c
|
||||
|
||||
// $(FF)FFFB00
|
||||
uint32_t hmsr; // RTC Hours Minutes Seconds Register
|
||||
uint32_t alarm; // RTC Alarm Register
|
||||
uint8_t unused38[4];
|
||||
uint16_t rtcctl; // RTC Control Register
|
||||
uint16_t rtcisr; // RTC Interrupt Status Register
|
||||
uint16_t rtcienr; // RTC Interrupt Enable Register
|
||||
uint16_t stpwtch; // Stopwatch Minutes
|
||||
uint8_t unused42[1260];
|
||||
};
|
||||
uint16_t spisr_r(); // 0x700
|
||||
|
||||
uint16_t spimdata_r(); // 0x800
|
||||
uint16_t spimcont_r(); // 0x802
|
||||
|
||||
uint16_t ustcnt_r(); // 0x900
|
||||
uint16_t ubaud_r(); // 0x902
|
||||
uint16_t urx_r(); // 0x904
|
||||
uint16_t utx_r(); // 0x906
|
||||
uint16_t umisc_r(); // 0x908
|
||||
|
||||
uint16_t lssa_msw_r(); // 0xa00
|
||||
uint16_t lssa_lsw_r(); // 0xa02
|
||||
uint8_t lvpw_r(); // 0xa05
|
||||
uint16_t lxmax_r(); // 0xa08
|
||||
uint16_t lymax_r(); // 0xa0a
|
||||
uint16_t lcxp_r(); // 0xa18
|
||||
uint16_t lcyp_r(); // 0xa1a
|
||||
uint16_t lcwch_r(); // 0xa1c
|
||||
uint8_t lblkc_r(); // 0xa1f
|
||||
uint8_t lpicf_r(); // 0xa20
|
||||
uint8_t lpolcf_r(); // 0xa21
|
||||
uint8_t lacdrc_r(); // 0xa23
|
||||
uint8_t lpxcd_r(); // 0xa25
|
||||
uint8_t lckcon_r(); // 0xa27
|
||||
uint8_t llbar_r(); // 0xa29
|
||||
uint8_t lotcr_r(); // 0xa2b
|
||||
uint8_t lposr_r(); // 0xa2d
|
||||
uint8_t lfrcm_r(); // 0xa31
|
||||
uint16_t lgpmr_r(); // 0xa32
|
||||
|
||||
uint16_t hmsr_msw_r(); // 0xb00
|
||||
uint16_t hmsr_lsw_r(); // 0xb02
|
||||
uint16_t alarm_msw_r(); // 0xb04
|
||||
uint16_t alarm_lsw_r(); // 0xb06
|
||||
uint16_t rtcctl_r(); // 0xb0c
|
||||
uint16_t rtcisr_r(); // 0xb0e
|
||||
uint16_t rtcienr_r(); // 0xb10
|
||||
uint16_t stpwtch_r(); // 0xb12
|
||||
|
||||
// $(FF)FFF000
|
||||
uint8_t m_scr; // System Control Register
|
||||
|
||||
// $(FF)FFF100
|
||||
uint16_t m_grpbasea; // Chip Select Group A Base Register
|
||||
uint16_t m_grpbaseb; // Chip Select Group B Base Register
|
||||
uint16_t m_grpbasec; // Chip Select Group C Base Register
|
||||
uint16_t m_grpbased; // Chip Select Group D Base Register
|
||||
uint16_t m_grpmaska; // Chip Select Group A Mask Register
|
||||
uint16_t m_grpmaskb; // Chip Select Group B Mask Register
|
||||
uint16_t m_grpmaskc; // Chip Select Group C Mask Register
|
||||
uint16_t m_grpmaskd; // Chip Select Group D Mask Register
|
||||
uint32_t m_csa[4]; // Group A Chip Select Registers
|
||||
uint32_t m_csb[4]; // Group B Chip Select Registers
|
||||
uint32_t m_csc[4]; // Group C Chip Select Registers
|
||||
uint32_t m_csd[4]; // Group D Chip Select Registers
|
||||
|
||||
// $(FF)FFF200
|
||||
uint16_t m_pllcr; // PLL Control Register
|
||||
uint16_t m_pllfsr; // PLL Frequency Select Register
|
||||
uint8_t m_pctlr; // Power Control Register
|
||||
|
||||
// $(FF)FFF300
|
||||
uint8_t m_ivr; // Interrupt Vector Register
|
||||
uint16_t m_icr; // Interrupt Control Register
|
||||
uint32_t m_imr; // Interrupt Mask Register
|
||||
uint32_t m_iwr; // Interrupt Wakeup Enable Register
|
||||
uint32_t m_isr; // Interrupt Status Register
|
||||
uint32_t m_ipr; // Interrupt Pending Register
|
||||
|
||||
// $(FF)FFF400
|
||||
uint8_t m_padir; // Port A Direction Register
|
||||
uint8_t m_padata; // Port A Data Register
|
||||
uint8_t m_pasel; // Port A Select Register
|
||||
|
||||
uint8_t m_pbdir; // Port B Direction Register
|
||||
uint8_t m_pbdata; // Port B Data Register
|
||||
uint8_t m_pbsel; // Port B Select Register
|
||||
|
||||
uint8_t m_pcdir; // Port C Direction Register
|
||||
uint8_t m_pcdata; // Port C Data Register
|
||||
uint8_t m_pcsel; // Port C Select Register
|
||||
|
||||
uint8_t m_pddir; // Port D Direction Register
|
||||
uint8_t m_pddata; // Port D Data Register
|
||||
uint8_t m_pdpuen; // Port D Pullup Enable Register
|
||||
uint8_t m_pdpol; // Port D Polarity Register
|
||||
uint8_t m_pdirqen; // Port D IRQ Enable Register
|
||||
uint8_t m_pddataedge; // Port D Data Edge Level
|
||||
uint8_t m_pdirqedge; // Port D IRQ Edge Register
|
||||
|
||||
uint8_t m_pedir; // Port E Direction Register
|
||||
uint8_t m_pedata; // Port E Data Register
|
||||
uint8_t m_pepuen; // Port E Pullup Enable Register
|
||||
uint8_t m_pesel; // Port E Select Register
|
||||
|
||||
uint8_t m_pfdir; // Port F Direction Register
|
||||
uint8_t m_pfdata; // Port F Data Register
|
||||
uint8_t m_pfpuen; // Port F Pullup Enable Register
|
||||
uint8_t m_pfsel; // Port F Select Register
|
||||
|
||||
uint8_t m_pgdir; // Port G Direction Register
|
||||
uint8_t m_pgdata; // Port G Data Register
|
||||
uint8_t m_pgpuen; // Port G Pullup Enable Register
|
||||
uint8_t m_pgsel; // Port G Select Register
|
||||
|
||||
uint8_t m_pjdir; // Port J Direction Register
|
||||
uint8_t m_pjdata; // Port J Data Register
|
||||
uint8_t m_pjsel; // Port J Select Register
|
||||
uint8_t m_pkdir; // Port K Direction Register
|
||||
uint8_t m_pkdata; // Port K Data Register
|
||||
uint8_t m_pkpuen; // Port K Pullup Enable Register
|
||||
uint8_t m_pksel; // Port K Select Register
|
||||
|
||||
uint8_t m_pmdir; // Port M Direction Register
|
||||
uint8_t m_pmdata; // Port M Data Register
|
||||
uint8_t m_pmpuen; // Port M Pullup Enable Register
|
||||
uint8_t m_pmsel; // Port M Select Register
|
||||
|
||||
// $(FF)FFF500
|
||||
uint16_t m_pwmc; // PWM Control Register
|
||||
uint16_t m_pwmp; // PWM Period Register
|
||||
uint16_t m_pwmw; // PWM Width Register
|
||||
uint16_t m_pwmcnt; // PWN Counter
|
||||
|
||||
// $(FF)FFF600
|
||||
uint16_t m_tctl[2]; // Timer Control Register
|
||||
uint16_t m_tprer[2]; // Timer Prescaler Register
|
||||
uint16_t m_tcmp[2]; // Timer Compare Register
|
||||
uint16_t m_tcr[2]; // Timer Capture Register
|
||||
uint16_t m_tcn[2]; // Timer Counter
|
||||
uint16_t m_tstat[2]; // Timer Status
|
||||
uint16_t m_wctlr; // Watchdog Control Register
|
||||
uint16_t m_wcmpr; // Watchdog Compare Register
|
||||
uint16_t m_wcn; // Watchdog Counter
|
||||
uint16_t m_tclear[2]; // Timer Clearable Status
|
||||
|
||||
// $(FF)FFF700
|
||||
uint16_t m_spisr; // SPIS Register
|
||||
|
||||
// $(FF)FFF800
|
||||
uint16_t m_spimdata; // SPIM Data Register
|
||||
uint16_t m_spimcont; // SPIM Control/Status Register
|
||||
|
||||
// $(FF)FFF900
|
||||
uint16_t m_ustcnt; // UART Status/Control Register
|
||||
uint16_t m_ubaud; // UART Baud Control Register
|
||||
uint16_t m_urx; // UART RX Register
|
||||
uint16_t m_utx; // UART TX Register
|
||||
uint16_t m_umisc; // UART Misc Register
|
||||
|
||||
// $(FF)FFFA00
|
||||
uint32_t m_lssa; // Screen Starting Address Register
|
||||
uint8_t m_lvpw; // Virtual Page Width Register
|
||||
uint16_t m_lxmax; // Screen Width Register
|
||||
uint16_t m_lymax; // Screen Height Register
|
||||
uint16_t m_lcxp; // Cursor X Position
|
||||
uint16_t m_lcyp; // Cursor Y Position
|
||||
uint16_t m_lcwch; // Cursor Width & Height Register
|
||||
uint8_t m_lblkc; // Blink Control Register
|
||||
uint8_t m_lpicf; // Panel Interface Config Register
|
||||
uint8_t m_lpolcf; // Polarity Config Register
|
||||
uint8_t m_lacdrc; // ACD (M) Rate Control Register
|
||||
uint8_t m_lpxcd; // Pixel Clock Divider Register
|
||||
uint8_t m_lckcon; // Clocking Control Register
|
||||
uint8_t m_llbar; // Last Buffer Address Register
|
||||
uint8_t m_lotcr; // Octet Terminal Count Register
|
||||
uint8_t m_lposr; // Panning Offset Register
|
||||
uint8_t m_lfrcm; // Frame Rate Control Modulation Register
|
||||
uint16_t m_lgpmr; // Gray Palette Mapping Register
|
||||
|
||||
// $(FF)FFFB00
|
||||
uint32_t m_hmsr; // RTC Hours Minutes Seconds Register
|
||||
uint32_t m_alarm; // RTC Alarm Register
|
||||
uint16_t m_rtcctl; // RTC Control Register
|
||||
uint16_t m_rtcisr; // RTC Interrupt Status Register
|
||||
uint16_t m_rtcienr; // RTC Interrupt Enable Register
|
||||
uint16_t m_stpwtch; // Stopwatch Minutes
|
||||
|
||||
void internal_map(address_map &map);
|
||||
|
||||
@ -332,9 +534,10 @@ private:
|
||||
void poll_port_d_interrupts();
|
||||
void cpu_space_map(address_map &map);
|
||||
uint8_t irq_callback(offs_t offset);
|
||||
uint32_t get_timer_frequency(uint32_t index);
|
||||
void maybe_start_timer(uint32_t index, uint32_t new_enable);
|
||||
void timer_compare_event(uint32_t index);
|
||||
|
||||
template<int Timer> uint32_t get_timer_frequency();
|
||||
template<int Timer> void maybe_start_timer(uint32_t new_enable);
|
||||
template<int Timer> void timer_compare_event();
|
||||
|
||||
void register_state_save();
|
||||
|
||||
@ -343,11 +546,6 @@ private:
|
||||
TIMER_CALLBACK_MEMBER(pwm_transition);
|
||||
TIMER_CALLBACK_MEMBER(rtc_tick);
|
||||
|
||||
void internal_write(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff);
|
||||
uint16_t internal_read(offs_t offset, uint16_t mem_mask = 0xffff);
|
||||
|
||||
mc68328_regs_t m_regs;
|
||||
|
||||
emu_timer *m_gptimer[2];
|
||||
emu_timer *m_rtc;
|
||||
emu_timer *m_pwm;
|
||||
@ -374,7 +572,7 @@ private:
|
||||
devcb_read8 m_in_port_k_cb; /* 8-bit input */
|
||||
devcb_read8 m_in_port_m_cb; /* 8-bit input */
|
||||
|
||||
devcb_write8 m_out_pwm_cb; /* 1-bit output */
|
||||
devcb_write_line m_out_pwm_cb; /* 1-bit output */
|
||||
|
||||
devcb_write16 m_out_spim_cb; /* 16-bit output */
|
||||
devcb_read16 m_in_spim_cb; /* 16-bit input */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user