diff --git a/src/emu/cpu/z180/z180.c b/src/emu/cpu/z180/z180.c
index 5906b4cf5d5..0eaef4f8e84 100644
--- a/src/emu/cpu/z180/z180.c
+++ b/src/emu/cpu/z180/z180.c
@@ -133,6 +133,7 @@ struct _z180_state
 	UINT32	ioltemp;
 	int icount;
 	int old_icount;				/* for burning cycles */
+	int extra_cycles;			/* extra cpu cycles */
 	UINT8 *cc[6];
 };
 
@@ -782,6 +783,21 @@ static void set_irq_line(z180_state *cpustate, int irqline, int state);
 #define Z180_IOCR_RMASK 		0xff
 #define Z180_IOCR_WMASK 		0xff
 
+/***************************************************************************
+    CPU PREFIXES
+
+    order is important here - see z180tbl.h
+***************************************************************************/
+
+#define Z180_PREFIX_op			0
+#define Z180_PREFIX_cb			1
+#define Z180_PREFIX_dd			2
+#define Z180_PREFIX_ed			3
+#define Z180_PREFIX_fd			4
+#define Z180_PREFIX_xycb		5
+
+#define Z180_PREFIX_COUNT		(Z180_PREFIX_xycb + 1)
+
 
 /***************************************************************************
     CPU STATE DESCRIPTION
@@ -919,8 +935,8 @@ static UINT8 *SZHVC_sub;
 
 static UINT8 z180_readcontrol(z180_state *cpustate, offs_t port);
 static void z180_writecontrol(z180_state *cpustate, offs_t port, UINT8 data);
-static void z180_dma0(z180_state *cpustate);
-static void z180_dma1(z180_state *cpustate);
+static int z180_dma0(z180_state *cpustate, int max_cycles);
+static int z180_dma1(z180_state *cpustate);
 static CPU_BURN( z180 );
 static CPU_SET_INFO( z180 );
 
@@ -1716,17 +1732,18 @@ static void z180_writecontrol(z180_state *cpustate, offs_t port, UINT8 data)
 	}
 }
 
-static void z180_dma0(z180_state *cpustate)
+static int z180_dma0(z180_state *cpustate, int max_cycles)
 {
 	offs_t sar0 = 65536 * cpustate->IO_SAR0B + 256 * cpustate->IO_SAR0H + cpustate->IO_SAR0L;
 	offs_t dar0 = 65536 * cpustate->IO_DAR0B + 256 * cpustate->IO_DAR0H + cpustate->IO_DAR0L;
 	int bcr0 = 256 * cpustate->IO_BCR0H + cpustate->IO_BCR0L;
 	int count = (cpustate->IO_DMODE & Z180_DMODE_MMOD) ? bcr0 : 1;
+	int cycles = 0;
 
 	if (bcr0 == 0)
 	{
 		cpustate->IO_DSTAT &= ~Z180_DSTAT_DE0;
-		return;
+		return 0;
 	}
 
 	while (count-- > 0)
@@ -1821,7 +1838,8 @@ static void z180_dma0(z180_state *cpustate)
 		}
 		bcr0--;
 		count--;
-		if ((cpustate->icount -= 6) < 0)
+		cycles += 6;
+		if (cycles > max_cycles)
 			break;
 	}
 
@@ -1841,24 +1859,26 @@ static void z180_dma0(z180_state *cpustate)
 		cpustate->IO_DSTAT &= ~Z180_DSTAT_DE0;
 		/* terminal count interrupt enabled? */
 		if (cpustate->IO_DSTAT & Z180_DSTAT_DIE0 && cpustate->IFF1)
-			take_interrupt(cpustate, Z180_INT_DMA0);
+			cycles += take_interrupt(cpustate, Z180_INT_DMA0);
 	}
+	return cycles;
 }
 
-static void z180_dma1(z180_state *cpustate)
+static int z180_dma1(z180_state *cpustate)
 {
 	offs_t mar1 = 65536 * cpustate->IO_MAR1B + 256 * cpustate->IO_MAR1H + cpustate->IO_MAR1L;
 	offs_t iar1 = 256 * cpustate->IO_IAR1H + cpustate->IO_IAR1L;
 	int bcr1 = 256 * cpustate->IO_BCR1H + cpustate->IO_BCR1L;
+	int cycles = 0;
 
 	if ((cpustate->iol & Z180_DREQ1) == 0)
-		return;
+		return 0;
 
 	/* counter is zero? */
 	if (bcr1 == 0)
 	{
 		cpustate->IO_DSTAT &= ~Z180_DSTAT_DE1;
-		return;
+		return 0;
 	}
 
 	/* last transfer happening now? */
@@ -1899,11 +1919,11 @@ static void z180_dma1(z180_state *cpustate)
 		cpustate->iol &= ~Z180_TEND1;
 		cpustate->IO_DSTAT &= ~Z180_DSTAT_DE1;
 		if (cpustate->IO_DSTAT & Z180_DSTAT_DIE1 && cpustate->IFF1)
-			take_interrupt(cpustate, Z180_INT_DMA1);
+			cycles += take_interrupt(cpustate, Z180_INT_DMA1);
 	}
 
 	/* six cycles per transfer (minimum) */
-	cpustate->icount -= 6;
+	return 6 + cycles;
 }
 
 static void z180_write_iolines(z180_state *cpustate, UINT32 data)
@@ -2263,6 +2283,8 @@ static int handle_timers(z180_state *cpustate, int current_icount, int previous_
 {
 	int diff = previous_icount - current_icount;
 	int new_icount_base;
+	/* FIXME: move interrupt handling elsewhere */
+	int cycles = 0;
 
 	if(diff >= 20)
 	{
@@ -2295,7 +2317,7 @@ static int handle_timers(z180_state *cpustate, int current_icount, int previous_
 			// check if we can take the interrupt
 			if(cpustate->IFF1 && !cpustate->after_EI)
 			{
-				take_interrupt(cpustate, Z180_INT_PRT0);
+				cycles += take_interrupt(cpustate, Z180_INT_PRT0);
 			}
 		}
 
@@ -2304,7 +2326,7 @@ static int handle_timers(z180_state *cpustate, int current_icount, int previous_
 			// check if we can take the interrupt
 			if(cpustate->IFF1 && !cpustate->after_EI)
 			{
-				take_interrupt(cpustate, Z180_INT_PRT1);
+				cycles += take_interrupt(cpustate, Z180_INT_PRT1);
 			}
 		}
 
@@ -2318,17 +2340,20 @@ static int handle_timers(z180_state *cpustate, int current_icount, int previous_
 	return new_icount_base;
 }
 
-static void check_interrupts(z180_state *cpustate)
+static int check_interrupts(z180_state *cpustate)
 {
 	int i;
+	int cycles = 0;
+
 	for(i = 0; i <= 2; i++)
 	{
 		/* check for IRQs before each instruction */
 		if(cpustate->irq_state[i] != CLEAR_LINE && cpustate->IFF1 && !cpustate->after_EI)
 		{
-			take_interrupt(cpustate, Z180_INT0 + i);
+			cycles += take_interrupt(cpustate, Z180_INT0 + i);
 		}
 	}
+	return cycles;
 }
 
 /****************************************************************************
@@ -2372,27 +2397,38 @@ again:
 		{
 			debugger_instruction_hook(device, cpustate->_PCD);
 
-			z180_dma0(cpustate);
+			cpustate->icount -= z180_dma0(cpustate, cpustate->icount);
 			cpustate->old_icount = handle_timers(cpustate, cpustate->icount, cpustate->old_icount);
 		}
 		else
 		{
 			do
 			{
-				check_interrupts(cpustate);
+				cpustate->icount -= check_interrupts(cpustate);
 				cpustate->after_EI = 0;
 
 				cpustate->_PPC = cpustate->_PCD;
 				debugger_instruction_hook(device, cpustate->_PCD);
 				cpustate->R++;
 
-				EXEC_INLINE(op,ROP(cpustate));
+				cpustate->extra_cycles = 0;
+				cpustate->icount -= exec_op(cpustate,ROP(cpustate));
+				cpustate->icount -= cpustate->extra_cycles;
+
 				cpustate->old_icount = handle_timers(cpustate, cpustate->icount, cpustate->old_icount);
 
-				z180_dma0(cpustate);
+				/* FIXME:
+				 * For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority
+				 * over channel 1. When channel 0 is performing a memory to/from memory
+				 * transfer, channel 1 cannot operate until the channel 0 operation has
+				 * terminated. If channel 1 is operating, channel 0 cannot operate until
+				 * channel 1 releases control of the bus.
+				 *
+				 */
+				cpustate->icount -= z180_dma0(cpustate, cpustate->icount);
 				cpustate->old_icount = handle_timers(cpustate, cpustate->icount, cpustate->old_icount);
 
-				z180_dma1(cpustate);
+				cpustate->icount -= z180_dma1(cpustate);
 				cpustate->old_icount = handle_timers(cpustate, cpustate->icount, cpustate->old_icount);
 
 				/* If DMA is done break out to the faster loop */
@@ -2406,13 +2442,17 @@ again:
     {
         do
 		{
-			check_interrupts(cpustate);
+        	int xx;
+        	cpustate->icount -= check_interrupts(cpustate);
 			cpustate->after_EI = 0;
 
 			cpustate->_PPC = cpustate->_PCD;
 			debugger_instruction_hook(device, cpustate->_PCD);
+			cpustate->extra_cycles = 0;
 			cpustate->R++;
-			EXEC_INLINE(op,ROP(cpustate));
+			xx = exec_op(cpustate,ROP(cpustate));
+			cpustate->icount -= xx;
+			cpustate->icount -= cpustate->extra_cycles;
 			cpustate->old_icount = handle_timers(cpustate, cpustate->icount, cpustate->old_icount);
 
 			/* If DMA is started go to check the mode */
diff --git a/src/emu/cpu/z180/z180dd.c b/src/emu/cpu/z180/z180dd.c
index ea8c05857a4..fc9a18bbb02 100644
--- a/src/emu/cpu/z180/z180dd.c
+++ b/src/emu/cpu/z180/z180dd.c
@@ -234,7 +234,7 @@ OP(dd,c7) { illegal_1(cpustate); op_c7(cpustate);									}		  /* DB   DD
 OP(dd,c8) { illegal_1(cpustate); op_c8(cpustate);									} /* DB   DD          */
 OP(dd,c9) { illegal_1(cpustate); op_c9(cpustate);									} /* DB   DD          */
 OP(dd,ca) { illegal_1(cpustate); op_ca(cpustate);									} /* DB   DD          */
-OP(dd,cb) { cpustate->R++; EAX(cpustate); EXEC(xycb,ARG(cpustate));							} /* **   DD CB xx    */
+OP(dd,cb) { cpustate->R++; EAX(cpustate); cpustate->extra_cycles += exec_xycb(cpustate,ARG(cpustate));							} /* **   DD CB xx    */
 OP(dd,cc) { illegal_1(cpustate); op_cc(cpustate);									} /* DB   DD          */
 OP(dd,cd) { illegal_1(cpustate); op_cd(cpustate);									} /* DB   DD          */
 OP(dd,ce) { illegal_1(cpustate); op_ce(cpustate);									} /* DB   DD          */
diff --git a/src/emu/cpu/z180/z180fd.c b/src/emu/cpu/z180/z180fd.c
index ee6d29706f2..1cd28612796 100644
--- a/src/emu/cpu/z180/z180fd.c
+++ b/src/emu/cpu/z180/z180fd.c
@@ -229,7 +229,7 @@ OP(fd,c7) { illegal_1(cpustate); op_c7(cpustate);									} /* DB   FD
 OP(fd,c8) { illegal_1(cpustate); op_c8(cpustate);									} /* DB   FD          */
 OP(fd,c9) { illegal_1(cpustate); op_c9(cpustate);									} /* DB   FD          */
 OP(fd,ca) { illegal_1(cpustate); op_ca(cpustate);									} /* DB   FD          */
-OP(fd,cb) { cpustate->R++; EAY(cpustate); EXEC(xycb,ARG(cpustate));							} /* **   FD CB xx    */
+OP(fd,cb) { cpustate->R++; EAY(cpustate); cpustate->extra_cycles += exec_xycb(cpustate,ARG(cpustate));							} /* **   FD CB xx    */
 OP(fd,cc) { illegal_1(cpustate); op_cc(cpustate);									} /* DB   FD          */
 OP(fd,cd) { illegal_1(cpustate); op_cd(cpustate);									} /* DB   FD          */
 OP(fd,ce) { illegal_1(cpustate); op_ce(cpustate);									} /* DB   FD          */
diff --git a/src/emu/cpu/z180/z180op.c b/src/emu/cpu/z180/z180op.c
index a163920596d..888347fec56 100644
--- a/src/emu/cpu/z180/z180op.c
+++ b/src/emu/cpu/z180/z180op.c
@@ -231,7 +231,7 @@ OP(op,c7) { RST(0x00);												} /* RST  0           */
 OP(op,c8) { RET_COND( cpustate->_F & ZF, 0xc8 );								} /* RET  Z           */
 OP(op,c9) { POP(cpustate, PC);												} /* RET              */
 OP(op,ca) { JP_COND( cpustate->_F & ZF );									} /* JP   Z,a         */
-OP(op,cb) { cpustate->R++; EXEC(cb,ROP(cpustate));									} /* **** CB xx       */
+OP(op,cb) { cpustate->R++; cpustate->extra_cycles += exec_cb(cpustate,ROP(cpustate));									} /* **** CB xx       */
 OP(op,cc) { CALL_COND( cpustate->_F & ZF, 0xcc );							} /* CALL Z,a         */
 OP(op,cd) { CALL(); 												} /* CALL a           */
 OP(op,ce) { ADC(ARG(cpustate)); 											} /* ADC  A,n         */
@@ -251,7 +251,7 @@ OP(op,d9) { EXX;													} /* EXX              */
 OP(op,da) { JP_COND( cpustate->_F & CF );									} /* JP   C,a         */
 OP(op,db) { unsigned n = ARG(cpustate) | (cpustate->_A << 8); cpustate->_A = IN( cpustate, n );			} /* IN   A,(n)       */
 OP(op,dc) { CALL_COND( cpustate->_F & CF, 0xdc );							} /* CALL C,a         */
-OP(op,dd) { cpustate->R++; EXEC(dd,ROP(cpustate));									} /* **** DD xx       */
+OP(op,dd) { cpustate->R++; cpustate->extra_cycles += exec_dd(cpustate,ROP(cpustate));									} /* **** DD xx       */
 OP(op,de) { SBC(ARG(cpustate)); 											} /* SBC  A,n         */
 OP(op,df) { RST(0x18);												} /* RST  3           */
 
@@ -269,7 +269,7 @@ OP(op,e9) { cpustate->_PC = cpustate->_HL;												} /* JP   (HL)        */
 OP(op,ea) { JP_COND( cpustate->_F & PF );									} /* JP   PE,a        */
 OP(op,eb) { EX_DE_HL;												} /* EX   DE,HL       */
 OP(op,ec) { CALL_COND( cpustate->_F & PF, 0xec );							} /* CALL PE,a        */
-OP(op,ed) { cpustate->R++; EXEC(ed,ROP(cpustate));									} /* **** ED xx       */
+OP(op,ed) { cpustate->R++; cpustate->extra_cycles += exec_ed(cpustate,ROP(cpustate));									} /* **** ED xx       */
 OP(op,ee) { XOR(ARG(cpustate)); 											} /* XOR  n           */
 OP(op,ef) { RST(0x28);												} /* RST  5           */
 
@@ -287,14 +287,15 @@ OP(op,f9) { cpustate->_SP = cpustate->_HL;												} /* LD   SP,HL       */
 OP(op,fa) { JP_COND(cpustate->_F & SF);										} /* JP   M,a         */
 OP(op,fb) { EI; 													} /* EI               */
 OP(op,fc) { CALL_COND( cpustate->_F & SF, 0xfc );							} /* CALL M,a         */
-OP(op,fd) { cpustate->R++; EXEC(fd,ROP(cpustate));									} /* **** FD xx       */
+OP(op,fd) { cpustate->R++; cpustate->extra_cycles += exec_fd(cpustate,ROP(cpustate));									} /* **** FD xx       */
 OP(op,fe) { CP(ARG(cpustate));												} /* CP   n           */
 OP(op,ff) { RST(0x38);												} /* RST  7           */
 
 
-static void take_interrupt(z180_state *cpustate, int irq)
+static int take_interrupt(z180_state *cpustate, int irq)
 {
 	int irq_vector;
+	int cycles = 0;
 
 	/* there isn't a valid previous program counter */
 	cpustate->_PPC = -1;
@@ -325,7 +326,7 @@ static void take_interrupt(z180_state *cpustate, int irq)
 			RM16( cpustate, irq_vector, &cpustate->PC );
 			LOG(("Z180 '%s' IM2 [$%04x] = $%04x\n",cpustate->device->tag() , irq_vector, cpustate->_PCD));
 			/* CALL opcode timing */
-			cpustate->icount -= cpustate->cc[Z180_TABLE_op][0xcd];
+			cycles += cpustate->cc[Z180_TABLE_op][0xcd];
 		}
 		else
 		/* Interrupt mode 1. RST 38h */
@@ -335,7 +336,7 @@ static void take_interrupt(z180_state *cpustate, int irq)
 			PUSH(cpustate,  PC );
 			cpustate->_PCD = 0x0038;
 			/* RST $38 + 'interrupt latency' cycles */
-			cpustate->icount -= cpustate->cc[Z180_TABLE_op][0xff] - cpustate->cc[Z180_TABLE_ex][0xff];
+			cycles += cpustate->cc[Z180_TABLE_op][0xff] - cpustate->cc[Z180_TABLE_ex][0xff];
 		}
 		else
 		{
@@ -349,18 +350,18 @@ static void take_interrupt(z180_state *cpustate, int irq)
 					PUSH(cpustate,  PC );
 					cpustate->_PCD = irq_vector & 0xffff;
 						/* CALL $xxxx + 'interrupt latency' cycles */
-					cpustate->icount -= cpustate->cc[Z180_TABLE_op][0xcd] - cpustate->cc[Z180_TABLE_ex][0xff];
+					cycles += cpustate->cc[Z180_TABLE_op][0xcd] - cpustate->cc[Z180_TABLE_ex][0xff];
 					break;
 				case 0xc30000:	/* jump */
 					cpustate->_PCD = irq_vector & 0xffff;
 					/* JP $xxxx + 2 cycles */
-					cpustate->icount -= cpustate->cc[Z180_TABLE_op][0xc3] - cpustate->cc[Z180_TABLE_ex][0xff];
+					cycles += cpustate->cc[Z180_TABLE_op][0xc3] - cpustate->cc[Z180_TABLE_ex][0xff];
 					break;
 				default:		/* rst (or other opcodes?) */
 					PUSH(cpustate,  PC );
 					cpustate->_PCD = irq_vector & 0x0038;
 					/* RST $xx + 2 cycles */
-					cpustate->icount -= cpustate->cc[Z180_TABLE_op][cpustate->_PCD] - cpustate->cc[Z180_TABLE_ex][cpustate->_PCD];
+					cycles += cpustate->cc[Z180_TABLE_op][cpustate->_PCD] - cpustate->cc[Z180_TABLE_ex][cpustate->_PCD];
 					break;
 			}
 		}
@@ -373,7 +374,9 @@ static void take_interrupt(z180_state *cpustate, int irq)
 		RM16( cpustate, irq_vector, &cpustate->PC );
 		LOG(("Z180 '%s' INT%d [$%04x] = $%04x\n", cpustate->device->tag(), irq, irq_vector, cpustate->_PCD));
 		/* CALL opcode timing */
-		cpustate->icount -= cpustate->cc[Z180_TABLE_op][0xcd];
+		cycles += cpustate->cc[Z180_TABLE_op][0xcd];
 	}
+
+	return cycles;
 }
 
diff --git a/src/emu/cpu/z180/z180tbl.h b/src/emu/cpu/z180/z180tbl.h
index 2732871607c..046f8bc9fc8 100644
--- a/src/emu/cpu/z180/z180tbl.h
+++ b/src/emu/cpu/z180/z180tbl.h
@@ -154,7 +154,7 @@ static const UINT8 *const cc_default[6] = { cc_op, cc_cb, cc_ed, cc_xy, cc_xycb,
 #define Z180_TABLE_dd	 Z180_TABLE_xy
 #define Z180_TABLE_fd	 Z180_TABLE_xy
 
-static void take_interrupt(z180_state *cpustate, int irqline);
+static int take_interrupt(z180_state *cpustate, int irqline);
 
 #define PROTOTYPES(tablename,prefix) \
 	INLINE void prefix##_00(z180_state *cpustate); INLINE void prefix##_01(z180_state *cpustate); INLINE void prefix##_02(z180_state *cpustate); INLINE void prefix##_03(z180_state *cpustate); \
@@ -220,8 +220,9 @@ static void take_interrupt(z180_state *cpustate, int irqline);
 	INLINE void prefix##_f0(z180_state *cpustate); INLINE void prefix##_f1(z180_state *cpustate); INLINE void prefix##_f2(z180_state *cpustate); INLINE void prefix##_f3(z180_state *cpustate); \
 	INLINE void prefix##_f4(z180_state *cpustate); INLINE void prefix##_f5(z180_state *cpustate); INLINE void prefix##_f6(z180_state *cpustate); INLINE void prefix##_f7(z180_state *cpustate); \
 	INLINE void prefix##_f8(z180_state *cpustate); INLINE void prefix##_f9(z180_state *cpustate); INLINE void prefix##_fa(z180_state *cpustate); INLINE void prefix##_fb(z180_state *cpustate); \
-	INLINE void prefix##_fc(z180_state *cpustate); INLINE void prefix##_fd(z180_state *cpustate); INLINE void prefix##_fe(z180_state *cpustate); INLINE void prefix##_ff(z180_state *cpustate); \
-static void (*const tablename[0x100])(z180_state *cpustate) = {	\
+	INLINE void prefix##_fc(z180_state *cpustate); INLINE void prefix##_fd(z180_state *cpustate); INLINE void prefix##_fe(z180_state *cpustate); INLINE void prefix##_ff(z180_state *cpustate);
+
+#define TABLE(prefix) {\
 	prefix##_00,prefix##_01,prefix##_02,prefix##_03,prefix##_04,prefix##_05,prefix##_06,prefix##_07, \
 	prefix##_08,prefix##_09,prefix##_0a,prefix##_0b,prefix##_0c,prefix##_0d,prefix##_0e,prefix##_0f, \
 	prefix##_10,prefix##_11,prefix##_12,prefix##_13,prefix##_14,prefix##_15,prefix##_16,prefix##_17, \
@@ -263,6 +264,16 @@ PROTOTYPES(Z180ed,ed);
 PROTOTYPES(Z180fd,fd);
 PROTOTYPES(Z180xycb,xycb);
 
+static void (*const Z180ops[Z180_PREFIX_COUNT][0x100])(z180_state *cpustate) =
+{
+	TABLE(op),
+	TABLE(cb),
+	TABLE(dd),
+	TABLE(ed),
+	TABLE(fd),
+	TABLE(xycb)
+};
+
 /***************************************************************
  * define an opcode function
  ***************************************************************/
@@ -271,91 +282,23 @@ PROTOTYPES(Z180xycb,xycb);
 /***************************************************************
  * adjust cycle count by n T-states
  ***************************************************************/
-#define CC(prefix,opcode) cpustate->icount -= cpustate->cc[Z180_TABLE_##prefix][opcode]
+#define CC(prefix,opcode) cpustate->extra_cycles += cpustate->cc[Z180_TABLE_##prefix][opcode]
 
 /***************************************************************
  * execute an opcode
  ***************************************************************/
-#define EXEC(prefix,opcode)                                     \
-{                                                               \
-    unsigned op = opcode;                                       \
-    CC(prefix,op);                                              \
-    (*Z180##prefix[op])(cpustate);                              \
+
+#define EXEC_PROTOTYPE(prefix) \
+INLINE int exec##_##prefix(z180_state *cpustate, const UINT8 opcode) 	\
+{																		\
+    (*Z180ops[Z180_PREFIX_##prefix][opcode])(cpustate);                 		            \
+    return cpustate->cc[Z180_TABLE_##prefix][opcode]; 					\
 }
 
-#if BIG_SWITCH
-#define EXEC_INLINE(prefix,opcode)                              \
-{                                                               \
-    unsigned op = opcode;                                       \
-    CC(prefix,op);                                              \
-    switch(op)                                                  \
-    {                                                           \
-    case 0x00:prefix##_##00(cpustate);break; case 0x01:prefix##_##01(cpustate);break; case 0x02:prefix##_##02(cpustate);break; case 0x03:prefix##_##03(cpustate);break; \
-    case 0x04:prefix##_##04(cpustate);break; case 0x05:prefix##_##05(cpustate);break; case 0x06:prefix##_##06(cpustate);break; case 0x07:prefix##_##07(cpustate);break; \
-    case 0x08:prefix##_##08(cpustate);break; case 0x09:prefix##_##09(cpustate);break; case 0x0a:prefix##_##0a(cpustate);break; case 0x0b:prefix##_##0b(cpustate);break; \
-    case 0x0c:prefix##_##0c(cpustate);break; case 0x0d:prefix##_##0d(cpustate);break; case 0x0e:prefix##_##0e(cpustate);break; case 0x0f:prefix##_##0f(cpustate);break; \
-    case 0x10:prefix##_##10(cpustate);break; case 0x11:prefix##_##11(cpustate);break; case 0x12:prefix##_##12(cpustate);break; case 0x13:prefix##_##13(cpustate);break; \
-    case 0x14:prefix##_##14(cpustate);break; case 0x15:prefix##_##15(cpustate);break; case 0x16:prefix##_##16(cpustate);break; case 0x17:prefix##_##17(cpustate);break; \
-    case 0x18:prefix##_##18(cpustate);break; case 0x19:prefix##_##19(cpustate);break; case 0x1a:prefix##_##1a(cpustate);break; case 0x1b:prefix##_##1b(cpustate);break; \
-    case 0x1c:prefix##_##1c(cpustate);break; case 0x1d:prefix##_##1d(cpustate);break; case 0x1e:prefix##_##1e(cpustate);break; case 0x1f:prefix##_##1f(cpustate);break; \
-    case 0x20:prefix##_##20(cpustate);break; case 0x21:prefix##_##21(cpustate);break; case 0x22:prefix##_##22(cpustate);break; case 0x23:prefix##_##23(cpustate);break; \
-    case 0x24:prefix##_##24(cpustate);break; case 0x25:prefix##_##25(cpustate);break; case 0x26:prefix##_##26(cpustate);break; case 0x27:prefix##_##27(cpustate);break; \
-    case 0x28:prefix##_##28(cpustate);break; case 0x29:prefix##_##29(cpustate);break; case 0x2a:prefix##_##2a(cpustate);break; case 0x2b:prefix##_##2b(cpustate);break; \
-    case 0x2c:prefix##_##2c(cpustate);break; case 0x2d:prefix##_##2d(cpustate);break; case 0x2e:prefix##_##2e(cpustate);break; case 0x2f:prefix##_##2f(cpustate);break; \
-    case 0x30:prefix##_##30(cpustate);break; case 0x31:prefix##_##31(cpustate);break; case 0x32:prefix##_##32(cpustate);break; case 0x33:prefix##_##33(cpustate);break; \
-    case 0x34:prefix##_##34(cpustate);break; case 0x35:prefix##_##35(cpustate);break; case 0x36:prefix##_##36(cpustate);break; case 0x37:prefix##_##37(cpustate);break; \
-    case 0x38:prefix##_##38(cpustate);break; case 0x39:prefix##_##39(cpustate);break; case 0x3a:prefix##_##3a(cpustate);break; case 0x3b:prefix##_##3b(cpustate);break; \
-    case 0x3c:prefix##_##3c(cpustate);break; case 0x3d:prefix##_##3d(cpustate);break; case 0x3e:prefix##_##3e(cpustate);break; case 0x3f:prefix##_##3f(cpustate);break; \
-    case 0x40:prefix##_##40(cpustate);break; case 0x41:prefix##_##41(cpustate);break; case 0x42:prefix##_##42(cpustate);break; case 0x43:prefix##_##43(cpustate);break; \
-    case 0x44:prefix##_##44(cpustate);break; case 0x45:prefix##_##45(cpustate);break; case 0x46:prefix##_##46(cpustate);break; case 0x47:prefix##_##47(cpustate);break; \
-    case 0x48:prefix##_##48(cpustate);break; case 0x49:prefix##_##49(cpustate);break; case 0x4a:prefix##_##4a(cpustate);break; case 0x4b:prefix##_##4b(cpustate);break; \
-    case 0x4c:prefix##_##4c(cpustate);break; case 0x4d:prefix##_##4d(cpustate);break; case 0x4e:prefix##_##4e(cpustate);break; case 0x4f:prefix##_##4f(cpustate);break; \
-    case 0x50:prefix##_##50(cpustate);break; case 0x51:prefix##_##51(cpustate);break; case 0x52:prefix##_##52(cpustate);break; case 0x53:prefix##_##53(cpustate);break; \
-    case 0x54:prefix##_##54(cpustate);break; case 0x55:prefix##_##55(cpustate);break; case 0x56:prefix##_##56(cpustate);break; case 0x57:prefix##_##57(cpustate);break; \
-    case 0x58:prefix##_##58(cpustate);break; case 0x59:prefix##_##59(cpustate);break; case 0x5a:prefix##_##5a(cpustate);break; case 0x5b:prefix##_##5b(cpustate);break; \
-    case 0x5c:prefix##_##5c(cpustate);break; case 0x5d:prefix##_##5d(cpustate);break; case 0x5e:prefix##_##5e(cpustate);break; case 0x5f:prefix##_##5f(cpustate);break; \
-    case 0x60:prefix##_##60(cpustate);break; case 0x61:prefix##_##61(cpustate);break; case 0x62:prefix##_##62(cpustate);break; case 0x63:prefix##_##63(cpustate);break; \
-    case 0x64:prefix##_##64(cpustate);break; case 0x65:prefix##_##65(cpustate);break; case 0x66:prefix##_##66(cpustate);break; case 0x67:prefix##_##67(cpustate);break; \
-    case 0x68:prefix##_##68(cpustate);break; case 0x69:prefix##_##69(cpustate);break; case 0x6a:prefix##_##6a(cpustate);break; case 0x6b:prefix##_##6b(cpustate);break; \
-    case 0x6c:prefix##_##6c(cpustate);break; case 0x6d:prefix##_##6d(cpustate);break; case 0x6e:prefix##_##6e(cpustate);break; case 0x6f:prefix##_##6f(cpustate);break; \
-    case 0x70:prefix##_##70(cpustate);break; case 0x71:prefix##_##71(cpustate);break; case 0x72:prefix##_##72(cpustate);break; case 0x73:prefix##_##73(cpustate);break; \
-    case 0x74:prefix##_##74(cpustate);break; case 0x75:prefix##_##75(cpustate);break; case 0x76:prefix##_##76(cpustate);break; case 0x77:prefix##_##77(cpustate);break; \
-    case 0x78:prefix##_##78(cpustate);break; case 0x79:prefix##_##79(cpustate);break; case 0x7a:prefix##_##7a(cpustate);break; case 0x7b:prefix##_##7b(cpustate);break; \
-    case 0x7c:prefix##_##7c(cpustate);break; case 0x7d:prefix##_##7d(cpustate);break; case 0x7e:prefix##_##7e(cpustate);break; case 0x7f:prefix##_##7f(cpustate);break; \
-    case 0x80:prefix##_##80(cpustate);break; case 0x81:prefix##_##81(cpustate);break; case 0x82:prefix##_##82(cpustate);break; case 0x83:prefix##_##83(cpustate);break; \
-    case 0x84:prefix##_##84(cpustate);break; case 0x85:prefix##_##85(cpustate);break; case 0x86:prefix##_##86(cpustate);break; case 0x87:prefix##_##87(cpustate);break; \
-    case 0x88:prefix##_##88(cpustate);break; case 0x89:prefix##_##89(cpustate);break; case 0x8a:prefix##_##8a(cpustate);break; case 0x8b:prefix##_##8b(cpustate);break; \
-    case 0x8c:prefix##_##8c(cpustate);break; case 0x8d:prefix##_##8d(cpustate);break; case 0x8e:prefix##_##8e(cpustate);break; case 0x8f:prefix##_##8f(cpustate);break; \
-    case 0x90:prefix##_##90(cpustate);break; case 0x91:prefix##_##91(cpustate);break; case 0x92:prefix##_##92(cpustate);break; case 0x93:prefix##_##93(cpustate);break; \
-    case 0x94:prefix##_##94(cpustate);break; case 0x95:prefix##_##95(cpustate);break; case 0x96:prefix##_##96(cpustate);break; case 0x97:prefix##_##97(cpustate);break; \
-    case 0x98:prefix##_##98(cpustate);break; case 0x99:prefix##_##99(cpustate);break; case 0x9a:prefix##_##9a(cpustate);break; case 0x9b:prefix##_##9b(cpustate);break; \
-    case 0x9c:prefix##_##9c(cpustate);break; case 0x9d:prefix##_##9d(cpustate);break; case 0x9e:prefix##_##9e(cpustate);break; case 0x9f:prefix##_##9f(cpustate);break; \
-    case 0xa0:prefix##_##a0(cpustate);break; case 0xa1:prefix##_##a1(cpustate);break; case 0xa2:prefix##_##a2(cpustate);break; case 0xa3:prefix##_##a3(cpustate);break; \
-    case 0xa4:prefix##_##a4(cpustate);break; case 0xa5:prefix##_##a5(cpustate);break; case 0xa6:prefix##_##a6(cpustate);break; case 0xa7:prefix##_##a7(cpustate);break; \
-    case 0xa8:prefix##_##a8(cpustate);break; case 0xa9:prefix##_##a9(cpustate);break; case 0xaa:prefix##_##aa(cpustate);break; case 0xab:prefix##_##ab(cpustate);break; \
-    case 0xac:prefix##_##ac(cpustate);break; case 0xad:prefix##_##ad(cpustate);break; case 0xae:prefix##_##ae(cpustate);break; case 0xaf:prefix##_##af(cpustate);break; \
-    case 0xb0:prefix##_##b0(cpustate);break; case 0xb1:prefix##_##b1(cpustate);break; case 0xb2:prefix##_##b2(cpustate);break; case 0xb3:prefix##_##b3(cpustate);break; \
-    case 0xb4:prefix##_##b4(cpustate);break; case 0xb5:prefix##_##b5(cpustate);break; case 0xb6:prefix##_##b6(cpustate);break; case 0xb7:prefix##_##b7(cpustate);break; \
-    case 0xb8:prefix##_##b8(cpustate);break; case 0xb9:prefix##_##b9(cpustate);break; case 0xba:prefix##_##ba(cpustate);break; case 0xbb:prefix##_##bb(cpustate);break; \
-    case 0xbc:prefix##_##bc(cpustate);break; case 0xbd:prefix##_##bd(cpustate);break; case 0xbe:prefix##_##be(cpustate);break; case 0xbf:prefix##_##bf(cpustate);break; \
-    case 0xc0:prefix##_##c0(cpustate);break; case 0xc1:prefix##_##c1(cpustate);break; case 0xc2:prefix##_##c2(cpustate);break; case 0xc3:prefix##_##c3(cpustate);break; \
-    case 0xc4:prefix##_##c4(cpustate);break; case 0xc5:prefix##_##c5(cpustate);break; case 0xc6:prefix##_##c6(cpustate);break; case 0xc7:prefix##_##c7(cpustate);break; \
-    case 0xc8:prefix##_##c8(cpustate);break; case 0xc9:prefix##_##c9(cpustate);break; case 0xca:prefix##_##ca(cpustate);break; case 0xcb:prefix##_##cb(cpustate);break; \
-    case 0xcc:prefix##_##cc(cpustate);break; case 0xcd:prefix##_##cd(cpustate);break; case 0xce:prefix##_##ce(cpustate);break; case 0xcf:prefix##_##cf(cpustate);break; \
-    case 0xd0:prefix##_##d0(cpustate);break; case 0xd1:prefix##_##d1(cpustate);break; case 0xd2:prefix##_##d2(cpustate);break; case 0xd3:prefix##_##d3(cpustate);break; \
-    case 0xd4:prefix##_##d4(cpustate);break; case 0xd5:prefix##_##d5(cpustate);break; case 0xd6:prefix##_##d6(cpustate);break; case 0xd7:prefix##_##d7(cpustate);break; \
-    case 0xd8:prefix##_##d8(cpustate);break; case 0xd9:prefix##_##d9(cpustate);break; case 0xda:prefix##_##da(cpustate);break; case 0xdb:prefix##_##db(cpustate);break; \
-    case 0xdc:prefix##_##dc(cpustate);break; case 0xdd:prefix##_##dd(cpustate);break; case 0xde:prefix##_##de(cpustate);break; case 0xdf:prefix##_##df(cpustate);break; \
-    case 0xe0:prefix##_##e0(cpustate);break; case 0xe1:prefix##_##e1(cpustate);break; case 0xe2:prefix##_##e2(cpustate);break; case 0xe3:prefix##_##e3(cpustate);break; \
-    case 0xe4:prefix##_##e4(cpustate);break; case 0xe5:prefix##_##e5(cpustate);break; case 0xe6:prefix##_##e6(cpustate);break; case 0xe7:prefix##_##e7(cpustate);break; \
-    case 0xe8:prefix##_##e8(cpustate);break; case 0xe9:prefix##_##e9(cpustate);break; case 0xea:prefix##_##ea(cpustate);break; case 0xeb:prefix##_##eb(cpustate);break; \
-    case 0xec:prefix##_##ec(cpustate);break; case 0xed:prefix##_##ed(cpustate);break; case 0xee:prefix##_##ee(cpustate);break; case 0xef:prefix##_##ef(cpustate);break; \
-    case 0xf0:prefix##_##f0(cpustate);break; case 0xf1:prefix##_##f1(cpustate);break; case 0xf2:prefix##_##f2(cpustate);break; case 0xf3:prefix##_##f3(cpustate);break; \
-    case 0xf4:prefix##_##f4(cpustate);break; case 0xf5:prefix##_##f5(cpustate);break; case 0xf6:prefix##_##f6(cpustate);break; case 0xf7:prefix##_##f7(cpustate);break; \
-    case 0xf8:prefix##_##f8(cpustate);break; case 0xf9:prefix##_##f9(cpustate);break; case 0xfa:prefix##_##fa(cpustate);break; case 0xfb:prefix##_##fb(cpustate);break; \
-    case 0xfc:prefix##_##fc(cpustate);break; case 0xfd:prefix##_##fd(cpustate);break; case 0xfe:prefix##_##fe(cpustate);break; case 0xff:prefix##_##ff(cpustate);break; \
-    }                                                                                                                                   \
-}
-#else
-#define EXEC_INLINE EXEC
-#endif
+EXEC_PROTOTYPE(op)
+EXEC_PROTOTYPE(cb)
+EXEC_PROTOTYPE(dd)
+EXEC_PROTOTYPE(ed)
+EXEC_PROTOTYPE(fd)
+EXEC_PROTOTYPE(xycb)
+