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Merged memory maps.

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This commit is contained in:
Aaron Giles 2009-04-17 06:10:29 +00:00
parent c3c3445c1f
commit fd03e99e65
5 changed files with 173 additions and 335 deletions
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232
src/mame/drivers/suna8.c
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@ -508,31 +508,20 @@ static WRITE8_HANDLER( hardhead_flipscreen_w )
coin_lockout_w ( 1, data & 0x10); coin_lockout_w ( 1, data & 0x10);
} }
static ADDRESS_MAP_START( hardhead_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( hardhead_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1 ) // Banked ROM AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1) // Banked ROM
AM_RANGE(0xc000, 0xd7ff) AM_READ(SMH_RAM ) // RAM AM_RANGE(0xc000, 0xd7ff) AM_RAM // RAM
AM_RANGE(0xd800, 0xd9ff) AM_READ(SMH_RAM ) // Palette AM_RANGE(0xd800, 0xd9ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram) // Palette
AM_RANGE(0xda00, 0xda00) AM_READ(hardhead_ip_r ) // Input Ports AM_RANGE(0xda00, 0xda00) AM_READWRITE(hardhead_ip_r, SMH_RAM) AM_BASE(&hardhead_ip) // Input Port Select
AM_RANGE(0xda80, 0xda80) AM_READ(soundlatch2_r ) // From Sound CPU AM_RANGE(0xda80, 0xda80) AM_READWRITE(soundlatch2_r, hardhead_bankswitch_w ) // ROM Banking
AM_RANGE(0xdd80, 0xddff) AM_READ(hardhead_protection_r ) // Protection
AM_RANGE(0xe000, 0xffff) AM_READ(SMH_RAM ) // Sprites
ADDRESS_MAP_END
static ADDRESS_MAP_START( hardhead_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x8000, 0xbfff) AM_WRITE(SMH_ROM ) // Banked ROM
AM_RANGE(0xc000, 0xd7ff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0xd800, 0xd9ff) AM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette
AM_RANGE(0xda00, 0xda00) AM_WRITE(SMH_RAM) AM_BASE(&hardhead_ip ) // Input Port Select
AM_RANGE(0xda80, 0xda80) AM_WRITE(hardhead_bankswitch_w ) // ROM Banking
AM_RANGE(0xdb00, 0xdb00) AM_WRITE(soundlatch_w ) // To Sound CPU AM_RANGE(0xdb00, 0xdb00) AM_WRITE(soundlatch_w ) // To Sound CPU
AM_RANGE(0xdb80, 0xdb80) AM_WRITE(hardhead_flipscreen_w ) // Flip Screen + Coin Lockout AM_RANGE(0xdb80, 0xdb80) AM_WRITE(hardhead_flipscreen_w ) // Flip Screen + Coin Lockout
AM_RANGE(0xdc00, 0xdc00) AM_WRITE(SMH_NOP ) // <- R (after bank select) AM_RANGE(0xdc00, 0xdc00) AM_NOP // <- R (after bank select)
AM_RANGE(0xdc80, 0xdc80) AM_WRITE(SMH_NOP ) // <- R (after bank select) AM_RANGE(0xdc80, 0xdc80) AM_NOP // <- R (after bank select)
AM_RANGE(0xdd00, 0xdd00) AM_WRITE(SMH_NOP ) // <- R (after ip select) AM_RANGE(0xdd00, 0xdd00) AM_NOP // <- R (after ip select)
AM_RANGE(0xdd80, 0xddff) AM_WRITE(hardhead_protection_w ) // Protection AM_RANGE(0xdd80, 0xddff) AM_READWRITE(hardhead_protection_r, hardhead_protection_w ) // Protection
AM_RANGE(0xe000, 0xffff) AM_WRITE(suna8_spriteram_w) AM_BASE(&spriteram ) // Sprites AM_RANGE(0xe000, 0xffff) AM_RAM_WRITE(suna8_spriteram_w) AM_BASE(&spriteram ) // Sprites
ADDRESS_MAP_END ADDRESS_MAP_END
@ -580,31 +569,21 @@ static READ8_HANDLER( rranger_soundstatus_r )
return 0x02; return 0x02;
} }
static ADDRESS_MAP_START( rranger_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( rranger_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1 ) // Banked ROM AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1) // Banked ROM
AM_RANGE(0xc000, 0xc000) AM_READ(watchdog_reset_r ) // Watchdog (Tested!) AM_RANGE(0xc000, 0xc000) AM_READWRITE(watchdog_reset_r, soundlatch_w) // To Sound CPU
AM_RANGE(0xc002, 0xc002) AM_WRITE(rranger_bankswitch_w ) // ROM Banking
AM_RANGE(0xc002, 0xc002) AM_READ_PORT("P1") // P1 (Inputs) AM_RANGE(0xc002, 0xc002) AM_READ_PORT("P1") // P1 (Inputs)
AM_RANGE(0xc003, 0xc003) AM_READ_PORT("P2") // P2 AM_RANGE(0xc003, 0xc003) AM_READ_PORT("P2") // P2
AM_RANGE(0xc004, 0xc004) AM_READ(rranger_soundstatus_r ) // Latch Status? AM_RANGE(0xc004, 0xc004) AM_READ(rranger_soundstatus_r ) // Latch Status?
AM_RANGE(0xc200, 0xc200) AM_READ(SMH_NOP ) // Protection? AM_RANGE(0xc200, 0xc200) AM_NOP // Protection?
AM_RANGE(0xc280, 0xc280) AM_WRITE(SMH_NOP ) // ? NMI Ack
AM_RANGE(0xc280, 0xc280) AM_READ_PORT("DSW1") // DSW 1 AM_RANGE(0xc280, 0xc280) AM_READ_PORT("DSW1") // DSW 1
AM_RANGE(0xc2c0, 0xc2c0) AM_READ_PORT("DSW2") // DSW 2 AM_RANGE(0xc2c0, 0xc2c0) AM_READ_PORT("DSW2") // DSW 2
AM_RANGE(0xc600, 0xc7ff) AM_READ(SMH_RAM ) // Palette AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram) // Palette
AM_RANGE(0xc800, 0xdfff) AM_READ(SMH_RAM ) // RAM AM_RANGE(0xc800, 0xdfff) AM_RAM // RAM
AM_RANGE(0xe000, 0xffff) AM_READ(SMH_RAM ) // Sprites AM_RANGE(0xe000, 0xffff) AM_RAM_WRITE(suna8_spriteram_w) AM_BASE(&spriteram ) // Sprites
ADDRESS_MAP_END
static ADDRESS_MAP_START( rranger_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x8000, 0xbfff) AM_WRITE(SMH_ROM ) // Banked ROM
AM_RANGE(0xc000, 0xc000) AM_WRITE(soundlatch_w ) // To Sound CPU
AM_RANGE(0xc002, 0xc002) AM_WRITE(rranger_bankswitch_w ) // ROM Banking
AM_RANGE(0xc200, 0xc200) AM_WRITE(SMH_NOP ) // Protection?
AM_RANGE(0xc280, 0xc280) AM_WRITE(SMH_NOP ) // ? NMI Ack
AM_RANGE(0xc600, 0xc7ff) AM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette
AM_RANGE(0xc800, 0xdfff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0xe000, 0xffff) AM_WRITE(suna8_spriteram_w) AM_BASE(&spriteram ) // Sprites
ADDRESS_MAP_END ADDRESS_MAP_END
@ -667,31 +646,23 @@ static WRITE8_HANDLER( brickzn_rombank_w )
suna8_rombank = data; suna8_rombank = data;
} }
static ADDRESS_MAP_START( brickzn_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( brickzn_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1 ) // Banked ROM AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1) // Banked ROM
AM_RANGE(0xc040, 0xc040) AM_WRITE(brickzn_rombank_w ) // ROM Bank
AM_RANGE(0xc060, 0xc060) AM_WRITE(brickzn_spritebank_w ) // Sprite RAM Bank + Flip Screen
AM_RANGE(0xc0a0, 0xc0a0) AM_WRITE(brickzn_palettebank_w ) // Palette RAM Bank + ?
AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_unknown_w ) // ???
AM_RANGE(0xc100, 0xc100) AM_READ_PORT("P1") // P1 (Buttons) AM_RANGE(0xc100, 0xc100) AM_READ_PORT("P1") // P1 (Buttons)
AM_RANGE(0xc101, 0xc101) AM_READ_PORT("P2") // P2 AM_RANGE(0xc101, 0xc101) AM_READ_PORT("P2") // P2
AM_RANGE(0xc102, 0xc102) AM_READ_PORT("DSW1") // DSW 1 AM_RANGE(0xc102, 0xc102) AM_READ_PORT("DSW1") // DSW 1
AM_RANGE(0xc103, 0xc103) AM_READ_PORT("DSW2") // DSW 2 AM_RANGE(0xc103, 0xc103) AM_READ_PORT("DSW2") // DSW 2
AM_RANGE(0xc108, 0xc108) AM_READ_PORT("TRACK1") // P1 (Analog) AM_RANGE(0xc108, 0xc108) AM_READ_PORT("TRACK1") // P1 (Analog)
AM_RANGE(0xc10c, 0xc10c) AM_READ_PORT("TRACK2") // P2 AM_RANGE(0xc10c, 0xc10c) AM_READ_PORT("TRACK2") // P2
AM_RANGE(0xc140, 0xc140) AM_READ(brickzn_c140_r ) // ??? AM_RANGE(0xc140, 0xc140) AM_READ(brickzn_c140_r) // ???
AM_RANGE(0xc600, 0xc7ff) AM_READ(suna8_banked_paletteram_r ) // Palette (Banked) AM_RANGE(0xc600, 0xc7ff) AM_READWRITE(suna8_banked_paletteram_r, brickzn_banked_paletteram_w) // Palette (Banked)
AM_RANGE(0xc800, 0xdfff) AM_READ(SMH_RAM ) // RAM AM_RANGE(0xc800, 0xdfff) AM_RAM // RAM
AM_RANGE(0xe000, 0xffff) AM_READ(suna8_banked_spriteram_r ) // Sprites (Banked) AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w) // Sprites (Banked)
ADDRESS_MAP_END
static ADDRESS_MAP_START( brickzn_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x8000, 0xbfff) AM_WRITE(SMH_ROM ) // Banked ROM
AM_RANGE(0xc040, 0xc040) AM_WRITE(brickzn_rombank_w ) // ROM Bank
AM_RANGE(0xc060, 0xc060) AM_WRITE(brickzn_spritebank_w ) // Sprite RAM Bank + Flip Screen
AM_RANGE(0xc0a0, 0xc0a0) AM_WRITE(brickzn_palettebank_w ) // Palette RAM Bank + ?
AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_unknown_w ) // ???
AM_RANGE(0xc600, 0xc7ff) AM_WRITE(brickzn_banked_paletteram_w ) // Palette (Banked)
AM_RANGE(0xc800, 0xdfff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0xe000, 0xffff) AM_WRITE(suna8_banked_spriteram_w ) // Sprites (Banked)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -770,22 +741,14 @@ static WRITE8_HANDLER( hardhea2_rambank_1_w )
} }
static ADDRESS_MAP_START( hardhea2_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( hardhea2_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1 ) // Banked ROM AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1) // Banked ROM
AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1") // P1 (Inputs) AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1") // P1 (Inputs)
AM_RANGE(0xc001, 0xc001) AM_READ_PORT("P2") // P2 AM_RANGE(0xc001, 0xc001) AM_READ_PORT("P2") // P2
AM_RANGE(0xc002, 0xc002) AM_READ_PORT("DSW1") // DSW 1 AM_RANGE(0xc002, 0xc002) AM_READ_PORT("DSW1") // DSW 1
AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2") // DSW 2 AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2") // DSW 2
AM_RANGE(0xc080, 0xc080) AM_READ_PORT("BUTTONS") // vblank? AM_RANGE(0xc080, 0xc080) AM_READ_PORT("BUTTONS") // vblank?
AM_RANGE(0xc600, 0xc7ff) AM_READ(SMH_RAM ) // Palette (Banked??)
AM_RANGE(0xc800, 0xdfff) AM_READ(SMH_BANK2 ) // RAM (Banked?)
AM_RANGE(0xe000, 0xffff) AM_READ(suna8_banked_spriteram_r ) // Sprites (Banked)
ADDRESS_MAP_END
static ADDRESS_MAP_START( hardhea2_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x8000, 0xbfff) AM_WRITE(SMH_ROM ) // Banked ROM
AM_RANGE(0xc200, 0xc200) AM_WRITE(hardhea2_spritebank_w ) // Sprite RAM Bank AM_RANGE(0xc200, 0xc200) AM_WRITE(hardhea2_spritebank_w ) // Sprite RAM Bank
AM_RANGE(0xc280, 0xc280) AM_WRITE(hardhea2_rombank_w ) // ROM Bank (?mirrored up to c2ff?) AM_RANGE(0xc280, 0xc280) AM_WRITE(hardhea2_rombank_w ) // ROM Bank (?mirrored up to c2ff?)
@ -813,9 +776,9 @@ static ADDRESS_MAP_START( hardhea2_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0xc533, 0xc533) AM_WRITE(hardhea2_rambank_0_w ) AM_RANGE(0xc533, 0xc533) AM_WRITE(hardhea2_rambank_0_w )
// Protection *** // Protection ***
AM_RANGE(0xc600, 0xc7ff) AM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette (Banked??) AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette (Banked??)
AM_RANGE(0xc800, 0xdfff) AM_WRITE(SMH_BANK2 ) // RAM (Banked?) AM_RANGE(0xc800, 0xdfff) AM_RAMBANK(2) // RAM (Banked?)
AM_RANGE(0xe000, 0xffff) AM_WRITE(suna8_banked_spriteram_w ) // Sprites (Banked) AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w) // Sprites (Banked)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -835,30 +798,22 @@ static WRITE8_HANDLER( starfigh_spritebank_w )
suna8_spritebank = spritebank_latch; suna8_spritebank = spritebank_latch;
} }
static ADDRESS_MAP_START( starfigh_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( starfigh_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1 ) // Banked ROM AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1) // Banked ROM
AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1") // P1 (Inputs) AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1") // P1 (Inputs)
AM_RANGE(0xc001, 0xc001) AM_READ_PORT("P2") // P2 AM_RANGE(0xc001, 0xc001) AM_READ_PORT("P2") // P2
AM_RANGE(0xc002, 0xc002) AM_READ_PORT("DSW1") // DSW 1 AM_RANGE(0xc002, 0xc002) AM_READ_PORT("DSW1") // DSW 1
AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2") // DSW 2 AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2") // DSW 2
AM_RANGE(0xc600, 0xc7ff) AM_READ(suna8_banked_paletteram_r ) // Palette (Banked??)
AM_RANGE(0xc800, 0xdfff) AM_READ(SMH_RAM ) // RAM
AM_RANGE(0xe000, 0xffff) AM_READ(suna8_banked_spriteram_r ) // Sprites (Banked)
ADDRESS_MAP_END
static ADDRESS_MAP_START( starfigh_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x8000, 0xbfff) AM_WRITE(SMH_ROM ) // Banked ROM
AM_RANGE(0xc200, 0xc200) AM_WRITE(starfigh_spritebank_w ) // Sprite RAM Bank AM_RANGE(0xc200, 0xc200) AM_WRITE(starfigh_spritebank_w ) // Sprite RAM Bank
AM_RANGE(0xc380, 0xc3ff) AM_WRITE(starfigh_spritebank_latch_w ) // Sprite RAM Bank AM_RANGE(0xc380, 0xc3ff) AM_WRITE(starfigh_spritebank_latch_w ) // Sprite RAM Bank
AM_RANGE(0xc280, 0xc280) AM_WRITE(hardhea2_rombank_w ) // ROM Bank (?mirrored up to c2ff?) AM_RANGE(0xc280, 0xc280) AM_WRITE(hardhea2_rombank_w ) // ROM Bank (?mirrored up to c2ff?)
AM_RANGE(0xc300, 0xc300) AM_WRITE(hardhea2_flipscreen_w ) // Flip Screen AM_RANGE(0xc300, 0xc300) AM_WRITE(hardhea2_flipscreen_w ) // Flip Screen
AM_RANGE(0xc400, 0xc400) AM_WRITE(hardhea2_leds_w ) // Leds + Coin Counter AM_RANGE(0xc400, 0xc400) AM_WRITE(hardhea2_leds_w ) // Leds + Coin Counter
AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w ) // To Sound CPU AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w ) // To Sound CPU
AM_RANGE(0xc600, 0xc7ff) AM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette (Banked??) AM_RANGE(0xc600, 0xc7ff) AM_READWRITE(suna8_banked_paletteram_r, paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette (Banked??)
AM_RANGE(0xc800, 0xdfff) AM_WRITE(SMH_RAM ) // RAM AM_RANGE(0xc800, 0xdfff) AM_RAM // RAM
AM_RANGE(0xe000, 0xffff) AM_WRITE(suna8_banked_spriteram_w ) // Sprites (Banked) AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w) // Sprites (Banked)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -921,32 +876,24 @@ static READ8_HANDLER( sparkman_c0a3_r )
return (video_screen_get_frame_number(space->machine->primary_screen) & 1) ? 0x80 : 0; return (video_screen_get_frame_number(space->machine->primary_screen) & 1) ? 0x80 : 0;
} }
static ADDRESS_MAP_START( sparkman_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( sparkman_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1 ) // Banked ROM AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1) // Banked ROM
AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1") // P1 (Inputs) AM_RANGE(0xc000, 0xc000) AM_READ_PORT("P1") // P1 (Inputs)
AM_RANGE(0xc001, 0xc001) AM_READ_PORT("P2") // P2 AM_RANGE(0xc001, 0xc001) AM_READ_PORT("P2") // P2
AM_RANGE(0xc002, 0xc002) AM_READ_PORT("DSW1") // DSW 1 AM_RANGE(0xc002, 0xc002) AM_READ_PORT("DSW1") // DSW 1
AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2") // DSW 2 AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2") // DSW 2
AM_RANGE(0xc080, 0xc080) AM_READ_PORT("BUTTONS") // Buttons AM_RANGE(0xc080, 0xc080) AM_READ_PORT("BUTTONS") // Buttons
AM_RANGE(0xc0a3, 0xc0a3) AM_READ(sparkman_c0a3_r ) // ??? AM_RANGE(0xc0a3, 0xc0a3) AM_READ(sparkman_c0a3_r ) // ???
AM_RANGE(0xc600, 0xc7ff) AM_READ(SMH_RAM ) // Palette (Banked??)
AM_RANGE(0xc800, 0xdfff) AM_READ(SMH_RAM ) // RAM
AM_RANGE(0xe000, 0xffff) AM_READ(suna8_banked_spriteram_r ) // Sprites (Banked)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sparkman_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x8000, 0xbfff) AM_WRITE(SMH_ROM ) // Banked ROM
AM_RANGE(0xc200, 0xc200) AM_WRITE(sparkman_spritebank_w ) // Sprite RAM Bank AM_RANGE(0xc200, 0xc200) AM_WRITE(sparkman_spritebank_w ) // Sprite RAM Bank
AM_RANGE(0xc280, 0xc280) AM_WRITE(sparkman_rombank_w ) // ROM Bank (?mirrored up to c2ff?) AM_RANGE(0xc280, 0xc280) AM_WRITE(sparkman_rombank_w ) // ROM Bank (?mirrored up to c2ff?)
AM_RANGE(0xc300, 0xc300) AM_WRITE(sparkman_flipscreen_w ) // Flip Screen AM_RANGE(0xc300, 0xc300) AM_WRITE(sparkman_flipscreen_w ) // Flip Screen
AM_RANGE(0xc380, 0xc380) AM_WRITE(sparkman_nmi_w ) // ? NMI related ? AM_RANGE(0xc380, 0xc380) AM_WRITE(sparkman_nmi_w ) // ? NMI related ?
AM_RANGE(0xc400, 0xc400) AM_WRITE(sparkman_leds_w ) // Leds + Coin Counter AM_RANGE(0xc400, 0xc400) AM_WRITE(sparkman_leds_w ) // Leds + Coin Counter
AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w ) // To Sound CPU AM_RANGE(0xc500, 0xc500) AM_WRITE(soundlatch_w ) // To Sound CPU
AM_RANGE(0xc600, 0xc7ff) AM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette (Banked??) AM_RANGE(0xc600, 0xc7ff) AM_RAM_WRITE(paletteram_RRRRGGGGBBBBxxxx_be_w) AM_BASE(&paletteram ) // Palette (Banked??)
AM_RANGE(0xc800, 0xdfff) AM_WRITE(SMH_RAM ) // RAM AM_RANGE(0xc800, 0xdfff) AM_RAM // RAM
AM_RANGE(0xe000, 0xffff) AM_WRITE(suna8_banked_spriteram_w ) // Sprites (Banked) AM_RANGE(0xe000, 0xffff) AM_READWRITE(suna8_banked_spriteram_r, suna8_banked_spriteram_w ) // Sprites (Banked)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -962,19 +909,14 @@ ADDRESS_MAP_END
Hard Head Hard Head
***************************************************************************/ ***************************************************************************/
static ADDRESS_MAP_START( hardhead_sound_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( hardhead_sound_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0xc000, 0xc7ff) AM_READ(SMH_RAM ) // RAM
AM_RANGE(0xc800, 0xc800) AM_DEVREAD("ym", ym3812_status_port_r) // ? unsure
AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_r ) // From Main CPU
ADDRESS_MAP_END
static ADDRESS_MAP_START( hardhead_sound_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0xc000, 0xc7ff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_w ) //
AM_RANGE(0xa000, 0xa001) AM_DEVREADWRITE("ym", ym3812_r, ym3812_w) AM_RANGE(0xa000, 0xa001) AM_DEVREADWRITE("ym", ym3812_r, ym3812_w)
AM_RANGE(0xa002, 0xa003) AM_DEVWRITE("ay", ay8910_address_data_w ) AM_RANGE(0xa002, 0xa003) AM_DEVWRITE("ay", ay8910_address_data_w )
AM_RANGE(0xc000, 0xc7ff) AM_RAM // RAM
AM_RANGE(0xc800, 0xc800) AM_DEVREAD("ym", ym3812_status_port_r) // ? unsure
AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_w ) //
AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_r ) // From Main CPU
ADDRESS_MAP_END ADDRESS_MAP_END
@ -988,18 +930,13 @@ ADDRESS_MAP_END
Rough Ranger Rough Ranger
***************************************************************************/ ***************************************************************************/
static ADDRESS_MAP_START( rranger_sound_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( rranger_sound_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0x7fff) AM_ROM // ROM
AM_RANGE(0xc000, 0xc7ff) AM_READ(SMH_RAM ) // RAM
AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_r ) // From Main CPU
ADDRESS_MAP_END
static ADDRESS_MAP_START( rranger_sound_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0xc000, 0xc7ff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_w ) // To Sound CPU
AM_RANGE(0xa000, 0xa001) AM_DEVWRITE("ym1", ym2203_w ) // Samples + Music AM_RANGE(0xa000, 0xa001) AM_DEVWRITE("ym1", ym2203_w ) // Samples + Music
AM_RANGE(0xa002, 0xa003) AM_DEVWRITE("ym2", ym2203_w ) // Music + FX AM_RANGE(0xa002, 0xa003) AM_DEVWRITE("ym2", ym2203_w ) // Music + FX
AM_RANGE(0xc000, 0xc7ff) AM_RAM // RAM
AM_RANGE(0xd000, 0xd000) AM_WRITE(soundlatch2_w ) // To Sound CPU
AM_RANGE(0xd800, 0xd800) AM_READ(soundlatch_r ) // From Main CPU
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1007,28 +944,20 @@ ADDRESS_MAP_END
Brick Zone Brick Zone
***************************************************************************/ ***************************************************************************/
static ADDRESS_MAP_START( brickzn_sound_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( brickzn_sound_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0xbfff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0xbfff) AM_ROM // ROM
AM_RANGE(0xe000, 0xe7ff) AM_READ(SMH_RAM ) // RAM
AM_RANGE(0xf800, 0xf800) AM_READ(soundlatch_r ) // From Main CPU
ADDRESS_MAP_END
static ADDRESS_MAP_START( brickzn_sound_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0xbfff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0xc000, 0xc001) AM_DEVWRITE("ym", ym3812_w ) AM_RANGE(0xc000, 0xc001) AM_DEVWRITE("ym", ym3812_w )
AM_RANGE(0xc002, 0xc003) AM_DEVWRITE("ay", ay8910_address_data_w ) AM_RANGE(0xc002, 0xc003) AM_DEVWRITE("ay", ay8910_address_data_w )
AM_RANGE(0xe000, 0xe7ff) AM_WRITE(SMH_RAM ) // RAM AM_RANGE(0xe000, 0xe7ff) AM_RAM // RAM
AM_RANGE(0xf000, 0xf000) AM_WRITE(soundlatch2_w ) // To PCM CPU AM_RANGE(0xf000, 0xf000) AM_WRITE(soundlatch2_w ) // To PCM CPU
AM_RANGE(0xf800, 0xf800) AM_READ(soundlatch_r ) // From Main CPU
ADDRESS_MAP_END ADDRESS_MAP_END
/* PCM Z80 , 4 DACs (4 bits per sample), NO RAM !! */ /* PCM Z80 , 4 DACs (4 bits per sample), NO RAM !! */
static ADDRESS_MAP_START( brickzn_pcm_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( brickzn_pcm_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0xffff) AM_READ(SMH_ROM ) // ROM AM_RANGE(0x0000, 0xffff) AM_ROM // ROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( brickzn_pcm_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0xffff) AM_WRITE(SMH_ROM ) // ROM
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1482,12 +1411,12 @@ static MACHINE_DRIVER_START( hardhead )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(hardhead_readmem,hardhead_writemem) MDRV_CPU_PROGRAM_MAP(hardhead_map,0)
MDRV_CPU_IO_MAP(hardhead_io_map,0) MDRV_CPU_IO_MAP(hardhead_io_map,0)
MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) /* No NMI */ MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) /* No NMI */
MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(hardhead_sound_readmem,hardhead_sound_writemem) MDRV_CPU_PROGRAM_MAP(hardhead_sound_map,0)
MDRV_CPU_IO_MAP(hardhead_sound_io_map,0) MDRV_CPU_IO_MAP(hardhead_sound_io_map,0)
MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* No NMI */ MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* No NMI */
@ -1548,12 +1477,12 @@ static MACHINE_DRIVER_START( rranger )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(rranger_readmem,rranger_writemem) MDRV_CPU_PROGRAM_MAP(rranger_map,0)
MDRV_CPU_IO_MAP(rranger_io_map,0) MDRV_CPU_IO_MAP(rranger_io_map,0)
MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) /* IRQ & NMI ! */ MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) /* IRQ & NMI ! */
MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(rranger_sound_readmem,rranger_sound_writemem) MDRV_CPU_PROGRAM_MAP(rranger_sound_map,0)
MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* NMI = retn */ MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* NMI = retn */
/* video hardware */ /* video hardware */
@ -1610,15 +1539,15 @@ static MACHINE_DRIVER_START( brickzn )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* SUNA PROTECTION BLOCK */ MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* SUNA PROTECTION BLOCK */
MDRV_CPU_PROGRAM_MAP(brickzn_readmem,brickzn_writemem) MDRV_CPU_PROGRAM_MAP(brickzn_map,0)
// MDRV_CPU_VBLANK_INT_HACK(brickzn_interrupt, 2) // MDRV_CPU_VBLANK_INT_HACK(brickzn_interrupt, 2)
MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) // nmi breaks ramtest but is needed! MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) // nmi breaks ramtest but is needed!
MDRV_CPU_ADD("soundcpu", Z80, SUNA8_MASTER_CLOCK / 4) /* Z0840006PSC */ MDRV_CPU_ADD("soundcpu", Z80, SUNA8_MASTER_CLOCK / 4) /* Z0840006PSC */
MDRV_CPU_PROGRAM_MAP(brickzn_sound_readmem,brickzn_sound_writemem) MDRV_CPU_PROGRAM_MAP(brickzn_sound_map,0)
MDRV_CPU_ADD("pcm", Z80, SUNA8_MASTER_CLOCK / 4) /* Z0840006PSC */ MDRV_CPU_ADD("pcm", Z80, SUNA8_MASTER_CLOCK / 4) /* Z0840006PSC */
MDRV_CPU_PROGRAM_MAP(brickzn_pcm_readmem,brickzn_pcm_writemem) MDRV_CPU_PROGRAM_MAP(brickzn_pcm_map,0)
MDRV_CPU_IO_MAP(brickzn_pcm_io_map,0) MDRV_CPU_IO_MAP(brickzn_pcm_io_map,0)
/* video hardware */ /* video hardware */
@ -1686,7 +1615,7 @@ static MACHINE_DRIVER_START( hardhea2 )
MDRV_IMPORT_FROM( brickzn ) MDRV_IMPORT_FROM( brickzn )
MDRV_CPU_MODIFY("maincpu") /* SUNA T568009 */ MDRV_CPU_MODIFY("maincpu") /* SUNA T568009 */
MDRV_CPU_PROGRAM_MAP(hardhea2_readmem,hardhea2_writemem) MDRV_CPU_PROGRAM_MAP(hardhea2_map,0)
MDRV_CPU_VBLANK_INT_HACK(hardhea2_interrupt,2) /* IRQ & NMI */ MDRV_CPU_VBLANK_INT_HACK(hardhea2_interrupt,2) /* IRQ & NMI */
MDRV_MACHINE_RESET(hardhea2) MDRV_MACHINE_RESET(hardhea2)
@ -1712,12 +1641,12 @@ static MACHINE_DRIVER_START( starfigh )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(starfigh_readmem,starfigh_writemem) MDRV_CPU_PROGRAM_MAP(starfigh_map,0)
MDRV_CPU_VBLANK_INT_HACK(brickzn_interrupt,2) /* IRQ & NMI */ MDRV_CPU_VBLANK_INT_HACK(brickzn_interrupt,2) /* IRQ & NMI */
/* The sound section is identical to that of hardhead */ /* The sound section is identical to that of hardhead */
MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(hardhead_sound_readmem,hardhead_sound_writemem) MDRV_CPU_PROGRAM_MAP(hardhead_sound_map,0)
MDRV_CPU_IO_MAP(hardhead_sound_io_map,0) MDRV_CPU_IO_MAP(hardhead_sound_io_map,0)
MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* No NMI */ MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* No NMI */
@ -1771,11 +1700,11 @@ static MACHINE_DRIVER_START( sparkman )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(sparkman_readmem,sparkman_writemem) MDRV_CPU_PROGRAM_MAP(sparkman_map,0)
MDRV_CPU_VBLANK_INT_HACK(sparkman_interrupt,2) /* IRQ & NMI */ MDRV_CPU_VBLANK_INT_HACK(sparkman_interrupt,2) /* IRQ & NMI */
MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */ MDRV_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
MDRV_CPU_PROGRAM_MAP(hardhead_sound_readmem,hardhead_sound_writemem) MDRV_CPU_PROGRAM_MAP(hardhead_sound_map,0)
MDRV_CPU_IO_MAP(hardhead_sound_io_map,0) MDRV_CPU_IO_MAP(hardhead_sound_io_map,0)
MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* No NMI */ MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,4) /* No NMI */
@ -2356,4 +2285,3 @@ GAME( 1989, sparkman, 0, sparkman, sparkman, sparkman, ROT0, "SunA", "Sp
GAME( 1990, starfigh, 0, starfigh, hardhea2, starfigh, ROT90, "SunA", "Star Fighter (v1)", GAME_NOT_WORKING ) GAME( 1990, starfigh, 0, starfigh, hardhea2, starfigh, ROT90, "SunA", "Star Fighter (v1)", GAME_NOT_WORKING )
GAME( 1992, brickzn, 0, brickzn, brickzn, brickzn, ROT90, "SunA", "Brick Zone (v5.0)", GAME_NOT_WORKING ) GAME( 1992, brickzn, 0, brickzn, brickzn, brickzn, ROT90, "SunA", "Brick Zone (v5.0)", GAME_NOT_WORKING )
GAME( 1992, brickzn3, brickzn, brickzn, brickzn, brickzn3, ROT90, "SunA", "Brick Zone (v4.0)", GAME_NOT_WORKING ) GAME( 1992, brickzn3, brickzn, brickzn, brickzn, brickzn3, ROT90, "SunA", "Brick Zone (v4.0)", GAME_NOT_WORKING )

100
src/mame/drivers/supbtime.c
View File

@ -59,82 +59,50 @@ static WRITE16_HANDLER( sound_w )
/******************************************************************************/ /******************************************************************************/
static ADDRESS_MAP_START( supbtime_readmem, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( supbtime_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x03ffff) AM_READ(SMH_ROM) AM_RANGE(0x000000, 0x03ffff) AM_ROM
AM_RANGE(0x100000, 0x103fff) AM_READ(SMH_RAM) AM_RANGE(0x100000, 0x103fff) AM_RAM
AM_RANGE(0x120000, 0x1207ff) AM_READ(SMH_RAM)
AM_RANGE(0x140000, 0x1407ff) AM_READ(SMH_RAM)
AM_RANGE(0x180000, 0x18000f) AM_READ(supbtime_controls_r)
AM_RANGE(0x320000, 0x321fff) AM_READ(SMH_RAM)
AM_RANGE(0x322000, 0x323fff) AM_READ(SMH_RAM)
AM_RANGE(0x340000, 0x3407ff) AM_READ(SMH_RAM)
AM_RANGE(0x342000, 0x3427ff) AM_READ(SMH_RAM)
ADDRESS_MAP_END
static ADDRESS_MAP_START( supbtime_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x03ffff) AM_WRITE(SMH_ROM)
AM_RANGE(0x100000, 0x103fff) AM_WRITE(SMH_RAM)
AM_RANGE(0x104000, 0x11ffff) AM_WRITENOP /* Nothing there */ AM_RANGE(0x104000, 0x11ffff) AM_WRITENOP /* Nothing there */
AM_RANGE(0x120000, 0x1207ff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_RANGE(0x120000, 0x1207ff) AM_RAM AM_BASE(&spriteram16)
AM_RANGE(0x120800, 0x13ffff) AM_WRITENOP /* Nothing there */ AM_RANGE(0x120800, 0x13ffff) AM_WRITENOP /* Nothing there */
AM_RANGE(0x140000, 0x1407ff) AM_WRITE(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE(&paletteram16) AM_RANGE(0x140000, 0x1407ff) AM_RAM_WRITE(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE(&paletteram16)
AM_RANGE(0x180000, 0x18000f) AM_READ(supbtime_controls_r)
AM_RANGE(0x18000a, 0x18000d) AM_WRITENOP AM_RANGE(0x18000a, 0x18000d) AM_WRITENOP
AM_RANGE(0x1a0000, 0x1a0001) AM_WRITE(sound_w) AM_RANGE(0x1a0000, 0x1a0001) AM_WRITE(sound_w)
AM_RANGE(0x300000, 0x30000f) AM_RAM AM_BASE(&deco16_pf12_control)
AM_RANGE(0x300000, 0x30000f) AM_WRITE(SMH_RAM) AM_BASE(&deco16_pf12_control) AM_RANGE(0x320000, 0x321fff) AM_RAM_WRITE(deco16_pf1_data_w) AM_BASE(&deco16_pf1_data)
AM_RANGE(0x320000, 0x321fff) AM_WRITE(deco16_pf1_data_w) AM_BASE(&deco16_pf1_data) AM_RANGE(0x322000, 0x323fff) AM_RAM_WRITE(deco16_pf2_data_w) AM_BASE(&deco16_pf2_data)
AM_RANGE(0x322000, 0x323fff) AM_WRITE(deco16_pf2_data_w) AM_BASE(&deco16_pf2_data) AM_RANGE(0x340000, 0x3407ff) AM_RAM AM_BASE(&deco16_pf1_rowscroll)
AM_RANGE(0x340000, 0x3407ff) AM_WRITE(SMH_RAM) AM_BASE(&deco16_pf1_rowscroll) AM_RANGE(0x342000, 0x3427ff) AM_RAM AM_BASE(&deco16_pf2_rowscroll)
AM_RANGE(0x342000, 0x3427ff) AM_WRITE(SMH_RAM) AM_BASE(&deco16_pf2_rowscroll)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( chinatwn_readmem, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( chinatwn_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x03ffff) AM_READ(SMH_ROM) AM_RANGE(0x000000, 0x03ffff) AM_ROM
AM_RANGE(0x120000, 0x1207ff) AM_READ(SMH_RAM)
AM_RANGE(0x140000, 0x1407ff) AM_READ(SMH_RAM)
AM_RANGE(0x180000, 0x18000f) AM_READ(supbtime_controls_r)
AM_RANGE(0x1a0000, 0x1a3fff) AM_READ(SMH_RAM)
AM_RANGE(0x320000, 0x321fff) AM_READ(SMH_RAM)
AM_RANGE(0x322000, 0x323fff) AM_READ(SMH_RAM)
AM_RANGE(0x340000, 0x3407ff) AM_READ(SMH_RAM)
AM_RANGE(0x342000, 0x3427ff) AM_READ(SMH_RAM)
ADDRESS_MAP_END
static ADDRESS_MAP_START( chinatwn_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x03ffff) AM_WRITE(SMH_ROM)
AM_RANGE(0x100000, 0x100001) AM_WRITE(sound_w) AM_RANGE(0x100000, 0x100001) AM_WRITE(sound_w)
AM_RANGE(0x120000, 0x1207ff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_RANGE(0x120000, 0x1207ff) AM_RAM AM_BASE(&spriteram16)
AM_RANGE(0x140000, 0x1407ff) AM_WRITE(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE(&paletteram16) AM_RANGE(0x140000, 0x1407ff) AM_RAM_WRITE(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE(&paletteram16)
AM_RANGE(0x180000, 0x18000f) AM_READ(supbtime_controls_r)
AM_RANGE(0x18000a, 0x18000d) AM_WRITENOP AM_RANGE(0x18000a, 0x18000d) AM_WRITENOP
AM_RANGE(0x1a0000, 0x1a3fff) AM_WRITE(SMH_RAM) AM_RANGE(0x1a0000, 0x1a3fff) AM_RAM
AM_RANGE(0x300000, 0x30000f) AM_RAM AM_BASE(&deco16_pf12_control)
AM_RANGE(0x300000, 0x30000f) AM_WRITE(SMH_RAM) AM_BASE(&deco16_pf12_control) AM_RANGE(0x320000, 0x321fff) AM_RAM_WRITE(deco16_pf1_data_w) AM_BASE(&deco16_pf1_data)
AM_RANGE(0x320000, 0x321fff) AM_WRITE(deco16_pf1_data_w) AM_BASE(&deco16_pf1_data) AM_RANGE(0x322000, 0x323fff) AM_RAM_WRITE(deco16_pf2_data_w) AM_BASE(&deco16_pf2_data)
AM_RANGE(0x322000, 0x323fff) AM_WRITE(deco16_pf2_data_w) AM_BASE(&deco16_pf2_data) AM_RANGE(0x340000, 0x3407ff) AM_RAM AM_BASE(&deco16_pf1_rowscroll) // unused
AM_RANGE(0x340000, 0x3407ff) AM_WRITE(SMH_RAM) AM_BASE(&deco16_pf1_rowscroll) // unused AM_RANGE(0x342000, 0x3427ff) AM_RAM AM_BASE(&deco16_pf2_rowscroll) // unused
AM_RANGE(0x342000, 0x3427ff) AM_WRITE(SMH_RAM) AM_BASE(&deco16_pf2_rowscroll) // unused
ADDRESS_MAP_END ADDRESS_MAP_END
/******************************************************************************/ /******************************************************************************/
/* Physical memory map (21 bits) */ /* Physical memory map (21 bits) */
static ADDRESS_MAP_START( sound_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( sound_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x000000, 0x00ffff) AM_READ(SMH_ROM) ADDRESS_MAP_GLOBAL_MASK(0x1fffff)
AM_RANGE(0x100000, 0x100001) AM_READNOP AM_RANGE(0x000000, 0x00ffff) AM_ROM
AM_RANGE(0x110000, 0x110001) AM_DEVREAD("ym", ym2151_r) AM_RANGE(0x100000, 0x100001) AM_NOP /* YM2203 - this board doesn't have one */
AM_RANGE(0x120000, 0x120001) AM_DEVREAD("oki", okim6295_r) AM_RANGE(0x110000, 0x110001) AM_DEVREADWRITE("ym", ym2151_r, ym2151_w)
AM_RANGE(0x130000, 0x130001) AM_READNOP /* This board only has 1 oki chip */ AM_RANGE(0x120000, 0x120001) AM_DEVREADWRITE("oki", okim6295_r, okim6295_w)
AM_RANGE(0x130000, 0x130001) AM_NOP /* This board only has 1 oki chip */
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_r) AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_READ(SMH_BANK8) AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK(8)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x000000, 0x00ffff) AM_WRITE(SMH_ROM)
AM_RANGE(0x100000, 0x100001) AM_WRITENOP /* YM2203 - this board doesn't have one */
AM_RANGE(0x110000, 0x110001) AM_DEVWRITE("ym", ym2151_w)
AM_RANGE(0x120000, 0x120001) AM_DEVWRITE("oki", okim6295_w)
AM_RANGE(0x130000, 0x130001) AM_WRITENOP
AM_RANGE(0x1f0000, 0x1f1fff) AM_WRITE(SMH_BANK8)
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE(h6280_timer_w) AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE(h6280_irq_status_w) AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE(h6280_irq_status_w)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -355,11 +323,11 @@ static MACHINE_DRIVER_START( supbtime )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", M68000, 14000000) MDRV_CPU_ADD("maincpu", M68000, 14000000)
MDRV_CPU_PROGRAM_MAP(supbtime_readmem,supbtime_writemem) MDRV_CPU_PROGRAM_MAP(supbtime_map,0)
MDRV_CPU_VBLANK_INT("screen", irq6_line_hold) MDRV_CPU_VBLANK_INT("screen", irq6_line_hold)
MDRV_CPU_ADD("audiocpu", H6280, 32220000/8) /* Custom chip 45, audio section crystal is 32.220 MHz */ MDRV_CPU_ADD("audiocpu", H6280, 32220000/8) /* Custom chip 45, audio section crystal is 32.220 MHz */
MDRV_CPU_PROGRAM_MAP(sound_readmem,sound_writemem) MDRV_CPU_PROGRAM_MAP(sound_map,0)
/* video hardware */ /* video hardware */
MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK) MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
@ -395,11 +363,11 @@ static MACHINE_DRIVER_START( chinatwn )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", M68000, 14000000) MDRV_CPU_ADD("maincpu", M68000, 14000000)
MDRV_CPU_PROGRAM_MAP(chinatwn_readmem,chinatwn_writemem) MDRV_CPU_PROGRAM_MAP(chinatwn_map,0)
MDRV_CPU_VBLANK_INT("screen", irq6_line_hold) MDRV_CPU_VBLANK_INT("screen", irq6_line_hold)
MDRV_CPU_ADD("audiocpu", H6280, 32220000/8) /* Custom chip 45, audio section crystal is 32.220 MHz */ MDRV_CPU_ADD("audiocpu", H6280, 32220000/8) /* Custom chip 45, audio section crystal is 32.220 MHz */
MDRV_CPU_PROGRAM_MAP(sound_readmem,sound_writemem) MDRV_CPU_PROGRAM_MAP(sound_map,0)
/* video hardware */ /* video hardware */
MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK) MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)

56
src/mame/drivers/superchs.c
View File

@ -230,46 +230,26 @@ static WRITE32_HANDLER( superchs_stick_w )
MEMORY STRUCTURES MEMORY STRUCTURES
***********************************************************/ ***********************************************************/
static ADDRESS_MAP_START( superchs_readmem, ADDRESS_SPACE_PROGRAM, 32 ) static ADDRESS_MAP_START( superchs_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x000000, 0x0fffff) AM_READ(SMH_ROM) AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100000, 0x11ffff) AM_READ(SMH_RAM) /* main CPUA ram */ AM_RANGE(0x100000, 0x11ffff) AM_RAM AM_BASE(&superchs_ram)
AM_RANGE(0x140000, 0x141fff) AM_READ(SMH_RAM) /* Sprite ram */ AM_RANGE(0x140000, 0x141fff) AM_RAM AM_BASE(&spriteram32) AM_SIZE(&spriteram_size)
AM_RANGE(0x180000, 0x18ffff) AM_READ(TC0480SCP_long_r) AM_RANGE(0x180000, 0x18ffff) AM_READWRITE(TC0480SCP_long_r, TC0480SCP_long_w)
AM_RANGE(0x1b0000, 0x1b002f) AM_READ(TC0480SCP_ctrl_long_r) AM_RANGE(0x1b0000, 0x1b002f) AM_READWRITE(TC0480SCP_ctrl_long_r, TC0480SCP_ctrl_long_w)
AM_RANGE(0x200000, 0x20ffff) AM_READ(SMH_RAM) /* Shared ram */ AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_BASE(&shared_ram)
AM_RANGE(0x280000, 0x287fff) AM_READ(SMH_RAM) /* Palette ram */
AM_RANGE(0x2c0000, 0x2c07ff) AM_READ(SMH_RAM) /* Sound shared ram */
AM_RANGE(0x300000, 0x300007) AM_READ(superchs_input_r)
AM_RANGE(0x340000, 0x340003) AM_READ(superchs_stick_r) /* stick coord read */
ADDRESS_MAP_END
static ADDRESS_MAP_START( superchs_writemem, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM)
AM_RANGE(0x100000, 0x11ffff) AM_WRITE(SMH_RAM) AM_BASE(&superchs_ram)
AM_RANGE(0x140000, 0x141fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram32) AM_SIZE(&spriteram_size)
AM_RANGE(0x180000, 0x18ffff) AM_WRITE(TC0480SCP_long_w)
AM_RANGE(0x1b0000, 0x1b002f) AM_WRITE(TC0480SCP_ctrl_long_w)
AM_RANGE(0x200000, 0x20ffff) AM_WRITE(SMH_RAM) AM_BASE(&shared_ram)
AM_RANGE(0x240000, 0x240003) AM_WRITE(cpua_ctrl_w) AM_RANGE(0x240000, 0x240003) AM_WRITE(cpua_ctrl_w)
AM_RANGE(0x280000, 0x287fff) AM_WRITE(superchs_palette_w) AM_BASE(&paletteram32) AM_RANGE(0x280000, 0x287fff) AM_RAM_WRITE(superchs_palette_w) AM_BASE(&paletteram32)
AM_RANGE(0x2c0000, 0x2c07ff) AM_WRITE(SMH_RAM) AM_BASE(&f3_shared_ram) AM_RANGE(0x2c0000, 0x2c07ff) AM_RAM AM_BASE(&f3_shared_ram)
AM_RANGE(0x300000, 0x300007) AM_WRITE(superchs_input_w) /* eerom etc. */ AM_RANGE(0x300000, 0x300007) AM_READWRITE(superchs_input_r, superchs_input_w) /* eerom etc. */
AM_RANGE(0x340000, 0x340003) AM_WRITE(superchs_stick_w) /* stick int request */ AM_RANGE(0x340000, 0x340003) AM_READWRITE(superchs_stick_r, superchs_stick_w) /* stick int request */
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( superchs_cpub_readmem, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( superchs_cpub_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x03ffff) AM_READ(SMH_ROM) AM_RANGE(0x000000, 0x03ffff) AM_ROM
AM_RANGE(0x200000, 0x20ffff) AM_READ(SMH_RAM) /* local ram */ AM_RANGE(0x200000, 0x20ffff) AM_RAM
AM_RANGE(0x800000, 0x80ffff) AM_READ(shared_ram_r)
AM_RANGE(0xa00000, 0xa001ff) AM_READ(SMH_RAM)
ADDRESS_MAP_END
static ADDRESS_MAP_START( superchs_cpub_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x03ffff) AM_WRITE(SMH_ROM)
AM_RANGE(0x200000, 0x20ffff) AM_WRITE(SMH_RAM)
AM_RANGE(0x600000, 0x60ffff) AM_WRITE(TC0480SCP_word_w) /* Only written upon errors */ AM_RANGE(0x600000, 0x60ffff) AM_WRITE(TC0480SCP_word_w) /* Only written upon errors */
AM_RANGE(0x800000, 0x80ffff) AM_WRITE(shared_ram_w) AM_RANGE(0x800000, 0x80ffff) AM_READWRITE(shared_ram_r, shared_ram_w)
AM_RANGE(0xa00000, 0xa001ff) AM_WRITE(SMH_RAM) /* Extra road control?? */ AM_RANGE(0xa00000, 0xa001ff) AM_RAM /* Extra road control?? */
ADDRESS_MAP_END ADDRESS_MAP_END
/***********************************************************/ /***********************************************************/
@ -416,13 +396,13 @@ static MACHINE_DRIVER_START( superchs )
/* basic machine hardware */ /* basic machine hardware */
MDRV_CPU_ADD("maincpu", M68EC020, 16000000) /* 16 MHz */ MDRV_CPU_ADD("maincpu", M68EC020, 16000000) /* 16 MHz */
MDRV_CPU_PROGRAM_MAP(superchs_readmem,superchs_writemem) MDRV_CPU_PROGRAM_MAP(superchs_map,0)
MDRV_CPU_VBLANK_INT("screen", irq2_line_hold)/* VBL */ MDRV_CPU_VBLANK_INT("screen", irq2_line_hold)/* VBL */
TAITO_F3_SOUND_SYSTEM_CPU(16000000) TAITO_F3_SOUND_SYSTEM_CPU(16000000)
MDRV_CPU_ADD("sub", M68000, 16000000) /* 16 MHz */ MDRV_CPU_ADD("sub", M68000, 16000000) /* 16 MHz */
MDRV_CPU_PROGRAM_MAP(superchs_cpub_readmem,superchs_cpub_writemem) MDRV_CPU_PROGRAM_MAP(superchs_cpub_map,0)
MDRV_CPU_VBLANK_INT("screen", irq4_line_hold)/* VBL */ MDRV_CPU_VBLANK_INT("screen", irq4_line_hold)/* VBL */
MDRV_QUANTUM_TIME(HZ(480)) /* CPU slices - Need to interleave Cpu's 1 & 3 */ MDRV_QUANTUM_TIME(HZ(480)) /* CPU slices - Need to interleave Cpu's 1 & 3 */

61
src/mame/drivers/suprnova.c
View File

@ -765,50 +765,30 @@ static WRITE32_HANDLER( skns_v3t_w )
btiles[offset*4+3] = (data & 0x000000ff) >> 0; btiles[offset*4+3] = (data & 0x000000ff) >> 0;
} }
static ADDRESS_MAP_START( skns_readmem, ADDRESS_SPACE_PROGRAM, 32 ) static ADDRESS_MAP_START( skns_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x00000000, 0x0007ffff) AM_READ(SMH_ROM) /* BIOS ROM */ AM_RANGE(0x00000000, 0x0007ffff) AM_ROM /* BIOS ROM */
AM_RANGE(0x00400000, 0x0040000f) AM_WRITE(skns_io_w) /* I/O Write */
AM_RANGE(0x00400000, 0x00400003) AM_READ_PORT("400000") AM_RANGE(0x00400000, 0x00400003) AM_READ_PORT("400000")
AM_RANGE(0x00400004, 0x00400007) AM_READ_PORT("400004") AM_RANGE(0x00400004, 0x00400007) AM_READ_PORT("400004")
AM_RANGE(0x00400008, 0x0040000b) AM_READ(SMH_RAM)
/* In between is write only */ /* In between is write only */
AM_RANGE(0x0040000c, 0x0040000f) AM_READ_PORT("40000c") AM_RANGE(0x0040000c, 0x0040000f) AM_READ_PORT("40000c")
AM_RANGE(0x00800000, 0x00801fff) AM_READ(SMH_RAM) /* 'backup' RAM */ AM_RANGE(0x00800000, 0x00801fff) AM_RAM AM_BASE(&generic_nvram32) AM_SIZE(&generic_nvram_size) /* 'backup' RAM */
// AM_RANGE(0x00c00000, 0x00c00003) AM_READ(skns_ymz280_r) /* ymz280 (sound) */ AM_RANGE(0x00c00000, 0x00c00003) AM_DEVREADWRITE8("ymz", ymz280b_r, ymz280b_w, 0xffff0000) /* ymz280_w (sound) */
AM_RANGE(0x01000000, 0x0100000f) AM_READ(skns_msm6242_r) AM_RANGE(0x01000000, 0x0100000f) AM_READWRITE(skns_msm6242_r, skns_msm6242_w)
AM_RANGE(0x02000000, 0x02003fff) AM_READ(SMH_RAM) /* 'spc' RAM */
AM_RANGE(0x02100000, 0x0210003f) AM_READ(SMH_RAM) /* 'spc' */
AM_RANGE(0x02400000, 0x0240007f) AM_READ(SMH_RAM) /* 'v3' */
AM_RANGE(0x02500000, 0x02507fff) AM_READ(SMH_RAM) /* 'v3tbl' RAM */
AM_RANGE(0x02600000, 0x02607fff) AM_READ(SMH_RAM) /* 'v3slc' RAM */
AM_RANGE(0x02a00000, 0x02a0001f) AM_READ(SMH_RAM) /* skns_pal_regs */
AM_RANGE(0x02a40000, 0x02a5ffff) AM_READ(SMH_RAM) /* 'palette' RAM */
AM_RANGE(0x02f00000, 0x02f000ff) AM_READ(skns_hit_r) /* hit */
AM_RANGE(0x04000000, 0x041fffff) AM_READ(SMH_BANK1) /* GAME ROM */
AM_RANGE(0x04800000, 0x0483ffff) AM_READ(SMH_RAM) /* 'v3t' RAM */
AM_RANGE(0x06000000, 0x060fffff) AM_READ(SMH_RAM) /* 'main' RAM */
AM_RANGE(0xc0000000, 0xc0000fff) AM_READ(SMH_RAM) /* 'cache' RAM */
ADDRESS_MAP_END
static ADDRESS_MAP_START( skns_writemem, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x00000000, 0x0007ffff) AM_WRITE(SMH_ROM) /* BIOS ROM */
AM_RANGE(0x00400000, 0x0040000f) AM_WRITE(skns_io_w) /* I/O Write */
AM_RANGE(0x00800000, 0x00801fff) AM_WRITE(SMH_RAM) AM_BASE(&generic_nvram32) AM_SIZE(&generic_nvram_size) /* 'backup' RAM */
AM_RANGE(0x00c00000, 0x00c00003) AM_DEVWRITE8("ymz", ymz280b_w, 0xffff0000) /* ymz280_w (sound) */
AM_RANGE(0x01000000, 0x0100000f) AM_WRITE(skns_msm6242_w)
AM_RANGE(0x01800000, 0x01800003) AM_WRITE(skns_hit2_w) AM_RANGE(0x01800000, 0x01800003) AM_WRITE(skns_hit2_w)
AM_RANGE(0x02000000, 0x02003fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram32) AM_SIZE(&spriteram_size) /* sprite ram */ AM_RANGE(0x02000000, 0x02003fff) AM_RAM AM_BASE(&spriteram32) AM_SIZE(&spriteram_size) /* sprite ram */
AM_RANGE(0x02100000, 0x0210003f) AM_WRITE(SMH_RAM) AM_BASE(&skns_spc_regs) /* sprite registers */ AM_RANGE(0x02100000, 0x0210003f) AM_RAM AM_BASE(&skns_spc_regs) /* sprite registers */
AM_RANGE(0x02400000, 0x0240007f) AM_WRITE(skns_v3_regs_w) AM_BASE(&skns_v3_regs) /* tilemap registers */ AM_RANGE(0x02400000, 0x0240007f) AM_RAM_WRITE(skns_v3_regs_w) AM_BASE(&skns_v3_regs) /* tilemap registers */
AM_RANGE(0x02500000, 0x02503fff) AM_WRITE(skns_tilemapA_w) AM_BASE(&skns_tilemapA_ram) /* tilemap A */ AM_RANGE(0x02500000, 0x02503fff) AM_RAM_WRITE(skns_tilemapA_w) AM_BASE(&skns_tilemapA_ram) /* tilemap A */
AM_RANGE(0x02504000, 0x02507fff) AM_WRITE(skns_tilemapB_w) AM_BASE(&skns_tilemapB_ram) /* tilemap B */ AM_RANGE(0x02504000, 0x02507fff) AM_RAM_WRITE(skns_tilemapB_w) AM_BASE(&skns_tilemapB_ram) /* tilemap B */
AM_RANGE(0x02600000, 0x02607fff) AM_WRITE(SMH_RAM) AM_BASE(&skns_v3slc_ram) /* tilemap linescroll */ AM_RANGE(0x02600000, 0x02607fff) AM_RAM_WRITE(SMH_RAM) AM_BASE(&skns_v3slc_ram) /* tilemap linescroll */
AM_RANGE(0x02a00000, 0x02a0001f) AM_WRITE(skns_pal_regs_w) AM_BASE(&skns_pal_regs) AM_RANGE(0x02a00000, 0x02a0001f) AM_RAM_WRITE(skns_pal_regs_w) AM_BASE(&skns_pal_regs)
AM_RANGE(0x02a40000, 0x02a5ffff) AM_WRITE(skns_palette_ram_w) AM_BASE(&skns_palette_ram) AM_RANGE(0x02a40000, 0x02a5ffff) AM_RAM_WRITE(skns_palette_ram_w) AM_BASE(&skns_palette_ram)
AM_RANGE(0x02f00000, 0x02f000ff) AM_WRITE(skns_hit_w) AM_RANGE(0x02f00000, 0x02f000ff) AM_READWRITE(skns_hit_r, skns_hit_w)
AM_RANGE(0x04000000, 0x041fffff) AM_WRITE(SMH_ROM) /* GAME ROM */ AM_RANGE(0x04000000, 0x041fffff) AM_ROMBANK(1) /* GAME ROM */
AM_RANGE(0x04800000, 0x0483ffff) AM_WRITE(skns_v3t_w) AM_BASE(&skns_v3t_ram) /* tilemap b ram based tiles */ AM_RANGE(0x04800000, 0x0483ffff) AM_RAM_WRITE(skns_v3t_w) AM_BASE(&skns_v3t_ram) /* tilemap b ram based tiles */
AM_RANGE(0x06000000, 0x060fffff) AM_WRITE(SMH_RAM) AM_BASE(&skns_main_ram) AM_RANGE(0x06000000, 0x060fffff) AM_RAM AM_BASE(&skns_main_ram)
AM_RANGE(0xc0000000, 0xc0000fff) AM_WRITE(SMH_RAM) AM_BASE(&skns_cache_ram) /* 'cache' RAM */ AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_BASE(&skns_cache_ram) /* 'cache' RAM */
ADDRESS_MAP_END ADDRESS_MAP_END
/***** GFX DECODE *****/ /***** GFX DECODE *****/
@ -856,7 +836,7 @@ static const ymz280b_interface ymz280b_intf =
static MACHINE_DRIVER_START(skns) static MACHINE_DRIVER_START(skns)
MDRV_CPU_ADD("maincpu", SH2,28638000) MDRV_CPU_ADD("maincpu", SH2,28638000)
MDRV_CPU_PROGRAM_MAP(skns_readmem,skns_writemem) MDRV_CPU_PROGRAM_MAP(skns_map,0)
MDRV_CPU_VBLANK_INT_HACK(skns_interrupt,2) MDRV_CPU_VBLANK_INT_HACK(skns_interrupt,2)
MDRV_MACHINE_RESET(skns) MDRV_MACHINE_RESET(skns)
@ -1675,4 +1655,3 @@ GAME( 1999, senknow , skns, skns, skns, senknow, ROT0, "Kaneko / Kou
GAME( 1999, teljan , skns, skns, skns_1p, teljan, ROT0, "Electro Design", "Tel Jan", GAME_IMPERFECT_GRAPHICS ) GAME( 1999, teljan , skns, skns, skns_1p, teljan, ROT0, "Electro Design", "Tel Jan", GAME_IMPERFECT_GRAPHICS )
GAME( 2000, gutsn, skns, skns, skns, gutsn, ROT0, "Kaneko / Kouyousha", "Guts'n (Japan)", GAME_IMPERFECT_GRAPHICS ) // quite fragile, started working of it's own accord in 0.69 :) GAME( 2000, gutsn, skns, skns, skns, gutsn, ROT0, "Kaneko / Kouyousha", "Guts'n (Japan)", GAME_IMPERFECT_GRAPHICS ) // quite fragile, started working of it's own accord in 0.69 :)
GAME( 2002, galpans3, skns, skns, galpanis, galpans3, ROT0, "Kaneko", "Gals Panic S3 (Japan)", GAME_IMPERFECT_GRAPHICS ) GAME( 2002, galpans3, skns, skns, galpanis, galpans3, ROT0, "Kaneko", "Gals Panic S3 (Japan)", GAME_IMPERFECT_GRAPHICS )

59
src/mame/drivers/suprslam.c
View File

@ -135,15 +135,19 @@ static WRITE8_HANDLER( suprslam_sh_bankswitch_w )
/*** MEMORY MAPS *************************************************************/ /*** MEMORY MAPS *************************************************************/
static ADDRESS_MAP_START( suprslam_readmem, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( suprslam_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_READ(SMH_ROM) AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0xfb0000, 0xfb1fff) AM_READ(SMH_RAM) AM_RANGE(0xfb0000, 0xfb1fff) AM_RAM AM_BASE(&suprslam_spriteram)
AM_RANGE(0xfc0000, 0xfcffff) AM_READ(SMH_RAM) AM_RANGE(0xfc0000, 0xfcffff) AM_RAM AM_BASE(&suprslam_sp_videoram)
AM_RANGE(0xfd0000, 0xfdffff) AM_READ(SMH_RAM) AM_RANGE(0xfd0000, 0xfdffff) AM_RAM
AM_RANGE(0xfe0000, 0xfe0fff) AM_READ(SMH_RAM) AM_RANGE(0xfe0000, 0xfe0fff) AM_RAM_WRITE(suprslam_screen_videoram_w) AM_BASE(&suprslam_screen_videoram)
AM_RANGE(0xff0000, 0xff1fff) AM_READ(SMH_RAM) AM_RANGE(0xff0000, 0xff1fff) AM_RAM_WRITE(suprslam_bg_videoram_w) AM_BASE(&suprslam_bg_videoram)
AM_RANGE(0xff8000, 0xff8fff) AM_READ(SMH_RAM) // AM_RANGE(0xff2000, 0xff203f) AM_RAM /* ?? */
AM_RANGE(0xffa000, 0xffafff) AM_READ(SMH_RAM) AM_RANGE(0xff8000, 0xff8fff) AM_RAM AM_BASE(&K053936_0_linectrl)
AM_RANGE(0xff9000, 0xff9001) AM_WRITE(sound_command_w)
AM_RANGE(0xffa000, 0xffafff) AM_RAM_WRITE(paletteram16_xGGGGGBBBBBRRRRR_word_w) AM_BASE(&paletteram16)
AM_RANGE(0xffd000, 0xffd01f) AM_WRITE(SMH_RAM) AM_BASE(&K053936_0_ctrl)
AM_RANGE(0xffe000, 0xffe001) AM_WRITE(suprslam_bank_w)
AM_RANGE(0xfff000, 0xfff001) AM_READ_PORT("P1") AM_RANGE(0xfff000, 0xfff001) AM_READ_PORT("P1")
AM_RANGE(0xfff002, 0xfff003) AM_READ_PORT("P2") AM_RANGE(0xfff002, 0xfff003) AM_READ_PORT("P2")
AM_RANGE(0xfff004, 0xfff005) AM_READ_PORT("SYSTEM") AM_RANGE(0xfff004, 0xfff005) AM_READ_PORT("SYSTEM")
@ -151,34 +155,13 @@ static ADDRESS_MAP_START( suprslam_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0xfff008, 0xfff009) AM_READ_PORT("DSW2") AM_RANGE(0xfff008, 0xfff009) AM_READ_PORT("DSW2")
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( suprslam_writemem, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( sound_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM) AM_RANGE(0x0000, 0x77ff) AM_ROM
AM_RANGE(0xfb0000, 0xfb1fff) AM_WRITE(SMH_RAM) AM_BASE(&suprslam_spriteram) AM_RANGE(0x7800, 0x7fff) AM_RAM
AM_RANGE(0xfc0000, 0xfcffff) AM_WRITE(SMH_RAM) AM_BASE(&suprslam_sp_videoram) AM_RANGE(0x8000, 0xffff) AM_ROMBANK(1)
AM_RANGE(0xfd0000, 0xfdffff) AM_WRITE(SMH_RAM)
AM_RANGE(0xfe0000, 0xfe0fff) AM_WRITE(suprslam_screen_videoram_w) AM_BASE(&suprslam_screen_videoram)
AM_RANGE(0xff0000, 0xff1fff) AM_WRITE(suprslam_bg_videoram_w) AM_BASE(&suprslam_bg_videoram)
// AM_RANGE(0xff2000, 0xff203f) AM_WRITE(SMH_RAM) /* ?? */
AM_RANGE(0xff8000, 0xff8fff) AM_WRITE(SMH_RAM) AM_BASE(&K053936_0_linectrl)
AM_RANGE(0xff9000, 0xff9001) AM_WRITE(sound_command_w)
AM_RANGE(0xffa000, 0xffafff) AM_WRITE(paletteram16_xGGGGGBBBBBRRRRR_word_w) AM_BASE(&paletteram16)
AM_RANGE(0xffd000, 0xffd01f) AM_WRITE(SMH_RAM) AM_BASE(&K053936_0_ctrl)
AM_RANGE(0xffe000, 0xffe001) AM_WRITE(suprslam_bank_w)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_readmem, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( sound_io_map, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x0000, 0x77ff) AM_READ(SMH_ROM)
AM_RANGE(0x7800, 0x7fff) AM_READ(SMH_RAM)
AM_RANGE(0x8000, 0xffff) AM_READ(SMH_BANK1)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x77ff) AM_WRITE(SMH_ROM)
AM_RANGE(0x7800, 0x7fff) AM_WRITE(SMH_RAM)
AM_RANGE(0x8000, 0xffff) AM_WRITE(SMH_ROM)
ADDRESS_MAP_END
static ADDRESS_MAP_START( suprslam_sound_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff) ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x00) AM_WRITE(suprslam_sh_bankswitch_w) AM_RANGE(0x00, 0x00) AM_WRITE(suprslam_sh_bankswitch_w)
AM_RANGE(0x04, 0x04) AM_READWRITE(soundlatch_r, pending_command_clear_w) AM_RANGE(0x04, 0x04) AM_READWRITE(soundlatch_r, pending_command_clear_w)
@ -316,12 +299,12 @@ static const ym2610_interface ym2610_config =
static MACHINE_DRIVER_START( suprslam ) static MACHINE_DRIVER_START( suprslam )
MDRV_CPU_ADD("maincpu", M68000, 16000000) MDRV_CPU_ADD("maincpu", M68000, 16000000)
MDRV_CPU_PROGRAM_MAP(suprslam_readmem,suprslam_writemem) MDRV_CPU_PROGRAM_MAP(suprslam_map,0)
MDRV_CPU_VBLANK_INT("screen", irq1_line_hold) MDRV_CPU_VBLANK_INT("screen", irq1_line_hold)
MDRV_CPU_ADD("audiocpu", Z80,8000000/2) /* 4 MHz ??? */ MDRV_CPU_ADD("audiocpu", Z80,8000000/2) /* 4 MHz ??? */
MDRV_CPU_PROGRAM_MAP(sound_readmem,sound_writemem) MDRV_CPU_PROGRAM_MAP(sound_map,0)
MDRV_CPU_IO_MAP(suprslam_sound_io_map,0) MDRV_CPU_IO_MAP(sound_io_map,0)
MDRV_GFXDECODE(suprslam) MDRV_GFXDECODE(suprslam)