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https://github.com/holub/mame
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atvtrack.cpp checkpoint (nw)
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MetalliC
parent
ffd5f6cc9c
commit
fd0f3b0657
@ -80,11 +80,12 @@ then it becomes (I suppose half) empty - SH4 IRL5 IRQ generated
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"control registers" (Smashing Drive)
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0 - read - various statuses, returning -1 is OK
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write - enable slave CPU, gpu, etc most of bits is unclear
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4 - r/w - communication port (for cabinet linking), returning 0 is OK
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also there some bits on SH4 PDTRA port, I'll hook it later by myself
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4 - w - RS422/485 communication port (for cabinet linking)
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about clocks - SH4s is clocked at 33000000*6
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but unlike to DC/AW/Naomi SH4 'peripheral clock' (at which works TMU timers and other internal stuff) is 1/6 from CPU clock, not 1/4
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SH4 XTAL is 33MHz, SH4 MD0-2 pins is 001 or 011 (CPU core clk = XTAL*6, preipheral clk = XTAL, bus clk is XTAL or XTAL*2)
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TODO:
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currently ATV Track dies during texture data upload to GPU RAM, most likely due to some SH4 core bugs
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*/
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@ -105,14 +106,14 @@ public:
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DECLARE_READ64_MEMBER(control_r);
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DECLARE_WRITE64_MEMBER(control_w);
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DECLARE_READ64_MEMBER(area2_r);
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DECLARE_WRITE64_MEMBER(area2_w);
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DECLARE_READ64_MEMBER(area3_r);
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DECLARE_WRITE64_MEMBER(area3_w);
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DECLARE_READ64_MEMBER(area4_r);
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DECLARE_WRITE64_MEMBER(area4_w);
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DECLARE_READ64_MEMBER(nand_data_r);
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DECLARE_WRITE64_MEMBER(nand_data_w);
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DECLARE_WRITE64_MEMBER(nand_cmd_w);
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DECLARE_WRITE64_MEMBER(nand_addr_w);
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DECLARE_READ64_MEMBER(ioport_r);
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DECLARE_WRITE64_MEMBER(ioport_w);
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DECLARE_READ32_MEMBER(gpu_r);
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DECLARE_WRITE32_MEMBER(gpu_w);
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virtual void machine_start() override;
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virtual void machine_reset() override;
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virtual void video_start() override;
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@ -126,6 +127,11 @@ public:
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required_device<sh4_device> m_maincpu;
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required_device<sh4_device> m_subcpu;
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u16 gpu_irq_pending;
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u16 gpu_irq_mask;
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void gpu_irq_test();
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void gpu_irq_set(int);
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protected:
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bool m_slaverun;
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};
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@ -198,12 +204,12 @@ WRITE64_MEMBER(atvtrack_state::control_w)
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else
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m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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}
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logerror("Write %08x at %08x ",dat, 0x20000+addr*4+0);
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logbinary(dat);
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logerror("\n");
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// logerror("Write %08x at %08x ",dat, 0x20000+addr*4+0);
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// logbinary(dat);
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// logerror("\n");
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}
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READ64_MEMBER(atvtrack_state::area2_r)
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READ64_MEMBER(atvtrack_state::nand_data_r)
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{
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uint32_t addr, dat;
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int c;
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@ -227,32 +233,12 @@ READ64_MEMBER(atvtrack_state::area2_r)
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return 0;
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}
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WRITE64_MEMBER(atvtrack_state::area2_w)
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WRITE64_MEMBER(atvtrack_state::nand_data_w)
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{
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// uint32_t addr, dat;
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// addr = 0;
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// dat = decode64_32(offset, data, mem_mask, addr);
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// if (addr == 0)
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// ;
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// else
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// ;
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// not implemented
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}
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READ64_MEMBER(atvtrack_state::area3_r)
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{
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// uint32_t addr, dat;
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// addr = 0;
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// dat = decode64_32(offset, 0, mem_mask, addr);
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// if (addr == 0)
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// ;
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// else
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// ;
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return 0;
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}
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WRITE64_MEMBER(atvtrack_state::area3_w)
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WRITE64_MEMBER(atvtrack_state::nand_cmd_w)
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{
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uint32_t addr; //, dat;
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int c;
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@ -286,20 +272,7 @@ WRITE64_MEMBER(atvtrack_state::area3_w)
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}
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}
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READ64_MEMBER(atvtrack_state::area4_r)
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{
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// uint32_t addr, dat;
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// addr = 0;
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// dat = decode64_32(offset, 0, mem_mask, addr);
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// if (addr == 0)
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// ;
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// else
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// ;
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return 0;
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}
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WRITE64_MEMBER(atvtrack_state::area4_w)
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WRITE64_MEMBER(atvtrack_state::nand_addr_w)
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{
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uint32_t addr; //, dat;
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int c;
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@ -323,18 +296,75 @@ WRITE64_MEMBER(atvtrack_state::area4_w)
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}
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}
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void atvtrack_state::gpu_irq_test()
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{
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if (gpu_irq_pending & ~gpu_irq_mask)
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m_subcpu->sh4_set_irln_input(14); // there hacky looking ASSERT+CLEAR pulse in SH4 core ?
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else
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m_subcpu->set_input_line(SH4_IRLn, CLEAR_LINE);
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}
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void atvtrack_state::gpu_irq_set(int bit)
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{
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gpu_irq_pending |= 1 << bit;
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gpu_irq_test();
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}
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READ32_MEMBER(atvtrack_state::gpu_r)
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{
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switch (offset)
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{
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case 0x70/4:
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return gpu_irq_pending;
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case 0x74/4:
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return gpu_irq_mask;
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default:
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logerror("GPU: unhandled reg read @ %04X\n", offset * 4);
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return 0;
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}
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}
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WRITE32_MEMBER(atvtrack_state::gpu_w)
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{
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switch (offset)
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{
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case 0x00/4:
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// not really required, game code will go even if GPU CPU shows no sings of live
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if (data) // internal CPU start ?
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m_subcpu->space(AS_PROGRAM).write_byte(0x18001350, 1); // simulate GPUs internal CPU reply to skip busy loop
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break;
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case 0x70/4:
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gpu_irq_pending &= ~data;
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gpu_irq_test();
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break;
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case 0x74/4:
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gpu_irq_mask = data;
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gpu_irq_test();
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break;
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case 0xb0/4:
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if (data == 0x0001)
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{
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// GPU render happens here
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gpu_irq_set(7);
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}
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// not really required, game code will go even if GPU CPU shows no sings of live
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if (data == 0x8001)
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m_subcpu->space(AS_PROGRAM).write_byte(0x18814804, 1); // simulate GPUs internal CPU reply to skip busy loop
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break;
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default:
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logerror("GPU: unhandled reg write @ %04X data %08X\n", offset * 4, data);
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break;
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}
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}
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READ64_MEMBER(atvtrack_state::ioport_r)
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{
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if (offset == SH4_IOPORT_16/8) {
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// much simplified way
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if (strcmp(space.device().tag(), ":maincpu") == 0)
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#ifndef SPECIALMODE
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return -1; // normal
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return -1; // normal
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#else
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return 0; // testing
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return 0; // testing
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#endif
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else
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return 0; // unknown
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}
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return 0;
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}
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@ -352,9 +382,9 @@ WRITE64_MEMBER(atvtrack_state::ioport_w)
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if (data & 0x0100)
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m_slaverun = true;
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}
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logerror("SH4 16bit i/o port write ");
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logbinary((uint32_t)data,15,0);
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logerror("\n");
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// logerror("SH4 16bit i/o port write ");
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// logbinary((uint32_t)data,15,0);
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// logerror("\n");
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}
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#ifdef SPECIALMODE
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if (offset == SH4_IOPORT_DMA/8) {
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@ -405,7 +435,7 @@ void get_altera10ke_eab(u8* dst, u8 *pof, int eab)
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void atvtrack_state::machine_start()
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{
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m_nandaddressstep = 0;
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m_nandregion = memregion("maincpu");
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m_nandregion = memregion("nand");
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}
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void atvtrack_state::machine_reset()
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@ -433,6 +463,8 @@ void atvtrack_state::machine_reset()
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}
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m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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gpu_irq_pending = 0;
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gpu_irq_mask = 0xFFFF;
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}
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@ -444,6 +476,8 @@ void smashdrv_state::machine_reset()
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{
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m_slaverun = false;
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m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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gpu_irq_pending = 0;
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gpu_irq_mask = 0xFFFF;
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}
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// ATV Track
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@ -452,9 +486,9 @@ static ADDRESS_MAP_START( atvtrack_main_map, AS_PROGRAM, 64, atvtrack_state )
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AM_RANGE(0x00000000, 0x000003ff) AM_RAM AM_SHARE("sharedmem")
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AM_RANGE(0x00020000, 0x00020007) AM_READWRITE(control_r, control_w) // control registers
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// AM_RANGE(0x00020040, 0x0002007f) // audio DAC buffer
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AM_RANGE(0x14000000, 0x14000007) AM_READWRITE(area2_r, area2_w) // data
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AM_RANGE(0x14100000, 0x14100007) AM_READWRITE(area3_r, area3_w) // command
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AM_RANGE(0x14200000, 0x14200007) AM_READWRITE(area4_r, area4_w) // address
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AM_RANGE(0x14000000, 0x14000007) AM_READWRITE(nand_data_r, nand_data_w)
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AM_RANGE(0x14100000, 0x14100007) AM_WRITE(nand_cmd_w)
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AM_RANGE(0x14200000, 0x14200007) AM_WRITE(nand_addr_w)
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AM_RANGE(0x0c000000, 0x0c7fffff) AM_RAM
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ADDRESS_MAP_END
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@ -484,29 +518,27 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( atvtrack_sub_map, AS_PROGRAM, 64, atvtrack_state )
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AM_RANGE(0x00000000, 0x000003ff) AM_RAM AM_SHARE("sharedmem")
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AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM
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// 0x14000000 - 0x1400xxxx GPU registers
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AM_RANGE(0x14000000, 0x14003fff) AM_READWRITE32(gpu_r, gpu_w, 0xffffffffffffffffU)
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// 0x14004xxx GPU PCI CONFIG registers
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AM_RANGE(0x18000000, 0x19ffffff) AM_RAM
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// 0x18000000 - 0x19FFFFFF GPU RAM (32MB)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( atvtrack_sub_port, AS_IO, 64, atvtrack_state )
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/*AM_RANGE(0x00, 0x1f) AM_READWRITE(ioport_r, ioport_w) */
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ADDRESS_MAP_END
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static INPUT_PORTS_START( atvtrack )
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INPUT_PORTS_END
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// ?
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#define ATV_CPU_CLOCK 200000000
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// ?
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#define ATV_CPU_CLOCK XTAL_33MHz*6
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static MACHINE_CONFIG_START( atvtrack, atvtrack_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", SH4LE, ATV_CPU_CLOCK)
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MCFG_SH4_MD0(1)
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MCFG_SH4_MD1(0)
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MCFG_SH4_MD2(1)
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MCFG_SH4_MD1(1)
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MCFG_SH4_MD2(0)
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MCFG_SH4_MD3(0)
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MCFG_SH4_MD4(0)
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MCFG_SH4_MD5(1)
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@ -519,8 +551,8 @@ static MACHINE_CONFIG_START( atvtrack, atvtrack_state )
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MCFG_CPU_ADD("subcpu", SH4LE, ATV_CPU_CLOCK)
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MCFG_SH4_MD0(1)
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MCFG_SH4_MD1(0)
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MCFG_SH4_MD2(1)
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MCFG_SH4_MD1(1)
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MCFG_SH4_MD2(0)
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MCFG_SH4_MD3(0)
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MCFG_SH4_MD4(0)
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MCFG_SH4_MD5(1)
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@ -551,7 +583,7 @@ MACHINE_CONFIG_END
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ROM_START( atvtrack )
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ROM_REGION( 0x4200000, "maincpu", ROMREGION_ERASEFF) // NAND roms, contain additional data hence the sizes
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ROM_REGION( 0x4200000, "nand", ROMREGION_ERASEFF) // NAND roms, contain additional data hence the sizes
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ROM_LOAD32_BYTE("15.bin", 0x0000000, 0x1080000, CRC(84eaede7) SHA1(6e6230165c3bb35e49c660dfd0d07c132ed89e6a) )
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ROM_LOAD32_BYTE("20.bin", 0x0000001, 0x1080000, CRC(649dc331) SHA1(0cac2d0c15dd564c7fdebdf4365422958f453d63) )
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ROM_LOAD32_BYTE("14.bin", 0x0000002, 0x1080000, CRC(67983453) SHA1(05389a0ffc1a1bae9bac16a53a97d78b6eccc626) )
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@ -562,7 +594,7 @@ ROM_START( atvtrack )
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ROM_END
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ROM_START( atvtracka )
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ROM_REGION( 0x4200000, "maincpu", ROMREGION_ERASEFF) // NAND roms, contain additional data hence the sizes
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ROM_REGION( 0x4200000, "nand", ROMREGION_ERASEFF) // NAND roms, contain additional data hence the sizes
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ROM_LOAD32_BYTE("k9f2808u0b.ic15", 0x0000000, 0x1080000, CRC(10730001) SHA1(48c685a6ff7135abd074dc7fb7d10834c44da58f) )
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ROM_LOAD32_BYTE("k9f2808u0b.ic20", 0x0000001, 0x1080000, CRC(b0c34433) SHA1(852c79bb3d7082cd2c056140071ae7d71679ec1d) )
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ROM_LOAD32_BYTE("k9f2808u0b.ic14", 0x0000002, 0x1080000, CRC(02a12085) SHA1(acb112c9c7b29d92610465fb92268ce787ca06f4) )
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