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(nw) more cleanups

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This commit is contained in:
Robbbert 2017-09-22 00:11:02 +10:00
parent ce256c6444
commit fd10ecb1fd
8 changed files with 78 additions and 135 deletions
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21
src/mame/drivers/ampro.cpp
View File

@ -46,11 +46,9 @@ public:
DECLARE_DRIVER_INIT(ampro);
DECLARE_MACHINE_RESET(ampro);
TIMER_DEVICE_CALLBACK_MEMBER(ctc_tick);
DECLARE_WRITE_LINE_MEMBER(ctc_z0_w);
DECLARE_WRITE8_MEMBER(port00_w);
DECLARE_READ8_MEMBER(io_r);
DECLARE_WRITE8_MEMBER(io_w);
DECLARE_WRITE_LINE_MEMBER(clock_w);
private:
required_device<cpu_device> m_maincpu;
@ -121,19 +119,6 @@ static const z80_daisy_config daisy_chain_intf[] =
{ nullptr }
};
// Baud rate generator. All inputs are 2MHz.
WRITE_LINE_MEMBER( ampro_state::clock_w )
{
m_ctc->trg0(state);
m_ctc->trg1(state);
}
WRITE_LINE_MEMBER( ampro_state::ctc_z0_w )
{
m_dart->rxca_w(state);
m_dart->txca_w(state);
}
static SLOT_INTERFACE_START( ampro_floppies )
SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
SLOT_INTERFACE_END
@ -166,12 +151,14 @@ static MACHINE_CONFIG_START( ampro )
MCFG_MACHINE_RESET_OVERRIDE(ampro_state, ampro)
MCFG_DEVICE_ADD("ctc_clock", CLOCK, XTAL_16MHz / 8) // 2MHz
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(ampro_state, clock_w))
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("ctc", z80ctc_device, trg0))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("ctc", z80ctc_device, trg1))
/* Devices */
MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_16MHz / 4)
MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_Z80CTC_ZC0_CB(WRITELINE(ampro_state, ctc_z0_w)) // Z80DART Ch A, SIO Ch A
MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("dart", z80dart_device, txca_w)) // Z80DART Ch A, SIO Ch A
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart", z80dart_device, rxca_w))
MCFG_Z80CTC_ZC1_CB(DEVWRITELINE("dart", z80dart_device, rxtxcb_w)) // SIO Ch B
MCFG_Z80DART_ADD("dart", XTAL_16MHz / 4, 0, 0, 0, 0 )

38
src/mame/drivers/dmax8000.cpp
View File

@ -42,13 +42,9 @@ public:
dmax8000_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_dart1(*this, "dart1")
, m_dart2(*this, "dart2")
, m_ctc (*this, "ctc")
, m_fdc(*this, "fdc")
, m_floppy0(*this, "fdc:0")
{
}
{ }
DECLARE_DRIVER_INIT(dmax8000);
DECLARE_MACHINE_RESET(dmax8000);
@ -56,15 +52,10 @@ public:
DECLARE_WRITE8_MEMBER(port0d_w);
DECLARE_WRITE8_MEMBER(port14_w);
DECLARE_WRITE8_MEMBER(port40_w);
DECLARE_WRITE_LINE_MEMBER(ctc_z0_w);
DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
DECLARE_WRITE_LINE_MEMBER(clock_w);
private:
required_device<cpu_device> m_maincpu;
required_device<z80dart_device> m_dart1;
required_device<z80dart_device> m_dart2;
required_device<z80ctc_device> m_ctc;
required_device<fd1793_device> m_fdc;
required_device<floppy_connector> m_floppy0;
};
@ -147,26 +138,11 @@ DRIVER_INIT_MEMBER( dmax8000_state, dmax8000 )
membank("bankw0")->configure_entry(0, &main[0x0000]);
}
// Baud rate generator. All inputs are 2MHz.
WRITE_LINE_MEMBER( dmax8000_state::clock_w )
{
m_ctc->trg0(state);
m_ctc->trg1(state);
m_ctc->trg2(state);
}
WRITE_LINE_MEMBER( dmax8000_state::ctc_z0_w )
{
m_dart1->rxca_w(state);
m_dart1->txca_w(state);
m_dart2->rxca_w(state);
m_dart2->txca_w(state);
}
static SLOT_INTERFACE_START( floppies )
SLOT_INTERFACE( "8dsdd", FLOPPY_8_DSDD )
SLOT_INTERFACE_END
static MACHINE_CONFIG_START( dmax8000 )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", Z80, XTAL_4MHz ) // no idea what crystal is used, but 4MHz clock is confirmed
@ -175,10 +151,15 @@ static MACHINE_CONFIG_START( dmax8000 )
MCFG_MACHINE_RESET_OVERRIDE(dmax8000_state, dmax8000)
MCFG_DEVICE_ADD("ctc_clock", CLOCK, XTAL_4MHz / 2) // 2MHz
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(dmax8000_state, clock_w))
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("ctc", z80ctc_device, trg0))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("ctc", z80ctc_device, trg1))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("ctc", z80ctc_device, trg2))
MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_4MHz)
MCFG_Z80CTC_ZC0_CB(WRITELINE(dmax8000_state, ctc_z0_w))
MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("dart1", z80dart_device, rxca_w))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart1", z80dart_device, txca_w))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart2", z80dart_device, rxca_w))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart2", z80dart_device, txca_w))
MCFG_Z80CTC_ZC1_CB(DEVWRITELINE("dart2", z80dart_device, rxtxcb_w))
MCFG_Z80CTC_ZC2_CB(DEVWRITELINE("dart1", z80dart_device, rxtxcb_w))
@ -186,6 +167,7 @@ static MACHINE_CONFIG_START( dmax8000 )
MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232", rs232_port_device, write_txd))
MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232", rs232_port_device, write_rts))
MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("dart1", z80dart_device, rxa_w))
MCFG_RS232_DCD_HANDLER(DEVWRITELINE("dart1", z80dart_device, dcda_w))

27
src/mame/drivers/konin.cpp
View File

@ -54,15 +54,11 @@ public:
konin_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_uart(*this, "uart")
{ }
DECLARE_WRITE_LINE_MEMBER(clock_w);
private:
virtual void machine_reset() override;
required_device<cpu_device> m_maincpu;
required_device<i8251_device> m_uart;
};
static ADDRESS_MAP_START( konin_mem, AS_PROGRAM, 8, konin_state )
@ -82,32 +78,21 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( konin )
INPUT_PORTS_END
static DEVICE_INPUT_DEFAULTS_START( konin )
DEVICE_INPUT_DEFAULTS( "RS232_TXBAUD", 0xff, RS232_BAUD_9600 )
DEVICE_INPUT_DEFAULTS( "RS232_RXBAUD", 0xff, RS232_BAUD_9600 )
DEVICE_INPUT_DEFAULTS( "RS232_STARTBITS", 0xff, RS232_STARTBITS_1 )
DEVICE_INPUT_DEFAULTS( "RS232_DATABITS", 0xff, RS232_DATABITS_8 )
DEVICE_INPUT_DEFAULTS( "RS232_PARITY", 0xff, RS232_PARITY_NONE )
DEVICE_INPUT_DEFAULTS( "RS232_STOPBITS", 0xff, RS232_STOPBITS_2 )
DEVICE_INPUT_DEFAULTS_END
void konin_state::machine_reset()
{
}
WRITE_LINE_MEMBER( konin_state::clock_w )
{
m_uart->write_txc(state);
m_uart->write_rxc(state);
}
static MACHINE_CONFIG_START( konin )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu",Z80, XTAL_4MHz)
MCFG_CPU_PROGRAM_MAP(konin_mem)
MCFG_CPU_IO_MAP(konin_io)
MCFG_DEVICE_ADD("uart_clock", CLOCK, 153600)
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("uart", i8251_device, write_txc))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("uart", i8251_device, write_rxc))
MCFG_DEVICE_ADD("uart", I8251, 0)
MCFG_I8251_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
MCFG_I8251_DTR_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
@ -117,10 +102,6 @@ static MACHINE_CONFIG_START( konin )
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart", i8251_device, write_rxd))
MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart", i8251_device, write_dsr))
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart", i8251_device, write_cts))
MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("terminal", konin )
MCFG_DEVICE_ADD("uart_clock", CLOCK, 153600)
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(konin_state, clock_w))
MACHINE_CONFIG_END
/* ROM definition */

59
src/mame/drivers/mx2178.cpp
View File

@ -16,6 +16,9 @@
- Need schematic / tech manual
- Gets stuck waiting for E011 to become zero somehow. If you skip that, a status line appears.
- Doesn't seem to be any dips, looks like all settings and modes are controlled by keystrokes.
- 8X305 is a 16-bit Microcontroller which should have an external ROM. It would communicate with
the Z80 via a common 8-bit I/O bus. No idea what it is used for here, but in another system it
acts as the floppy disk controller.
***************************************************************************************************/
@ -24,7 +27,6 @@
#include "cpu/z80/z80.h"
#include "machine/6850acia.h"
#include "machine/clock.h"
#include "machine/keyboard.h"
#include "video/mc6845.h"
#include "screen.h"
@ -37,23 +39,17 @@ public:
, m_palette(*this, "palette")
, m_p_videoram(*this, "videoram")
, m_maincpu(*this, "maincpu")
, m_acia(*this, "acia")
, m_p_chargen(*this, "chargen")
{
}
DECLARE_READ8_MEMBER(keyin_r);
void kbd_put(u8 data);
DECLARE_WRITE_LINE_MEMBER(write_acia_clock);
MC6845_UPDATE_ROW(crtc_update_row);
private:
uint8_t m_term_data;
virtual void machine_reset() override;
required_device<palette_device> m_palette;
required_shared_ptr<uint8_t> m_p_videoram;
required_device<z80_device> m_maincpu;
required_device<acia6850_device> m_acia;
required_region_ptr<u8> m_p_chargen;
};
@ -67,11 +63,10 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(mx2178_io, AS_IO, 8, mx2178_state)
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x00) AM_DEVWRITE("crtc", mc6845_device, address_w)
AM_RANGE(0x00, 0x00) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
//AM_RANGE(0xa0, 0xa0) AM_DEVREADWRITE("acia", acia6850_device, status_r, control_w)
//AM_RANGE(0xa1, 0xa1) AM_DEVREADWRITE("acia", acia6850_device, data_r, data_w)
AM_RANGE(0xa0, 0xa1) AM_READ(keyin_r)
AM_RANGE(0xa0, 0xa0) AM_DEVREADWRITE("acia", acia6850_device, status_r, control_w)
AM_RANGE(0xa1, 0xa1) AM_DEVREADWRITE("acia", acia6850_device, data_r, data_w)
ADDRESS_MAP_END
@ -79,24 +74,6 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( mx2178 )
INPUT_PORTS_END
READ8_MEMBER( mx2178_state::keyin_r )
{
if (offset)
{
uint8_t ret = m_term_data;
m_term_data = 0;
return ret;
}
else
return (m_term_data) ? 0x83 : 0x82;
}
void mx2178_state::kbd_put(u8 data)
{
m_term_data = data;
m_maincpu->set_input_line(0, HOLD_LINE);
}
MC6845_UPDATE_ROW( mx2178_state::crtc_update_row )
{
const rgb_t *pens = m_palette->palette()->entry_list_raw();
@ -146,12 +123,6 @@ void mx2178_state::machine_reset()
{
}
WRITE_LINE_MEMBER(mx2178_state::write_acia_clock)
{
m_acia->write_txc(state);
m_acia->write_rxc(state);
}
static MACHINE_CONFIG_START( mx2178 )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", Z80, 18869600/5) // guess
@ -174,16 +145,18 @@ static MACHINE_CONFIG_START( mx2178 )
MCFG_MC6845_CHAR_WIDTH(8)
MCFG_MC6845_UPDATE_ROW_CB(mx2178_state, crtc_update_row)
MCFG_DEVICE_ADD("acia_clock", CLOCK, 18869600/30)
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("acia", acia6850_device, write_txc))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("acia", acia6850_device, write_rxc))
MCFG_DEVICE_ADD("acia", ACIA6850, 0)
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
MCFG_ACIA6850_IRQ_HANDLER(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
/// TODO: hook up acia to keyboard and memory map
MCFG_DEVICE_ADD("keyboard", GENERIC_KEYBOARD, 0)
MCFG_GENERIC_KEYBOARD_CB(PUT(mx2178_state, kbd_put))
MCFG_DEVICE_ADD("acia_clock", CLOCK, 614400)
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(mx2178_state, write_acia_clock))
MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "keyboard")
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
MACHINE_CONFIG_END
/* ROM definition */

15
src/mame/drivers/savia84.cpp
View File

@ -38,22 +38,24 @@ class savia84_state : public driver_device
{
public:
savia84_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_ppi8255(*this, "ppi8255")
{ }
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_ppi8255(*this, "ppi8255")
{ }
required_device<cpu_device> m_maincpu;
required_device<i8255_device> m_ppi8255;
DECLARE_READ8_MEMBER(savia84_8255_portc_r);
DECLARE_WRITE8_MEMBER(savia84_8255_porta_w);
DECLARE_WRITE8_MEMBER(savia84_8255_portb_w);
DECLARE_WRITE8_MEMBER(savia84_8255_portc_w);
private:
uint8_t m_kbd;
uint8_t m_segment;
uint8_t m_digit;
uint8_t m_digit_last;
virtual void machine_reset() override;
required_device<cpu_device> m_maincpu;
required_device<i8255_device> m_ppi8255;
};
static ADDRESS_MAP_START( savia84_mem, AS_PROGRAM, 8, savia84_state )
@ -183,7 +185,6 @@ static MACHINE_CONFIG_START( savia84 )
MCFG_I8255_OUT_PORTB_CB(WRITE8(savia84_state, savia84_8255_portb_w))
MCFG_I8255_IN_PORTC_CB(READ8(savia84_state, savia84_8255_portc_r))
MCFG_I8255_OUT_PORTC_CB(WRITE8(savia84_state, savia84_8255_portc_w))
MACHINE_CONFIG_END
/* ROM definition */

1
src/mame/drivers/sun1.cpp
View File

@ -54,7 +54,6 @@
#include "cpu/m68000/m68000.h"
#include "machine/z80sio.h"
#define TERMINAL_TAG "terminal"
class sun1_state : public driver_device
{

11
src/mame/drivers/univac.cpp
View File

@ -27,6 +27,7 @@
#include "machine/nvram.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/clock.h"
#include "screen.h"
@ -91,8 +92,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( uts20_io, AS_IO, 8, univac_state)
ADDRESS_MAP_GLOBAL_MASK(0xff)
ADDRESS_MAP_UNMAP_HIGH
//AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("dart", z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("dart", z80dart_device, cd_ba_r, cd_ba_w) // ?? no idea
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("dart", z80dart_device, cd_ba_r, cd_ba_w)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x43, 0x43) AM_WRITE(port43_w)
AM_RANGE(0x80, 0xbf) AM_RAM AM_SHARE("nvram")
@ -185,6 +185,13 @@ static MACHINE_CONFIG_START( uts20 )
MCFG_PALETTE_ADD_MONOCHROME("palette")
MCFG_NVRAM_ADD_1FILL("nvram")
MCFG_DEVICE_ADD("uart_clock", CLOCK, 153600)
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("dart", z80dart_device, txca_w))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart", z80dart_device, rxca_w))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart", z80dart_device, txcb_w))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("dart", z80dart_device, rxcb_w))
MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_4MHz)
MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_Z80DART_ADD("dart", XTAL_4MHz, 0, 0, 0, 0 )

41
src/mame/drivers/votrtnt.cpp
View File

@ -46,20 +46,19 @@
class votrtnt_state : public driver_device
{
public:
votrtnt_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_votrax(*this, "votrax"),
m_acia(*this, "acia")
{
}
votrtnt_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_votrax(*this, "votrax")
, m_clock(*this, "acia_clock")
{ }
DECLARE_WRITE_LINE_MEMBER(write_acia_clock);
DECLARE_MACHINE_RESET(votrtnt);
private:
required_device<cpu_device> m_maincpu;
required_device<votrax_sc01_device> m_votrax;
required_device<acia6850_device> m_acia;
required_device<clock_device> m_clock;
};
@ -113,14 +112,25 @@ static INPUT_PORTS_START(votrtnt)
PORT_DIPSETTING( 0x80, "9600" )
INPUT_PORTS_END
WRITE_LINE_MEMBER(votrtnt_state::write_acia_clock)
MACHINE_RESET_MEMBER( votrtnt_state, votrtnt )
{
m_acia->write_txc(state);
m_acia->write_rxc(state);
// Read the dips, whichever one is found to be on first is accepted
u8 dips = ioport("DSW1")->read();
u8 speed = 1;
for (u8 i = 0; i < 7; i++)
{
if (BIT(dips, i))
{
m_clock->set_unscaled_clock(75*speed*16);
return;
}
speed *= 2;
}
// if none are on we'll leave the default which is 9600 baud
}
/******************************************************************************
Machine Drivers
******************************************************************************/
@ -130,6 +140,8 @@ static MACHINE_CONFIG_START( votrtnt )
MCFG_CPU_ADD("maincpu", M6802, XTAL_2_4576MHz) /* 2.4576MHz XTAL, verified; divided by 4 inside the m6802*/
MCFG_CPU_PROGRAM_MAP(6802_mem)
MCFG_MACHINE_RESET_OVERRIDE(votrtnt_state, votrtnt)
/* video hardware */
//MCFG_DEFAULT_LAYOUT(layout_votrtnt)
@ -143,7 +155,8 @@ static MACHINE_CONFIG_START( votrtnt )
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
MCFG_DEVICE_ADD("acia_clock", CLOCK, 153600)
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(votrtnt_state, write_acia_clock))
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("acia", acia6850_device, write_txc))
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("acia", acia6850_device, write_rxc))
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")