mirror of
https://github.com/holub/mame
synced 2025-04-20 23:42:22 +03:00
pc/pcipc.cpp: add base PCI for Cirrus Logic CL-GD5465 Laguna 3D
This commit is contained in:
angelosa
parent
508c6c119a
commit
fe898720e9
@ -953,6 +953,20 @@ if (VIDEOS["PC_XGA"]~=null) then
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/clgd546x_laguna.h,VIDEOS["CLGD546X_LAGUNA"] = true
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--------------------------------------------------
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if (VIDEOS["CLGD546X_LAGUNA"]~=null) then
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files {
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MAME_DIR .. "src/devices/video/clgd546x_laguna.cpp",
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MAME_DIR .. "src/devices/video/clgd546x_laguna.h",
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/virge_pci.h,VIDEOS["VIRGE_PCI"] = true
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@ -965,6 +979,7 @@ if (VIDEOS["VIRGE_PCI"]~=null) then
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/pcd8544.h,VIDEOS["PCD8544"] = true
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219
src/devices/video/clgd546x_laguna.cpp
Normal file
219
src/devices/video/clgd546x_laguna.cpp
Normal file
@ -0,0 +1,219 @@
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// license:BSD-3-Clause
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// copyright-holders:Angelo Salese
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#include "emu.h"
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#include "clgd546x_laguna.h"
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#include "screen.h"
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#define LOG_WARN (1U << 1)
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#define LOG_TODO (1U << 2) // log unimplemented registers
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#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_TODO)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__)
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#define LOGTODO(...) LOGMASKED(LOG_TODO, __VA_ARGS__)
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DEFINE_DEVICE_TYPE(CIRRUS_GD5465_LAGUNA3D, cirrus_gd5465_laguna3d_device, "clgd5465_laguna", "Cirrus Logic GD-5465 \"Laguna 3D\"")
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cirrus_gd5465_laguna3d_device::cirrus_gd5465_laguna3d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_device(mconfig, CIRRUS_GD5465_LAGUNA3D, tag, owner, clock)
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, m_svga(*this, "svga")
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, m_vga_rom(*this, "vga_rom")
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{
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// device ID 0x1013 Cirrus Logic
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// 0x00dx for Laguna revs
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// subvendor ID: Returns values from ROM 0x7ff8-0x7ffb
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set_ids_agp(0x101300d6, 0x00, 0x10130000);
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// TODO: class can be 0x80 (other display controller) with P18 pin.
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}
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ROM_START( gd5465 )
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ROM_REGION32_LE( 0x8000, "vga_rom", ROMREGION_ERASEFF )
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ROM_SYSTEM_BIOS( 0, "chaintech", "Chaintech GA-5465AS 1.62c" )
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ROMX_LOAD( "chaintech.vbi", 0x0000, 0x8000, CRC(8afa1afb) SHA1(251a953d442dc34738f80371cfbd0fd9f1097635), ROM_BIOS(0) )
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ROM_END
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const tiny_rom_entry *cirrus_gd5465_laguna3d_device::device_rom_region() const
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{
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return ROM_NAME(gd5465);
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}
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void cirrus_gd5465_laguna3d_device::device_add_mconfig(machine_config &config)
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{
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screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
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screen.set_raw(XTAL(25'174'800), 900, 0, 640, 526, 0, 480);
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screen.set_screen_update(m_svga, FUNC(cirrus_gd5446_device::screen_update));
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// TODO: bump to GD5465
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CIRRUS_GD5446(config, m_svga, 0);
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m_svga->set_screen("screen");
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// FIXME: shared RAM
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// in 4 and 8 MB versions
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m_svga->set_vram_size(8*1024*1024);
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}
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void cirrus_gd5465_laguna3d_device::device_start()
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{
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pci_device::device_start();
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add_map( 32*1024, M_MEM, FUNC(cirrus_gd5465_laguna3d_device::mmio_map));
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add_map( 32*1024*1024, M_MEM, FUNC(cirrus_gd5465_laguna3d_device::vram_aperture_map));
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add_rom((u8 *)m_vga_rom->base(), 0x8000);
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expansion_rom_base = 0xc0000;
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// INTA#
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intr_pin = 1;
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save_item(NAME(m_vga_legacy_enable));
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// TODO: fast back-to-back
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}
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void cirrus_gd5465_laguna3d_device::device_reset()
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{
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pci_device::device_reset();
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// TODO: to be checked
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command = 0x0000;
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status = 0x0000;
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m_vga_legacy_enable = true;
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remap_cb();
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}
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void cirrus_gd5465_laguna3d_device::config_map(address_map &map)
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{
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pci_device::config_map(map);
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// TODO: AGP CAPPTR
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// map(0xf8, 0xf8) PCI VGA Shadow Register
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// map(0xfc, 0xfc) PCI Vendor Specific Control Register
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}
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void cirrus_gd5465_laguna3d_device::mmio_map(address_map &map)
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{
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}
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void cirrus_gd5465_laguna3d_device::vram_aperture_map(address_map &map)
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{
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}
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// TODO: this should really be a subclass of VGA
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void cirrus_gd5465_laguna3d_device::legacy_memory_map(address_map &map)
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{
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map(0xa0000, 0xbffff).rw(FUNC(cirrus_gd5465_laguna3d_device::vram_r), FUNC(cirrus_gd5465_laguna3d_device::vram_w));
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}
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void cirrus_gd5465_laguna3d_device::legacy_io_map(address_map &map)
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{
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map(0x03b0, 0x03bf).rw(FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_r), FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_w));
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map(0x03c0, 0x03cf).rw(FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_r), FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_w));
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map(0x03d0, 0x03df).rw(FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_r), FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_w));
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}
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uint8_t cirrus_gd5465_laguna3d_device::vram_r(offs_t offset)
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{
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return downcast<cirrus_gd5446_device *>(m_svga.target())->mem_r(offset);
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}
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void cirrus_gd5465_laguna3d_device::vram_w(offs_t offset, uint8_t data)
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{
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downcast<cirrus_gd5446_device *>(m_svga.target())->mem_w(offset, data);
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}
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u32 cirrus_gd5465_laguna3d_device::vga_3b0_r(offs_t offset, uint32_t mem_mask)
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{
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uint32_t result = 0;
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if (ACCESSING_BITS_0_7)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_r(offset * 4 + 0) << 0;
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if (ACCESSING_BITS_8_15)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_r(offset * 4 + 1) << 8;
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if (ACCESSING_BITS_16_23)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_r(offset * 4 + 2) << 16;
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if (ACCESSING_BITS_24_31)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_r(offset * 4 + 3) << 24;
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return result;
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}
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void cirrus_gd5465_laguna3d_device::vga_3b0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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if (ACCESSING_BITS_0_7)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_w(offset * 4 + 0, data >> 0);
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if (ACCESSING_BITS_8_15)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_w(offset * 4 + 1, data >> 8);
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if (ACCESSING_BITS_16_23)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_w(offset * 4 + 2, data >> 16);
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if (ACCESSING_BITS_24_31)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03b0_w(offset * 4 + 3, data >> 24);
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}
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u32 cirrus_gd5465_laguna3d_device::vga_3c0_r(offs_t offset, uint32_t mem_mask)
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{
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uint32_t result = 0;
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if (ACCESSING_BITS_0_7)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_r(offset * 4 + 0) << 0;
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if (ACCESSING_BITS_8_15)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_r(offset * 4 + 1) << 8;
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if (ACCESSING_BITS_16_23)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_r(offset * 4 + 2) << 16;
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if (ACCESSING_BITS_24_31)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_r(offset * 4 + 3) << 24;
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return result;
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}
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void cirrus_gd5465_laguna3d_device::vga_3c0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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if (ACCESSING_BITS_0_7)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_w(offset * 4 + 0, data >> 0);
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if (ACCESSING_BITS_8_15)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_w(offset * 4 + 1, data >> 8);
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if (ACCESSING_BITS_16_23)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_w(offset * 4 + 2, data >> 16);
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if (ACCESSING_BITS_24_31)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03c0_w(offset * 4 + 3, data >> 24);
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}
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u32 cirrus_gd5465_laguna3d_device::vga_3d0_r(offs_t offset, uint32_t mem_mask)
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{
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uint32_t result = 0;
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if (ACCESSING_BITS_0_7)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_r(offset * 4 + 0) << 0;
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if (ACCESSING_BITS_8_15)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_r(offset * 4 + 1) << 8;
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if (ACCESSING_BITS_16_23)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_r(offset * 4 + 2) << 16;
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if (ACCESSING_BITS_24_31)
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result |= downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_r(offset * 4 + 3) << 24;
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return result;
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}
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void cirrus_gd5465_laguna3d_device::vga_3d0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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if (ACCESSING_BITS_0_7)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_w(offset * 4 + 0, data >> 0);
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if (ACCESSING_BITS_8_15)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_w(offset * 4 + 1, data >> 8);
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if (ACCESSING_BITS_16_23)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_w(offset * 4 + 2, data >> 16);
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if (ACCESSING_BITS_24_31)
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downcast<cirrus_gd5446_device *>(m_svga.target())->port_03d0_w(offset * 4 + 3, data >> 24);
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}
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void cirrus_gd5465_laguna3d_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
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{
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if (m_vga_legacy_enable)
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{
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memory_space->install_readwrite_handler(0xa0000, 0xbffff, read8sm_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vram_r)), write8sm_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vram_w)));
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io_space->install_readwrite_handler(0x3b0, 0x3bf, read32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_r)), write32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3b0_w)));
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io_space->install_readwrite_handler(0x3c0, 0x3cf, read32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_r)), write32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3c0_w)));
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io_space->install_readwrite_handler(0x3d0, 0x3df, read32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_r)), write32s_delegate(*this, FUNC(cirrus_gd5465_laguna3d_device::vga_3d0_w)));
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//memory_space->install_rom(0xc0000, 0xcffff, (void *)expansion_rom);
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}
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}
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56
src/devices/video/clgd546x_laguna.h
Normal file
56
src/devices/video/clgd546x_laguna.h
Normal file
@ -0,0 +1,56 @@
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// license:BSD-3-Clause
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// copyright-holders:Angelo Salese
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#ifndef MAME_VIDEO_CLGD546X_LAGUNA_H
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#define MAME_VIDEO_CLGD546X_LAGUNA_H
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#pragma once
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#include "machine/pci.h"
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//#include "video/pc_vga.h"
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#include "video/clgd542x.h"
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class cirrus_gd5465_laguna3d_device : public pci_device
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{
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public:
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cirrus_gd5465_laguna3d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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void legacy_memory_map(address_map &map);
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void legacy_io_map(address_map &map);
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual const tiny_rom_entry *device_rom_region() const override;
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virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
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virtual void config_map(address_map &map) override;
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virtual void mmio_map(address_map &map);
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virtual void vram_aperture_map(address_map &map);
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private:
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required_device<cirrus_gd5446_device> m_svga;
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required_memory_region m_vga_rom;
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u8 vram_r(offs_t offset);
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void vram_w(offs_t offset, uint8_t data);
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u32 vga_3b0_r(offs_t offset, uint32_t mem_mask = ~0);
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void vga_3b0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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u32 vga_3c0_r(offs_t offset, uint32_t mem_mask = ~0);
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void vga_3c0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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u32 vga_3d0_r(offs_t offset, uint32_t mem_mask = ~0);
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void vga_3d0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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// u32 unmap_log_r(offs_t offset, u32 mem_mask = ~0);
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// void unmap_log_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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bool m_vga_legacy_enable = false;
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u32 m_main_scratchpad_id = 0;
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};
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DECLARE_DEVICE_TYPE(CIRRUS_GD5465_LAGUNA3D, cirrus_gd5465_laguna3d_device)
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#endif // MAME_VIDEO_CLGD546X_LAGUNA_H
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@ -41,6 +41,7 @@
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#include "video/mga2064w.h"
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#include "video/virge_pci.h"
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#include "video/riva128.h"
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#include "video/clgd546x_laguna.h"
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namespace {
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@ -661,8 +662,8 @@ void pcipc_state::pciagp(machine_config &config)
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serport1.cts_handler().set("board4:w83977tf", FUNC(fdc37c93x_device::ncts2_w));
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#endif
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// TODO: temp, to be converted to a proper AGP card once we make this to boot
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VIRGE_PCI(config, "pci:0e.0", 0); // J4C1
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// TODO: temp link, to be moved to quakeat.cpp
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CIRRUS_GD5465_LAGUNA3D(config, "pci:01.0:00.0", 0);
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}
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ROM_START(pcipc)
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