mirror of
https://github.com/holub/mame
synced 2025-04-26 10:13:37 +03:00
Preliminary work for ATV Track, in order to get the second SH-4 into
business [Samuele Zannoli]
Added support for dma transfers between the processor and external
devices in SH-4 CPU core [Samuele Zannoli]
Modified naomibd device so that it allocates the memory for the gdrom
data on startup based on a parameter that specifies the size in
megabytes. [Samuele Zannoli]
Added two new commands to the unidasm utility [Samuele Zannoli]
-skip <n> allows to skip the first <n> bytes from the file
-count <n> specifiest that only <n> bytes from the file must be
disassembled
This commit is contained in:
Angelo Salese
parent
c59f407916
commit
fecff8f387
@ -57,9 +57,10 @@ enum
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{
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SH4_IOPORT_16=8*0,
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SH4_IOPORT_4=8*1,
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SH4_IOPORT_DMA=8*2,
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// future use
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SH4_IOPORT_SCI=8*2,
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SH4_IOPORT_SCIF=8*3
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SH4_IOPORT_SCI=8*3,
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SH4_IOPORT_SCIF=8*4
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};
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struct sh4_config
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@ -76,6 +77,14 @@ struct sh4_config
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int clock;
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};
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struct sh4_device_dma
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{
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UINT32 length;
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UINT32 size;
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void *buffer;
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int channel;
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};
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struct sh4_ddt_dma
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{
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UINT32 source;
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@ -99,6 +108,7 @@ READ32_HANDLER( sh4_internal_r );
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void sh4_set_frt_input(device_t *device, int state);
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void sh4_set_irln_input(device_t *device, int value);
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void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback);
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int sh4_dma_data(device_t *device, struct sh4_device_dma *s);
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void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s);
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/***************************************************************************
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@ -404,26 +404,26 @@ static TIMER_CALLBACK( sh4_dmac_callback )
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{
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case 0:
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sh4->m[DMATCR0] = 0;
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sh4->m[CHCR0] |= 2;
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if (sh4->m[CHCR0] & 4)
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sh4->m[CHCR0] |= CHCR_TE;
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if (sh4->m[CHCR0] & CHCR_IE)
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sh4_exception_request(sh4, SH4_INTC_DMTE0);
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break;
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case 1:
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sh4->m[DMATCR1] = 0;
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sh4->m[CHCR1] |= 2;
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if (sh4->m[CHCR1] & 4)
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sh4->m[CHCR1] |= CHCR_TE;
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if (sh4->m[CHCR1] & CHCR_IE)
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sh4_exception_request(sh4, SH4_INTC_DMTE1);
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break;
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case 2:
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sh4->m[DMATCR2] = 0;
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sh4->m[CHCR2] |= 2;
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if (sh4->m[CHCR2] & 4)
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sh4->m[CHCR2] |= CHCR_TE;
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if (sh4->m[CHCR2] & CHCR_IE)
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sh4_exception_request(sh4, SH4_INTC_DMTE2);
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break;
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case 3:
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sh4->m[DMATCR3] = 0;
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sh4->m[CHCR3] |= 2;
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if (sh4->m[CHCR3] & 4)
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sh4->m[CHCR3] |= CHCR_TE;
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if (sh4->m[CHCR3] & CHCR_IE)
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sh4_exception_request(sh4, SH4_INTC_DMTE3);
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break;
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}
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@ -434,9 +434,9 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
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int incs, incd, size;
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UINT32 src, dst, count;
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incd = (chcr >> 14) & 3;
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incs = (chcr >> 12) & 3;
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size = dmasize[(chcr >> 4) & 7];
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incd = (chcr & CHCR_DM) >> 14;
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incs = (chcr & CHCR_SM) >> 12;
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size = dmasize[(chcr & CHCR_TS) >> 4];
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if(incd == 3 || incs == 3)
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{
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logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr);
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@ -450,12 +450,12 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
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LOG(("SH4: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
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if (timermode == 1)
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if (timermode == 1) // timer actvated after a time based on the number of words to transfer
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{
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sh4->dma_timer_active[channel] = 1;
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sh4->dma_timer[channel]->adjust(sh4->device->cycles_to_attotime(2*count+1), channel);
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}
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else if (timermode == 2)
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else if (timermode == 2) // timer activated immediately
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{
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sh4->dma_timer_active[channel] = 1;
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sh4->dma_timer[channel]->adjust(attotime::zero, channel);
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@ -556,9 +556,50 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
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return 1;
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}
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static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
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{
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int incs, incd, size, mod;
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UINT32 src, dst, count;
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incd = (chcr & CHCR_DM) >> 14;
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incs = (chcr & CHCR_SM) >> 12;
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size = dmasize[(chcr & CHCR_TS) >> 4];
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mod = ((chcr & CHCR_RS) >> 8);
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if (incd == 3 || incs == 3)
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{
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logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr);
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return 0;
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}
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src = *sar;
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dst = *dar;
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count = *dmatcr;
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if (!count)
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count = 0x1000000;
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LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
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sh4->dma_timer_active[channel] = 1;
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src &= AM;
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dst &= AM;
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// remember parameters
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sh4->dma_source[channel]=src;
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sh4->dma_destination[channel]=dst;
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sh4->dma_count[channel]=count;
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sh4->dma_wordsize[channel]=size;
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sh4->dma_source_increment[channel]=incs;
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sh4->dma_destination_increment[channel]=incd;
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sh4->dma_mode[channel]=mod;
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// inform device its ready to transfer
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sh4->io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16));
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return 1;
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}
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static void sh4_dmac_check(sh4_state *sh4, int channel)
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{
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UINT32 dmatcr,chcr,sar,dar;
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UINT32 dmatcr, chcr, sar, dar;
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switch (channel)
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{
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@ -589,12 +630,17 @@ UINT32 dmatcr,chcr,sar,dar;
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default:
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return;
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}
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if (chcr & sh4->m[DMAOR] & 1)
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if (chcr & sh4->m[DMAOR] & DMAOR_DME)
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{
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if ((((chcr >> 8) & 15) < 4) || (((chcr >> 8) & 15) > 6))
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if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6))
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return;
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if (!sh4->dma_timer_active[channel] && !(chcr & 2) && !(sh4->m[DMAOR] & 6))
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sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr);
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if (!sh4->dma_timer_active[channel] && !(chcr & CHCR_TE) && !(sh4->m[DMAOR] & (DMAOR_AE | DMAOR_NMIF)))
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{
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if (((chcr & CHCR_RS) >> 8) > 3)
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sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr);
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else if ((sh4->m[DMAOR] & DMAOR_DDT) == 0)
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sh4_dma_transfer_device(sh4, channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer
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}
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}
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else
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{
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@ -607,11 +653,11 @@ UINT32 dmatcr,chcr,sar,dar;
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}
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}
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static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi
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static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi gets asserted
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{
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int s;
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sh4->m[DMAOR] |= 2; // nmif = 1
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sh4->m[DMAOR] |= DMAOR_NMIF;
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for (s = 0;s < 4;s++)
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{
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if (sh4->dma_timer_active[s])
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@ -638,7 +684,7 @@ WRITE32_HANDLER( sh4_internal_w )
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switch( offset )
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{
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case MMUCR: // MMU Control
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if (data & 1)
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if (data & MMUCR_AT)
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{
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printf("SH4 MMU Enabled\n");
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printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n");
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@ -880,10 +926,10 @@ WRITE32_HANDLER( sh4_internal_w )
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sh4_dmac_check(sh4, 3);
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break;
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case DMAOR:
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if ((sh4->m[DMAOR] & 4) && (~old & 4))
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sh4->m[DMAOR] &= ~4;
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if ((sh4->m[DMAOR] & 2) && (~old & 2))
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sh4->m[DMAOR] &= ~2;
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if ((sh4->m[DMAOR] & DMAOR_AE) && (~old & DMAOR_AE))
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sh4->m[DMAOR] &= ~DMAOR_AE;
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if ((sh4->m[DMAOR] & DMAOR_NMIF) && (~old & DMAOR_NMIF))
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sh4->m[DMAOR] &= ~DMAOR_NMIF;
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sh4_dmac_check(sh4, 0);
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sh4_dmac_check(sh4, 1);
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sh4_dmac_check(sh4, 2);
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@ -953,7 +999,10 @@ READ32_HANDLER( sh4_internal_r )
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switch( offset )
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{
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case VERSION:
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return 0x040205c1; // this is what a real SH7750 in a Dreamcast returns - the later Naomi BIOSes check and care!
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return PVR_SH7091; // 0x040205c1, this is what a real SH7091 in a Dreamcast returns - the later Naomi BIOSes check and care!
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break;
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case PRR:
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return 0;
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break;
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case IPRD:
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return 0x00000000; // SH7750 ignores writes here and always returns zero
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@ -1197,6 +1246,140 @@ void sh4_common_init(device_t *device)
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sh4->m = auto_alloc_array(device->machine(), UINT32, 16384);
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}
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// called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu
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int sh4_dma_data(device_t *device, struct sh4_device_dma *s)
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{
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UINT32 pos, len, siz;
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int channel = s->channel;
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void *data = s->buffer;
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sh4_state *sh4 = get_safe_token(device);
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if (!sh4->dma_timer_active[channel])
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return 0;
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if (sh4->dma_mode[channel] == 2)
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{
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// device receives data
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len = sh4->dma_count[channel];
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if (s->length < len)
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len = s->length;
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siz = sh4->dma_wordsize[channel];
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for (pos = 0;pos < len;pos++) {
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switch (siz)
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{
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case 8:
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if (sh4->dma_source_increment[channel] == 2)
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sh4->dma_source[channel] -= 8;
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*(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~7);
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if (sh4->dma_source_increment[channel] == 1)
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sh4->dma_source[channel] += 8;
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break;
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case 1:
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if (sh4->dma_source_increment[channel] == 2)
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sh4->dma_source[channel]--;
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*(UINT8 *)data = sh4->program->read_byte(sh4->dma_source[channel]);
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if (sh4->dma_source_increment[channel] == 1)
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sh4->dma_source[channel]++;
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break;
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case 2:
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if (sh4->dma_source_increment[channel] == 2)
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sh4->dma_source[channel] -= 2;
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*(UINT16 *)data = sh4->program->read_word(sh4->dma_source[channel] & ~1);
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if (sh4->dma_source_increment[channel] == 1)
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sh4->dma_source[channel] += 2;
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break;
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case 4:
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if (sh4->dma_source_increment[channel] == 2)
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sh4->dma_source[channel] -= 4;
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*(UINT32 *)data = sh4->program->read_dword(sh4->dma_source[channel] & ~3);
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if (sh4->dma_source_increment[channel] == 1)
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sh4->dma_source[channel] += 4;
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break;
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case 32:
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if (sh4->dma_source_increment[channel] == 2)
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sh4->dma_source[channel] -= 32;
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*(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~31);
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*((UINT64 *)data+1) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+8);
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*((UINT64 *)data+2) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+16);
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*((UINT64 *)data+3) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+24);
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if (sh4->dma_source_increment[channel] == 1)
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sh4->dma_source[channel] += 32;
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break;
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}
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sh4->dma_count[channel]--;
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}
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if (sh4->dma_count[channel] == 0) // all data transferred ?
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{
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sh4->dma_timer[channel]->adjust(attotime::zero, channel);
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return 2;
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}
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return 1;
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}
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else if (sh4->dma_mode[channel] == 3)
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{
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// device sends data
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len = sh4->dma_count[channel];
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if (s->length < len)
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len = s->length;
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siz = sh4->dma_wordsize[channel];
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for (pos = 0;pos < len;pos++) {
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switch (siz)
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{
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case 8:
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if (sh4->dma_destination_increment[channel] == 2)
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sh4->dma_destination[channel]-=8;
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sh4->program->write_qword(sh4->dma_destination[channel] & ~7, *(UINT64 *)data);
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if (sh4->dma_destination_increment[channel] == 1)
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sh4->dma_destination[channel]+=8;
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break;
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case 1:
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if (sh4->dma_destination_increment[channel] == 2)
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sh4->dma_destination[channel]--;
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sh4->program->write_byte(sh4->dma_destination[channel], *(UINT8 *)data);
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if (sh4->dma_destination_increment[channel] == 1)
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sh4->dma_destination[channel]++;
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break;
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case 2:
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if (sh4->dma_destination_increment[channel] == 2)
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sh4->dma_destination[channel]-=2;
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sh4->program->write_word(sh4->dma_destination[channel] & ~1, *(UINT16 *)data);
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if (sh4->dma_destination_increment[channel] == 1)
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sh4->dma_destination[channel]+=2;
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break;
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case 4:
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if (sh4->dma_destination_increment[channel] == 2)
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sh4->dma_destination[channel]-=4;
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sh4->program->write_dword(sh4->dma_destination[channel] & ~3, *(UINT32 *)data);
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if (sh4->dma_destination_increment[channel] == 1)
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sh4->dma_destination[channel]+=4;
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break;
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case 32:
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if (sh4->dma_destination_increment[channel] == 2)
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sh4->dma_destination[channel]-=32;
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sh4->program->write_qword(sh4->dma_destination[channel] & ~31, *(UINT64 *)data);
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sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+8, *((UINT64 *)data+1));
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sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+16, *((UINT64 *)data+2));
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sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+24, *((UINT64 *)data+3));
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if (sh4->dma_destination_increment[channel] == 1)
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sh4->dma_destination[channel]+=32;
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break;
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}
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sh4->dma_count[channel]--;
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}
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if (sh4->dma_count[channel] == 0) // all data transferred ?
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{
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sh4->dma_timer[channel]->adjust(attotime::zero, channel);
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return 2;
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}
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return 1;
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}
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else
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return 0;
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}
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// called by drivers to transfer data in a DDT dma. 'device' must be a SH4 cpu
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void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
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{
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sh4_state *sh4 = get_safe_token(device);
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@ -94,6 +94,13 @@ typedef struct
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emu_timer *timer[3];
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UINT32 refresh_timer_base;
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int dma_timer_active[4];
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UINT32 dma_source[4];
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UINT32 dma_destination[4];
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UINT32 dma_count[4];
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int dma_wordsize[4];
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int dma_source_increment[4];
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int dma_destination_increment[4];
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int dma_mode[4];
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int sh4_icount;
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int is_slave;
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@ -19,6 +19,7 @@
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#define PTEA 0x200D /* FF000034 */
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#define QACR0 0x200E /* FF000038 */
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#define QACR1 0x200F /* FF00003C */
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#define PRR 0x2011 /* FF000044 */
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#define BARA 0x2400 /* FF200000 */
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#define BAMRA 0x2401 /* FF200004 */
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#define BBRA 0x2402 /* FF200008 */
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@ -157,4 +158,47 @@
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#define SDINT 0x3E05 /* FFF00014 */
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#define SIZEREGS 15878
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|
||||
/* bit definitions */
|
||||
#define CHCR_SSA 0xe0000000
|
||||
#define CHCR_STC 0x10000000
|
||||
#define CHCR_DSA 0x0e000000
|
||||
#define CHCR_DTC 0x01000000
|
||||
#define CHCR_DS 0x00080000
|
||||
#define CHCR_RL 0x00040000
|
||||
#define CHCR_AM 0x00020000
|
||||
#define CHCR_AL 0x00010000
|
||||
#define CHCR_DM 0x0000c000
|
||||
#define CHCR_SM 0x00003000
|
||||
#define CHCR_RS 0x00000f00
|
||||
#define CHCR_TM 0x00000080
|
||||
#define CHCR_TS 0x00000070
|
||||
#define CHCR_IE 0x00000004
|
||||
#define CHCR_TE 0x00000002
|
||||
#define CHCR_DE 0x00000001
|
||||
|
||||
#define DMAOR_DDT 0x8000
|
||||
#define DMAOR_PR 0x0300
|
||||
#define DMAOR_COD 0x0010
|
||||
#define DMAOR_AE 0x0004
|
||||
#define DMAOR_NMIF 0x0002
|
||||
#define DMAOR_DME 0x0001
|
||||
|
||||
#define MMUCR_LRUI 0xfc000000
|
||||
#define MMUCR_URB 0x00fc0000
|
||||
#define MMUCR_URC 0x0000fc00
|
||||
#define MMUCR_SQMD 0x00000200
|
||||
#define MMUCR_SV 0x00000100
|
||||
#define MMUCR_TI 0x00000004
|
||||
#define MMUCR_AT 0x00000001
|
||||
|
||||
/* constants */
|
||||
#define PVR_SH7091 0x040205c1
|
||||
#define PVR_SH7750 0x04020500 // from TN-SH7-361B/E
|
||||
#define PVR_SH7750S 0x04020600
|
||||
#define PVR_SH7750R 0x04050000
|
||||
#define PRR_SH7750R 0x00000100
|
||||
#define PVR_SH7751 0x04110000
|
||||
#define PVR_SH7751R 0x04050000
|
||||
#define PRR_SH7751R 0x00000110
|
||||
|
||||
#endif /* __SH4REGS_H__ */
|
||||
|
||||
@ -50,15 +50,21 @@ Notes:
|
||||
L4955 - ST Microelectronics L4955 low-power, quad channel, 8-bit buffered voltage output DAC and amplifier
|
||||
7LB176 - Texas Instruments 7LB176 Differential Bus Tranceiver (SOIC8)
|
||||
385-1 - National LM385 Adjustable Micropower Voltage Reference Diode (SOIC8)
|
||||
CN1 - Multi-pin connector for filter board (input power & controls connectors etc)
|
||||
DB9 - Video output connector (for twin monitors)
|
||||
CN1 - Multi-pin connector for filter board (input, video, power & controls connectors etc)
|
||||
DB9 - Probably used for cabinet linking
|
||||
SW3 - Push button switch
|
||||
|
||||
*/
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/sh4/sh4.h"
|
||||
#include "debugger.h"
|
||||
|
||||
const memory_region *nandregion;
|
||||
int nandcommand[4], nandoffset[4], nandaddressstep, nandaddress[4];
|
||||
UINT32 area1_data[4];
|
||||
|
||||
//#define SPECIALMODE 1 // Alternate code path
|
||||
|
||||
class atvtrack_state : public driver_device
|
||||
{
|
||||
@ -68,6 +74,232 @@ public:
|
||||
|
||||
};
|
||||
|
||||
static void logbinary(UINT32 data,int high=31,int low=0)
|
||||
{
|
||||
UINT32 s;
|
||||
int z;
|
||||
|
||||
s=1 << high;
|
||||
for (z = high;z >= low;z--) {
|
||||
if (data & s)
|
||||
logerror("1");
|
||||
else
|
||||
logerror("0");
|
||||
s=s >> 1;
|
||||
}
|
||||
}
|
||||
|
||||
static inline UINT32 decode64_32(offs_t offset64, UINT64 data, UINT64 mem_mask, offs_t &offset32)
|
||||
{
|
||||
if (ACCESSING_BITS_0_31) {
|
||||
offset32 = offset64 << 1;
|
||||
return (UINT32)data;
|
||||
}
|
||||
if (ACCESSING_BITS_32_63) {
|
||||
offset32 = (offset64 << 1)+1;
|
||||
return (UINT32)(data >> 32);
|
||||
}
|
||||
logerror("Wrong word size in external access\n");
|
||||
//debugger_break(NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static READ64_HANDLER( area1_r )
|
||||
{
|
||||
UINT32 addr;
|
||||
|
||||
addr = 0;
|
||||
decode64_32(offset, 0, mem_mask, addr);
|
||||
if (addr == (0x00020000-0x00020000)/4)
|
||||
return -1;
|
||||
else if (addr == (0x00020004-0x00020000)/4)
|
||||
return -1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
static WRITE64_HANDLER( area1_w )
|
||||
{
|
||||
UINT32 addr, dat, old;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, data, mem_mask, addr);
|
||||
old = area1_data[addr];
|
||||
area1_data[addr] = dat;
|
||||
if (addr == (0x00020000-0x00020000)/4) {
|
||||
if (data & 4) {
|
||||
device_execute_interface *exec = dynamic_cast<device_execute_interface *>(space->machine().device("subcpu"));
|
||||
exec->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
logerror("Write %08x at %08x ",dat, 0x20000+addr*4+0);
|
||||
logbinary(dat);
|
||||
logerror("\n");
|
||||
}
|
||||
|
||||
static READ64_HANDLER( area2_r )
|
||||
{
|
||||
UINT32 addr, dat;
|
||||
int c;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, 0, mem_mask, addr);
|
||||
if (addr == 0) {
|
||||
dat = 0;
|
||||
for (c = 3;c >= 0;c--) {
|
||||
if (nandcommand[c] <= 0x50) {
|
||||
addr = nandaddress[c]+nandoffset[c];
|
||||
dat = (dat << 8) | nandregion->u8(addr+c);
|
||||
nandoffset[c] += 4;
|
||||
} else
|
||||
dat = (dat << 8) | 0xc0;
|
||||
}
|
||||
return dat;
|
||||
} else
|
||||
;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static WRITE64_HANDLER( area2_w )
|
||||
{
|
||||
UINT32 addr, dat;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, data, mem_mask, addr);
|
||||
if (addr == 0)
|
||||
;
|
||||
else
|
||||
;
|
||||
}
|
||||
|
||||
static READ64_HANDLER( area3_r )
|
||||
{
|
||||
UINT32 addr, dat;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, 0, mem_mask, addr);
|
||||
if (addr == 0)
|
||||
;
|
||||
else
|
||||
;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static WRITE64_HANDLER( area3_w )
|
||||
{
|
||||
UINT32 addr, dat;
|
||||
int c;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, data, mem_mask, addr);
|
||||
if (addr == 0) {
|
||||
for (c = 0;c < 4;c++) {
|
||||
nandcommand[c] = data & 0xff;
|
||||
if (nandcommand[c] == 0x00) {
|
||||
nandoffset[c] = 0;
|
||||
} else if (nandcommand[c] == 0x01) {
|
||||
nandoffset[c] = 256*4;
|
||||
} else if (nandcommand[c] == 0x50) {
|
||||
nandoffset[c] = 512*4;
|
||||
} else if (nandcommand[c] == 0x90) {
|
||||
} else if (nandcommand[c] == 0xff) {
|
||||
} else if (nandcommand[c] == 0x80) {
|
||||
} else if (nandcommand[c] == 0x60) {
|
||||
} else if (nandcommand[c] == 0x70) {
|
||||
} else if (nandcommand[c] == 0x10) {
|
||||
} else if (nandcommand[c] == 0xd0) {
|
||||
} else {
|
||||
nandcommand[c] = 0xff;
|
||||
}
|
||||
data=data >> 8;
|
||||
}
|
||||
nandaddressstep = 0;
|
||||
} else
|
||||
;
|
||||
}
|
||||
|
||||
static READ64_HANDLER( area4_r )
|
||||
{
|
||||
UINT32 addr, dat;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, 0, mem_mask, addr);
|
||||
if (addr == 0)
|
||||
;
|
||||
else
|
||||
;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static WRITE64_HANDLER( area4_w )
|
||||
{
|
||||
UINT32 addr, dat;
|
||||
int c;
|
||||
|
||||
addr = 0;
|
||||
dat = decode64_32(offset, data, mem_mask, addr);
|
||||
if (addr == 0) {
|
||||
for (c = 0;c < 4;c++) {
|
||||
if (nandaddressstep == 0) {
|
||||
nandaddress[c] = (data & 0xff)*4;
|
||||
} else if (nandaddressstep == 1) {
|
||||
nandaddress[c] = nandaddress[c]+(data & 0xff)*0x840;
|
||||
} else if (nandaddressstep == 2) {
|
||||
nandaddress[c] = nandaddress[c]+(data & 0xff)*0x84000;
|
||||
}
|
||||
data = data >> 8;
|
||||
}
|
||||
nandaddressstep++;
|
||||
} else
|
||||
;
|
||||
}
|
||||
|
||||
static READ64_HANDLER( ioport_r )
|
||||
{
|
||||
if (offset == SH4_IOPORT_16/8) {
|
||||
// much simplified way
|
||||
if (strcmp(space->device().tag(), "maincpu") == 0)
|
||||
#ifndef SPECIALMODE
|
||||
return -1; // normal
|
||||
#else
|
||||
return 0; // testing
|
||||
#endif
|
||||
else
|
||||
return 0; // unknown
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static WRITE64_HANDLER( ioport_w )
|
||||
{
|
||||
#ifdef SPECIALMODE
|
||||
UINT64 d;
|
||||
static int cnt=0;
|
||||
sh4_device_dma dm;
|
||||
#endif
|
||||
|
||||
if (offset == SH4_IOPORT_16/8) {
|
||||
logerror("SH4 16bit i/o port write ");
|
||||
logbinary((UINT32)data,15,0);
|
||||
logerror("\n");
|
||||
}
|
||||
#ifdef SPECIALMODE
|
||||
if (offset == SH4_IOPORT_DMA/8) {
|
||||
dm.buffer = &d;
|
||||
dm.channel = data & 0xffff;
|
||||
dm.length = 1;
|
||||
dm.size = 4;
|
||||
if (cnt == 0)
|
||||
d=0x12340153;
|
||||
else
|
||||
d=0x11223344;
|
||||
if (cnt == 0)
|
||||
sh4_dma_data(space->cpu,&dm);
|
||||
else
|
||||
sh4_dma_data(space->cpu,&dm);
|
||||
cnt++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
VIDEO_START(atvtrack)
|
||||
{
|
||||
@ -78,11 +310,57 @@ SCREEN_UPDATE(atvtrack)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( atvtrack_map, AS_PROGRAM, 64 )
|
||||
AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_REGION("maincpu", 0)
|
||||
static MACHINE_START(atvtrack)
|
||||
{
|
||||
UINT8 *src, *dst;
|
||||
address_space *as;
|
||||
|
||||
nandaddressstep = 0;
|
||||
nandregion = machine.region("maincpu");
|
||||
as = machine.device("maincpu")->memory().space(AS_PROGRAM);
|
||||
dst = (UINT8 *)(as->get_write_ptr(0x0c7f0000));
|
||||
src = nandregion->base()+0x10;
|
||||
// copy 0x10000 bytes from region "maincpu" offset 0x10 to 0x0c7f0000
|
||||
memcpy(dst, src, 0x10000);
|
||||
}
|
||||
|
||||
static MACHINE_RESET(atvtrack)
|
||||
{
|
||||
address_space *as;
|
||||
|
||||
// Probably just after reset the cpu executes some bootsrtap routine from a memory inside the fpga.
|
||||
// The routine initializes the cpu, copies the boot program from the flash memories into the cpu sdram
|
||||
// and finally executes it.
|
||||
// Here there is the setup of the cpu, the boot program is copied in machine_start
|
||||
as = machine.device("maincpu")->memory().space(AS_PROGRAM);
|
||||
// set cpu PC register to 0x0c7f0000
|
||||
cpu_set_reg(machine.device("maincpu"), STATE_GENPC, 0x0c7f0000);
|
||||
// set BCR2 to 1
|
||||
sh4_internal_w(as, 0x3001, 1, 0xffffffff);
|
||||
device_execute_interface *exec = dynamic_cast<device_execute_interface *>(machine.device("subcpu"));
|
||||
exec->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( atvtrack_main_map, AS_PROGRAM, 64 )
|
||||
AM_RANGE(0x00000000, 0x000003ff) AM_RAM AM_SHARE("sharedmem")
|
||||
AM_RANGE(0x00020000, 0x00020007) AM_READWRITE(area1_r, area1_w)
|
||||
AM_RANGE(0x14000000, 0x14000007) AM_READWRITE(area2_r, area2_w) // data
|
||||
AM_RANGE(0x14100000, 0x14100007) AM_READWRITE(area3_r, area3_w) // command
|
||||
AM_RANGE(0x14200000, 0x14200007) AM_READWRITE(area4_r, area4_w) // address
|
||||
AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( atvtrack_port, AS_IO, 64 )
|
||||
static ADDRESS_MAP_START( atvtrack_main_port, AS_IO, 64 )
|
||||
AM_RANGE(0x00, 0x1f) AM_READWRITE(ioport_r, ioport_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( atvtrack_sub_map, AS_PROGRAM, 64 )
|
||||
AM_RANGE(0x00000000, 0x000003ff) AM_RAM AM_SHARE("sharedmem")
|
||||
AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( atvtrack_sub_port, AS_IO, 64 )
|
||||
/*AM_RANGE(0x00, 0x1f) AM_READWRITE(ioport_r, ioport_w) */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -98,14 +376,13 @@ static MACHINE_CONFIG_START( atvtrack, atvtrack_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", SH4, ATV_CPU_CLOCK)
|
||||
MCFG_CPU_CONFIG(sh4cpu_config)
|
||||
MCFG_CPU_PROGRAM_MAP(atvtrack_map)
|
||||
MCFG_CPU_IO_MAP(atvtrack_port)
|
||||
MCFG_CPU_PROGRAM_MAP(atvtrack_main_map)
|
||||
MCFG_CPU_IO_MAP(atvtrack_main_port)
|
||||
|
||||
MCFG_CPU_ADD("subcpu", SH4, ATV_CPU_CLOCK)
|
||||
MCFG_CPU_CONFIG(sh4cpu_config)
|
||||
MCFG_CPU_PROGRAM_MAP(atvtrack_map)
|
||||
MCFG_CPU_IO_MAP(atvtrack_port)
|
||||
MCFG_DEVICE_DISABLE()
|
||||
MCFG_CPU_PROGRAM_MAP(atvtrack_sub_map)
|
||||
MCFG_CPU_IO_MAP(atvtrack_sub_port)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
@ -118,6 +395,8 @@ static MACHINE_CONFIG_START( atvtrack, atvtrack_state )
|
||||
|
||||
MCFG_PALETTE_LENGTH(0x1000)
|
||||
|
||||
MCFG_MACHINE_RESET(atvtrack)
|
||||
MCFG_MACHINE_START(atvtrack)
|
||||
MCFG_VIDEO_START(atvtrack)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
@ -129,7 +408,7 @@ ROM_START( atvtrack )
|
||||
ROM_LOAD32_BYTE("19.bin", 0x0000003, 0x1080000, CRC(9fc5c579) SHA1(8829329ef229564952aea2108ef1750dc226cbac) )
|
||||
|
||||
ROM_REGION( 0x20000, "eeprom", ROMREGION_ERASEFF)
|
||||
ROM_LOAD("epc1pc8.ic23", 0x0000000, 0x1ff01, CRC(752444c7) SHA1(c77e8fcfcbe15b53eda25553763bdac45f0ef7df) ) // contains a large amount of data, maybe used for some form of protection
|
||||
ROM_LOAD("epc1pc8.ic23", 0x0000000, 0x1ff01, CRC(752444c7) SHA1(c77e8fcfcbe15b53eda25553763bdac45f0ef7df) ) // contains configuration data for the fpga, maybe used for some form of protection
|
||||
ROM_END
|
||||
|
||||
ROM_START( atvtracka )
|
||||
|
||||
@ -661,7 +661,7 @@ static MACHINE_CONFIG_START( chihiro_base, driver_device )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( chihirogd, chihiro_base )
|
||||
MCFG_NAOMI_DIMM_BOARD_ADD("rom_board", "gdrom", "user1", "picreturn")
|
||||
MCFG_NAOMI_DIMM_BOARD_ADD("rom_board", "gdrom", NULL, 512, "picreturn")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \
|
||||
|
||||
@ -2545,7 +2545,7 @@ static MACHINE_CONFIG_DERIVED( naomigd, naomi_base )
|
||||
MCFG_SEGA_837_13551_DEVICE_ADD("837_13551", "mie", "TILT", "P1", "P2", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "OUTPUT")
|
||||
MCFG_EEPROM_93C46_8BIT_ADD("mie_eeprom")
|
||||
|
||||
MCFG_NAOMI_DIMM_BOARD_ADD("rom_board", "gdrom", "user1", "picreturn")
|
||||
MCFG_NAOMI_DIMM_BOARD_ADD("rom_board", "gdrom", NULL, 512, "picreturn")
|
||||
MCFG_X76F100_ADD("naomibd_eeprom")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -443,7 +443,7 @@ static MACHINE_CONFIG_START( triforce_base, driver_device )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( triforcegd, triforce_base )
|
||||
MCFG_NAOMI_DIMM_BOARD_ADD("rom_board", "gdrom", "user1", "picreturn")
|
||||
MCFG_NAOMI_DIMM_BOARD_ADD("rom_board", "gdrom", NULL, 256, "picreturn")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \
|
||||
|
||||
@ -26,16 +26,17 @@ enum
|
||||
TYPE DEFINITIONS
|
||||
***************************************************************************/
|
||||
|
||||
typedef void (*naomibd_interrupt_func)(device_t *device, int state);
|
||||
typedef void (*naomibd_signal_func)(device_t *device, int signal, int state);
|
||||
|
||||
typedef struct _naomibd_config naomibd_config;
|
||||
struct _naomibd_config
|
||||
{
|
||||
int type;
|
||||
int size;
|
||||
const char * regiontag;
|
||||
const char * gdromregiontag;
|
||||
const char * picregiontag;
|
||||
naomibd_interrupt_func interrupt;
|
||||
naomibd_signal_func signal;
|
||||
};
|
||||
|
||||
|
||||
@ -56,10 +57,11 @@ struct _naomibd_config
|
||||
MCFG_NAOMIBD_ADD(_tag, AW_ROM_BOARD) \
|
||||
MCFG_NAOMIBD_REGION(_region)
|
||||
|
||||
#define MCFG_NAOMI_DIMM_BOARD_ADD(_tag, _gdrom, _region, _pic) \
|
||||
#define MCFG_NAOMI_DIMM_BOARD_ADD(_tag, _gdrom, _callback, _sizemb, _pic) \
|
||||
MCFG_NAOMIBD_ADD(_tag, DIMM_BOARD) \
|
||||
MCFG_NAOMIBD_REGION(_region) \
|
||||
MCFG_DEVICE_CONFIG_DATAPTR(naomibd_config, signal, _callback) \
|
||||
MCFG_NAOMIBD_GDROM_REGION(_gdrom) \
|
||||
MCFG_NAOMIBD_SIZE(_sizemb) \
|
||||
MCFG_NAOMIBD_PIC_REGION(_pic)
|
||||
|
||||
#define MCFG_NAOMIBD_REGION(_region) \
|
||||
@ -71,6 +73,9 @@ struct _naomibd_config
|
||||
#define MCFG_NAOMIBD_PIC_REGION(_region) \
|
||||
MCFG_DEVICE_CONFIG_DATAPTR(naomibd_config, picregiontag, _region)
|
||||
|
||||
#define MCFG_NAOMIBD_SIZE(_sizemb) \
|
||||
MCFG_DEVICE_CONFIG_DATA32(naomibd_config, size, _sizemb)
|
||||
|
||||
#define MCFG_NAOMIBD_MODIFY(_tag) \
|
||||
MCFG_DEVICE_MODIFY(_tag)
|
||||
|
||||
@ -84,7 +89,6 @@ struct _naomibd_config
|
||||
FUNCTION PROTOTYPES
|
||||
***************************************************************************/
|
||||
|
||||
int naomibd_interrupt_callback(device_t *device, naomibd_interrupt_func callback);
|
||||
int naomibd_get_type(device_t *device);
|
||||
void *naomibd_get_memory(device_t *device, UINT32 length);
|
||||
offs_t naomibd_get_dmaoffset(device_t *device);
|
||||
|
||||
@ -238,7 +238,9 @@ struct _naomibd_state
|
||||
|
||||
UINT8 * memory;
|
||||
chd_file * gdromchd;
|
||||
cdrom_file * gdrom;
|
||||
UINT8 * picdata;
|
||||
UINT32 size; /* size of installed dimm memory */
|
||||
UINT32 rom_offset, rom_offset_flags, dma_count;
|
||||
UINT32 dma_offset, dma_offset_flags;
|
||||
UINT32 prot_offset, prot_key;
|
||||
@ -351,11 +353,14 @@ INLINE naomibd_state *get_safe_token(device_t *device)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
int naomibd_interrupt_callback(device_t *device, naomibd_interrupt_func callback)
|
||||
// send interrupt to host system
|
||||
void output_interrupt(naomibd_state *st, int state)
|
||||
{
|
||||
naomibd_config *config = (naomibd_config *)downcast<const legacy_device_base *>(device)->inline_config();
|
||||
config->interrupt = callback;
|
||||
return 0;
|
||||
naomibd_config *config = (naomibd_config *)downcast<const legacy_device_base *>(st->device)->inline_config();
|
||||
|
||||
/* send out an interrupt */
|
||||
if (config->signal != NULL)
|
||||
(*config->signal)(st->device, 0, state); // 0: this signal is an interrupt
|
||||
}
|
||||
|
||||
int naomibd_get_type(device_t *device)
|
||||
@ -1438,6 +1443,8 @@ static void load_rom_gdrom(running_machine& machine, naomibd_state *v)
|
||||
}
|
||||
if (start != 0)
|
||||
{
|
||||
// check for size
|
||||
assert(size <= v->size);
|
||||
// read encrypted data into memory
|
||||
ptr = v->memory;
|
||||
sectors = (size+2047)/2048;
|
||||
@ -2093,7 +2100,9 @@ static DEVICE_START( naomibd )
|
||||
break;
|
||||
|
||||
case DIMM_BOARD:
|
||||
v->memory = (UINT8 *)auto_alloc_array_clear(device->machine(), UINT8, 0x40000000/4); // 0x40000000 is needed for some Chihiro sets, Naomi should be less, we should pass as device param
|
||||
assert((config->size >= 256) && !(config->size & 255)); // size multiple of 256 megabytes ?
|
||||
v->size = config->size << 20;
|
||||
v->memory = (UINT8 *)auto_alloc_array_clear(device->machine(), UINT8, v->size); // 0x40000000 is needed for some Chihiro sets, Naomi should be less
|
||||
v->gdromchd = get_disk_handle(device->machine(), config->gdromregiontag);
|
||||
v->picdata = (UINT8 *)device->machine().region(config->picregiontag)->base();
|
||||
if (v->memory != NULL && v->gdromchd != NULL && v->picdata != NULL)
|
||||
|
||||
@ -83,6 +83,8 @@ struct _options
|
||||
UINT8 flipped;
|
||||
int mode;
|
||||
const dasm_table_entry *dasm;
|
||||
UINT32 skip;
|
||||
UINT32 count;
|
||||
};
|
||||
|
||||
|
||||
@ -356,6 +358,8 @@ static int parse_options(int argc, char *argv[], options *opts)
|
||||
int pending_base = FALSE;
|
||||
int pending_arch = FALSE;
|
||||
int pending_mode = FALSE;
|
||||
int pending_skip = FALSE;
|
||||
int pending_count = FALSE;
|
||||
int curarch;
|
||||
int numrows;
|
||||
int arg;
|
||||
@ -370,7 +374,7 @@ static int parse_options(int argc, char *argv[], options *opts)
|
||||
// is it a switch?
|
||||
if (curarg[0] == '-')
|
||||
{
|
||||
if (pending_base || pending_arch || pending_mode)
|
||||
if (pending_base || pending_arch || pending_mode || pending_skip || pending_count)
|
||||
goto usage;
|
||||
|
||||
if (tolower((UINT8)curarg[1]) == 'a')
|
||||
@ -383,6 +387,10 @@ static int parse_options(int argc, char *argv[], options *opts)
|
||||
opts->lower = TRUE;
|
||||
else if (tolower((UINT8)curarg[1]) == 'm')
|
||||
pending_mode = TRUE;
|
||||
else if (tolower((UINT8)curarg[1]) == 's')
|
||||
pending_skip = TRUE;
|
||||
else if (tolower((UINT8)curarg[1]) == 'c')
|
||||
pending_count = TRUE;
|
||||
else if (tolower((UINT8)curarg[1]) == 'n')
|
||||
opts->norawbytes = TRUE;
|
||||
else if (tolower((UINT8)curarg[1]) == 'u')
|
||||
@ -426,6 +434,22 @@ static int parse_options(int argc, char *argv[], options *opts)
|
||||
pending_arch = FALSE;
|
||||
}
|
||||
|
||||
// skip bytes
|
||||
else if (pending_skip)
|
||||
{
|
||||
if (sscanf(curarg, "%d", &opts->skip) != 1)
|
||||
goto usage;
|
||||
pending_skip = FALSE;
|
||||
}
|
||||
|
||||
// size
|
||||
else if (pending_count)
|
||||
{
|
||||
if (sscanf(curarg, "%d", &opts->count) != 1)
|
||||
goto usage;
|
||||
pending_count = FALSE;
|
||||
}
|
||||
|
||||
// filename
|
||||
else if (opts->filename == NULL)
|
||||
opts->filename = curarg;
|
||||
@ -436,7 +460,7 @@ static int parse_options(int argc, char *argv[], options *opts)
|
||||
}
|
||||
|
||||
// if we have a dangling option, error
|
||||
if (pending_base || pending_arch || pending_mode)
|
||||
if (pending_base || pending_arch || pending_mode || pending_skip || pending_count)
|
||||
goto usage;
|
||||
|
||||
// if no file or no architecture, fail
|
||||
@ -447,6 +471,7 @@ static int parse_options(int argc, char *argv[], options *opts)
|
||||
usage:
|
||||
printf("Usage: %s <filename> -arch <architecture> [-basepc <pc>] \n", argv[0]);
|
||||
printf(" [-mode <n>] [-norawbytes] [-flipped] [-upper] [-lower]\n");
|
||||
printf(" [-skip <n>] [-count <n>]\n");
|
||||
printf("\n");
|
||||
printf("Supported architectures:");
|
||||
numrows = (ARRAY_LENGTH(dasm_table) + 6) / 7;
|
||||
@ -504,10 +529,14 @@ int main(int argc, char *argv[])
|
||||
// run it
|
||||
try
|
||||
{
|
||||
if (length > opts.skip)
|
||||
length = length - opts.skip;
|
||||
if ((length > opts.count) && (opts.count != 0))
|
||||
length = opts.count;
|
||||
curpc = opts.basepc;
|
||||
for (curbyte = 0; curbyte < length; curbyte += numbytes)
|
||||
{
|
||||
UINT8 *oprom = (UINT8 *)data + curbyte;
|
||||
UINT8 *oprom = (UINT8 *)data + opts.skip + curbyte;
|
||||
char buffer[1024];
|
||||
UINT32 pcdelta;
|
||||
int numchunks;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user