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fix line endings

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This commit is contained in:
miodragm 2014-10-27 18:50:29 +01:00
parent 0b6577ccc0
commit ff6a09c72f
2 changed files with 171 additions and 171 deletions
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14
src/mame/drivers/jackie.c
View File

@ -264,13 +264,13 @@ void jackie_state::machine_reset()
}
void jackie_state::show_out()
{
#ifdef MAME_DEBUG
// popmessage("%02x %02x %02x", m_out[0], m_out[1], m_out[2]);
popmessage("520: %04x %04x %04x %04x %04x\n560: %04x %04x %04x %04x %04x\n5A0: %04x %04x %04x %04x %04x",
m_unk_reg[0][0],m_unk_reg[0][1],m_unk_reg[0][2],m_unk_reg[0][3],m_unk_reg[0][4],
m_unk_reg[1][0],m_unk_reg[1][1],m_unk_reg[1][2],m_unk_reg[1][3],m_unk_reg[1][4],
void jackie_state::show_out()
{
#ifdef MAME_DEBUG
// popmessage("%02x %02x %02x", m_out[0], m_out[1], m_out[2]);
popmessage("520: %04x %04x %04x %04x %04x\n560: %04x %04x %04x %04x %04x\n5A0: %04x %04x %04x %04x %04x",
m_unk_reg[0][0],m_unk_reg[0][1],m_unk_reg[0][2],m_unk_reg[0][3],m_unk_reg[0][4],
m_unk_reg[1][0],m_unk_reg[1][1],m_unk_reg[1][2],m_unk_reg[1][3],m_unk_reg[1][4],
m_unk_reg[2][0],m_unk_reg[2][1],m_unk_reg[2][2],m_unk_reg[2][3],m_unk_reg[2][4]
);
#endif

328
src/mame/drivers/peplus.c
View File

@ -203,49 +203,49 @@ public:
{
TIMER_ASSERT_LP
};
peplus_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_crtc(*this, "crtc"),
m_i2cmem(*this, "i2cmem"),
m_screen(*this, "screen"),
m_gfxdecode(*this, "gfxdecode"),
m_palette(*this, "palette"),
m_cmos_ram(*this, "cmos"),
m_program_ram(*this, "prograram"),
m_s3000_ram(*this, "s3000_ram"),
m_s5000_ram(*this, "s5000_ram"),
peplus_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_crtc(*this, "crtc"),
m_i2cmem(*this, "i2cmem"),
m_screen(*this, "screen"),
m_gfxdecode(*this, "gfxdecode"),
m_palette(*this, "palette"),
m_cmos_ram(*this, "cmos"),
m_program_ram(*this, "prograram"),
m_s3000_ram(*this, "s3000_ram"),
m_s5000_ram(*this, "s5000_ram"),
m_videoram(*this, "videoram"),
m_s7000_ram(*this, "s7000_ram"),
m_sb000_ram(*this, "sb000_ram"),
m_sd000_ram(*this, "sd000_ram"),
m_sf000_ram(*this, "sf000_ram"),
m_io_port(*this, "io_port")
{
}
required_device<cpu_device> m_maincpu;
required_device<r6545_1_device> m_crtc;
required_device<i2cmem_device> m_i2cmem;
required_device<screen_device> m_screen;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
required_shared_ptr<UINT8> m_cmos_ram;
required_shared_ptr<UINT8> m_program_ram;
required_shared_ptr<UINT8> m_s3000_ram;
m_sb000_ram(*this, "sb000_ram"),
m_sd000_ram(*this, "sd000_ram"),
m_sf000_ram(*this, "sf000_ram"),
m_io_port(*this, "io_port")
{
}
required_device<cpu_device> m_maincpu;
required_device<r6545_1_device> m_crtc;
required_device<i2cmem_device> m_i2cmem;
required_device<screen_device> m_screen;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
required_shared_ptr<UINT8> m_cmos_ram;
required_shared_ptr<UINT8> m_program_ram;
required_shared_ptr<UINT8> m_s3000_ram;
required_shared_ptr<UINT8> m_s5000_ram;
required_shared_ptr<UINT8> m_videoram;
required_shared_ptr<UINT8> m_s7000_ram;
required_shared_ptr<UINT8> m_sb000_ram;
required_shared_ptr<UINT8> m_sd000_ram;
required_shared_ptr<UINT8> m_sf000_ram;
required_shared_ptr<UINT8> m_io_port;
tilemap_t *m_bg_tilemap;
UINT8 m_wingboard;
UINT8 m_doorcycle;
required_shared_ptr<UINT8> m_sd000_ram;
required_shared_ptr<UINT8> m_sf000_ram;
required_shared_ptr<UINT8> m_io_port;
tilemap_t *m_bg_tilemap;
UINT8 m_wingboard;
UINT8 m_doorcycle;
UINT16 door_wait;
UINT8 m_jumper_e16_e17;
UINT16 m_vid_address;
@ -267,21 +267,21 @@ public:
UINT8 m_bv_last_enable_state;
UINT8 m_bv_enable_state;
UINT8 m_bv_enable_count;
UINT8 m_bv_data_bit;
UINT8 m_bv_loop_count;
UINT16 id023_data;
DECLARE_WRITE8_MEMBER(peplus_bgcolor_w);
DECLARE_WRITE8_MEMBER(peplus_crtc_display_w);
DECLARE_WRITE8_MEMBER(peplus_duart_w);
DECLARE_WRITE8_MEMBER(peplus_cmos_w);
DECLARE_WRITE8_MEMBER(peplus_output_bank_a_w);
DECLARE_WRITE8_MEMBER(peplus_output_bank_b_w);
DECLARE_WRITE8_MEMBER(peplus_output_bank_c_w);
DECLARE_READ8_MEMBER(peplus_duart_r);
DECLARE_READ8_MEMBER(peplus_bgcolor_r);
DECLARE_READ8_MEMBER(peplus_dropdoor_r);
DECLARE_READ8_MEMBER(peplus_watchdog_r);
UINT8 m_bv_data_bit;
UINT8 m_bv_loop_count;
UINT16 id023_data;
DECLARE_WRITE8_MEMBER(peplus_bgcolor_w);
DECLARE_WRITE8_MEMBER(peplus_crtc_display_w);
DECLARE_WRITE8_MEMBER(peplus_duart_w);
DECLARE_WRITE8_MEMBER(peplus_cmos_w);
DECLARE_WRITE8_MEMBER(peplus_output_bank_a_w);
DECLARE_WRITE8_MEMBER(peplus_output_bank_b_w);
DECLARE_WRITE8_MEMBER(peplus_output_bank_c_w);
DECLARE_READ8_MEMBER(peplus_duart_r);
DECLARE_READ8_MEMBER(peplus_bgcolor_r);
DECLARE_READ8_MEMBER(peplus_dropdoor_r);
DECLARE_READ8_MEMBER(peplus_watchdog_r);
DECLARE_CUSTOM_INPUT_MEMBER(peplus_input_r);
DECLARE_WRITE8_MEMBER(peplus_crtc_mode_w);
DECLARE_WRITE_LINE_MEMBER(crtc_vsync);
@ -296,13 +296,13 @@ public:
MC6845_ON_UPDATE_ADDR_CHANGED(crtc_addr);
virtual void machine_reset();
virtual void video_start();
UINT32 screen_update_peplus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void peplus_load_superdata(const char *bank_name);
DECLARE_PALETTE_INIT(peplus);
void handle_lightpen();
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
UINT32 screen_update_peplus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void peplus_load_superdata(const char *bank_name);
DECLARE_PALETTE_INIT(peplus);
void handle_lightpen();
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
};
static const UINT8 id_022[8] = { 0x00, 0x01, 0x04, 0x09, 0x13, 0x16, 0x18, 0x00 };
@ -382,50 +382,50 @@ WRITE8_MEMBER(peplus_state::peplus_crtc_mode_w)
void peplus_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_ASSERT_LP:
m_crtc->assert_light_pen_input();
break;
default:
assert_always(FALSE, "Unknown id in peplus_state::device_timer");
switch (id)
{
case TIMER_ASSERT_LP:
m_crtc->assert_light_pen_input();
break;
default:
assert_always(FALSE, "Unknown id in peplus_state::device_timer");
}
}
void peplus_state::handle_lightpen()
{
int x_val = ioport("TOUCH_X")->read_safe(0x00);
int y_val = ioport("TOUCH_Y")->read_safe(0x00);
const rectangle &vis_area = m_screen->visible_area();
int xt, yt;
xt = x_val * vis_area.width() / 1024 + vis_area.min_x;
yt = y_val * vis_area.height() / 1024 + vis_area.min_y;
timer_set(m_screen->time_until_pos(yt, xt), TIMER_ASSERT_LP, 0);
}
WRITE_LINE_MEMBER(peplus_state::crtc_vsync)
{
m_maincpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
handle_lightpen();
}
WRITE8_MEMBER(peplus_state::peplus_crtc_display_w)
}
void peplus_state::handle_lightpen()
{
int x_val = ioport("TOUCH_X")->read_safe(0x00);
int y_val = ioport("TOUCH_Y")->read_safe(0x00);
const rectangle &vis_area = m_screen->visible_area();
int xt, yt;
xt = x_val * vis_area.width() / 1024 + vis_area.min_x;
yt = y_val * vis_area.height() / 1024 + vis_area.min_y;
timer_set(m_screen->time_until_pos(yt, xt), TIMER_ASSERT_LP, 0);
}
WRITE_LINE_MEMBER(peplus_state::crtc_vsync)
{
m_maincpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
handle_lightpen();
}
WRITE8_MEMBER(peplus_state::peplus_crtc_display_w)
{
UINT8 *videoram = m_videoram;
videoram[m_vid_address] = data;
m_palette_ram[m_vid_address] = m_io_port[1];
m_palette_ram2[m_vid_address] = m_io_port[3];
m_bg_tilemap->mark_tile_dirty(m_vid_address);
/* An access here triggers a device read !*/
m_crtc->register_r(space, 0);
}
WRITE8_MEMBER(peplus_state::peplus_duart_w)
m_bg_tilemap->mark_tile_dirty(m_vid_address);
/* An access here triggers a device read !*/
m_crtc->register_r(space, 0);
}
WRITE8_MEMBER(peplus_state::peplus_duart_w)
{
// Used for Slot Accounting System Communication
}
@ -441,12 +441,12 @@ WRITE8_MEMBER(peplus_state::peplus_cmos_w)
peplus_load_superdata(bank_name);
}
m_cmos_ram[offset] = data;
}
WRITE8_MEMBER(peplus_state::peplus_output_bank_a_w)
{
output_set_value("pe_bnka0",(data >> 0) & 1); /* Coin Lockout */
m_cmos_ram[offset] = data;
}
WRITE8_MEMBER(peplus_state::peplus_output_bank_a_w)
{
output_set_value("pe_bnka0",(data >> 0) & 1); /* Coin Lockout */
output_set_value("pe_bnka1",(data >> 1) & 1); /* Diverter */
output_set_value("pe_bnka2",(data >> 2) & 1); /* Bell */
output_set_value("pe_bnka3",(data >> 3) & 1); /* N/A */
@ -495,18 +495,18 @@ WRITE8_MEMBER(peplus_state::i2c_nvram_w)
/****************
* Read Handlers *
****************/
READ8_MEMBER(peplus_state::peplus_duart_r)
{
// Used for Slot Accounting System Communication
return 0x00;
}
/* Last Color in Every Palette is bgcolor */
READ8_MEMBER(peplus_state::peplus_bgcolor_r)
{
* Read Handlers *
****************/
READ8_MEMBER(peplus_state::peplus_duart_r)
{
// Used for Slot Accounting System Communication
return 0x00;
}
/* Last Color in Every Palette is bgcolor */
READ8_MEMBER(peplus_state::peplus_bgcolor_r)
{
return m_palette->pen_color(15); // Return bgcolor from First Palette
}
@ -969,65 +969,65 @@ GFXDECODE_END
static ADDRESS_MAP_START( peplus_map, AS_PROGRAM, 8, peplus_state )
AM_RANGE(0x0000, 0xffff) AM_ROM AM_SHARE("prograram")
ADDRESS_MAP_END
static ADDRESS_MAP_START( peplus_iomap, AS_IO, 8, peplus_state )
// Battery-backed RAM (0x1000-0x01fff Extended RAM for Superboards Only)
AM_RANGE(0x0000, 0x1fff) AM_RAM_WRITE(peplus_cmos_w) AM_SHARE("cmos")
// CRT Controller
AM_RANGE(0x2008, 0x2008) AM_WRITE(peplus_crtc_mode_w)
static ADDRESS_MAP_START( peplus_iomap, AS_IO, 8, peplus_state )
// Battery-backed RAM (0x1000-0x01fff Extended RAM for Superboards Only)
AM_RANGE(0x0000, 0x1fff) AM_RAM_WRITE(peplus_cmos_w) AM_SHARE("cmos")
// CRT Controller
AM_RANGE(0x2008, 0x2008) AM_WRITE(peplus_crtc_mode_w)
AM_RANGE(0x2080, 0x2080) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
AM_RANGE(0x2081, 0x2081) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
AM_RANGE(0x2083, 0x2083) AM_DEVREAD("crtc", mc6845_device, register_r) AM_WRITE(peplus_crtc_display_w)
// Superboard Data
AM_RANGE(0x3000, 0x3fff) AM_RAM AM_SHARE("s3000_ram")
// Sound and Dipswitches
AM_RANGE(0x4000, 0x4000) AM_DEVWRITE("aysnd", ay8910_device, address_w)
AM_RANGE(0x4004, 0x4004) AM_READ_PORT("SW1")/* likely ay8910 input port, not direct */ AM_DEVWRITE("aysnd", ay8910_device, data_w)
// Superboard Data
AM_RANGE(0x5000, 0x5fff) AM_RAM AM_SHARE("s5000_ram")
// Background Color Latch
AM_RANGE(0x6000, 0x6000) AM_READ(peplus_bgcolor_r) AM_WRITE(peplus_bgcolor_w)
AM_RANGE(0x2083, 0x2083) AM_DEVREAD("crtc", mc6845_device, register_r) AM_WRITE(peplus_crtc_display_w)
// Superboard Data
AM_RANGE(0x3000, 0x3fff) AM_RAM AM_SHARE("s3000_ram")
// Sound and Dipswitches
AM_RANGE(0x4000, 0x4000) AM_DEVWRITE("aysnd", ay8910_device, address_w)
AM_RANGE(0x4004, 0x4004) AM_READ_PORT("SW1")/* likely ay8910 input port, not direct */ AM_DEVWRITE("aysnd", ay8910_device, data_w)
// Superboard Data
AM_RANGE(0x5000, 0x5fff) AM_RAM AM_SHARE("s5000_ram")
// Background Color Latch
AM_RANGE(0x6000, 0x6000) AM_READ(peplus_bgcolor_r) AM_WRITE(peplus_bgcolor_w)
// Bogus Location for Video RAM
AM_RANGE(0x06001, 0x06400) AM_RAM AM_SHARE("videoram")
// Superboard Data
AM_RANGE(0x7000, 0x7fff) AM_RAM AM_SHARE("s7000_ram")
// Input Bank A, Output Bank C
AM_RANGE(0x8000, 0x8000) AM_READ(peplus_input_bank_a_r) AM_WRITE(peplus_output_bank_c_w)
AM_RANGE(0x06001, 0x06400) AM_RAM AM_SHARE("videoram")
// Superboard Data
AM_RANGE(0x7000, 0x7fff) AM_RAM AM_SHARE("s7000_ram")
// Input Bank A, Output Bank C
AM_RANGE(0x8000, 0x8000) AM_READ(peplus_input_bank_a_r) AM_WRITE(peplus_output_bank_c_w)
// Drop Door, I2C EEPROM Writes
AM_RANGE(0x9000, 0x9000) AM_READ(peplus_dropdoor_r) AM_WRITE(i2c_nvram_w)
// Input Banks B & C, Output Bank B
AM_RANGE(0xa000, 0xa000) AM_READ(peplus_input0_r) AM_WRITE(peplus_output_bank_b_w)
// Superboard Data
AM_RANGE(0xb000, 0xbfff) AM_RAM AM_SHARE("sb000_ram")
// Output Bank A
AM_RANGE(0xc000, 0xc000) AM_READ(peplus_watchdog_r) AM_WRITE(peplus_output_bank_a_w)
// Superboard Data
AM_RANGE(0xd000, 0xdfff) AM_RAM AM_SHARE("sd000_ram")
// DUART
AM_RANGE(0xe000, 0xe00f) AM_READWRITE(peplus_duart_r, peplus_duart_w)
// Superboard Data
AM_RANGE(0xf000, 0xffff) AM_RAM AM_SHARE("sf000_ram")
/* Ports start here */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_RAM AM_SHARE("io_port")
ADDRESS_MAP_END
AM_RANGE(0xa000, 0xa000) AM_READ(peplus_input0_r) AM_WRITE(peplus_output_bank_b_w)
// Superboard Data
AM_RANGE(0xb000, 0xbfff) AM_RAM AM_SHARE("sb000_ram")
// Output Bank A
AM_RANGE(0xc000, 0xc000) AM_READ(peplus_watchdog_r) AM_WRITE(peplus_output_bank_a_w)
// Superboard Data
AM_RANGE(0xd000, 0xdfff) AM_RAM AM_SHARE("sd000_ram")
// DUART
AM_RANGE(0xe000, 0xe00f) AM_READWRITE(peplus_duart_r, peplus_duart_w)
// Superboard Data
AM_RANGE(0xf000, 0xffff) AM_RAM AM_SHARE("sf000_ram")
/* Ports start here */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_RAM AM_SHARE("io_port")
ADDRESS_MAP_END
/*************************
* Input ports *
*************************/