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vrc5074: Only clear edge triggered interrupts and initialize timer from counter register. (nw)

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This commit is contained in:
Ted Green 2018-01-18 17:20:28 -07:00
parent 6b95ab4c88
commit ff77ea54f1
1 changed files with 12 additions and 11 deletions
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23
src/devices/machine/vrc5074.cpp
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@ -788,20 +788,20 @@ READ32_MEMBER(vrc5074_device::cpu_reg_r)
case NREG_INTCTRL + 0: /* Interrupt control */ case NREG_INTCTRL + 0: /* Interrupt control */
case NREG_INTCTRL + 1: /* Interrupt control */ case NREG_INTCTRL + 1: /* Interrupt control */
if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE READ: interrupt control(%03X) = %08X\n", machine().describe_context(), offset * 4, result); if (LOG_NILE) logerror("%s NILE READ: interrupt control(%03X) = %08X\n", machine().describe_context(), offset * 4, result);
update_nile_irqs(); //update_nile_irqs();
logit = 0; logit = 0;
break; break;
case NREG_INTSTAT0 + 0: /* Interrupt status 0 */ case NREG_INTSTAT0 + 0: /* Interrupt status 0 */
case NREG_INTSTAT0 + 1: /* Interrupt status 0 */ case NREG_INTSTAT0 + 1: /* Interrupt status 0 */
if (LOG_NILE) logerror("%s NILE READ: interrupt status 0(%03X) = %08X\n", machine().describe_context(), offset * 4, result); if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE READ: interrupt status 0(%03X) = %08X\n", machine().describe_context(), offset * 4, result);
logit = 0; logit = 0;
break; break;
case NREG_INTSTAT1 + 0: /* Interrupt status 1 */ case NREG_INTSTAT1 + 0: /* Interrupt status 1 */
case NREG_INTSTAT1 + 1: /* Interrupt status 1 */ case NREG_INTSTAT1 + 1: /* Interrupt status 1 */
if (LOG_NILE) logerror("%s NILE READ: interrupt status 1/enable(%03X) = %08X\n", machine().describe_context(), offset * 4, result); if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE READ: interrupt status 1/enable(%03X) = %08X\n", machine().describe_context(), offset * 4, result);
logit = 0; logit = 0;
break; break;
@ -899,24 +899,25 @@ WRITE32_MEMBER(vrc5074_device::cpu_reg_w)
case NREG_INTSTAT0 + 0: /* Interrupt status 0 */ case NREG_INTSTAT0 + 0: /* Interrupt status 0 */
case NREG_INTSTAT0 + 1: /* Interrupt status 0 */ case NREG_INTSTAT0 + 1: /* Interrupt status 0 */
if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt status 0(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt status 0/1(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask);
logit = 0; logit = 0;
update_nile_irqs(); //update_nile_irqs();
break; break;
case NREG_INTSTAT1 + 0: /* Interrupt status 1 */ case NREG_INTSTAT1 + 0: /* Interrupt status 1 */
case NREG_INTSTAT1 + 1: /* Interrupt status 1 */ case NREG_INTSTAT1 + 1: /* Interrupt status 1 */
if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt status 1/enable(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt status 0/1 enable(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask);
logit = 0; logit = 0;
update_nile_irqs(); //update_nile_irqs();
break; break;
case NREG_INTCLR + 0: /* Interrupt clear */ case NREG_INTCLR + 0: /* Interrupt clear */
//case NREG_INTCLR + 1: /* Interrupt clear */ //case NREG_INTCLR + 1: /* Interrupt clear */
if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt clear(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt clear(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask);
logit = 0; logit = 0;
//m_nile_irq_state &= ~(m_cpu_regs[offset] & ~0xf00); // Only edge triggered interrupts are cleared
m_nile_irq_state &= ~(data); // TODO: Check which are edge triggered for midway vegas it is only the lower (non-pci) interrupts
m_nile_irq_state &= ~(m_cpu_regs[offset] & ~0xf00);
update_nile_irqs(); update_nile_irqs();
break; break;
@ -966,7 +967,7 @@ WRITE32_MEMBER(vrc5074_device::cpu_reg_w)
/* timer just enabled? */ /* timer just enabled? */
if (!(olddata & 1) && (m_cpu_regs[offset] & 1)) if (!(olddata & 1) && (m_cpu_regs[offset] & 1))
{ {
m_timer[which]->adjust(attotime::from_double(m_timer_period[which]), which); m_timer[which]->adjust(attotime::from_hz(SYSTEM_CLOCK) * m_cpu_regs[NREG_T0CNTR + which * 4], which);
if (LOG_TIMERS) logerror("Starting timer %d at a rate of %f Hz\n", which, ATTOSECONDS_TO_HZ(attotime::from_double(m_timer_period[which]).as_attoseconds())); if (LOG_TIMERS) logerror("Starting timer %d at a rate of %f Hz\n", which, ATTOSECONDS_TO_HZ(attotime::from_double(m_timer_period[which]).as_attoseconds()));
} }