diff --git a/src/mame/drivers/39in1.c b/src/mame/drivers/39in1.c index 10990e6a19d..38bd1bdc47d 100644 --- a/src/mame/drivers/39in1.c +++ b/src/mame/drivers/39in1.c @@ -27,9 +27,32 @@ #include "machine/pxa255.h" #include "sound/dmadac.h" -static UINT32* ram; +typedef struct __39in1_state _39in1_state; +struct __39in1_state +{ + UINT32 seed; + UINT32 magic; + UINT32 state; + + UINT32* ram; + + PXA255_DMA_Regs dma_regs; + PXA255_I2S_Regs i2s_regs; + PXA255_OSTMR_Regs ostimer_regs; + PXA255_INTC_Regs intc_regs; + PXA255_GPIO_Regs gpio_regs; + PXA255_LCD_Regs lcd_regs; + + running_device *dmadac[2]; + running_device *eeprom; + UINT32 pxa255_lcd_palette[0x100]; + UINT8 pxa255_lcd_framebuffer[0x100000]; + + //FILE* audio_dump; + UINT32 words[0x800]; + INT16 samples[0x1000]; +}; -static running_device *dmadac[2]; static void pxa255_dma_irq_check(running_machine* machine); static READ32_HANDLER( pxa255_dma_r ); @@ -51,8 +74,6 @@ static WRITE32_HANDLER( pxa255_intc_w ); static READ32_HANDLER( pxa255_gpio_r ); static WRITE32_HANDLER( pxa255_gpio_w ); -static UINT32 pxa255_lcd_palette[0x100]; -static UINT8 pxa255_lcd_framebuffer[0x100000]; static void pxa255_lcd_load_dma_descriptor(const address_space* space, UINT32 address, int channel); static void pxa255_lcd_irq_check(running_machine* machine); static void pxa255_lcd_dma_kickoff(running_machine* machine, int channel); @@ -60,13 +81,6 @@ static void pxa255_lcd_check_load_next_branch(running_machine* machine, int chan static READ32_HANDLER( pxa255_lcd_r ); static WRITE32_HANDLER( pxa255_lcd_w ); -static PXA255_DMA_Regs dma_regs; -static PXA255_I2S_Regs i2s_regs; -static PXA255_OSTMR_Regs ostimer_regs; -static PXA255_INTC_Regs intc_regs; -static PXA255_GPIO_Regs gpio_regs; -static PXA255_LCD_Regs lcd_regs; - #define VERBOSE_LEVEL ( 3 ) INLINE void ATTR_PRINTF(3,4) verboselog( running_machine* machine, int n_level, const char* s_fmt, ... ) @@ -93,29 +107,32 @@ INLINE void ATTR_PRINTF(3,4) verboselog( running_machine* machine, int n_level, static READ32_HANDLER( pxa255_i2s_r ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_I2S_Regs *i2s_regs = &state->i2s_regs; + switch(PXA255_I2S_BASE_ADDR | (offset << 2)) { case PXA255_SACR0: - verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Controller Global Control Register: %08x & %08x\n", i2s_regs.sacr0, mem_mask ); - return i2s_regs.sacr0; + verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Controller Global Control Register: %08x & %08x\n", i2s_regs->sacr0, mem_mask ); + return i2s_regs->sacr0; case PXA255_SACR1: - verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", i2s_regs.sacr1, mem_mask ); - return i2s_regs.sacr1; + verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", i2s_regs->sacr1, mem_mask ); + return i2s_regs->sacr1; case PXA255_SASR0: - verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", i2s_regs.sasr0, mem_mask ); - return i2s_regs.sasr0; + verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", i2s_regs->sasr0, mem_mask ); + return i2s_regs->sasr0; case PXA255_SAIMR: - verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Interrupt Mask Register: %08x & %08x\n", i2s_regs.saimr, mem_mask ); - return i2s_regs.saimr; + verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Interrupt Mask Register: %08x & %08x\n", i2s_regs->saimr, mem_mask ); + return i2s_regs->saimr; case PXA255_SAICR: - verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Interrupt Clear Register: %08x & %08x\n", i2s_regs.saicr, mem_mask ); - return i2s_regs.saicr; + verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Interrupt Clear Register: %08x & %08x\n", i2s_regs->saicr, mem_mask ); + return i2s_regs->saicr; case PXA255_SADIV: - verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Clock Divider Register: %08x & %08x\n", i2s_regs.sadiv, mem_mask ); - return i2s_regs.sadiv; + verboselog( space->machine, 3, "pxa255_i2s_r: Serial Audio Clock Divider Register: %08x & %08x\n", i2s_regs->sadiv, mem_mask ); + return i2s_regs->sadiv; case PXA255_SADR: - verboselog( space->machine, 5, "pxa255_i2s_r: Serial Audio Data Register: %08x & %08x\n", i2s_regs.sadr, mem_mask ); - return i2s_regs.sadr; + verboselog( space->machine, 5, "pxa255_i2s_r: Serial Audio Data Register: %08x & %08x\n", i2s_regs->sadr, mem_mask ); + return i2s_regs->sadr; default: verboselog( space->machine, 0, "pxa255_i2s_r: Unknown address: %08x\n", PXA255_I2S_BASE_ADDR | (offset << 2)); break; @@ -123,68 +140,70 @@ static READ32_HANDLER( pxa255_i2s_r ) return 0; } -//static FILE* audio_dump = NULL; - static WRITE32_HANDLER( pxa255_i2s_w ) { - /* - if(!audio_dump) - { - int count = 0; - char filename[256]; - do - { - sprintf(filename, "39in1_%04d.raw", count++); - audio_dump = fopen(filename, "rb"); - }while(audio_dump != NULL); - count--; - sprintf(filename, "39in1_%04d.raw", count); - audio_dump = fopen(filename, "wb"); - }*/ + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_I2S_Regs *i2s_regs = &state->i2s_regs; + +#if 0 + if(!audio_dump) + { + int count = 0; + char filename[256]; + do + { + sprintf(filename, "39in1_%04d.raw", count++); + audio_dump = fopen(filename, "rb"); + }while(audio_dump != NULL); + count--; + sprintf(filename, "39in1_%04d.raw", count); + audio_dump = fopen(filename, "wb"); + } +#endif switch(PXA255_I2S_BASE_ADDR | (offset << 2)) { case PXA255_SACR0: verboselog( space->machine, 3, "pxa255_i2s_w: Serial Audio Controller Global Control Register: %08x & %08x\n", data, mem_mask ); - i2s_regs.sacr0 = data & 0x0000ff3d; + i2s_regs->sacr0 = data & 0x0000ff3d; break; case PXA255_SACR1: verboselog( space->machine, 3, "pxa255_i2s_w: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", data, mem_mask ); - i2s_regs.sacr1 = data & 0x00000039; + i2s_regs->sacr1 = data & 0x00000039; break; case PXA255_SASR0: verboselog( space->machine, 3, "pxa255_i2s_w: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", data, mem_mask ); - i2s_regs.sasr0 = data & 0x0000ff7f; + i2s_regs->sasr0 = data & 0x0000ff7f; break; case PXA255_SAIMR: verboselog( space->machine, 3, "pxa255_i2s_w: Serial Audio Interrupt Mask Register: %08x & %08x\n", data, mem_mask ); - i2s_regs.saimr = data & 0x00000078; + i2s_regs->saimr = data & 0x00000078; break; case PXA255_SAICR: verboselog( space->machine, 3, "pxa255_i2s_w: Serial Audio Interrupt Clear Register: %08x & %08x\n", data, mem_mask ); - if(i2s_regs.saicr & PXA255_SAICR_ROR) + if(i2s_regs->saicr & PXA255_SAICR_ROR) { - i2s_regs.sasr0 &= ~PXA255_SASR0_ROR; + i2s_regs->sasr0 &= ~PXA255_SASR0_ROR; } - if(i2s_regs.saicr & PXA255_SAICR_TUR) + if(i2s_regs->saicr & PXA255_SAICR_TUR) { - i2s_regs.sasr0 &= ~PXA255_SASR0_TUR; + i2s_regs->sasr0 &= ~PXA255_SASR0_TUR; } break; case PXA255_SADIV: verboselog( space->machine, 3, "pxa255_i2s_w: Serial Audio Clock Divider Register: %08x & %08x\n", data, mem_mask ); - i2s_regs.sadiv = data & 0x0000007f; - dmadac[0] = devtag_get_device(space->machine, "dac1"); - dmadac[1] = devtag_get_device(space->machine, "dac2"); - dmadac_set_frequency(&dmadac[0], 2, ((double)147600000 / (double)i2s_regs.sadiv) / 256.0); - dmadac_enable(&dmadac[0], 2, 1); + i2s_regs->sadiv = data & 0x0000007f; + dmadac_set_frequency(&state->dmadac[0], 2, ((double)147600000 / (double)i2s_regs->sadiv) / 256.0); + dmadac_enable(&state->dmadac[0], 2, 1); break; case PXA255_SADR: verboselog( space->machine, 4, "pxa255_i2s_w: Serial Audio Data Register: %08x & %08x\n", data, mem_mask ); - i2s_regs.sadr = data; - /*if(audio_dump) - { - fwrite(&data, 4, 1, audio_dump); - }*/ + i2s_regs->sadr = data; +#if 0 + if(audio_dump) + { + fwrite(&data, 4, 1, audio_dump); + } +#endif break; default: verboselog( space->machine, 0, "pxa255_i2s_w: Unknown address: %08x = %08x & %08x\n", PXA255_I2S_BASE_ADDR | (offset << 2), data, mem_mask); @@ -202,92 +221,97 @@ static WRITE32_HANDLER( pxa255_i2s_w ) static void pxa255_dma_irq_check(running_machine* machine) { + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_DMA_Regs *dma_regs = &state->dma_regs; int channel = 0; int set_intr = 0; + for(channel = 0; channel < 16; channel++) { - if(dma_regs.dcsr[channel] & (PXA255_DCSR_ENDINTR | PXA255_DCSR_STARTINTR | PXA255_DCSR_BUSERRINTR)) + if (dma_regs->dcsr[channel] & (PXA255_DCSR_ENDINTR | PXA255_DCSR_STARTINTR | PXA255_DCSR_BUSERRINTR)) { - dma_regs.dint |= 1 << channel; + dma_regs->dint |= 1 << channel; set_intr = 1; } else { - dma_regs.dint &= ~(1 << channel); + dma_regs->dint &= ~(1 << channel); } } + pxa255_set_irq_line(machine, PXA255_INT_DMA, set_intr); } static void pxa255_dma_load_descriptor_and_start(running_machine* machine, int channel) { + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_DMA_Regs *dma_regs = &state->dma_regs; attotime period; // Shut down any transfers that are currently going on, software should be smart enough to check if a // transfer is running before starting another one on the same channel. - if(timer_enabled(dma_regs.timer[channel])) + if (timer_enabled(dma_regs->timer[channel])) { - timer_adjust_oneshot(dma_regs.timer[channel], attotime_never, 0); + timer_adjust_oneshot(dma_regs->timer[channel], attotime_never, 0); } // Load the next descriptor - dma_regs.dsadr[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs.ddadr[channel] + 0x4); - dma_regs.dtadr[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs.ddadr[channel] + 0x8); - dma_regs.dcmd[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs.ddadr[channel] + 0xc); - dma_regs.ddadr[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs.ddadr[channel]); + dma_regs->dsadr[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs->ddadr[channel] + 0x4); + dma_regs->dtadr[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs->ddadr[channel] + 0x8); + dma_regs->dcmd[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs->ddadr[channel] + 0xc); + dma_regs->ddadr[channel] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), dma_regs->ddadr[channel]); // Start our end-of-transfer timer switch(channel) { case 3: - period = attotime_mul(ATTOTIME_IN_HZ((147600000 / i2s_regs.sadiv) / (4 * 64)), dma_regs.dcmd[channel] & 0x00001fff); + period = attotime_mul(ATTOTIME_IN_HZ((147600000 / state->i2s_regs.sadiv) / (4 * 64)), dma_regs->dcmd[channel] & 0x00001fff); break; default: - period = attotime_mul(ATTOTIME_IN_HZ(100000000), dma_regs.dcmd[channel] & 0x00001fff); + period = attotime_mul(ATTOTIME_IN_HZ(100000000), dma_regs->dcmd[channel] & 0x00001fff); break; } - timer_adjust_oneshot(dma_regs.timer[channel], period, channel); + timer_adjust_oneshot(dma_regs->timer[channel], period, channel); // Interrupt as necessary - if(dma_regs.dcmd[channel] & PXA255_DCMD_STARTIRQEN) + if(dma_regs->dcmd[channel] & PXA255_DCMD_STARTIRQEN) { - dma_regs.dcsr[channel] |= PXA255_DCSR_STARTINTR; + dma_regs->dcsr[channel] |= PXA255_DCSR_STARTINTR; } - dma_regs.dcsr[channel] &= ~PXA255_DCSR_STOPSTATE; + dma_regs->dcsr[channel] &= ~PXA255_DCSR_STOPSTATE; } static TIMER_CALLBACK( pxa255_dma_dma_end ) { - UINT32 sadr = dma_regs.dsadr[param]; - UINT32 tadr = dma_regs.dtadr[param]; - UINT32 count = dma_regs.dcmd[param] & 0x00001fff; + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_DMA_Regs *dma_regs = &state->dma_regs; + UINT32 sadr = dma_regs->dsadr[param]; + UINT32 tadr = dma_regs->dtadr[param]; + UINT32 count = dma_regs->dcmd[param] & 0x00001fff; UINT32 index = 0; UINT8 temp8; UINT16 temp16; UINT32 temp32; - static UINT32 words[0x800]; - static INT16 samples[0x1000]; + switch(param) { case 3: for(index = 0; index < count; index += 4) { - words[index >> 2] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), sadr); - samples[(index >> 1) + 0] = (INT16)(words[index >> 2] >> 16); - samples[(index >> 1) + 1] = (INT16)(words[index >> 2] & 0xffff); + state->words[index >> 2] = memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), sadr); + state->samples[(index >> 1) + 0] = (INT16)(state->words[index >> 2] >> 16); + state->samples[(index >> 1) + 1] = (INT16)(state->words[index >> 2] & 0xffff); sadr += 4; } - dmadac[0] = devtag_get_device(machine, "dac1"); - dmadac[1] = devtag_get_device(machine, "dac2"); - dmadac_transfer(&dmadac[0], 2, 2, 2, count/4, samples); + dmadac_transfer(&state->dmadac[0], 2, 2, 2, count/4, state->samples); break; default: for(index = 0; index < count;) { - switch(dma_regs.dcmd[param] & PXA255_DCMD_SIZE) + switch(dma_regs->dcmd[param] & PXA255_DCMD_SIZE) { case PXA255_DCMD_SIZE_8: temp8 = memory_read_byte_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), sadr); @@ -308,9 +332,9 @@ static TIMER_CALLBACK( pxa255_dma_dma_end ) printf( "pxa255_dma_dma_end: Unsupported DMA size\n" ); break; } - if(dma_regs.dcmd[param] & PXA255_DCMD_INCSRCADDR) + if(dma_regs->dcmd[param] & PXA255_DCMD_INCSRCADDR) { - switch(dma_regs.dcmd[param] & PXA255_DCMD_SIZE) + switch(dma_regs->dcmd[param] & PXA255_DCMD_SIZE) { case PXA255_DCMD_SIZE_8: sadr++; @@ -325,9 +349,9 @@ static TIMER_CALLBACK( pxa255_dma_dma_end ) break; } } - if(dma_regs.dcmd[param] & PXA255_DCMD_INCTRGADDR) + if(dma_regs->dcmd[param] & PXA255_DCMD_INCTRGADDR) { - switch(dma_regs.dcmd[param] & PXA255_DCMD_SIZE) + switch(dma_regs->dcmd[param] & PXA255_DCMD_SIZE) { case PXA255_DCMD_SIZE_8: tadr++; @@ -345,44 +369,47 @@ static TIMER_CALLBACK( pxa255_dma_dma_end ) } break; } - if(dma_regs.dcmd[param] & PXA255_DCMD_ENDIRQEN) + if(dma_regs->dcmd[param] & PXA255_DCMD_ENDIRQEN) { - dma_regs.dcsr[param] |= PXA255_DCSR_ENDINTR; + dma_regs->dcsr[param] |= PXA255_DCSR_ENDINTR; } - if(!(dma_regs.ddadr[param] & PXA255_DDADR_STOP) && - (dma_regs.dcsr[param] & PXA255_DCSR_RUN)) + if(!(dma_regs->ddadr[param] & PXA255_DDADR_STOP) && + (dma_regs->dcsr[param] & PXA255_DCSR_RUN)) { - if(dma_regs.dcsr[param] & PXA255_DCSR_RUN) + if(dma_regs->dcsr[param] & PXA255_DCSR_RUN) { pxa255_dma_load_descriptor_and_start(machine, param); } else { - dma_regs.dcsr[param] &= ~PXA255_DCSR_RUN; - dma_regs.dcsr[param] |= PXA255_DCSR_STOPSTATE; + dma_regs->dcsr[param] &= ~PXA255_DCSR_RUN; + dma_regs->dcsr[param] |= PXA255_DCSR_STOPSTATE; } } else { - dma_regs.dcsr[param] &= ~PXA255_DCSR_RUN; - dma_regs.dcsr[param] |= PXA255_DCSR_STOPSTATE; + dma_regs->dcsr[param] &= ~PXA255_DCSR_RUN; + dma_regs->dcsr[param] |= PXA255_DCSR_STOPSTATE; } pxa255_dma_irq_check(machine); } static READ32_HANDLER( pxa255_dma_r ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_DMA_Regs *dma_regs = &state->dma_regs; + switch(PXA255_DMA_BASE_ADDR | (offset << 2)) { case PXA255_DCSR0: case PXA255_DCSR1: case PXA255_DCSR2: case PXA255_DCSR3: case PXA255_DCSR4: case PXA255_DCSR5: case PXA255_DCSR6: case PXA255_DCSR7: case PXA255_DCSR8: case PXA255_DCSR9: case PXA255_DCSR10: case PXA255_DCSR11: case PXA255_DCSR12: case PXA255_DCSR13: case PXA255_DCSR14: case PXA255_DCSR15: - verboselog( space->machine, 4, "pxa255_dma_r: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, dma_regs.dcsr[offset], mem_mask ); - return dma_regs.dcsr[offset]; + verboselog( space->machine, 4, "pxa255_dma_r: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, dma_regs->dcsr[offset], mem_mask ); + return dma_regs->dcsr[offset]; case PXA255_DINT: -// verboselog( space->machine, 3, "pxa255_dma_r: DMA Interrupt Register: %08x & %08x\n", dma_regs.dint, mem_mask ); - return dma_regs.dint; + if (0) verboselog( space->machine, 3, "pxa255_dma_r: DMA Interrupt Register: %08x & %08x\n", dma_regs->dint, mem_mask ); + return dma_regs->dint; case PXA255_DRCMR0: case PXA255_DRCMR1: case PXA255_DRCMR2: case PXA255_DRCMR3: case PXA255_DRCMR4: case PXA255_DRCMR5: case PXA255_DRCMR6: case PXA255_DRCMR7: case PXA255_DRCMR8: case PXA255_DRCMR9: case PXA255_DRCMR10: case PXA255_DRCMR11: @@ -394,31 +421,31 @@ static READ32_HANDLER( pxa255_dma_r ) case PXA255_DRCMR32: case PXA255_DRCMR33: case PXA255_DRCMR34: case PXA255_DRCMR35: case PXA255_DRCMR36: case PXA255_DRCMR37: case PXA255_DRCMR38: case PXA255_DRCMR39: verboselog( space->machine, 3, "pxa255_dma_r: DMA Request to Channel Map Register %d: %08x & %08x\n", offset - (0x100 >> 2), 0, mem_mask ); - return dma_regs.drcmr[offset - (0x100 >> 2)]; + return dma_regs->drcmr[offset - (0x100 >> 2)]; case PXA255_DDADR0: case PXA255_DDADR1: case PXA255_DDADR2: case PXA255_DDADR3: case PXA255_DDADR4: case PXA255_DDADR5: case PXA255_DDADR6: case PXA255_DDADR7: case PXA255_DDADR8: case PXA255_DDADR9: case PXA255_DDADR10: case PXA255_DDADR11: case PXA255_DDADR12: case PXA255_DDADR13: case PXA255_DDADR14: case PXA255_DDADR15: verboselog( space->machine, 3, "pxa255_dma_r: DMA Descriptor Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask ); - return dma_regs.ddadr[(offset - (0x200 >> 2)) >> 2]; + return dma_regs->ddadr[(offset - (0x200 >> 2)) >> 2]; case PXA255_DSADR0: case PXA255_DSADR1: case PXA255_DSADR2: case PXA255_DSADR3: case PXA255_DSADR4: case PXA255_DSADR5: case PXA255_DSADR6: case PXA255_DSADR7: case PXA255_DSADR8: case PXA255_DSADR9: case PXA255_DSADR10: case PXA255_DSADR11: case PXA255_DSADR12: case PXA255_DSADR13: case PXA255_DSADR14: case PXA255_DSADR15: verboselog( space->machine, 3, "pxa255_dma_r: DMA Source Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask ); - return dma_regs.dsadr[(offset - (0x200 >> 2)) >> 2]; + return dma_regs->dsadr[(offset - (0x200 >> 2)) >> 2]; case PXA255_DTADR0: case PXA255_DTADR1: case PXA255_DTADR2: case PXA255_DTADR3: case PXA255_DTADR4: case PXA255_DTADR5: case PXA255_DTADR6: case PXA255_DTADR7: case PXA255_DTADR8: case PXA255_DTADR9: case PXA255_DTADR10: case PXA255_DTADR11: case PXA255_DTADR12: case PXA255_DTADR13: case PXA255_DTADR14: case PXA255_DTADR15: verboselog( space->machine, 3, "pxa255_dma_r: DMA Target Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask ); - return dma_regs.dtadr[(offset - (0x200 >> 2)) >> 2]; + return dma_regs->dtadr[(offset - (0x200 >> 2)) >> 2]; case PXA255_DCMD0: case PXA255_DCMD1: case PXA255_DCMD2: case PXA255_DCMD3: case PXA255_DCMD4: case PXA255_DCMD5: case PXA255_DCMD6: case PXA255_DCMD7: case PXA255_DCMD8: case PXA255_DCMD9: case PXA255_DCMD10: case PXA255_DCMD11: case PXA255_DCMD12: case PXA255_DCMD13: case PXA255_DCMD14: case PXA255_DCMD15: verboselog( space->machine, 3, "pxa255_dma_r: DMA Command Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask ); - return dma_regs.dcmd[(offset - (0x200 >> 2)) >> 2]; + return dma_regs->dcmd[(offset - (0x200 >> 2)) >> 2]; default: verboselog( space->machine, 0, "pxa255_dma_r: Unknown address: %08x\n", PXA255_DMA_BASE_ADDR | (offset << 2)); break; @@ -428,19 +455,22 @@ static READ32_HANDLER( pxa255_dma_r ) static WRITE32_HANDLER( pxa255_dma_w ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_DMA_Regs *dma_regs = &state->dma_regs; + switch(PXA255_DMA_BASE_ADDR | (offset << 2)) { case PXA255_DCSR0: case PXA255_DCSR1: case PXA255_DCSR2: case PXA255_DCSR3: case PXA255_DCSR4: case PXA255_DCSR5: case PXA255_DCSR6: case PXA255_DCSR7: case PXA255_DCSR8: case PXA255_DCSR9: case PXA255_DCSR10: case PXA255_DCSR11: case PXA255_DCSR12: case PXA255_DCSR13: case PXA255_DCSR14: case PXA255_DCSR15: -// verboselog( space->machine, 3, "pxa255_dma_w: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, data, mem_mask ); - dma_regs.dcsr[offset] &= ~(data & 0x00000007); - dma_regs.dcsr[offset] &= ~0x60000000; - dma_regs.dcsr[offset] |= data & 0x60000000; - if((data & PXA255_DCSR_RUN) && !(dma_regs.dcsr[offset] & PXA255_DCSR_RUN)) + if (0) verboselog( space->machine, 3, "pxa255_dma_w: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, data, mem_mask ); + dma_regs->dcsr[offset] &= ~(data & 0x00000007); + dma_regs->dcsr[offset] &= ~0x60000000; + dma_regs->dcsr[offset] |= data & 0x60000000; + if((data & PXA255_DCSR_RUN) && !(dma_regs->dcsr[offset] & PXA255_DCSR_RUN)) { - dma_regs.dcsr[offset] |= PXA255_DCSR_RUN; + dma_regs->dcsr[offset] |= PXA255_DCSR_RUN; if(data & PXA255_DCSR_NODESCFETCH) { verboselog( space->machine, 0, " No-Descriptor-Fetch mode is not supported.\n" ); @@ -451,14 +481,14 @@ static WRITE32_HANDLER( pxa255_dma_w ) } else if(!(data & PXA255_DCSR_RUN)) { - dma_regs.dcsr[offset] &= ~PXA255_DCSR_RUN; + dma_regs->dcsr[offset] &= ~PXA255_DCSR_RUN; } pxa255_dma_irq_check(space->machine); break; case PXA255_DINT: verboselog( space->machine, 3, "pxa255_dma_w: DMA Interrupt Register: %08x & %08x\n", data, mem_mask ); - dma_regs.dint &= ~data; + dma_regs->dint &= ~data; break; case PXA255_DRCMR0: case PXA255_DRCMR1: case PXA255_DRCMR2: case PXA255_DRCMR3: case PXA255_DRCMR4: case PXA255_DRCMR5: case PXA255_DRCMR6: case PXA255_DRCMR7: @@ -471,35 +501,35 @@ static WRITE32_HANDLER( pxa255_dma_w ) case PXA255_DRCMR32: case PXA255_DRCMR33: case PXA255_DRCMR34: case PXA255_DRCMR35: case PXA255_DRCMR36: case PXA255_DRCMR37: case PXA255_DRCMR38: case PXA255_DRCMR39: verboselog( space->machine, 3, "pxa255_dma_w: DMA Request to Channel Map Register %d: %08x & %08x\n", offset - (0x100 >> 2), data, mem_mask ); - dma_regs.drcmr[offset - (0x100 >> 2)] = data & 0x0000008f; + dma_regs->drcmr[offset - (0x100 >> 2)] = data & 0x0000008f; break; case PXA255_DDADR0: case PXA255_DDADR1: case PXA255_DDADR2: case PXA255_DDADR3: case PXA255_DDADR4: case PXA255_DDADR5: case PXA255_DDADR6: case PXA255_DDADR7: case PXA255_DDADR8: case PXA255_DDADR9: case PXA255_DDADR10: case PXA255_DDADR11: case PXA255_DDADR12: case PXA255_DDADR13: case PXA255_DDADR14: case PXA255_DDADR15: verboselog( space->machine, 3, "pxa255_dma_w: DMA Descriptor Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask ); - dma_regs.ddadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffff1; + dma_regs->ddadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffff1; break; case PXA255_DSADR0: case PXA255_DSADR1: case PXA255_DSADR2: case PXA255_DSADR3: case PXA255_DSADR4: case PXA255_DSADR5: case PXA255_DSADR6: case PXA255_DSADR7: case PXA255_DSADR8: case PXA255_DSADR9: case PXA255_DSADR10: case PXA255_DSADR11: case PXA255_DSADR12: case PXA255_DSADR13: case PXA255_DSADR14: case PXA255_DSADR15: verboselog( space->machine, 3, "pxa255_dma_w: DMA Source Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask ); - dma_regs.dsadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffffc; + dma_regs->dsadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffffc; break; case PXA255_DTADR0: case PXA255_DTADR1: case PXA255_DTADR2: case PXA255_DTADR3: case PXA255_DTADR4: case PXA255_DTADR5: case PXA255_DTADR6: case PXA255_DTADR7: case PXA255_DTADR8: case PXA255_DTADR9: case PXA255_DTADR10: case PXA255_DTADR11: case PXA255_DTADR12: case PXA255_DTADR13: case PXA255_DTADR14: case PXA255_DTADR15: verboselog( space->machine, 3, "pxa255_dma_w: DMA Target Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask ); - dma_regs.dtadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffffc; + dma_regs->dtadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffffc; break; case PXA255_DCMD0: case PXA255_DCMD1: case PXA255_DCMD2: case PXA255_DCMD3: case PXA255_DCMD4: case PXA255_DCMD5: case PXA255_DCMD6: case PXA255_DCMD7: case PXA255_DCMD8: case PXA255_DCMD9: case PXA255_DCMD10: case PXA255_DCMD11: case PXA255_DCMD12: case PXA255_DCMD13: case PXA255_DCMD14: case PXA255_DCMD15: verboselog( space->machine, 3, "pxa255_dma_w: DMA Command Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask ); - dma_regs.dcmd[(offset - (0x200 >> 2)) >> 2] = data & 0xf067dfff; + dma_regs->dcmd[(offset - (0x200 >> 2)) >> 2] = data & 0xf067dfff; break; default: verboselog( space->machine, 0, "pxa255_dma_w: Unknown address: %08x = %08x & %08x\n", PXA255_DMA_BASE_ADDR | (offset << 2), data, mem_mask); @@ -517,52 +547,61 @@ static WRITE32_HANDLER( pxa255_dma_w ) static void pxa255_ostimer_irq_check(running_machine* machine) { - pxa255_set_irq_line(machine, PXA255_INT_OSTIMER0, (ostimer_regs.oier & PXA255_OIER_E0) ? ((ostimer_regs.ossr & PXA255_OSSR_M0) ? 1 : 0) : 0); - //pxa255_set_irq_line(machine, PXA255_INT_OSTIMER1, (ostimer_regs.oier & PXA255_OIER_E1) ? ((ostimer_regs.ossr & PXA255_OSSR_M1) ? 1 : 0) : 0); - //pxa255_set_irq_line(machine, PXA255_INT_OSTIMER2, (ostimer_regs.oier & PXA255_OIER_E2) ? ((ostimer_regs.ossr & PXA255_OSSR_M2) ? 1 : 0) : 0); - //pxa255_set_irq_line(machine, PXA255_INT_OSTIMER3, (ostimer_regs.oier & PXA255_OIER_E3) ? ((ostimer_regs.ossr & PXA255_OSSR_M3) ? 1 : 0) : 0); + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_OSTMR_Regs *ostimer_regs = &state->ostimer_regs; + + pxa255_set_irq_line(machine, PXA255_INT_OSTIMER0, (ostimer_regs->oier & PXA255_OIER_E0) ? ((ostimer_regs->ossr & PXA255_OSSR_M0) ? 1 : 0) : 0); + //pxa255_set_irq_line(machine, PXA255_INT_OSTIMER1, (ostimer_regs->oier & PXA255_OIER_E1) ? ((ostimer_regs->ossr & PXA255_OSSR_M1) ? 1 : 0) : 0); + //pxa255_set_irq_line(machine, PXA255_INT_OSTIMER2, (ostimer_regs->oier & PXA255_OIER_E2) ? ((ostimer_regs->ossr & PXA255_OSSR_M2) ? 1 : 0) : 0); + //pxa255_set_irq_line(machine, PXA255_INT_OSTIMER3, (ostimer_regs->oier & PXA255_OIER_E3) ? ((ostimer_regs->ossr & PXA255_OSSR_M3) ? 1 : 0) : 0); } static TIMER_CALLBACK( pxa255_ostimer_match ) { -// verboselog(machine, 3, "pxa255_ostimer_match channel %d\n", param); - ostimer_regs.ossr |= (1 << param); - ostimer_regs.oscr = ostimer_regs.osmr[param]; + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_OSTMR_Regs *ostimer_regs = &state->ostimer_regs; + + if (0) verboselog(machine, 3, "pxa255_ostimer_match channel %d\n", param); + ostimer_regs->ossr |= (1 << param); + ostimer_regs->oscr = ostimer_regs->osmr[param]; pxa255_ostimer_irq_check(machine); } static READ32_HANDLER( pxa255_ostimer_r ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_OSTMR_Regs *ostimer_regs = &state->ostimer_regs; + switch(PXA255_OSTMR_BASE_ADDR | (offset << 2)) { case PXA255_OSMR0: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs.osmr[0], mem_mask ); - return ostimer_regs.osmr[0]; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs->osmr[0], mem_mask ); + return ostimer_regs->osmr[0]; case PXA255_OSMR1: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs.osmr[1], mem_mask ); - return ostimer_regs.osmr[1]; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs->osmr[1], mem_mask ); + return ostimer_regs->osmr[1]; case PXA255_OSMR2: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs.osmr[2], mem_mask ); - return ostimer_regs.osmr[2]; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs->osmr[2], mem_mask ); + return ostimer_regs->osmr[2]; case PXA255_OSMR3: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs.osmr[3], mem_mask ); - return ostimer_regs.osmr[3]; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs->osmr[3], mem_mask ); + return ostimer_regs->osmr[3]; case PXA255_OSCR: -// verboselog( space->machine, 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs.oscr, mem_mask ); + if (0) verboselog( space->machine, 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs->oscr, mem_mask ); // free-running 3.something MHz counter. this is a complete hack. - ostimer_regs.oscr += 0x300; - return ostimer_regs.oscr; + ostimer_regs->oscr += 0x300; + return ostimer_regs->oscr; case PXA255_OSSR: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs.ossr, mem_mask ); - return ostimer_regs.ossr; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs->ossr, mem_mask ); + return ostimer_regs->ossr; case PXA255_OWER: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs.ower, mem_mask ); - return ostimer_regs.ower; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs->ower, mem_mask ); + return ostimer_regs->ower; case PXA255_OIER: -// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs.oier, mem_mask ); - return ostimer_regs.oier; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs->oier, mem_mask ); + return ostimer_regs->oier; default: -// verboselog( space->machine, 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2)); + if (0) verboselog( space->machine, 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2)); break; } return 0; @@ -570,74 +609,77 @@ static READ32_HANDLER( pxa255_ostimer_r ) static WRITE32_HANDLER( pxa255_ostimer_w ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_OSTMR_Regs *ostimer_regs = &state->ostimer_regs; + switch(PXA255_OSTMR_BASE_ADDR | (offset << 2)) { case PXA255_OSMR0: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask ); - ostimer_regs.osmr[0] = data; - if(ostimer_regs.oier & PXA255_OIER_E0) + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask ); + ostimer_regs->osmr[0] = data; + if(ostimer_regs->oier & PXA255_OIER_E0) { - attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs.osmr[0] - ostimer_regs.oscr); + attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs->osmr[0] - ostimer_regs->oscr); - //printf( "Adjusting one-shot timer to 200MHz * %08x\n", ostimer_regs.osmr[0]); - timer_adjust_oneshot(ostimer_regs.timer[0], period, 0); + //printf( "Adjusting one-shot timer to 200MHz * %08x\n", ostimer_regs->osmr[0]); + timer_adjust_oneshot(ostimer_regs->timer[0], period, 0); } break; case PXA255_OSMR1: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask ); - ostimer_regs.osmr[1] = data; - if(ostimer_regs.oier & PXA255_OIER_E1) + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask ); + ostimer_regs->osmr[1] = data; + if(ostimer_regs->oier & PXA255_OIER_E1) { - attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs.osmr[1] - ostimer_regs.oscr); + attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs->osmr[1] - ostimer_regs->oscr); - timer_adjust_oneshot(ostimer_regs.timer[1], period, 1); + timer_adjust_oneshot(ostimer_regs->timer[1], period, 1); } break; case PXA255_OSMR2: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask ); - ostimer_regs.osmr[2] = data; - if(ostimer_regs.oier & PXA255_OIER_E2) + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask ); + ostimer_regs->osmr[2] = data; + if(ostimer_regs->oier & PXA255_OIER_E2) { - attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs.osmr[2] - ostimer_regs.oscr); + attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs->osmr[2] - ostimer_regs->oscr); - timer_adjust_oneshot(ostimer_regs.timer[2], period, 2); + timer_adjust_oneshot(ostimer_regs->timer[2], period, 2); } break; case PXA255_OSMR3: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask ); - ostimer_regs.osmr[3] = data; - if(ostimer_regs.oier & PXA255_OIER_E3) + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask ); + ostimer_regs->osmr[3] = data; + if(ostimer_regs->oier & PXA255_OIER_E3) { - //attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs.osmr[3] - ostimer_regs.oscr); + //attotime period = attotime_mul(ATTOTIME_IN_HZ(3846400), ostimer_regs->osmr[3] - ostimer_regs->oscr); - //timer_adjust_oneshot(ostimer_regs.timer[3], period, 3); + //timer_adjust_oneshot(ostimer_regs->timer[3], period, 3); } break; case PXA255_OSCR: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask ); - ostimer_regs.oscr = data; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask ); + ostimer_regs->oscr = data; break; case PXA255_OSSR: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask ); - ostimer_regs.ossr &= ~data; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask ); + ostimer_regs->ossr &= ~data; pxa255_ostimer_irq_check(space->machine); break; case PXA255_OWER: -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask ); - ostimer_regs.ower = data & 0x00000001; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask ); + ostimer_regs->ower = data & 0x00000001; break; case PXA255_OIER: { int index = 0; -// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask ); - ostimer_regs.oier = data & 0x0000000f; + if (0) verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask ); + ostimer_regs->oier = data & 0x0000000f; for(index = 0; index < 4; index++) { - if(ostimer_regs.oier & (1 << index)) + if(ostimer_regs->oier & (1 << index)) { - //attotime period = attotime_mul(ATTOTIME_IN_HZ(200000000), ostimer_regs.osmr[index]); + //attotime period = attotime_mul(ATTOTIME_IN_HZ(200000000), ostimer_regs->osmr[index]); - //timer_adjust_oneshot(ostimer_regs.timer[index], period, index); + //timer_adjust_oneshot(ostimer_regs->timer[index], period, index); } } @@ -659,42 +701,51 @@ static WRITE32_HANDLER( pxa255_ostimer_w ) static void pxa255_update_interrupts(running_machine* machine) { - intc_regs.icfp = (intc_regs.icpr & intc_regs.icmr) & intc_regs.iclr; - intc_regs.icip = (intc_regs.icpr & intc_regs.icmr) & (~intc_regs.iclr); - cputag_set_input_line(machine, "maincpu", ARM7_FIRQ_LINE, intc_regs.icfp ? ASSERT_LINE : CLEAR_LINE); - cputag_set_input_line(machine, "maincpu", ARM7_IRQ_LINE, intc_regs.icip ? ASSERT_LINE : CLEAR_LINE); + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_INTC_Regs *intc_regs = &state->intc_regs; + + intc_regs->icfp = (intc_regs->icpr & intc_regs->icmr) & intc_regs->iclr; + intc_regs->icip = (intc_regs->icpr & intc_regs->icmr) & (~intc_regs->iclr); + cputag_set_input_line(machine, "maincpu", ARM7_FIRQ_LINE, intc_regs->icfp ? ASSERT_LINE : CLEAR_LINE); + cputag_set_input_line(machine, "maincpu", ARM7_IRQ_LINE, intc_regs->icip ? ASSERT_LINE : CLEAR_LINE); } -static void pxa255_set_irq_line(running_machine* machine, UINT32 line, int state) +static void pxa255_set_irq_line(running_machine* machine, UINT32 line, int irq_state) { - intc_regs.icpr &= ~line; - intc_regs.icpr |= state ? line : 0; - //printf( "Setting IRQ line %08x to %d\n", line, state ); + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_INTC_Regs *intc_regs = &state->intc_regs; + + intc_regs->icpr &= ~line; + intc_regs->icpr |= irq_state ? line : 0; + //printf( "Setting IRQ line %08x to %d\n", line, irq_state ); pxa255_update_interrupts(machine); } static READ32_HANDLER( pxa255_intc_r ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_INTC_Regs *intc_regs = &state->intc_regs; + switch(PXA255_INTC_BASE_ADDR | (offset << 2)) { case PXA255_ICIP: -// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs.icip, mem_mask ); - return intc_regs.icip; + if (0) verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs->icip, mem_mask ); + return intc_regs->icip; case PXA255_ICMR: -// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs.icmr, mem_mask ); - return intc_regs.icmr; + if (0) verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs->icmr, mem_mask ); + return intc_regs->icmr; case PXA255_ICLR: -// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs.iclr, mem_mask ); - return intc_regs.iclr; + if (0) verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs->iclr, mem_mask ); + return intc_regs->iclr; case PXA255_ICFP: -// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs.icfp, mem_mask ); - return intc_regs.icfp; + if (0) verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs->icfp, mem_mask ); + return intc_regs->icfp; case PXA255_ICPR: -// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs.icpr, mem_mask ); - return intc_regs.icpr; + if (0) verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs->icpr, mem_mask ); + return intc_regs->icpr; case PXA255_ICCR: -// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs.iccr, mem_mask ); - return intc_regs.iccr; + if (0) verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs->iccr, mem_mask ); + return intc_regs->iccr; default: verboselog( space->machine, 0, "pxa255_intc_r: Unknown address: %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2)); break; @@ -704,28 +755,31 @@ static READ32_HANDLER( pxa255_intc_r ) static WRITE32_HANDLER( pxa255_intc_w ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_INTC_Regs *intc_regs = &state->intc_regs; + switch(PXA255_INTC_BASE_ADDR | (offset << 2)) { case PXA255_ICIP: verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller IRQ Pending Register: %08x & %08x\n", data, mem_mask ); break; case PXA255_ICMR: -// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask ); - intc_regs.icmr = data & 0xfffe7f00; + if (0) verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask ); + intc_regs->icmr = data & 0xfffe7f00; break; case PXA255_ICLR: -// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask ); - intc_regs.iclr = data & 0xfffe7f00; + if (0) verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask ); + intc_regs->iclr = data & 0xfffe7f00; break; case PXA255_ICFP: -// verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask ); + if (0) verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask ); break; case PXA255_ICPR: -// verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask ); + if (0) verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask ); break; case PXA255_ICCR: -// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask ); - intc_regs.iccr = data & 0x00000001; + if (0) verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask ); + intc_regs->iccr = data & 0x00000001; break; default: verboselog( space->machine, 0, "pxa255_intc_w: Unknown address: %08x = %08x & %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2), data, mem_mask); @@ -743,29 +797,32 @@ static WRITE32_HANDLER( pxa255_intc_w ) static READ32_HANDLER( pxa255_gpio_r ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_GPIO_Regs *gpio_regs = &state->gpio_regs; + switch(PXA255_GPIO_BASE_ADDR | (offset << 2)) { case PXA255_GPLR0: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin-Level Register 0: %08x & %08x\n", gpio_regs.gplr0 | (1 << 1), mem_mask ); - return gpio_regs.gplr0 | (1 << 1) | (eeprom_read_bit(devtag_get_device(space->machine, "eeprom")) << 5); // Must be on. Probably a DIP switch. + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin-Level Register 0: %08x & %08x\n", gpio_regs->gplr0 | (1 << 1), mem_mask ); + return gpio_regs->gplr0 | (1 << 1) | (eeprom_read_bit(state->eeprom) << 5); // Must be on. Probably a DIP switch. case PXA255_GPLR1: - verboselog( space->machine, 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 1: %08x & %08x\n", gpio_regs.gplr1, mem_mask ); + verboselog( space->machine, 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 1: %08x & %08x\n", gpio_regs->gplr1, mem_mask ); return 0xff9fffff; /* 0x200000 = flip screen */ case PXA255_GPLR2: - verboselog( space->machine, 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 2: %08x & %08x\n", gpio_regs.gplr2, mem_mask ); - return gpio_regs.gplr2; + verboselog( space->machine, 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 2: %08x & %08x\n", gpio_regs->gplr2, mem_mask ); + return gpio_regs->gplr2; case PXA255_GPDR0: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin Direction Register 0: %08x & %08x\n", gpio_regs.gpdr0, mem_mask ); - return gpio_regs.gpdr0; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin Direction Register 0: %08x & %08x\n", gpio_regs->gpdr0, mem_mask ); + return gpio_regs->gpdr0; case PXA255_GPDR1: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin Direction Register 1: %08x & %08x\n", gpio_regs.gpdr1, mem_mask ); - return gpio_regs.gpdr1; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin Direction Register 1: %08x & %08x\n", gpio_regs->gpdr1, mem_mask ); + return gpio_regs->gpdr1; case PXA255_GPDR2: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin Direction Register 2: %08x & %08x\n", gpio_regs.gpdr2, mem_mask ); - return gpio_regs.gpdr2; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Pin Direction Register 2: %08x & %08x\n", gpio_regs->gpdr2, mem_mask ); + return gpio_regs->gpdr2; case PXA255_GPSR0: verboselog( space->machine, 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 0: %08x & %08x\n", mame_rand(space->machine), mem_mask ); return mame_rand(space->machine); @@ -785,50 +842,50 @@ static READ32_HANDLER( pxa255_gpio_r ) verboselog( space->machine, 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 2: %08x & %08x\n", mame_rand(space->machine), mem_mask ); return mame_rand(space->machine); case PXA255_GRER0: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs.grer0, mem_mask ); - return gpio_regs.grer0; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs->grer0, mem_mask ); + return gpio_regs->grer0; case PXA255_GRER1: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs.grer1, mem_mask ); - return gpio_regs.grer1; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs->grer1, mem_mask ); + return gpio_regs->grer1; case PXA255_GRER2: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs.grer2, mem_mask ); - return gpio_regs.grer2; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs->grer2, mem_mask ); + return gpio_regs->grer2; case PXA255_GFER0: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs.gfer0, mem_mask ); - return gpio_regs.gfer0; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs->gfer0, mem_mask ); + return gpio_regs->gfer0; case PXA255_GFER1: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs.gfer1, mem_mask ); - return gpio_regs.gfer1; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs->gfer1, mem_mask ); + return gpio_regs->gfer1; case PXA255_GFER2: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs.gfer2, mem_mask ); - return gpio_regs.gfer2; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs->gfer2, mem_mask ); + return gpio_regs->gfer2; case PXA255_GEDR0: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs.gedr0, mem_mask ); - return gpio_regs.gedr0; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs->gedr0, mem_mask ); + return gpio_regs->gedr0; case PXA255_GEDR1: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs.gedr1, mem_mask ); - return gpio_regs.gedr1; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs->gedr1, mem_mask ); + return gpio_regs->gedr1; case PXA255_GEDR2: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs.gedr2, mem_mask ); - return gpio_regs.gedr2; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs->gedr2, mem_mask ); + return gpio_regs->gedr2; case PXA255_GAFR0_L: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs.gafr0l, mem_mask ); - return gpio_regs.gafr0l; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs->gafr0l, mem_mask ); + return gpio_regs->gafr0l; case PXA255_GAFR0_U: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs.gafr0u, mem_mask ); - return gpio_regs.gafr0u; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs->gafr0u, mem_mask ); + return gpio_regs->gafr0u; case PXA255_GAFR1_L: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs.gafr1l, mem_mask ); - return gpio_regs.gafr1l; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs->gafr1l, mem_mask ); + return gpio_regs->gafr1l; case PXA255_GAFR1_U: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs.gafr1u, mem_mask ); - return gpio_regs.gafr1u; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs->gafr1u, mem_mask ); + return gpio_regs->gafr1u; case PXA255_GAFR2_L: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs.gafr2l, mem_mask ); - return gpio_regs.gafr2l; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs->gafr2l, mem_mask ); + return gpio_regs->gafr2l; case PXA255_GAFR2_U: - verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs.gafr2u, mem_mask ); - return gpio_regs.gafr2u; + verboselog( space->machine, 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs->gafr2u, mem_mask ); + return gpio_regs->gafr2u; default: verboselog( space->machine, 0, "pxa255_gpio_r: Unknown address: %08x\n", PXA255_GPIO_BASE_ADDR | (offset << 2)); break; @@ -838,7 +895,9 @@ static READ32_HANDLER( pxa255_gpio_r ) static WRITE32_HANDLER( pxa255_gpio_w ) { - running_device *device; + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_GPIO_Regs *gpio_regs = &state->gpio_regs; + switch(PXA255_GPIO_BASE_ADDR | (offset << 2)) { case PXA255_GPLR0: @@ -852,125 +911,123 @@ static WRITE32_HANDLER( pxa255_gpio_w ) break; case PXA255_GPDR0: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Direction Register 0: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpdr0 = data; + gpio_regs->gpdr0 = data; break; case PXA255_GPDR1: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Direction Register 1: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpdr1 = data; + gpio_regs->gpdr1 = data; break; case PXA255_GPDR2: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Direction Register 2: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpdr2 = data; + gpio_regs->gpdr2 = data; break; case PXA255_GPSR0: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Output Set Register 0: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpsr0 |= data & gpio_regs.gpdr0; - device = devtag_get_device(space->machine, "eeprom"); + gpio_regs->gpsr0 |= data & gpio_regs->gpdr0; if(data & 0x00000004) { - eeprom_set_cs_line(device, CLEAR_LINE); + eeprom_set_cs_line(state->eeprom, CLEAR_LINE); } if(data & 0x00000008) { - eeprom_set_clock_line(device, ASSERT_LINE); + eeprom_set_clock_line(state->eeprom, ASSERT_LINE); } if(data & 0x00000010) { - eeprom_write_bit(device, 1); + eeprom_write_bit(state->eeprom, 1); } break; case PXA255_GPSR1: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Output Set Register 1: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpsr1 |= data & gpio_regs.gpdr1; + gpio_regs->gpsr1 |= data & gpio_regs->gpdr1; break; case PXA255_GPSR2: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Output Set Register 2: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpsr2 |= data & gpio_regs.gpdr2; + gpio_regs->gpsr2 |= data & gpio_regs->gpdr2; break; case PXA255_GPCR0: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 0: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpsr0 &= ~(data & gpio_regs.gpdr0); - device = devtag_get_device(space->machine, "eeprom"); + gpio_regs->gpsr0 &= ~(data & gpio_regs->gpdr0); if(data & 0x00000004) { - eeprom_set_cs_line(device, ASSERT_LINE); + eeprom_set_cs_line(state->eeprom, ASSERT_LINE); } if(data & 0x00000008) { - eeprom_set_clock_line(device, CLEAR_LINE); + eeprom_set_clock_line(state->eeprom, CLEAR_LINE); } if(data & 0x00000010) { - eeprom_write_bit(device, 0); + eeprom_write_bit(state->eeprom, 0); } break; case PXA255_GPCR1: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 1: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpsr1 &= ~(data & gpio_regs.gpdr1); + gpio_regs->gpsr1 &= ~(data & gpio_regs->gpdr1); break; case PXA255_GPCR2: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 2: %08x & %08x\n", data, mem_mask ); - gpio_regs.gpsr2 &= ~(data & gpio_regs.gpdr2); + gpio_regs->gpsr2 &= ~(data & gpio_regs->gpdr2); break; case PXA255_GRER0: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", data, mem_mask ); - gpio_regs.grer0 = data; + gpio_regs->grer0 = data; break; case PXA255_GRER1: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", data, mem_mask ); - gpio_regs.grer1 = data; + gpio_regs->grer1 = data; break; case PXA255_GRER2: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", data, mem_mask ); - gpio_regs.grer2 = data; + gpio_regs->grer2 = data; break; case PXA255_GFER0: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", data, mem_mask ); - gpio_regs.gfer0 = data; + gpio_regs->gfer0 = data; break; case PXA255_GFER1: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", data, mem_mask ); - gpio_regs.gfer1 = data; + gpio_regs->gfer1 = data; break; case PXA255_GFER2: verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", data, mem_mask ); - gpio_regs.gfer2 = data; + gpio_regs->gfer2 = data; break; case PXA255_GEDR0: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs.gedr0, mem_mask ); - gpio_regs.gedr0 &= ~data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs->gedr0, mem_mask ); + gpio_regs->gedr0 &= ~data; break; case PXA255_GEDR1: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs.gedr1, mem_mask ); - gpio_regs.gedr1 &= ~data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs->gedr1, mem_mask ); + gpio_regs->gedr1 &= ~data; break; case PXA255_GEDR2: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs.gedr2, mem_mask ); - gpio_regs.gedr2 &= ~data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs->gedr2, mem_mask ); + gpio_regs->gedr2 &= ~data; break; case PXA255_GAFR0_L: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs.gafr0l, mem_mask ); - gpio_regs.gafr0l = data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs->gafr0l, mem_mask ); + gpio_regs->gafr0l = data; break; case PXA255_GAFR0_U: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs.gafr0u, mem_mask ); - gpio_regs.gafr0u = data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs->gafr0u, mem_mask ); + gpio_regs->gafr0u = data; break; case PXA255_GAFR1_L: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs.gafr1l, mem_mask ); - gpio_regs.gafr1l = data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs->gafr1l, mem_mask ); + gpio_regs->gafr1l = data; break; case PXA255_GAFR1_U: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs.gafr1u, mem_mask ); - gpio_regs.gafr1u = data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs->gafr1u, mem_mask ); + gpio_regs->gafr1u = data; break; case PXA255_GAFR2_L: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs.gafr2l, mem_mask ); - gpio_regs.gafr2l = data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs->gafr2l, mem_mask ); + gpio_regs->gafr2l = data; break; case PXA255_GAFR2_U: - verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs.gafr2u, mem_mask ); - gpio_regs.gafr2u = data; + verboselog( space->machine, 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs->gafr2u, mem_mask ); + gpio_regs->gafr2u = data; break; default: verboselog( space->machine, 0, "pxa255_gpio_w: Unknown address: %08x = %08x & %08x\n", PXA255_GPIO_BASE_ADDR | (offset << 2), data, mem_mask); @@ -988,22 +1045,28 @@ static WRITE32_HANDLER( pxa255_gpio_w ) static void pxa255_lcd_load_dma_descriptor(const address_space* space, UINT32 address, int channel) { - lcd_regs.dma[channel].fdadr = memory_read_dword_32le(space, address); - lcd_regs.dma[channel].fsadr = memory_read_dword_32le(space, address + 0x04); - lcd_regs.dma[channel].fidr = memory_read_dword_32le(space, address + 0x08); - lcd_regs.dma[channel].ldcmd = memory_read_dword_32le(space, address + 0x0c); + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + + lcd_regs->dma[channel].fdadr = memory_read_dword_32le(space, address); + lcd_regs->dma[channel].fsadr = memory_read_dword_32le(space, address + 0x04); + lcd_regs->dma[channel].fidr = memory_read_dword_32le(space, address + 0x08); + lcd_regs->dma[channel].ldcmd = memory_read_dword_32le(space, address + 0x0c); verboselog( space->machine, 4, "pxa255_lcd_load_dma_descriptor, address = %08x, channel = %d\n", address, channel); - verboselog( space->machine, 4, " DMA Frame Descriptor: %08x\n", lcd_regs.dma[channel].fdadr ); - verboselog( space->machine, 4, " DMA Frame Source Address: %08x\n", lcd_regs.dma[channel].fsadr ); - verboselog( space->machine, 4, " DMA Frame ID: %08x\n", lcd_regs.dma[channel].fidr ); - verboselog( space->machine, 4, " DMA Command: %08x\n", lcd_regs.dma[channel].ldcmd ); + verboselog( space->machine, 4, " DMA Frame Descriptor: %08x\n", lcd_regs->dma[channel].fdadr ); + verboselog( space->machine, 4, " DMA Frame Source Address: %08x\n", lcd_regs->dma[channel].fsadr ); + verboselog( space->machine, 4, " DMA Frame ID: %08x\n", lcd_regs->dma[channel].fidr ); + verboselog( space->machine, 4, " DMA Command: %08x\n", lcd_regs->dma[channel].ldcmd ); } static void pxa255_lcd_irq_check(running_machine* machine) { - if(((lcd_regs.lcsr & PXA255_LCSR_BS) != 0 && (lcd_regs.lccr0 & PXA255_LCCR0_BM) == 0) || - ((lcd_regs.lcsr & PXA255_LCSR_EOF) != 0 && (lcd_regs.lccr0 & PXA255_LCCR0_EFM) == 0) || - ((lcd_regs.lcsr & PXA255_LCSR_SOF) != 0 && (lcd_regs.lccr0 & PXA255_LCCR0_SFM) == 0)) + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + + if(((lcd_regs->lcsr & PXA255_LCSR_BS) != 0 && (lcd_regs->lccr0 & PXA255_LCCR0_BM) == 0) || + ((lcd_regs->lcsr & PXA255_LCSR_EOF) != 0 && (lcd_regs->lccr0 & PXA255_LCCR0_EFM) == 0) || + ((lcd_regs->lcsr & PXA255_LCSR_SOF) != 0 && (lcd_regs->lccr0 & PXA255_LCCR0_SFM) == 0)) { pxa255_set_irq_line(machine, PXA255_INT_LCD, 1); } @@ -1015,37 +1078,40 @@ static void pxa255_lcd_irq_check(running_machine* machine) static void pxa255_lcd_dma_kickoff(running_machine* machine, int channel) { - if(lcd_regs.dma[channel].fdadr != 0) + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + + if(lcd_regs->dma[channel].fdadr != 0) { - attotime period = attotime_mul(ATTOTIME_IN_HZ(20000000), lcd_regs.dma[channel].ldcmd & 0x000fffff); + attotime period = attotime_mul(ATTOTIME_IN_HZ(20000000), lcd_regs->dma[channel].ldcmd & 0x000fffff); - timer_adjust_oneshot(lcd_regs.dma[channel].eof, period, channel); + timer_adjust_oneshot(lcd_regs->dma[channel].eof, period, channel); - if(lcd_regs.dma[channel].ldcmd & PXA255_LDCMD_SOFINT) + if(lcd_regs->dma[channel].ldcmd & PXA255_LDCMD_SOFINT) { - lcd_regs.liidr = lcd_regs.dma[channel].fidr; - lcd_regs.lcsr |= PXA255_LCSR_SOF; + lcd_regs->liidr = lcd_regs->dma[channel].fidr; + lcd_regs->lcsr |= PXA255_LCSR_SOF; pxa255_lcd_irq_check(machine); } - if(lcd_regs.dma[channel].ldcmd & PXA255_LDCMD_PAL) + if(lcd_regs->dma[channel].ldcmd & PXA255_LDCMD_PAL) { - int length = lcd_regs.dma[channel].ldcmd & 0x000fffff; + int length = lcd_regs->dma[channel].ldcmd & 0x000fffff; int index = 0; for(index = 0; index < length; index += 2) { - UINT16 color = memory_read_word_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), (lcd_regs.dma[channel].fsadr &~ 1) + index); - pxa255_lcd_palette[index >> 1] = (((((color >> 11) & 0x1f) << 3) | (color >> 13)) << 16) | (((((color >> 5) & 0x3f) << 2) | ((color >> 9) & 0x3)) << 8) | (((color & 0x1f) << 3) | ((color >> 2) & 0x7)); + UINT16 color = memory_read_word_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), (lcd_regs->dma[channel].fsadr &~ 1) + index); + state->pxa255_lcd_palette[index >> 1] = (((((color >> 11) & 0x1f) << 3) | (color >> 13)) << 16) | (((((color >> 5) & 0x3f) << 2) | ((color >> 9) & 0x3)) << 8) | (((color & 0x1f) << 3) | ((color >> 2) & 0x7)); palette_set_color_rgb(machine, index >> 1, (((color >> 11) & 0x1f) << 3) | (color >> 13), (((color >> 5) & 0x3f) << 2) | ((color >> 9) & 0x3), ((color & 0x1f) << 3) | ((color >> 2) & 0x7)); } } else { - int length = lcd_regs.dma[channel].ldcmd & 0x000fffff; + int length = lcd_regs->dma[channel].ldcmd & 0x000fffff; int index = 0; for(index = 0; index < length; index++) { - pxa255_lcd_framebuffer[index] = memory_read_byte_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs.dma[channel].fsadr + index); + state->pxa255_lcd_framebuffer[index] = memory_read_byte_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs->dma[channel].fsadr + index); } } } @@ -1053,37 +1119,43 @@ static void pxa255_lcd_dma_kickoff(running_machine* machine, int channel) static void pxa255_lcd_check_load_next_branch(running_machine* machine, int channel) { - if(lcd_regs.fbr[channel] & 1) + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + + if(lcd_regs->fbr[channel] & 1) { verboselog( machine, 4, "pxa255_lcd_check_load_next_branch: Taking branch\n" ); - lcd_regs.fbr[channel] &= ~1; - //lcd_regs.fbr[channel] = (memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs.fbr[channel] & 0xfffffff0) & 0xfffffff0) | (lcd_regs.fbr[channel] & 0x00000003); - //printf( "%08x\n", lcd_regs.fbr[channel] ); - pxa255_lcd_load_dma_descriptor(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs.fbr[channel] & 0xfffffff0, 0); - lcd_regs.fbr[channel] = (memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs.fbr[channel] & 0xfffffff0) & 0xfffffff0) | (lcd_regs.fbr[channel] & 0x00000003); + lcd_regs->fbr[channel] &= ~1; + //lcd_regs->fbr[channel] = (memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs->fbr[channel] & 0xfffffff0) & 0xfffffff0) | (lcd_regs->fbr[channel] & 0x00000003); + //printf( "%08x\n", lcd_regs->fbr[channel] ); + pxa255_lcd_load_dma_descriptor(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs->fbr[channel] & 0xfffffff0, 0); + lcd_regs->fbr[channel] = (memory_read_dword_32le(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lcd_regs->fbr[channel] & 0xfffffff0) & 0xfffffff0) | (lcd_regs->fbr[channel] & 0x00000003); pxa255_lcd_dma_kickoff(machine, 0); - if(lcd_regs.fbr[channel] & 2) + if(lcd_regs->fbr[channel] & 2) { - lcd_regs.fbr[channel] &= ~2; - if(!(lcd_regs.lccr0 & PXA255_LCCR0_BM)) + lcd_regs->fbr[channel] &= ~2; + if(!(lcd_regs->lccr0 & PXA255_LCCR0_BM)) { - lcd_regs.lcsr |= PXA255_LCSR_BS; + lcd_regs->lcsr |= PXA255_LCSR_BS; } } } else { -// verboselog( machine, 3, "pxa255_lcd_check_load_next_branch: Not taking branch\n" ); + if (0) verboselog( machine, 3, "pxa255_lcd_check_load_next_branch: Not taking branch\n" ); } } static TIMER_CALLBACK( pxa255_lcd_dma_eof ) { -// verboselog( machine, 3, "End of frame callback\n" ); - if(lcd_regs.dma[param].ldcmd & PXA255_LDCMD_EOFINT) + _39in1_state *state = (_39in1_state *)machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + + if (0) verboselog( machine, 3, "End of frame callback\n" ); + if(lcd_regs->dma[param].ldcmd & PXA255_LDCMD_EOFINT) { - lcd_regs.liidr = lcd_regs.dma[param].fidr; - lcd_regs.lcsr |= PXA255_LCSR_EOF; + lcd_regs->liidr = lcd_regs->dma[param].fidr; + lcd_regs->lcsr |= PXA255_LCSR_EOF; } pxa255_lcd_check_load_next_branch(machine, param); pxa255_lcd_irq_check(machine); @@ -1091,62 +1163,65 @@ static TIMER_CALLBACK( pxa255_lcd_dma_eof ) static READ32_HANDLER( pxa255_lcd_r ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + switch(PXA255_LCD_BASE_ADDR | (offset << 2)) { case PXA255_LCCR0: // 0x44000000 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 0: %08x & %08x\n", lcd_regs.lccr0, mem_mask ); - return lcd_regs.lccr0; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 0: %08x & %08x\n", lcd_regs->lccr0, mem_mask ); + return lcd_regs->lccr0; case PXA255_LCCR1: // 0x44000004 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 1: %08x & %08x\n", lcd_regs.lccr1, mem_mask ); - return lcd_regs.lccr1; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 1: %08x & %08x\n", lcd_regs->lccr1, mem_mask ); + return lcd_regs->lccr1; case PXA255_LCCR2: // 0x44000008 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 2: %08x & %08x\n", lcd_regs.lccr2, mem_mask ); - return lcd_regs.lccr2; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 2: %08x & %08x\n", lcd_regs->lccr2, mem_mask ); + return lcd_regs->lccr2; case PXA255_LCCR3: // 0x4400000c - verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 3: %08x & %08x\n", lcd_regs.lccr3, mem_mask ); - return lcd_regs.lccr3; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD Control 3: %08x & %08x\n", lcd_regs->lccr3, mem_mask ); + return lcd_regs->lccr3; case PXA255_FBR0: // 0x44000020 - verboselog( space->machine, 4, "pxa255_lcd_r: LCD Frame Branch Register 0: %08x & %08x\n", lcd_regs.fbr[0], mem_mask ); - return lcd_regs.fbr[0]; + verboselog( space->machine, 4, "pxa255_lcd_r: LCD Frame Branch Register 0: %08x & %08x\n", lcd_regs->fbr[0], mem_mask ); + return lcd_regs->fbr[0]; case PXA255_FBR1: // 0x44000024 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD Frame Branch Register 1: %08x & %08x\n", lcd_regs.fbr[1], mem_mask ); - return lcd_regs.fbr[1]; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD Frame Branch Register 1: %08x & %08x\n", lcd_regs->fbr[1], mem_mask ); + return lcd_regs->fbr[1]; case PXA255_LCSR: // 0x44000038 - verboselog( space->machine, 4, "pxa255_lcd_r: LCD Status Register: %08x & %08x\n", lcd_regs.lcsr, mem_mask ); - return lcd_regs.lcsr; + verboselog( space->machine, 4, "pxa255_lcd_r: LCD Status Register: %08x & %08x\n", lcd_regs->lcsr, mem_mask ); + return lcd_regs->lcsr; case PXA255_LIIDR: // 0x4400003c - verboselog( space->machine, 3, "pxa255_lcd_r: LCD Interrupt ID Register: %08x & %08x\n", lcd_regs.liidr, mem_mask ); - return lcd_regs.liidr; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD Interrupt ID Register: %08x & %08x\n", lcd_regs->liidr, mem_mask ); + return lcd_regs->liidr; case PXA255_TRGBR: // 0x44000040 - verboselog( space->machine, 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs.trgbr, mem_mask ); - return lcd_regs.trgbr; + verboselog( space->machine, 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs->trgbr, mem_mask ); + return lcd_regs->trgbr; case PXA255_TCR: // 0x44000044 - verboselog( space->machine, 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs.tcr, mem_mask ); - return lcd_regs.tcr; + verboselog( space->machine, 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs->tcr, mem_mask ); + return lcd_regs->tcr; case PXA255_FDADR0: // 0x44000200 -// verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", lcd_regs.dma[0].fdadr, mem_mask ); - return lcd_regs.dma[0].fdadr; + if (0) verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", lcd_regs->dma[0].fdadr, mem_mask ); + return lcd_regs->dma[0].fdadr; case PXA255_FSADR0: // 0x44000204 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 0: %08x & %08x\n", lcd_regs.dma[0].fsadr, mem_mask ); - return lcd_regs.dma[0].fsadr; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 0: %08x & %08x\n", lcd_regs->dma[0].fsadr, mem_mask ); + return lcd_regs->dma[0].fsadr; case PXA255_FIDR0: // 0x44000208 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame ID Register 0: %08x & %08x\n", lcd_regs.dma[0].fidr, mem_mask ); - return lcd_regs.dma[0].fidr; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame ID Register 0: %08x & %08x\n", lcd_regs->dma[0].fidr, mem_mask ); + return lcd_regs->dma[0].fidr; case PXA255_LDCMD0: // 0x4400020c -// verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Command Register 0: %08x & %08x\n", lcd_regs.dma[0].ldcmd & 0xfff00000, mem_mask ); - return lcd_regs.dma[0].ldcmd & 0xfff00000; + if (0) verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Command Register 0: %08x & %08x\n", lcd_regs->dma[0].ldcmd & 0xfff00000, mem_mask ); + return lcd_regs->dma[0].ldcmd & 0xfff00000; case PXA255_FDADR1: // 0x44000210 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", lcd_regs.dma[1].fdadr, mem_mask ); - return lcd_regs.dma[1].fdadr; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", lcd_regs->dma[1].fdadr, mem_mask ); + return lcd_regs->dma[1].fdadr; case PXA255_FSADR1: // 0x44000214 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 1: %08x & %08x\n", lcd_regs.dma[1].fsadr, mem_mask ); - return lcd_regs.dma[1].fsadr; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 1: %08x & %08x\n", lcd_regs->dma[1].fsadr, mem_mask ); + return lcd_regs->dma[1].fsadr; case PXA255_FIDR1: // 0x44000218 - verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame ID Register 1: %08x & %08x\n", lcd_regs.dma[1].fidr, mem_mask ); - return lcd_regs.dma[1].fidr; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame ID Register 1: %08x & %08x\n", lcd_regs->dma[1].fidr, mem_mask ); + return lcd_regs->dma[1].fidr; case PXA255_LDCMD1: // 0x4400021c - verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Command Register 1: %08x & %08x\n", lcd_regs.dma[1].ldcmd & 0xfff00000, mem_mask ); - return lcd_regs.dma[1].ldcmd & 0xfff00000; + verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Command Register 1: %08x & %08x\n", lcd_regs->dma[1].ldcmd & 0xfff00000, mem_mask ); + return lcd_regs->dma[1].ldcmd & 0xfff00000; default: verboselog( space->machine, 0, "pxa255_lcd_r: Unknown address: %08x\n", PXA255_LCD_BASE_ADDR | (offset << 2)); break; @@ -1156,38 +1231,41 @@ static READ32_HANDLER( pxa255_lcd_r ) static WRITE32_HANDLER( pxa255_lcd_w ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + PXA255_LCD_Regs *lcd_regs = &state->lcd_regs; + switch(PXA255_LCD_BASE_ADDR | (offset << 2)) { case PXA255_LCCR0: // 0x44000000 verboselog( space->machine, 3, "pxa255_lcd_w: LCD Control 0: %08x & %08x\n", data, mem_mask ); - lcd_regs.lccr0 = data & 0x00fffeff; + lcd_regs->lccr0 = data & 0x00fffeff; break; case PXA255_LCCR1: // 0x44000004 verboselog( space->machine, 3, "pxa255_lcd_w: LCD Control 1: %08x & %08x\n", data, mem_mask ); - lcd_regs.lccr1 = data; + lcd_regs->lccr1 = data; break; case PXA255_LCCR2: // 0x44000008 verboselog( space->machine, 3, "pxa255_lcd_w: LCD Control 2: %08x & %08x\n", data, mem_mask ); - lcd_regs.lccr2 = data; + lcd_regs->lccr2 = data; break; case PXA255_LCCR3: // 0x4400000c verboselog( space->machine, 3, "pxa255_lcd_w: LCD Control 3: %08x & %08x\n", data, mem_mask ); - lcd_regs.lccr3 = data; + lcd_regs->lccr3 = data; break; case PXA255_FBR0: // 0x44000020 verboselog( space->machine, 4l, "pxa255_lcd_w: LCD Frame Branch Register 0: %08x & %08x\n", data, mem_mask ); - lcd_regs.fbr[0] = data & 0xfffffff3; - if(!timer_enabled(lcd_regs.dma[0].eof)) + lcd_regs->fbr[0] = data & 0xfffffff3; + if(!timer_enabled(lcd_regs->dma[0].eof)) { -// verboselog( space->machine, 3, "ch0 EOF timer is not enabled, taking branch now\n" ); + if (0) verboselog( space->machine, 3, "ch0 EOF timer is not enabled, taking branch now\n" ); pxa255_lcd_check_load_next_branch(space->machine, 0); pxa255_lcd_irq_check(space->machine); } break; case PXA255_FBR1: // 0x44000024 verboselog( space->machine, 3, "pxa255_lcd_w: LCD Frame Branch Register 1: %08x & %08x\n", data, mem_mask ); - lcd_regs.fbr[1] = data & 0xfffffff3; - if(!timer_enabled(lcd_regs.dma[1].eof)) + lcd_regs->fbr[1] = data & 0xfffffff3; + if(!timer_enabled(lcd_regs->dma[1].eof)) { verboselog( space->machine, 3, "ch1 EOF timer is not enabled, taking branch now\n" ); pxa255_lcd_check_load_next_branch(space->machine, 1); @@ -1196,7 +1274,7 @@ static WRITE32_HANDLER( pxa255_lcd_w ) break; case PXA255_LCSR: // 0x44000038 verboselog( space->machine, 4, "pxa255_lcd_w: LCD Controller Status Register: %08x & %08x\n", data, mem_mask ); - lcd_regs.lcsr &= ~data; + lcd_regs->lcsr &= ~data; pxa255_lcd_irq_check(space->machine); break; case PXA255_LIIDR: // 0x4400003c @@ -1204,22 +1282,22 @@ static WRITE32_HANDLER( pxa255_lcd_w ) break; case PXA255_TRGBR: // 0x44000040 verboselog( space->machine, 3, "pxa255_lcd_w: TMED RGB Seed Register: %08x & %08x\n", data, mem_mask ); - lcd_regs.trgbr = data & 0x00ffffff; + lcd_regs->trgbr = data & 0x00ffffff; break; case PXA255_TCR: // 0x44000044 verboselog( space->machine, 3, "pxa255_lcd_w: TMED Control Register: %08x & %08x\n", data, mem_mask ); - lcd_regs.tcr = data & 0x00004fff; + lcd_regs->tcr = data & 0x00004fff; break; case PXA255_FDADR0: // 0x44000200 verboselog( space->machine, 4, "pxa255_lcd_w: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", data, mem_mask ); - if(!timer_enabled(lcd_regs.dma[0].eof)) + if(!timer_enabled(lcd_regs->dma[0].eof)) { pxa255_lcd_load_dma_descriptor(space, data & 0xfffffff0, 0); } else { - lcd_regs.fbr[0] &= 0x00000003; - lcd_regs.fbr[0] |= data & 0xfffffff0; + lcd_regs->fbr[0] &= 0x00000003; + lcd_regs->fbr[0] |= data & 0xfffffff0; } break; case PXA255_FSADR0: // 0x44000204 @@ -1233,14 +1311,14 @@ static WRITE32_HANDLER( pxa255_lcd_w ) break; case PXA255_FDADR1: // 0x44000210 verboselog( space->machine, 4, "pxa255_lcd_w: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", data, mem_mask ); - if(!timer_enabled(lcd_regs.dma[1].eof)) + if(!timer_enabled(lcd_regs->dma[1].eof)) { pxa255_lcd_load_dma_descriptor(space, data & 0xfffffff0, 1); } else { - lcd_regs.fbr[1] &= 0x00000003; - lcd_regs.fbr[1] |= data & 0xfffffff0; + lcd_regs->fbr[1] &= 0x00000003; + lcd_regs->fbr[1] |= data & 0xfffffff0; } break; case PXA255_FSADR1: // 0x44000214 @@ -1262,21 +1340,23 @@ static INTERRUPT_GEN( pxa255_vblank_start ) { } -//static READ32_HANDLER( return_zero ) -//{ -// return 0; -//} +#ifdef UNUSED_FUNCTION +static READ32_HANDLER( return_zero ) +{ + return 0; +} -//static READ32_HANDLER( unknown_r ) -//{ -// //return 0x00008000; -//} +static READ32_HANDLER( unknown_r ) +{ + return 0x00008000; +} +#endif -static UINT32 seed, magic; -static UINT32 state = 0; static READ32_HANDLER( cpld_r ) { -// if (cpu_get_pc(space->cpu) != 0xe3af4) printf("CPLD read @ %x (PC %x state %d)\n", offset, cpu_get_pc(space->cpu), state); + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + + //if (cpu_get_pc(space->cpu) != 0xe3af4) printf("CPLD read @ %x (PC %x state %d)\n", offset, cpu_get_pc(space->cpu), state); if (cpu_get_pc(space->cpu) == 0x3f04) { @@ -1288,11 +1368,11 @@ static READ32_HANDLER( cpld_r ) } else { - if (state == 0) + if (state->state == 0) { return 0; } - else if (state == 1) + else if (state->state == 1) { switch (offset & ~1) { @@ -1307,18 +1387,22 @@ static READ32_HANDLER( cpld_r ) default: printf("State 1 unknown offset %x\n", offset); break; } } - else if (state == 2) // 29c0: 53 ac 0c 2b a2 07 e6 be 31 + else if (state->state == 2) // 29c0: 53 ac 0c 2b a2 07 e6 be 31 { - magic = ( (((~(seed >> 16)) ^ (magic >> 1)) & 0x01) | - (((~((seed >> 19) << 1)) ^ ((magic >> 5) << 1)) & 0x02) | - (((~((seed >> 20) << 2)) ^ ((magic >> 3) << 2)) & 0x04) | - (((~((seed >> 22) << 3)) ^ ((magic >> 6) << 3)) & 0x08) | - (((~((seed >> 23) << 4)) ^ magic) & 0x10) | - (((~(((seed >> 16) >> 2) << 5)) ^ ((magic >> 2) << 5)) & 0x20) | - (((~(((seed >> 16) >> 1) << 6)) ^ ((magic >> 7) << 6)) & 0x40) | - (((~(((seed >> 16) >> 5) << 7)) ^ (magic << 7)) & 0x80)); + UINT32 seed = state->seed; + UINT32 magic = state->magic; - return magic; + magic = ( (((~(seed >> 16)) ^ (magic >> 1)) & 0x01) | + (((~((seed >> 19) << 1)) ^ ((magic >> 5) << 1)) & 0x02) | + (((~((seed >> 20) << 2)) ^ ((magic >> 3) << 2)) & 0x04) | + (((~((seed >> 22) << 3)) ^ ((magic >> 6) << 3)) & 0x08) | + (((~((seed >> 23) << 4)) ^ magic) & 0x10) | + (((~(((seed >> 16) >> 2) << 5)) ^ ((magic >> 2) << 5)) & 0x20) | + (((~(((seed >> 16) >> 1) << 6)) ^ ((magic >> 7) << 6)) & 0x40) | + (((~(((seed >> 16) >> 5) << 7)) ^ (magic << 7)) & 0x80)); + + state->magic = magic; + return magic; } } @@ -1327,27 +1411,31 @@ static READ32_HANDLER( cpld_r ) static WRITE32_HANDLER( cpld_w ) { + _39in1_state *state = (_39in1_state *)space->machine->driver_data; + if (mem_mask == 0xffff) { - seed = data<<16; + state->seed = data<<16; } if (cpu_get_pc(space->cpu) == 0x280c) { - state = 1; + state->state = 1; } if (cpu_get_pc(space->cpu) == 0x2874) { - state = 2; - magic = memory_read_byte_32le(space, 0x2d4ff0); + state->state = 2; + state->magic = memory_read_byte_32le(space, 0x2d4ff0); } else if (offset == 0xa) { } -// else -// { -// printf("%08x: CPLD_W: %08x = %08x & %08x\n", cpu_get_pc(space->cpu), offset, data, mem_mask); -// } +#if 0 + else + { + printf("%08x: CPLD_W: %08x = %08x & %08x\n", cpu_get_pc(space->cpu), offset, data, mem_mask); + } +#endif } static READ32_HANDLER( prot_cheater_r ) @@ -1357,6 +1445,12 @@ static READ32_HANDLER( prot_cheater_r ) static DRIVER_INIT( 39in1 ) { + _39in1_state *state = (_39in1_state *)machine->driver_data; + + state->dmadac[0] = devtag_get_device(machine, "dac1"); + state->dmadac[1] = devtag_get_device(machine, "dac2"); + state->eeprom = devtag_get_device(machine, "eeprom"); + memory_install_read32_handler (cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa0151648, 0xa015164b, 0, 0, prot_cheater_r); } @@ -1370,7 +1464,7 @@ static ADDRESS_MAP_START( 39in1_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0x40d00000, 0x40d00017) AM_READWRITE( pxa255_intc_r, pxa255_intc_w ) AM_RANGE(0x40e00000, 0x40e0006b) AM_READWRITE( pxa255_gpio_r, pxa255_gpio_w ) AM_RANGE(0x44000000, 0x4400021f) AM_READWRITE( pxa255_lcd_r, pxa255_lcd_w ) - AM_RANGE(0xa0000000, 0xa07fffff) AM_RAM AM_BASE(&ram) + AM_RANGE(0xa0000000, 0xa07fffff) AM_RAM AM_BASE_MEMBER(_39in1_state,ram) ADDRESS_MAP_END static INPUT_PORTS_START( 39in1 ) @@ -1411,14 +1505,16 @@ INPUT_PORTS_END static VIDEO_UPDATE( 39in1 ) { + _39in1_state *state = (_39in1_state *)screen->machine->driver_data; int x = 0; int y = 0; - for(y = 0; y <= (lcd_regs.lccr2 & PXA255_LCCR2_LPP); y++) + + for(y = 0; y <= (state->lcd_regs.lccr2 & PXA255_LCCR2_LPP); y++) { UINT32 *d = BITMAP_ADDR32(bitmap, y, 0); - for(x = 0; x <= (lcd_regs.lccr1 & PXA255_LCCR1_PPL); x++) + for(x = 0; x <= (state->lcd_regs.lccr1 & PXA255_LCCR1_PPL); x++) { - d[x] = pxa255_lcd_palette[pxa255_lcd_framebuffer[y*((lcd_regs.lccr1 & PXA255_LCCR1_PPL) + 1) + x]]; + d[x] = state->pxa255_lcd_palette[state->pxa255_lcd_framebuffer[y*((state->lcd_regs.lccr1 & PXA255_LCCR1_PPL) + 1) + x]]; } } return 0; @@ -1427,39 +1523,35 @@ static VIDEO_UPDATE( 39in1 ) /* To be moved to DEVICE_START( pxa255 ) upon completion */ static void pxa255_start(running_machine* machine) { + _39in1_state *state = (_39in1_state *)machine->driver_data; int index = 0; - //pxa255_t* pxa255 = pxa255_get_safe_token( device ); + //pxa255_t* pxa255 = pxa255_get_safe_token( device ); - //pxa255->iface = device->baseconfig().static_config; + //pxa255->iface = device->base_config().static_config; for(index = 0; index < 16; index++) { - dma_regs.dcsr[index] = 0x00000008; - dma_regs.timer[index] = timer_alloc(machine, pxa255_dma_dma_end, 0); + state->dma_regs.dcsr[index] = 0x00000008; + state->dma_regs.timer[index] = timer_alloc(machine, pxa255_dma_dma_end, 0); } - ostimer_regs.oscr = ostimer_regs.ossr = ostimer_regs.ower = ostimer_regs.oier = 0; + memset(&state->ostimer_regs, 0, sizeof(state->ostimer_regs)); for(index = 0; index < 4; index++) { - ostimer_regs.osmr[index] = 0; - ostimer_regs.timer[index] = timer_alloc(machine, pxa255_ostimer_match, 0); + state->ostimer_regs.osmr[index] = 0; + state->ostimer_regs.timer[index] = timer_alloc(machine, pxa255_ostimer_match, 0); } - intc_regs.icmr = intc_regs.iclr = intc_regs.iccr = intc_regs.icip = intc_regs.icfp = intc_regs.icpr = 0; + memset(&state->intc_regs, 0, sizeof(state->intc_regs)); - lcd_regs.lccr0 = lcd_regs.lccr1 = lcd_regs.lccr2 = lcd_regs.lccr3 = 0; - lcd_regs.dma[0].fdadr = lcd_regs.dma[1].fdadr = 0; - lcd_regs.dma[0].fsadr = lcd_regs.dma[1].fsadr = 0; - lcd_regs.dma[0].fidr = lcd_regs.dma[1].fidr = 0; - lcd_regs.dma[0].ldcmd = lcd_regs.dma[1].ldcmd = 0; - lcd_regs.dma[0].eof = timer_alloc(machine, pxa255_lcd_dma_eof, 0); - lcd_regs.dma[1].eof = timer_alloc(machine, pxa255_lcd_dma_eof, 0); - lcd_regs.fbr[0] = lcd_regs.fbr[1] = lcd_regs.lcsr = lcd_regs.liidr = 0; - lcd_regs.trgbr = 0x00aa5500; - lcd_regs.tcr = 0x0000754f; + memset(&state->lcd_regs, 0, sizeof(state->lcd_regs)); + state->lcd_regs.dma[0].eof = timer_alloc(machine, pxa255_lcd_dma_eof, 0); + state->lcd_regs.dma[1].eof = timer_alloc(machine, pxa255_lcd_dma_eof, 0); + state->lcd_regs.trgbr = 0x00aa5500; + state->lcd_regs.tcr = 0x0000754f; - //pxa255_register_state_save(device); + //pxa255_register_state_save(device); } static MACHINE_START(39in1) @@ -1482,6 +1574,9 @@ static MACHINE_START(39in1) } static MACHINE_DRIVER_START( 39in1 ) + + MDRV_DRIVER_DATA( _39in1_state ) + MDRV_CPU_ADD("maincpu", PXA255, 200000000) MDRV_CPU_PROGRAM_MAP(39in1_map) MDRV_CPU_VBLANK_INT("screen", pxa255_vblank_start) @@ -1512,11 +1607,11 @@ MACHINE_DRIVER_END ROM_START( 39in1 ) // main program, encrypted ROM_REGION( 0x80000, "maincpu", 0 ) - ROM_LOAD( "27c4096_plz-v001_ver.300.bin", 0x000000, 0x080000, CRC(9149dbc4) SHA1(40efe1f654f11474f75ae7fee1613f435dbede38) ) + ROM_LOAD( "27c4096_plz-v001_ver.300.bin", 0x000000, 0x080000, CRC(9149dbc4) SHA1(40efe1f654f11474f75ae7fee1613f435dbede38) ) // data ROM - contains a filesystem with ROMs, fonts, graphics, etc. in an unknown compressed format ROM_REGION32_LE( 0x200000, "data", 0 ) - ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) ) + ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) ) // EEPROM - contains security data ROM_REGION16_BE( 0x200, "eeprom", 0 ) @@ -1526,11 +1621,11 @@ ROM_END ROM_START( 48in1 ) // main program, encrypted ROM_REGION( 0x80000, "maincpu", 0 ) - ROM_LOAD( "hph_ver309", 0x000000, 0x080000, CRC(27023186) SHA1(a2b3770c4b03d6026c6a0ff2e62ab17c3b359b12) ) + ROM_LOAD( "hph_ver309", 0x000000, 0x080000, CRC(27023186) SHA1(a2b3770c4b03d6026c6a0ff2e62ab17c3b359b12) ) // data ROM - contains a filesystem with ROMs, fonts, graphics, etc. in an unknown compressed format ROM_REGION32_LE( 0x200000, "data", 0 ) - ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) ) + ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) ) // EEPROM - contains security data ROM_REGION16_BE( 0x200, "eeprom", 0 ) @@ -1540,11 +1635,11 @@ ROM_END ROM_START( 48in1a ) // main program, encrypted ROM_REGION( 0x80000, "maincpu", 0 ) - ROM_LOAD( "ver302.u2", 0x000000, 0x080000, CRC(5ea25870) SHA1(66edc59a3d355bc3462e98d2062ada721c371af6) ) + ROM_LOAD( "ver302.u2", 0x000000, 0x080000, CRC(5ea25870) SHA1(66edc59a3d355bc3462e98d2062ada721c371af6) ) // data ROM - contains a filesystem with ROMs, fonts, graphics, etc. in an unknown compressed format ROM_REGION32_LE( 0x200000, "data", 0 ) - ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) ) + ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) ) // EEPROM - contains security data ROM_REGION16_BE( 0x200, "eeprom", 0 ) diff --git a/src/mame/drivers/raiden2.c b/src/mame/drivers/raiden2.c index c92fb7b222f..046f4578a91 100644 --- a/src/mame/drivers/raiden2.c +++ b/src/mame/drivers/raiden2.c @@ -145,15 +145,58 @@ Current Problem(s) - in order of priority #include "includes/raiden2.h" -static tilemap_t *background_layer,*midground_layer,*foreground_layer,*text_layer; -static UINT16 *back_data,*fore_data,*mid_data, *w1ram; -static int bg_bank, fg_bank, mid_bank; -static int bg_col, fg_col, mid_col; +typedef struct _sprcpt_state sprcpt_state; +struct _sprcpt_state +{ + UINT32 adr; + UINT32 idx; -static int tick; -static UINT16 *mainram; + UINT16 flags2; + UINT32 val[2]; + UINT32 flags1; + UINT32 data_1[0x100]; + UINT32 data_2[0x40]; + UINT32 data_3[6]; + UINT32 data_4[4]; +}; -static int c_r[0xc000], c_w[0xc000]; + +typedef struct _raiden2_state raiden2_state; +struct _raiden2_state +{ + tilemap_t *background_layer; + tilemap_t *midground_layer; + tilemap_t *foreground_layer; + tilemap_t *text_layer; + + UINT16 *back_data; + UINT16 *fore_data; + UINT16 *mid_data; + UINT16 *w1ram; + UINT16 *mainram; + UINT16 *spriteram; + UINT16 *videoram; + + int bg_bank; + int fg_bank; + int mid_bank; + int bg_col; + int fg_col; + int mid_col; + + //int tick; + + sprcpt_state sprcpt; + + UINT16 mcu_prog[0x400]; + int mcu_prog_offs; + + struct + { + int read; + int write; + } stat[0xc000]; +}; static void combine32(UINT32 *val, int offset, UINT16 data, UINT16 mem_mask) { @@ -165,10 +208,11 @@ static void combine32(UINT32 *val, int offset, UINT16 data, UINT16 mem_mask) /* SPRITE DRAWING (move to video file) */ -static void draw_sprites(running_machine *machine, bitmap_t *bitmap, const rectangle *cliprect ,int pri_mask ) +static void draw_sprites(running_machine *machine, bitmap_t *bitmap, const rectangle *cliprect, int pri_mask ) { - const UINT16 *source = machine->generic.spriteram.u16 + 0x1000/2 - 4; - const UINT16 *finish = machine->generic.spriteram.u16; + raiden2_state *state = (raiden2_state *)machine->driver_data; + const UINT16 *source = state->spriteram + 0x1000/2 - 4; + const UINT16 *finish = state->spriteram; const gfx_element *gfx = machine->gfx[2]; @@ -262,57 +306,68 @@ static void draw_sprites(running_machine *machine, bitmap_t *bitmap, const recta static WRITE16_HANDLER(raiden2_background_w) { - COMBINE_DATA(&back_data[offset]); - tilemap_mark_tile_dirty(background_layer, offset); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + COMBINE_DATA(&state->back_data[offset]); + tilemap_mark_tile_dirty(state->background_layer, offset); } static WRITE16_HANDLER(raiden2_midground_w) { - COMBINE_DATA(&mid_data[offset]); - tilemap_mark_tile_dirty(midground_layer,offset); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + COMBINE_DATA(&state->mid_data[offset]); + tilemap_mark_tile_dirty(state->midground_layer,offset); } static WRITE16_HANDLER(raiden2_foreground_w) { - COMBINE_DATA(&fore_data[offset]); - tilemap_mark_tile_dirty(foreground_layer,offset); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + COMBINE_DATA(&state->fore_data[offset]); + tilemap_mark_tile_dirty(state->foreground_layer,offset); } static WRITE16_HANDLER(raiden2_text_w) { - COMBINE_DATA(&space->machine->generic.videoram.u16[offset]); - tilemap_mark_tile_dirty(text_layer, offset); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + COMBINE_DATA(&state->videoram[offset]); + tilemap_mark_tile_dirty(state->text_layer, offset); } /* TILEMAP RELATED (move to video file) */ static TILE_GET_INFO( get_back_tile_info ) { - int tile = back_data[tile_index]; - int color = (tile >> 12) | (bg_col << 4); + raiden2_state *state = (raiden2_state *)machine->driver_data; + int tile = state->back_data[tile_index]; + int color = (tile >> 12) | (state->bg_col << 4); - tile = (tile & 0xfff) | (bg_bank << 12); + tile = (tile & 0xfff) | (state->bg_bank << 12); SET_TILE_INFO(1,tile+0x0000,color,0); } static TILE_GET_INFO( get_mid_tile_info ) { - int tile = mid_data[tile_index]; - int color = (tile >> 12) | (mid_col << 4); + raiden2_state *state = (raiden2_state *)machine->driver_data; + int tile = state->mid_data[tile_index]; + int color = (tile >> 12) | (state->mid_col << 4); - tile = (tile & 0xfff) | (mid_bank << 12); + tile = (tile & 0xfff) | (state->mid_bank << 12); SET_TILE_INFO(1,tile,color,0); } static TILE_GET_INFO( get_fore_tile_info ) { - int tile = fore_data[tile_index]; - int color = (tile >> 12) | (fg_col << 4); + raiden2_state *state = (raiden2_state *)machine->driver_data; + int tile = state->fore_data[tile_index]; + int color = (tile >> 12) | (state->fg_col << 4); - tile = (tile & 0xfff) | (fg_bank << 12); + tile = (tile & 0xfff) | (state->fg_bank << 12); // tile = (tile & 0xfff) | (3<<12); // 3000 intro (cliff) 1000 game (bg ) SET_TILE_INFO(1,tile,color,0); @@ -320,7 +375,8 @@ static TILE_GET_INFO( get_fore_tile_info ) static TILE_GET_INFO( get_text_tile_info ) { - int tile = machine->generic.videoram.u16[tile_index]; + raiden2_state *state = (raiden2_state *)machine->driver_data; + int tile = state->videoram[tile_index]; int color = (tile>>12)&0xf; tile &= 0xfff; @@ -341,16 +397,18 @@ static void set_scroll(tilemap_t *tm, int plane) static VIDEO_START( raiden2 ) { - text_layer = tilemap_create(machine, get_text_tile_info, tilemap_scan_rows, 8, 8, 64,32 ); - background_layer = tilemap_create(machine, get_back_tile_info, tilemap_scan_rows, 16,16, 32,32 ); - midground_layer = tilemap_create(machine, get_mid_tile_info, tilemap_scan_rows, 16,16, 32,32 ); - foreground_layer = tilemap_create(machine, get_fore_tile_info, tilemap_scan_rows, 16,16, 32,32 ); + raiden2_state *state = (raiden2_state *)machine->driver_data; - tilemap_set_transparent_pen(midground_layer, 15); - tilemap_set_transparent_pen(foreground_layer, 15); - tilemap_set_transparent_pen(text_layer, 15); + state->text_layer = tilemap_create(machine, get_text_tile_info, tilemap_scan_rows, 8, 8, 64,32 ); + state->background_layer = tilemap_create(machine, get_back_tile_info, tilemap_scan_rows, 16,16, 32,32 ); + state->midground_layer = tilemap_create(machine, get_mid_tile_info, tilemap_scan_rows, 16,16, 32,32 ); + state->foreground_layer = tilemap_create(machine, get_fore_tile_info, tilemap_scan_rows, 16,16, 32,32 ); - tick = 0; + tilemap_set_transparent_pen(state->midground_layer, 15); + tilemap_set_transparent_pen(state->foreground_layer, 15); + tilemap_set_transparent_pen(state->text_layer, 15); + + //state->tick = 0; } // XXX @@ -366,7 +424,7 @@ static VIDEO_START( raiden2 ) static VIDEO_UPDATE ( raiden2 ) { - + raiden2_state *state = (raiden2_state *)screen->machine->driver_data; #if 0 int info_1, info_2, info_3; @@ -540,16 +598,16 @@ static VIDEO_UPDATE ( raiden2 ) bitmap_fill(bitmap, cliprect, get_black_pen(screen->machine)); if (!input_code_pressed(screen->machine, KEYCODE_Q)) - tilemap_draw(bitmap, cliprect, background_layer, 0, 0); + tilemap_draw(bitmap, cliprect, state->background_layer, 0, 0); if (!input_code_pressed(screen->machine, KEYCODE_W)) - tilemap_draw(bitmap, cliprect, midground_layer, 0, 0); + tilemap_draw(bitmap, cliprect, state->midground_layer, 0, 0); if (!input_code_pressed(screen->machine, KEYCODE_E)) - tilemap_draw(bitmap, cliprect, foreground_layer, 0, 0); + tilemap_draw(bitmap, cliprect, state->foreground_layer, 0, 0); draw_sprites(screen->machine, bitmap, cliprect, 0); if (!input_code_pressed(screen->machine, KEYCODE_A)) - tilemap_draw(bitmap, cliprect, text_layer, 0, 0); + tilemap_draw(bitmap, cliprect, state->text_layer, 0, 0); return 0; } @@ -575,90 +633,105 @@ static INTERRUPT_GEN( raiden2_interrupt ) // Sprite encryption key upload -static UINT32 sprcpt_adr, sprcpt_idx; - -static UINT16 sprcpt_flags2; -static UINT32 sprcpt_val[2], sprcpt_flags1; -static UINT32 sprcpt_data_1[0x100], sprcpt_data_2[0x40], sprcpt_data_3[6], sprcpt_data_4[4]; - -static void sprcpt_init(void) +static void sprcpt_init(running_machine *machine) { - memset(sprcpt_data_1, 0, sizeof(sprcpt_data_1)); - memset(sprcpt_data_2, 0, sizeof(sprcpt_data_2)); - memset(sprcpt_data_3, 0, sizeof(sprcpt_data_3)); - memset(sprcpt_data_4, 0, sizeof(sprcpt_data_4)); + raiden2_state *state = (raiden2_state *)machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; - sprcpt_adr = 0; - sprcpt_idx = 0; + memset(sprcpt, 0, sizeof(*sprcpt)); } WRITE16_HANDLER(sprcpt_adr_w) { - combine32(&sprcpt_adr, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(&sprcpt->adr, offset, data, mem_mask); } WRITE16_HANDLER(sprcpt_data_1_w) { - combine32(sprcpt_data_1+sprcpt_adr, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(sprcpt->data_1+sprcpt->adr, offset, data, mem_mask); } WRITE16_HANDLER(sprcpt_data_2_w) { - combine32(sprcpt_data_2+sprcpt_adr, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(sprcpt->data_2+sprcpt->adr, offset, data, mem_mask); } WRITE16_HANDLER(sprcpt_data_3_w) { - combine32(sprcpt_data_3+sprcpt_idx, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(sprcpt->data_3+sprcpt->idx, offset, data, mem_mask); if(offset == 1) { - sprcpt_idx ++; - if(sprcpt_idx == 6) - sprcpt_idx = 0; + sprcpt->idx ++; + if(sprcpt->idx == 6) + sprcpt->idx = 0; } } WRITE16_HANDLER(sprcpt_data_4_w) { - combine32(sprcpt_data_4+sprcpt_idx, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(sprcpt->data_4+sprcpt->idx, offset, data, mem_mask); if(offset == 1) { - sprcpt_idx ++; - if(sprcpt_idx == 4) - sprcpt_idx = 0; + sprcpt->idx ++; + if(sprcpt->idx == 4) + sprcpt->idx = 0; } } WRITE16_HANDLER(sprcpt_val_1_w) { - combine32(sprcpt_val+0, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(sprcpt->val+0, offset, data, mem_mask); } WRITE16_HANDLER(sprcpt_val_2_w) { - combine32(sprcpt_val+1, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(sprcpt->val+1, offset, data, mem_mask); } WRITE16_HANDLER(sprcpt_flags_1_w) { - combine32(&sprcpt_flags1, offset, data, mem_mask); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + combine32(&sprcpt->flags1, offset, data, mem_mask); if(offset == 1) { // bit 31: 1 = allow write on sprcpt data - if(!(sprcpt_flags1 & 0x80000000U)) { + if(!(sprcpt->flags1 & 0x80000000U)) { // Upload finished if(1) { int i; - logerror("sprcpt_val 1: %08x\n", sprcpt_val[0]); - logerror("sprcpt_val 2: %08x\n", sprcpt_val[1]); + logerror("sprcpt_val 1: %08x\n", sprcpt->val[0]); + logerror("sprcpt_val 2: %08x\n", sprcpt->val[1]); logerror("sprcpt_data 1:\n"); for(i=0; i<0x100; i++) { - logerror(" %08x", sprcpt_data_1[i]); + logerror(" %08x", sprcpt->data_1[i]); if(!((i+1) & 7)) logerror("\n"); } logerror("sprcpt_data 2:\n"); for(i=0; i<0x40; i++) { - logerror(" %08x", sprcpt_data_2[i]); + logerror(" %08x", sprcpt->data_2[i]); if(!((i+1) & 7)) logerror("\n"); } @@ -669,9 +742,12 @@ WRITE16_HANDLER(sprcpt_flags_1_w) WRITE16_HANDLER(sprcpt_flags_2_w) { - COMBINE_DATA(&sprcpt_flags2); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + sprcpt_state *sprcpt = &state->sprcpt; + + COMBINE_DATA(&sprcpt->flags2); if(offset == 0) { - if(sprcpt_flags2 & 0x8000) { + if(sprcpt->flags2 & 0x8000) { // Reset decryption -> redo it } } @@ -684,13 +760,17 @@ WRITE16_HANDLER(sprcpt_flags_2_w) static UINT16 handle_io_r(const address_space *space, int offset) { - logerror("io_r %04x, %04x (%x)\n", offset*2, mainram[offset], cpu_get_pc(space->cpu)); - return mainram[offset]; + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + logerror("io_r %04x, %04x (%x)\n", offset*2, state->mainram[offset], cpu_get_pc(space->cpu)); + return state->mainram[offset]; } static void handle_io_w(const address_space *space, int offset, UINT16 data, UINT16 mem_mask) { - COMBINE_DATA(&mainram[offset]); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + COMBINE_DATA(&state->mainram[offset]); switch(offset) { default: logerror("io_w %04x, %04x & %04x (%x)\n", offset*2, data, mem_mask, cpu_get_pc(space->cpu)); @@ -699,23 +779,27 @@ static void handle_io_w(const address_space *space, int offset, UINT16 data, UIN static READ16_HANDLER(any_r) { - c_r[offset]++; + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + state->stat[offset].read++; if(offset >= 0x400/2 && offset < 0x800/2) return handle_io_r(space, offset); - return mainram[offset]; + return state->mainram[offset]; } static WRITE16_HANDLER(any_w) { + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + int show = 0; if(offset >= 0x400/2 && offset < 0x800/2) handle_io_w(space, offset, data, mem_mask); - c_w[offset]++; + state->stat[offset].write++; + // logerror("mainram_w %04x, %02x (%x)\n", offset, data, cpu_get_pc(space->cpu)); - if(mainram[offset] != data && offset >= 0x400 && offset < 0x800) { + if(state->mainram[offset] != data && offset >= 0x400 && offset < 0x800) { if(0 && offset != 0x4c0/2 && offset != 0x500/2 && offset != 0x444/2 && offset != 0x6de/2 && offset != 0x47e/2 && @@ -724,9 +808,9 @@ static WRITE16_HANDLER(any_w) logerror("mainram_w %04x, %04x & %04x (%x)\n", offset*2, data, mem_mask, cpu_get_pc(space->cpu)); } - if(0 && c_w[offset]>1000 && !c_r[offset]) { + if(0 && state->stat[offset].write>1000 && !state->stat[offset].read) { if(offset != 0x4c0/2 && (offset<0x500/2 || offset > 0x503/2)) - logerror("mainram_w %04x, %04x & %04x [%d.%d] (%x)\n", offset*2, data, mem_mask, c_w[offset], c_r[offset], cpu_get_pc(space->cpu)); + logerror("mainram_w %04x, %04x & %04x [%d.%d] (%x)\n", offset*2, data, mem_mask, state->stat[offset].write, state->stat[offset].read, cpu_get_pc(space->cpu)); } // if(offset == 0x471 || (offset >= 0xb146 && offset < 0xb156)) @@ -742,12 +826,14 @@ static WRITE16_HANDLER(any_w) // if(offset == 0x700) // cpu_setbank(2, memory_region(space->machine, "user1")+0x20000*data); - COMBINE_DATA(&mainram[offset]); + COMBINE_DATA(&state->mainram[offset]); } static WRITE16_HANDLER(w1x) { - COMBINE_DATA(&w1ram[offset]); + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + COMBINE_DATA(&state->w1ram[offset]); if(0 && offset < 0x800/2) logerror("w1x %05x, %04x & %04x (%05x)\n", offset*2+0x10000, data, mem_mask, cpu_get_pc(space->cpu)); } @@ -755,7 +841,8 @@ static WRITE16_HANDLER(w1x) #ifdef UNUSED_FUNCTION static void r2_dt(UINT16 sc, UINT16 cc, UINT16 ent, UINT16 tm, UINT16 x, UINT16 y) { - int bank = mainram[0x704/2]; + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + int bank = state->mainram[0x704/2]; #if 0 switch(ent) { @@ -813,20 +900,22 @@ static void r2_6f6c(UINT16 cc, UINT16 v1, UINT16 v2) } #endif -static void common_reset(void) +static void common_reset(running_machine *machine) { - bg_bank=0; - fg_bank=6; - mid_bank=1; - bg_col=0; - fg_col=1; - mid_col=2; + raiden2_state *state = (raiden2_state *)machine->driver_data; + + state->bg_bank=0; + state->fg_bank=6; + state->mid_bank=1; + state->bg_col=0; + state->fg_col=1; + state->mid_col=2; } static MACHINE_RESET(raiden2) { - common_reset(); - sprcpt_init(); + common_reset(machine); + sprcpt_init(machine); MACHINE_RESET_CALL(seibu_sound); //cop_init(); @@ -838,17 +927,17 @@ static MACHINE_RESET(raiden2) static ADDRESS_MAP_START( raiden2_mem, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0x00400, 0x007ff) AM_READWRITE(raiden2_mcu_r, raiden2_mcu_w) AM_BASE(&cop_mcu_ram) - AM_RANGE(0x00000, 0x0bfff) AM_READWRITE(any_r, any_w) AM_BASE(&mainram) + AM_RANGE(0x00000, 0x0bfff) AM_READWRITE(any_r, any_w) AM_BASE_MEMBER(raiden2_state,mainram) // AM_RANGE(0x00000, 0x003ff) AM_RAM - AM_RANGE(0x0c000, 0x0cfff) AM_RAM AM_BASE_SIZE_GENERIC(spriteram) - AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(raiden2_background_w) AM_BASE(&back_data) - AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(raiden2_foreground_w) AM_BASE(&fore_data) - AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(raiden2_midground_w) AM_BASE(&mid_data) - AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(raiden2_text_w) AM_BASE_GENERIC(videoram) + AM_RANGE(0x0c000, 0x0cfff) AM_RAM AM_BASE_MEMBER(raiden2_state,spriteram) + AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(raiden2_background_w) AM_BASE_MEMBER(raiden2_state,back_data) + AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(raiden2_foreground_w) AM_BASE_MEMBER(raiden2_state,fore_data) + AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(raiden2_midground_w) AM_BASE_MEMBER(raiden2_state,mid_data) + AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(raiden2_text_w) AM_BASE_MEMBER(raiden2_state,videoram) AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */ - AM_RANGE(0x10000, 0x1efff) AM_RAM_WRITE(w1x) AM_BASE(&w1ram) + AM_RANGE(0x10000, 0x1efff) AM_RAM_WRITE(w1x) AM_BASE_MEMBER(raiden2_state,w1ram) AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram) AM_RANGE(0x20000, 0x3ffff) AM_ROMBANK("bank1") @@ -858,17 +947,18 @@ ADDRESS_MAP_END /* new zero team uses the copd3 protection... and uploads a 0x400 byte table, probably the mcu code, encrypted */ -static UINT16 mcu_prog[0x400]; -static int mcu_prog_offs = 0; - static WRITE16_HANDLER( mcu_prog_w ) { - mcu_prog[mcu_prog_offs*2] = data; + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + state->mcu_prog[state->mcu_prog_offs*2] = data; } static WRITE16_HANDLER( mcu_prog_w2 ) { - mcu_prog[mcu_prog_offs*2+1] = data; + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + state->mcu_prog[state->mcu_prog_offs*2+1] = data; // both new zero team and raiden2/dx v33 version upload the same table.. #if 1 @@ -880,7 +970,7 @@ static WRITE16_HANDLER( mcu_prog_w2 ) fp=fopen(tmp, "w+b"); if (fp) { - fwrite(mcu_prog, 0x400, 2, fp); + fwrite(state->mcu_prog, 0x400, 2, fp); fclose(fp); } } @@ -889,7 +979,9 @@ static WRITE16_HANDLER( mcu_prog_w2 ) static WRITE16_HANDLER( mcu_prog_offs_w ) { - mcu_prog_offs = data; + raiden2_state *state = (raiden2_state *)space->machine->driver_data; + + state->mcu_prog_offs = data; } @@ -946,17 +1038,17 @@ static ADDRESS_MAP_START( nzerotea_mem, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0x00788, 0x00789) AM_READ(nzerotea_unknown_r) AM_RANGE(0x00794, 0x00795) AM_READ(nzerotea_unknown_r) - AM_RANGE(0x00000, 0x0bfff) AM_READWRITE(any_r, any_w) AM_BASE(&mainram) + AM_RANGE(0x00000, 0x0bfff) AM_READWRITE(any_r, any_w) AM_BASE_MEMBER(raiden2_state,mainram) // AM_RANGE(0x00000, 0x003ff) AM_RAM - AM_RANGE(0x0c000, 0x0cfff) AM_RAM AM_BASE_SIZE_GENERIC(spriteram) - AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(raiden2_background_w) AM_BASE(&back_data) - AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(raiden2_foreground_w) AM_BASE(&fore_data) - AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(raiden2_midground_w) AM_BASE(&mid_data) - AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(raiden2_text_w) AM_BASE_GENERIC(videoram) + AM_RANGE(0x0c000, 0x0cfff) AM_RAM AM_BASE_MEMBER(raiden2_state,spriteram) + AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(raiden2_background_w) AM_BASE_MEMBER(raiden2_state,back_data) + AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(raiden2_foreground_w) AM_BASE_MEMBER(raiden2_state,fore_data) + AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(raiden2_midground_w) AM_BASE_MEMBER(raiden2_state,mid_data) + AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(raiden2_text_w) AM_BASE_MEMBER(raiden2_state,videoram) AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */ - AM_RANGE(0x10000, 0x1efff) AM_RAM_WRITE(w1x) AM_BASE(&w1ram) + AM_RANGE(0x10000, 0x1efff) AM_RAM_WRITE(w1x) AM_BASE_MEMBER(raiden2_state,w1ram) AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram) AM_RANGE(0x20000, 0x3ffff) AM_ROMBANK("bank1") @@ -1186,6 +1278,8 @@ GFXDECODE_END static MACHINE_DRIVER_START( raiden2 ) + MDRV_DRIVER_DATA( raiden2_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", V30,XTAL_32MHz/2) /* verified on pcb */ MDRV_CPU_PROGRAM_MAP(raiden2_mem) @@ -2124,11 +2218,11 @@ static ADDRESS_MAP_START( rdx_v33_map, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0x00800, 0x0087f) AM_RAM // copies eeprom here? AM_RANGE(0x00880, 0x0bfff) AM_RAM - AM_RANGE(0x0c000, 0x0cfff) AM_RAM AM_BASE_SIZE_GENERIC(spriteram) - AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(raiden2_background_w) AM_BASE(&back_data) - AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(raiden2_foreground_w) AM_BASE(&fore_data) - AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(raiden2_midground_w) AM_BASE(&mid_data) - AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(raiden2_text_w) AM_BASE_GENERIC(videoram) + AM_RANGE(0x0c000, 0x0cfff) AM_RAM AM_BASE_MEMBER(raiden2_state,spriteram) + AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(raiden2_background_w) AM_BASE_MEMBER(raiden2_state,back_data) + AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(raiden2_foreground_w) AM_BASE_MEMBER(raiden2_state,fore_data) + AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(raiden2_midground_w) AM_BASE_MEMBER(raiden2_state,mid_data) + AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(raiden2_text_w) AM_BASE_MEMBER(raiden2_state,videoram) AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */ AM_RANGE(0x10000, 0x1efff) AM_RAM AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram) @@ -2236,11 +2330,13 @@ static INTERRUPT_GEN( rdx_v33_interrupt ) static MACHINE_RESET( rdx_v33 ) { - common_reset(); + common_reset(machine); } static MACHINE_DRIVER_START( rdx_v33 ) + MDRV_DRIVER_DATA( raiden2_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", V33, 32000000/2 ) // ? MDRV_CPU_PROGRAM_MAP(rdx_v33_map) diff --git a/src/mame/drivers/safarir.c b/src/mame/drivers/safarir.c index 55267981e48..b9691caa66a 100644 --- a/src/mame/drivers/safarir.c +++ b/src/mame/drivers/safarir.c @@ -50,13 +50,19 @@ modified by Hau #include "cpu/i8085/i8085.h" #include "sound/samples.h" - -static UINT8 *ram_1, *ram_2; -static size_t ram_size; -static UINT8 ram_bank; -static tilemap_t *bg_tilemap, *fg_tilemap; -static UINT8 *bg_scroll; - +typedef struct _safarir_state safarir_state; +struct _safarir_state +{ + UINT8 *ram_1, *ram_2; + size_t ram_size; + UINT8 ram_bank; + tilemap_t *bg_tilemap; + tilemap_t *fg_tilemap; + UINT8 *bg_scroll; + UINT8 port_last; + UINT8 port_last2; + running_device *samples; +}; /************************************* @@ -67,24 +73,30 @@ static UINT8 *bg_scroll; static WRITE8_HANDLER( ram_w ) { - if (ram_bank) - ram_2[offset] = data; - else - ram_1[offset] = data; + safarir_state *state = (safarir_state *)space->machine->driver_data; - tilemap_mark_tile_dirty((offset & 0x0400) ? bg_tilemap : fg_tilemap, offset & 0x03ff); + if (state->ram_bank) + state->ram_2[offset] = data; + else + state->ram_1[offset] = data; + + tilemap_mark_tile_dirty((offset & 0x0400) ? state->bg_tilemap : state->fg_tilemap, offset & 0x03ff); } static READ8_HANDLER( ram_r ) { - return ram_bank ? ram_2[offset] : ram_1[offset]; + safarir_state *state = (safarir_state *)space->machine->driver_data; + + return state->ram_bank ? state->ram_2[offset] : state->ram_1[offset]; } static WRITE8_HANDLER( ram_bank_w ) { - ram_bank = data & 0x01; + safarir_state *state = (safarir_state *)space->machine->driver_data; + + state->ram_bank = data & 0x01; tilemap_mark_all_tiles_dirty_all(space->machine); } @@ -168,19 +180,23 @@ static TILE_GET_INFO( get_fg_tile_info ) static VIDEO_START( safarir ) { - bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32); - fg_tilemap = tilemap_create(machine, get_fg_tile_info, tilemap_scan_rows, 8, 8, 32, 32); + safarir_state *state = (safarir_state *)machine->driver_data; - tilemap_set_transparent_pen(fg_tilemap, 0); + state->bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32); + state->fg_tilemap = tilemap_create(machine, get_fg_tile_info, tilemap_scan_rows, 8, 8, 32, 32); + + tilemap_set_transparent_pen(state->fg_tilemap, 0); } static VIDEO_UPDATE( safarir ) { - tilemap_set_scrollx(bg_tilemap, 0, *bg_scroll); + safarir_state *state = (safarir_state *)screen->machine->driver_data; - tilemap_draw(bitmap, cliprect, bg_tilemap, 0, 0); - tilemap_draw(bitmap, cliprect, fg_tilemap, 0, 0); + tilemap_set_scrollx(state->bg_tilemap, 0, *state->bg_scroll); + + tilemap_draw(bitmap, cliprect, state->bg_tilemap, 0, 0); + tilemap_draw(bitmap, cliprect, state->fg_tilemap, 0, 0); return 0; } @@ -210,14 +226,12 @@ static VIDEO_UPDATE( safarir ) #define CHANNEL_SOUND5 4 #define CHANNEL_SOUND6 5 -static UINT8 port_last; -static UINT8 port_last2; - static WRITE8_HANDLER( safarir_audio_w ) { - running_device *samples = devtag_get_device(space->machine, "samples"); - UINT8 rising_bits = data & ~port_last; + safarir_state *state = (safarir_state *)space->machine->driver_data; + running_device *samples = state->samples; + UINT8 rising_bits = data & ~state->port_last; if (rising_bits == 0x12) sample_start(samples, CHANNEL_SOUND1, SAMPLE_SOUND1_1, 0); if (rising_bits == 0x02) sample_start(samples, CHANNEL_SOUND1, SAMPLE_SOUND1_2, 0); @@ -230,16 +244,16 @@ static WRITE8_HANDLER( safarir_audio_w ) if (data == 0x13) { - if ((rising_bits == 0x13 && port_last != 0x04) || (rising_bits == 0x01 && port_last == 0x12)) + if ((rising_bits == 0x13 && state->port_last != 0x04) || (rising_bits == 0x01 && state->port_last == 0x12)) { sample_start(samples, CHANNEL_SOUND4, SAMPLE_SOUND7, 0); } - else if (rising_bits == 0x03 && port_last2 == 0x15 && !sample_playing(samples, CHANNEL_SOUND4)) + else if (rising_bits == 0x03 && state->port_last2 == 0x15 && !sample_playing(samples, CHANNEL_SOUND4)) { sample_start(samples, CHANNEL_SOUND4, SAMPLE_SOUND4_1, 0); } } - if (data == 0x53 && port_last == 0x55) sample_start(samples, CHANNEL_SOUND4, SAMPLE_SOUND4_2, 0); + if (data == 0x53 && state->port_last == 0x55) sample_start(samples, CHANNEL_SOUND4, SAMPLE_SOUND4_2, 0); if (data == 0x1f && rising_bits == 0x1f) sample_start(samples, CHANNEL_SOUND5, SAMPLE_SOUND5_1, 0); if (data == 0x14 && (rising_bits == 0x14 || rising_bits == 0x04)) sample_start(samples, CHANNEL_SOUND5, SAMPLE_SOUND5_2, 0); @@ -247,8 +261,8 @@ static WRITE8_HANDLER( safarir_audio_w ) if (data == 0x07 && rising_bits == 0x07 && !sample_playing(samples, CHANNEL_SOUND6)) sample_start(samples, CHANNEL_SOUND6, SAMPLE_SOUND8, 0); - port_last2 = port_last; - port_last = data; + state->port_last2 = state->port_last; + state->port_last = data; } @@ -294,17 +308,20 @@ MACHINE_DRIVER_END static MACHINE_START( safarir ) { - ram_1 = auto_alloc_array(machine, UINT8, ram_size); - ram_2 = auto_alloc_array(machine, UINT8, ram_size); - port_last = 0; - port_last2 = 0; + safarir_state *state = (safarir_state *)machine->driver_data; + + state->ram_1 = auto_alloc_array(machine, UINT8, state->ram_size); + state->ram_2 = auto_alloc_array(machine, UINT8, state->ram_size); + state->port_last = 0; + state->port_last2 = 0; + state->samples = devtag_get_device(machine, "samples"); /* setup for save states */ - state_save_register_global_pointer(machine, ram_1, ram_size); - state_save_register_global_pointer(machine, ram_2, ram_size); - state_save_register_global(machine, ram_bank); - state_save_register_global(machine, port_last); - state_save_register_global(machine, port_last2); + state_save_register_global_pointer(machine, state->ram_1, state->ram_size); + state_save_register_global_pointer(machine, state->ram_2, state->ram_size); + state_save_register_global(machine, state->ram_bank); + state_save_register_global(machine, state->port_last); + state_save_register_global(machine, state->port_last2); } @@ -317,9 +334,9 @@ static MACHINE_START( safarir ) static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0x17ff) AM_ROM - AM_RANGE(0x2000, 0x27ff) AM_READWRITE(ram_r, ram_w) AM_SIZE(&ram_size) + AM_RANGE(0x2000, 0x27ff) AM_READWRITE(ram_r, ram_w) AM_SIZE_MEMBER(safarir_state,ram_size) AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_READNOP AM_WRITE(ram_bank_w) - AM_RANGE(0x2c00, 0x2cff) AM_MIRROR(0x03ff) AM_READNOP AM_WRITEONLY AM_BASE(&bg_scroll) + AM_RANGE(0x2c00, 0x2cff) AM_MIRROR(0x03ff) AM_READNOP AM_WRITEONLY AM_BASE_MEMBER(safarir_state,bg_scroll) AM_RANGE(0x3000, 0x30ff) AM_MIRROR(0x03ff) AM_WRITE(safarir_audio_w) /* goes to SN76477 */ AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_WRITENOP /* cleared at the beginning */ AM_RANGE(0x3800, 0x38ff) AM_MIRROR(0x03ff) AM_READ_PORT("INPUTS") AM_WRITENOP @@ -377,6 +394,8 @@ INPUT_PORTS_END static MACHINE_DRIVER_START( safarir ) + MDRV_DRIVER_DATA( safarir_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", 8085A, 18000000/8) /* 2.25 MHz ? */ MDRV_CPU_PROGRAM_MAP(main_map) diff --git a/src/mame/drivers/sbowling.c b/src/mame/drivers/sbowling.c index ac3e0b3128a..82a903183e6 100644 --- a/src/mame/drivers/sbowling.c +++ b/src/mame/drivers/sbowling.c @@ -45,18 +45,25 @@ PROMs : NEC B406 (1kx4) x2 #include "sound/ay8910.h" -static int bgmap = 0; +typedef struct _sbowling_state sbowling_state; +struct _sbowling_state +{ + int bgmap; + UINT8 *videoram; -static int sbw_system = 0; -static tilemap_t *sb_tilemap; -static UINT32 color_prom_address = 0; -static UINT8 pix_sh = 0; -static UINT8 pix[2] = {0, 0}; + int sbw_system; + tilemap_t *sb_tilemap; + bitmap_t *tmpbitmap; + UINT32 color_prom_address; + UINT8 pix_sh; + UINT8 pix[2]; +}; static TILE_GET_INFO( get_sb_tile_info ) { + sbowling_state *state = (sbowling_state *)machine->driver_data; UINT8 *rom = memory_region(machine, "user1"); - int tileno = rom[tile_index + bgmap * 1024]; + int tileno = rom[tile_index + state->bgmap * 1024]; SET_TILE_INFO(0, tileno, 0, 0); } @@ -73,22 +80,23 @@ static void plot_pixel_sbw(bitmap_t *tmpbitmap, int x, int y, int col, int flip) static WRITE8_HANDLER( sbw_videoram_w ) { + sbowling_state *state = (sbowling_state *)space->machine->driver_data; int flip = flip_screen_get(space->machine); int x,y,i,v1,v2; - space->machine->generic.videoram.u8[offset] = data; + state->videoram[offset] = data; offset &= 0x1fff; y = offset / 32; x = (offset % 32) * 8; - v1 = space->machine->generic.videoram.u8[offset]; - v2 = space->machine->generic.videoram.u8[offset+0x2000]; + v1 = state->videoram[offset]; + v2 = state->videoram[offset+0x2000]; - for(i = 0; i < 8; i++) + for (i = 0; i < 8; i++) { - plot_pixel_sbw(space->machine->generic.tmpbitmap, x++, y, color_prom_address | ( ((v1&1)*0x20) | ((v2&1)*0x40) ), flip); + plot_pixel_sbw(state->tmpbitmap, x++, y, state->color_prom_address | ( ((v1&1)*0x20) | ((v2&1)*0x40) ), flip); v1 >>= 1; v2 >>= 1; } @@ -96,35 +104,44 @@ static WRITE8_HANDLER( sbw_videoram_w ) static VIDEO_UPDATE(sbowling) { - bitmap_fill(bitmap,cliprect,0x18); - tilemap_draw(bitmap,cliprect,sb_tilemap,0,0); - copybitmap_trans(bitmap,screen->machine->generic.tmpbitmap,0,0,0,0,cliprect, color_prom_address); + sbowling_state *state = (sbowling_state *)screen->machine->driver_data; + + bitmap_fill(bitmap, cliprect, 0x18); + tilemap_draw(bitmap, cliprect,state->sb_tilemap, 0, 0); + copybitmap_trans(bitmap, state->tmpbitmap, 0, 0, 0, 0, cliprect, state->color_prom_address); return 0; } static VIDEO_START(sbowling) { - machine->generic.tmpbitmap = auto_bitmap_alloc(machine,32*8,32*8,video_screen_get_format(machine->primary_screen)); - sb_tilemap = tilemap_create(machine, get_sb_tile_info, tilemap_scan_rows, 8, 8, 32, 32); + sbowling_state *state = (sbowling_state *)machine->driver_data; + + state->tmpbitmap = auto_bitmap_alloc(machine,32*8,32*8,video_screen_get_format(machine->primary_screen)); + state->sb_tilemap = tilemap_create(machine, get_sb_tile_info, tilemap_scan_rows, 8, 8, 32, 32); } static WRITE8_HANDLER( pix_shift_w ) { - pix_sh = data; + sbowling_state *state = (sbowling_state *)space->machine->driver_data; + + state->pix_sh = data; } static WRITE8_HANDLER( pix_data_w ) { - pix[0] = pix[1]; - pix[1] = data; + sbowling_state *state = (sbowling_state *)space->machine->driver_data; + + state->pix[0] = state->pix[1]; + state->pix[1] = data; } static READ8_HANDLER( pix_data_r ) { + sbowling_state *state = (sbowling_state *)space->machine->driver_data; UINT32 p1, p0; int res; - int sh = pix_sh & 7; + int sh = state->pix_sh & 7; - p1 = pix[1]; - p0 = pix[0]; + p1 = state->pix[1]; + p0 = state->pix[0]; res = (((p1 << (sh+8)) | (p0 << sh)) & 0xff00) >> 8; @@ -149,15 +166,17 @@ static WRITE8_HANDLER (system_w) -----x-- 1 ? ----x--- flip screen/controls */ + sbowling_state *state = (sbowling_state *)space->machine->driver_data; + flip_screen_set(space->machine, data&1); - if((sbw_system^data)&1) + if ((state->sbw_system^data)&1) { int offs; - for (offs = 0;offs < space->machine->generic.videoram_size; offs++) + for (offs = 0;offs < 0x4000; offs++) sbw_videoram_w(space, offs, space->machine->generic.videoram.u8[offs]); } - sbw_system = data; + state->sbw_system = data; } static WRITE8_HANDLER(graph_control_w) @@ -170,15 +189,19 @@ static WRITE8_HANDLER(graph_control_w) xx------ color PROM address lines A4,A3 */ - color_prom_address = ((data&0x07)<<7) | ((data&0xc0)>>3); + sbowling_state *state = (sbowling_state *)space->machine->driver_data; - bgmap = ((data>>4)^3) & 0x3; - tilemap_mark_all_tiles_dirty(sb_tilemap); + state->color_prom_address = ((data&0x07)<<7) | ((data&0xc0)>>3); + + state->bgmap = ((data>>4)^3) & 0x3; + tilemap_mark_all_tiles_dirty(state->sb_tilemap); } static READ8_HANDLER (controls_r) { - if(sbw_system & 2) + sbowling_state *state = (sbowling_state *)space->machine->driver_data; + + if (state->sbw_system & 2) return input_port_read(space->machine, "TRACKY"); else return input_port_read(space->machine, "TRACKX"); @@ -186,7 +209,7 @@ static READ8_HANDLER (controls_r) static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0x2fff) AM_ROM - AM_RANGE(0x8000, 0xbfff) AM_RAM_WRITE(sbw_videoram_w) AM_BASE_GENERIC(videoram) AM_SIZE_GENERIC(videoram) + AM_RANGE(0x8000, 0xbfff) AM_RAM_WRITE(sbw_videoram_w) AM_BASE_MEMBER(sbowling_state,videoram) AM_RANGE(0xf800, 0xf801) AM_DEVWRITE("aysnd", ay8910_address_data_w) AM_RANGE(0xf801, 0xf801) AM_DEVREAD("aysnd", ay8910_r) AM_RANGE(0xfc00, 0xffff) AM_RAM @@ -344,6 +367,8 @@ static PALETTE_INIT( sbowling ) static MACHINE_DRIVER_START( sbowling ) + MDRV_DRIVER_DATA( sbowling_state ) + MDRV_CPU_ADD("maincpu", 8080, XTAL_19_968MHz/10) /* ? */ MDRV_CPU_PROGRAM_MAP(main_map) MDRV_CPU_IO_MAP(port_map) @@ -389,4 +414,3 @@ ROM_START( sbowling ) ROM_END GAME( 1982, sbowling, 0, sbowling, sbowling, 0, ROT90, "Taito Corporation", "Strike Bowling",GAME_IMPERFECT_SOUND) - diff --git a/src/mame/drivers/shougi.c b/src/mame/drivers/shougi.c index fd63b1fe4ed..c2bb2ad8dc5 100644 --- a/src/mame/drivers/shougi.c +++ b/src/mame/drivers/shougi.c @@ -87,6 +87,17 @@ PROM : Type MB7051 #include "sound/ay8910.h" #include "video/resnet.h" +typedef struct _shougi_state shougi_state; +struct _shougi_state +{ + UINT8 *videoram; + int nmi_enabled; + //UINT8 *cpu_sharedram; + //UINT8 cpu_sharedram_control_val; + int r; +}; + + /*************************************************************************** @@ -148,6 +159,7 @@ static PALETTE_INIT( shougi ) static VIDEO_UPDATE( shougi ) { + shougi_state *state = (shougi_state *)screen->machine->driver_data; int offs; for (offs = 0;offs <0x4000; offs++) @@ -156,11 +168,11 @@ static VIDEO_UPDATE( shougi ) sx = offs >> 8; /*00..0x3f (64*4=256)*/ sy = offs & 0xff; /*00..0xff*/ -// if (flipscreen[0]) sx = 31 - sx; -// if (flipscreen[1]) sy = 31 - sy; + //if (flipscreen[0]) sx = 31 - sx; + //if (flipscreen[1]) sy = 31 - sy; - data1 = screen->machine->generic.videoram.u8[offs]; /* color */ - data2 = screen->machine->generic.videoram.u8[0x4000 + offs]; /* pixel data */ + data1 = state->videoram[offs]; /* color */ + data2 = state->videoram[0x4000 + offs]; /* pixel data */ for (x=0; x<4; x++) /*4 pixels per byte (2 bitplanes in 2 nibbles: 1st=bits 7-4, 2nd=bits 3-0)*/ { @@ -176,9 +188,6 @@ static VIDEO_UPDATE( shougi ) #if 0 -static UINT8 *cpu_sharedram; -static UINT8 cpu_sharedram_control_val = 0; - //to do: // add separate sharedram/r/w() for both CPUs and use control value to verify access @@ -203,14 +212,14 @@ static READ8_HANDLER ( cpu_sharedram_r ) static WRITE8_HANDLER ( cpu_shared_ctrl_sub_w ) { -// cpu_sharedram_control_val = 0; -//logerror("cpu_sharedram_ctrl=SUB"); + //cpu_sharedram_control_val = 0; + //logerror("cpu_sharedram_ctrl=SUB"); } static WRITE8_HANDLER ( cpu_shared_ctrl_main_w ) { -// cpu_sharedram_control_val = 1; -//logerror("cpu_sharedram_ctrl=MAIN"); + //cpu_sharedram_control_val = 1; + //logerror("cpu_sharedram_ctrl=MAIN"); } static WRITE8_HANDLER( shougi_watchdog_reset_w ) @@ -231,11 +240,11 @@ static WRITE8_HANDLER( shougi_mcu_halt_on_w ) } -static int nmi_enabled = 0; - static WRITE8_HANDLER( nmi_disable_and_clear_line_w ) { - nmi_enabled = 0; /* disable NMIs */ + shougi_state *state = (shougi_state *)space->machine->driver_data; + + state->nmi_enabled = 0; /* disable NMIs */ /* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */ cputag_set_input_line(space->machine, "maincpu", INPUT_LINE_NMI, CLEAR_LINE); @@ -244,12 +253,16 @@ static WRITE8_HANDLER( nmi_disable_and_clear_line_w ) static WRITE8_HANDLER( nmi_enable_w ) { - nmi_enabled = 1; /* enable NMIs */ + shougi_state *state = (shougi_state *)space->machine->driver_data; + + state->nmi_enabled = 1; /* enable NMIs */ } static INTERRUPT_GEN( shougi_vblank_nmi ) { - if ( nmi_enabled == 1 ) + shougi_state *state = (shougi_state *)device->machine->driver_data; + + if ( state->nmi_enabled == 1 ) { /* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */ cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, ASSERT_LINE); @@ -283,15 +296,16 @@ static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x7000, 0x73ff) AM_RAM AM_SHARE("share1") /* 2114 x 2 (0x400 x 4bit each) */ AM_RANGE(0x7800, 0x7bff) AM_RAM AM_SHARE("share2") /* 2114 x 2 (0x400 x 4bit each) */ - AM_RANGE(0x8000, 0xffff) AM_RAM AM_BASE_GENERIC(videoram) AM_SIZE_GENERIC(videoram) /* 4116 x 16 (32K) */ + AM_RANGE(0x8000, 0xffff) AM_RAM AM_BASE_MEMBER(shougi_state,videoram) /* 4116 x 16 (32K) */ ADDRESS_MAP_END /* sub */ -static int r=0; static READ8_HANDLER ( dummy_r ) { - r ^= 1; - if(r) + shougi_state *state = (shougi_state *)space->machine->driver_data; + state->r ^= 1; + + if(state->r) return 0xff; else return 0; @@ -375,6 +389,8 @@ INPUT_PORTS_END static MACHINE_DRIVER_START( shougi ) + MDRV_DRIVER_DATA( shougi_state ) + MDRV_CPU_ADD("maincpu", Z80,10000000/4) MDRV_CPU_PROGRAM_MAP(main_map) MDRV_CPU_VBLANK_INT("screen", shougi_vblank_nmi) diff --git a/src/mame/drivers/skeetsht.c b/src/mame/drivers/skeetsht.c index 78967970350..f75681854c1 100644 --- a/src/mame/drivers/skeetsht.c +++ b/src/mame/drivers/skeetsht.c @@ -13,13 +13,21 @@ /************************************* * - * Statics + * Structs * *************************************/ -static UINT16 *tms_vram; -static UINT8 porta_latch; -static UINT8 ay_sel; +typedef struct _skeetsht_state skeetsht_state; +struct _skeetsht_state +{ + UINT16 *tms_vram; + UINT8 porta_latch; + UINT8 ay_sel; + UINT8 lastdataw; + UINT16 lastdatar; + running_device *ay; + running_device *tms; +}; /************************************* @@ -30,6 +38,11 @@ static UINT8 ay_sel; static MACHINE_RESET( skeetsht ) { + skeetsht_state *state = (skeetsht_state *)machine->driver_data; + + state->ay = devtag_get_device(machine, "aysnd"); + state->tms = devtag_get_device(machine, "tms"); + /* Setup the Bt476 VGA RAMDAC palette chip */ tlc34076_reset(6); } @@ -43,13 +56,13 @@ static MACHINE_RESET( skeetsht ) static VIDEO_START ( skeetsht ) { - } static void skeetsht_scanline_update(running_device *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params) { + skeetsht_state *state = (skeetsht_state *)screen->machine->driver_data; const rgb_t *const pens = tlc34076_get_pens(); - UINT16 *vram = &tms_vram[(params->rowaddr << 8) & 0x3ff00]; + UINT16 *vram = &state->tms_vram[(params->rowaddr << 8) & 0x3ff00]; UINT32 *dest = BITMAP_ADDR32(bitmap, scanline, 0); int coladdr = params->coladdr; int x; @@ -97,22 +110,22 @@ static void skeetsht_tms_irq(running_device *device, int state) static WRITE8_HANDLER( tms_w ) { - static UINT8 lastdata; + skeetsht_state *state = (skeetsht_state *)space->machine->driver_data; if ((offset & 1) == 0) - lastdata = data; + state->lastdataw = data; else - tms34010_host_w(devtag_get_device(space->machine, "tms"), offset >> 1, (lastdata << 8) | data); + tms34010_host_w(state->tms, offset >> 1, (state->lastdataw << 8) | data); } static READ8_HANDLER( tms_r ) { - static UINT16 data; + skeetsht_state *state = (skeetsht_state *)space->machine->driver_data; if ((offset & 1) == 0) - data = tms34010_host_r(devtag_get_device(space->machine, "tms"), offset >> 1); + state->lastdatar = tms34010_host_r(state->tms, offset >> 1); - return data >> ((offset & 1) ? 0 : 8); + return state->lastdatar >> ((offset & 1) ? 0 : 8); } @@ -124,25 +137,29 @@ static READ8_HANDLER( tms_r ) static READ8_HANDLER( hc11_porta_r ) { - return porta_latch; + skeetsht_state *state = (skeetsht_state *)space->machine->driver_data; + + return state->porta_latch; } static WRITE8_HANDLER( hc11_porta_w ) { - if (!(data & 0x8) && (porta_latch & 8)) - ay_sel = porta_latch & 0x10; + skeetsht_state *state = (skeetsht_state *)space->machine->driver_data; - porta_latch = data; + if (!(data & 0x8) && (state->porta_latch & 8)) + state->ay_sel = state->porta_latch & 0x10; + + state->porta_latch = data; } static WRITE8_HANDLER( ay8910_w ) { - running_device *ay = devtag_get_device(space->machine, "aysnd"); + skeetsht_state *state = (skeetsht_state *)space->machine->driver_data; - if (ay_sel) - ay8910_data_w(ay, 0, data); + if (state->ay_sel) + ay8910_data_w(state->ay, 0, data); else - ay8910_address_w(ay, 0, data); + ay8910_address_w(state->ay, 0, data); } @@ -172,7 +189,7 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( tms_program_map, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE(tms34010_io_register_r, tms34010_io_register_w) - AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(&tms_vram) + AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE_MEMBER(skeetsht_state,tms_vram) AM_RANGE(0x00440000, 0x004fffff) AM_READWRITE(ramdac_r, ramdac_w) AM_RANGE(0xff800000, 0xffbfffff) AM_ROM AM_MIRROR(0x00400000) AM_REGION("tms", 0) ADDRESS_MAP_END @@ -228,6 +245,9 @@ static const tms34010_config tms_config = *************************************/ static MACHINE_DRIVER_START( skeetsht ) + + MDRV_DRIVER_DATA( skeetsht_state ) + MDRV_CPU_ADD("68hc11", MC68HC11, 4000000) // ? MDRV_CPU_PROGRAM_MAP(hc11_pgm_map) MDRV_CPU_IO_MAP(hc11_io_map) diff --git a/src/mame/drivers/skyarmy.c b/src/mame/drivers/skyarmy.c index 2a26dde3b6d..fbf7947f6c8 100644 --- a/src/mame/drivers/skyarmy.c +++ b/src/mame/drivers/skyarmy.c @@ -24,29 +24,40 @@ #include "cpu/z80/z80.h" #include "sound/ay8910.h" -static UINT8 *skyarmy_videoram; -static UINT8 *skyarmy_colorram; -static UINT8 *skyarmy_scrollram; -static tilemap_t* skyarmy_tilemap; +typedef struct _skyarmy_state skyarmy_state; +struct _skyarmy_state +{ + UINT8 *spriteram; + UINT8 *videoram; + UINT8 *colorram; + UINT8 *scrollram; + tilemap_t* tilemap; + int nmi; +}; static TILE_GET_INFO( get_skyarmy_tile_info ) { - int code = skyarmy_videoram[tile_index]; - int attr = BITSWAP8(skyarmy_colorram[tile_index], 7, 6, 5, 4, 3, 0, 1, 2) & 7; + skyarmy_state *state = (skyarmy_state *)machine->driver_data; + int code = state->videoram[tile_index]; + int attr = BITSWAP8(state->colorram[tile_index], 7, 6, 5, 4, 3, 0, 1, 2) & 7; SET_TILE_INFO( 0, code, attr, 0); } static WRITE8_HANDLER( skyarmy_videoram_w ) { - skyarmy_videoram[offset] = data; - tilemap_mark_tile_dirty(skyarmy_tilemap,offset); + skyarmy_state *state = (skyarmy_state *)space->machine->driver_data; + + state->videoram[offset] = data; + tilemap_mark_tile_dirty(state->tilemap,offset); } static WRITE8_HANDLER( skyarmy_colorram_w ) { - skyarmy_colorram[offset] = data; - tilemap_mark_tile_dirty(skyarmy_tilemap,offset); + skyarmy_state *state = (skyarmy_state *)space->machine->driver_data; + + state->colorram[offset] = data; + tilemap_mark_tile_dirty(state->tilemap,offset); } static PALETTE_INIT( skyarmy ) @@ -79,21 +90,24 @@ static PALETTE_INIT( skyarmy ) static VIDEO_START( skyarmy ) { - skyarmy_tilemap = tilemap_create(machine, get_skyarmy_tile_info,tilemap_scan_rows,8,8,32,32); - tilemap_set_scroll_cols(skyarmy_tilemap,32); + skyarmy_state *state = (skyarmy_state *)machine->driver_data; + + state->tilemap = tilemap_create(machine, get_skyarmy_tile_info, tilemap_scan_rows, 8, 8, 32, 32); + tilemap_set_scroll_cols(state->tilemap,32); } static VIDEO_UPDATE( skyarmy ) { - UINT8 *spriteram = screen->machine->generic.spriteram.u8; + skyarmy_state *state = (skyarmy_state *)screen->machine->driver_data; + UINT8 *spriteram = state->spriteram; int sx, sy, flipx, flipy, offs,pal; int i; for(i=0;i<0x20;i++) - tilemap_set_scrolly( skyarmy_tilemap,i,skyarmy_scrollram[i]); + tilemap_set_scrolly( state->tilemap,i,state->scrollram[i]); - tilemap_draw(bitmap,cliprect,skyarmy_tilemap,0,0); + tilemap_draw(bitmap,cliprect,state->tilemap,0,0); for (offs = 0 ; offs < 0x40; offs+=4) { @@ -114,27 +128,29 @@ static VIDEO_UPDATE( skyarmy ) return 0; } -static int skyarmy_nmi=0; - static INTERRUPT_GEN( skyarmy_nmi_source ) { - if(skyarmy_nmi) cpu_set_input_line(device,INPUT_LINE_NMI, PULSE_LINE); + skyarmy_state *state = (skyarmy_state *)device->machine->driver_data; + + if(state->nmi) cpu_set_input_line(device,INPUT_LINE_NMI, PULSE_LINE); } static WRITE8_HANDLER( nmi_enable_w ) { - skyarmy_nmi=data&1; + skyarmy_state *state = (skyarmy_state *)space->machine->driver_data; + + state->nmi=data&1; } static ADDRESS_MAP_START( skyarmy_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0x7fff) AM_ROM AM_RANGE(0x8000, 0x87ff) AM_RAM - AM_RANGE(0x8800, 0x8fff) AM_RAM_WRITE(skyarmy_videoram_w) AM_BASE(&skyarmy_videoram) /* Video RAM */ - AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(skyarmy_colorram_w) AM_BASE(&skyarmy_colorram) /* Color RAM */ - AM_RANGE(0x9800, 0x983f) AM_RAM AM_BASE_SIZE_GENERIC(spriteram) /* Sprites */ - AM_RANGE(0x9840, 0x985f) AM_RAM AM_BASE(&skyarmy_scrollram) /* Scroll RAM */ + AM_RANGE(0x8800, 0x8fff) AM_RAM_WRITE(skyarmy_videoram_w) AM_BASE_MEMBER(skyarmy_state,videoram) /* Video RAM */ + AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(skyarmy_colorram_w) AM_BASE_MEMBER(skyarmy_state,colorram) /* Color RAM */ + AM_RANGE(0x9800, 0x983f) AM_RAM AM_BASE_MEMBER(skyarmy_state,spriteram) /* Sprites */ + AM_RANGE(0x9840, 0x985f) AM_RAM AM_BASE_MEMBER(skyarmy_state,scrollram) /* Scroll RAM */ AM_RANGE(0xa000, 0xa000) AM_READ_PORT("DSW") AM_RANGE(0xa001, 0xa001) AM_READ_PORT("P1") AM_RANGE(0xa002, 0xa002) AM_READ_PORT("P2") @@ -222,6 +238,9 @@ static GFXDECODE_START( skyarmy ) GFXDECODE_END static MACHINE_DRIVER_START( skyarmy ) + + MDRV_DRIVER_DATA( skyarmy_state ) + MDRV_CPU_ADD("maincpu", Z80,4000000) MDRV_CPU_PROGRAM_MAP(skyarmy_map) MDRV_CPU_IO_MAP(skyarmy_io_map) diff --git a/src/mame/drivers/sliver.c b/src/mame/drivers/sliver.c index 9ea3a5ea8c0..19154697abb 100644 --- a/src/mame/drivers/sliver.c +++ b/src/mame/drivers/sliver.c @@ -76,25 +76,30 @@ Notes: #define x_offset 0x45 #define y_offset 0x0d -static UINT16 io_offset; -static UINT16 io_reg[IO_SIZE]; -static UINT16 fifo[FIFO_SIZE]; -static UINT16 fptr; +typedef struct _sliver_state sliver_state; +struct _sliver_state +{ + UINT16 io_offset; + UINT16 io_reg[IO_SIZE]; + UINT16 fifo[FIFO_SIZE]; + UINT16 fptr; -static int jpeg_addr; -static UINT16 jpeg1,jpeg2; -static int jpeg_h=0; -static int jpeg_w=0; -static int jpeg_x=0; -static int jpeg_y=0; -static int tmp_counter; -static int clr_offset=0; + int jpeg_addr; + UINT16 jpeg1; + UINT16 jpeg2; + int jpeg_h; + int jpeg_w; + int jpeg_x; + int jpeg_y; + int tmp_counter; + int clr_offset; -static UINT8 *colorram; -static bitmap_t *sliver_bitmap_fg; -static bitmap_t *sliver_bitmap_bg; + UINT8 *colorram; + bitmap_t *bitmap_fg; + bitmap_t *bitmap_bg; -static UINT16 tempbuf[8]; + UINT16 tempbuf[8]; +}; static const int gfxlookup[][4]= { @@ -179,24 +184,29 @@ static const int gfxlookup[][4]= static WRITE16_HANDLER( sliver_RAMDAC_offset_w ) { - clr_offset=data*3; + sliver_state *state = (sliver_state *)space->machine->driver_data; + + state->clr_offset=data*3; } static WRITE16_HANDLER( sliver_RAMDAC_color_w ) { - colorram[clr_offset]=data; - clr_offset=(clr_offset+1)%768; + sliver_state *state = (sliver_state *)space->machine->driver_data; + + state->colorram[state->clr_offset]=data; + state->clr_offset=(state->clr_offset+1)%768; } -static void plot_pixel_rgb(int x, int y, UINT32 r, UINT32 g, UINT32 b) +static void plot_pixel_rgb(sliver_state *state, int x, int y, UINT32 r, UINT32 g, UINT32 b) { UINT16 color; - if(y<0 ||x<0 || x>383 || y> 255) return; + if (y < 0 || x < 0 || x > 383 || y > 255) + return; - if (sliver_bitmap_bg->bpp == 32) + if (state->bitmap_bg->bpp == 32) { - *BITMAP_ADDR32(sliver_bitmap_bg, y, x) = r | (g<<8) | (b<<16); + *BITMAP_ADDR32(state->bitmap_bg, y, x) = r | (g<<8) | (b<<16); } else { @@ -204,25 +214,29 @@ static void plot_pixel_rgb(int x, int y, UINT32 r, UINT32 g, UINT32 b) g>>=3; b>>=3; color = r|(g<<5)|(b<<10); - *BITMAP_ADDR16(sliver_bitmap_bg, y, x) = color; + *BITMAP_ADDR16(state->bitmap_bg, y, x) = color; } } static void plot_pixel_pal(running_machine *machine, int x, int y, int addr) { + sliver_state *state = (sliver_state *)machine->driver_data; UINT32 r,g,b; UINT16 color; - if(y<0 ||x<0 || x>383 || y> 255) return; + + if (y < 0 || x < 0 || x > 383 || y > 255) + return; + addr*=3; - b=colorram[addr]<<2; - g=colorram[addr+1]<<2; - r=colorram[addr+2]<<2; + b=state->colorram[addr] << 2; + g=state->colorram[addr+1] << 2; + r=state->colorram[addr+2] << 2; - if (sliver_bitmap_fg->bpp == 32) + if (state->bitmap_fg->bpp == 32) { - *BITMAP_ADDR32(sliver_bitmap_fg, y, x) = r | (g<<8) | (b<<16); + *BITMAP_ADDR32(state->bitmap_fg, y, x) = r | (g<<8) | (b<<16); } else { @@ -230,55 +244,58 @@ static void plot_pixel_pal(running_machine *machine, int x, int y, int addr) g>>=3; b>>=3; color = r|(g<<5)|(b<<10); - *BITMAP_ADDR16(sliver_bitmap_fg, y, x) = color; + *BITMAP_ADDR16(state->bitmap_fg, y, x) = color; } } static WRITE16_HANDLER( fifo_data_w ) { - if(tmp_counter<8) + sliver_state *state = (sliver_state *)space->machine->driver_data; + + if (state->tmp_counter < 8) { - COMBINE_DATA(&tempbuf[tmp_counter]); - tmp_counter++; - if(tmp_counter==8) // copy 8 bytes to fifo, every byte should be copied directly, but it's easier to copy whole commands + COMBINE_DATA(&state->tempbuf[state->tmp_counter]); + state->tmp_counter++; + if (state->tmp_counter == 8) // copy 8 bytes to fifo, every byte should be copied directly, but it's easier to copy whole commands { do { - fifo[fptr++]=tempbuf[8-tmp_counter]; - if(fptr>(FIFO_SIZE-1)) + state->fifo[state->fptr++]=state->tempbuf[8-state->tmp_counter]; + if (state->fptr > (FIFO_SIZE - 1)) { - fptr=FIFO_SIZE-1; + state->fptr=FIFO_SIZE-1; } } - while(--tmp_counter>0); + while (--state->tmp_counter > 0); } } } static void blit_gfx(running_machine *machine) { + sliver_state *state = (sliver_state *)machine->driver_data; int tmpptr=0; const UINT8 *rom = memory_region(machine, "user1"); - while(tmpptrfptr) { int x,y,romdata; int w,h; - int romoffs=fifo[tmpptr+0]+(fifo[tmpptr+1]<<8)+(fifo[tmpptr+2]<<16); + int romoffs=state->fifo[tmpptr+0]+(state->fifo[tmpptr+1] << 8)+(state->fifo[tmpptr+2] << 16); - w=fifo[tmpptr+3]+1; - h=fifo[tmpptr+4]+1; + w=state->fifo[tmpptr+3]+1; + h=state->fifo[tmpptr+4]+1; - if( fifo[tmpptr+7]==0) + if (state->fifo[tmpptr+7] == 0) { - for (y=0;yfifo[tmpptr+5]+state->fifo[tmpptr+3]-x, state->fifo[tmpptr+6]+state->fifo[tmpptr+4]-y, romdata); } romoffs++; } @@ -290,39 +307,45 @@ static void blit_gfx(running_machine *machine) static WRITE16_HANDLER( fifo_clear_w ) { - bitmap_fill(sliver_bitmap_fg, 0,0); - fptr=0; - tmp_counter=0; + sliver_state *state = (sliver_state *)space->machine->driver_data; + + bitmap_fill(state->bitmap_fg, 0,0); + state->fptr=0; + state->tmp_counter=0; } static WRITE16_HANDLER( fifo_flush_w ) { - blit_gfx(space->machine); + blit_gfx(space->machine); } static WRITE16_HANDLER( jpeg1_w ) { - COMBINE_DATA(&jpeg1); + sliver_state *state = (sliver_state *)space->machine->driver_data; + + COMBINE_DATA(&state->jpeg1); } static void render_jpeg(running_machine *machine) { + sliver_state *state = (sliver_state *)machine->driver_data; int x, y; - int addr = jpeg_addr; + int addr = state->jpeg_addr; UINT8 *rom; - bitmap_fill(sliver_bitmap_bg, 0, 0); - if(jpeg_addr < 0) + bitmap_fill(state->bitmap_bg, 0, 0); + if (addr < 0) { return; } + rom = memory_region(machine, "user3"); - for (y = 0; y < jpeg_h; y++) + for (y = 0; y < state->jpeg_h; y++) { - for (x = 0; x < jpeg_w; x++) + for (x = 0; x < state->jpeg_w; x++) { - plot_pixel_rgb(x - x_offset + jpeg_x, jpeg_h - y - y_offset - jpeg_y, rom[addr], rom[addr + 1], rom[addr + 2]); + plot_pixel_rgb(state, x - x_offset + state->jpeg_x, state->jpeg_h - y - y_offset - state->jpeg_y, rom[addr], rom[addr + 1], rom[addr + 2]); addr+=3; } } @@ -331,9 +354,9 @@ static void render_jpeg(running_machine *machine) static int find_data(int offset) { int idx = 0; - while(gfxlookup[idx][0] >= 0) + while (gfxlookup[idx][0] >= 0) { - if(offset == gfxlookup[idx][1]) + if (offset == gfxlookup[idx][1]) { return idx; } @@ -344,56 +367,61 @@ static int find_data(int offset) static WRITE16_HANDLER( jpeg2_w ) { - COMBINE_DATA(&jpeg2); + sliver_state *state = (sliver_state *)space->machine->driver_data; + int idx; - { - int idx = find_data((int)jpeg2 + (((int)jpeg1) << 16)); - if(idx >= 0) - { - jpeg_addr = gfxlookup[idx][0]; - jpeg_w = gfxlookup[idx][2]; - jpeg_h = gfxlookup[idx][3]; - render_jpeg(space->machine); - } - else - { - jpeg_addr = -1; - } - } + COMBINE_DATA(&state->jpeg2); + + idx = find_data((int)state->jpeg2 + (((int)state->jpeg1) << 16)); + if (idx >= 0) + { + state->jpeg_addr = gfxlookup[idx][0]; + state->jpeg_w = gfxlookup[idx][2]; + state->jpeg_h = gfxlookup[idx][3]; + render_jpeg(space->machine); + } + else + { + state->jpeg_addr = -1; + } } static WRITE16_HANDLER(io_offset_w) { - COMBINE_DATA(&io_offset); + sliver_state *state = (sliver_state *)space->machine->driver_data; + + COMBINE_DATA(&state->io_offset); } static WRITE16_HANDLER(io_data_w) { - if(io_offsetmachine->driver_data; + + if (state->io_offset < IO_SIZE) { int tmpx, tmpy; - COMBINE_DATA(&io_reg[io_offset]); + COMBINE_DATA(&state->io_reg[state->io_offset]); - tmpy = io_reg[0x1a] + (io_reg[0x1b] << 8) - io_reg[0x20]; //0x20 ??? - tmpx = io_reg[0x1e] + (io_reg[0x1f] << 8); + tmpy = state->io_reg[0x1a] + (state->io_reg[0x1b] << 8) - state->io_reg[0x20]; //0x20 ??? + tmpx = state->io_reg[0x1e] + (state->io_reg[0x1f] << 8); - if(tmpy != jpeg_y || tmpx != jpeg_x) + if (tmpy != state->jpeg_y || tmpx != state->jpeg_x) { - jpeg_x = tmpx; - jpeg_y = tmpy; + state->jpeg_x = tmpx; + state->jpeg_y = tmpy; render_jpeg(space->machine); } } else { - logerror("I/O access out of range: %x\n", io_offset); + logerror("I/O access out of range: %x\n", state->io_offset); } } static WRITE16_HANDLER(sound_w) { - soundlatch_w(space, 0, data & 0xff); - cputag_set_input_line(space->machine, "audiocpu", MCS51_INT0_LINE, HOLD_LINE); + soundlatch_w(space, 0, data & 0xff); + cputag_set_input_line(space->machine, "audiocpu", MCS51_INT0_LINE, HOLD_LINE); } static ADDRESS_MAP_START( sliver_map, ADDRESS_SPACE_PROGRAM, 16 ) @@ -446,14 +474,18 @@ ADDRESS_MAP_END static VIDEO_START(sliver) { - sliver_bitmap_bg = video_screen_auto_bitmap_alloc(machine->primary_screen); - sliver_bitmap_fg = video_screen_auto_bitmap_alloc(machine->primary_screen); + sliver_state *state = (sliver_state *)machine->driver_data; + + state->bitmap_bg = video_screen_auto_bitmap_alloc(machine->primary_screen); + state->bitmap_fg = video_screen_auto_bitmap_alloc(machine->primary_screen); } static VIDEO_UPDATE(sliver) { - copybitmap (bitmap, sliver_bitmap_bg, 0, 0, 0, 0, cliprect); - copybitmap_trans(bitmap, sliver_bitmap_fg, 0, 0, 0, 0, cliprect, 0); + sliver_state *state = (sliver_state *)screen->machine->driver_data; + + copybitmap (bitmap, state->bitmap_bg, 0, 0, 0, 0, cliprect); + copybitmap_trans(bitmap, state->bitmap_fg, 0, 0, 0, 0, cliprect, 0); return 0; } @@ -534,6 +566,9 @@ static INTERRUPT_GEN( sliver_int ) } static MACHINE_DRIVER_START( sliver ) + + MDRV_DRIVER_DATA( sliver_state ) + MDRV_CPU_ADD("maincpu", M68000, 12000000) MDRV_CPU_PROGRAM_MAP(sliver_map) MDRV_CPU_VBLANK_INT_HACK(sliver_int,3) @@ -590,8 +625,10 @@ ROM_END static DRIVER_INIT(sliver) { - jpeg_addr = -1; - colorram=auto_alloc_array(machine, UINT8, 256*3); + sliver_state *state = (sliver_state *)machine->driver_data; + + state->jpeg_addr = -1; + state->colorram=auto_alloc_array(machine, UINT8, 256*3); } GAME( 1996, sliver, 0, sliver, sliver, sliver, ROT0, "Hollow Corp", "Sliver", GAME_IMPERFECT_GRAPHICS ) diff --git a/src/mame/drivers/spoker.c b/src/mame/drivers/spoker.c index 3f5bf4159b0..3fb79a6b303 100644 --- a/src/mame/drivers/spoker.c +++ b/src/mame/drivers/spoker.c @@ -18,60 +18,76 @@ TODO: Video Hardware ***************************************************************************/ +typedef struct _spoker_state spoker_state; +struct _spoker_state +{ + UINT8 *bg_tile_ram; + tilemap_t *bg_tilemap; -static UINT8 *bg_tile_ram; -static tilemap_t *bg_tilemap; + UINT8 *fg_tile_ram; + UINT8 *fg_color_ram; + tilemap_t *fg_tilemap; -static UINT8 *fg_tile_ram, *fg_color_ram; -static tilemap_t *fg_tilemap; - -static int video_enable; + int video_enable; + int nmi_enable, hopper; + UINT8 igs_magic[2]; + UINT8 out[3]; +}; static WRITE8_HANDLER( bg_tile_w ) { - bg_tile_ram[offset] = data; - tilemap_mark_tile_dirty(bg_tilemap,offset); + spoker_state *state = (spoker_state *)space->machine->driver_data; + + state->bg_tile_ram[offset] = data; + tilemap_mark_tile_dirty(state->bg_tilemap,offset); } static TILE_GET_INFO( get_bg_tile_info ) { - int code = bg_tile_ram[tile_index]; + spoker_state *state = (spoker_state *)machine->driver_data; + int code = state->bg_tile_ram[tile_index]; SET_TILE_INFO(1 + (tile_index & 3), code & 0xff, 0, 0); } static TILE_GET_INFO( get_fg_tile_info ) { - int code = fg_tile_ram[tile_index] | (fg_color_ram[tile_index] << 8); + spoker_state *state = (spoker_state *)machine->driver_data; + int code = state->fg_tile_ram[tile_index] | (state->fg_color_ram[tile_index] << 8); SET_TILE_INFO(0, code, (4*(code >> 14)+3), 0); } static WRITE8_HANDLER( fg_tile_w ) { - fg_tile_ram[offset] = data; - tilemap_mark_tile_dirty(fg_tilemap,offset); + spoker_state *state = (spoker_state *)space->machine->driver_data; + + state->fg_tile_ram[offset] = data; + tilemap_mark_tile_dirty(state->fg_tilemap,offset); } static WRITE8_HANDLER( fg_color_w ) { - fg_color_ram[offset] = data; - tilemap_mark_tile_dirty(fg_tilemap,offset); + spoker_state *state = (spoker_state *)space->machine->driver_data; + + state->fg_color_ram[offset] = data; + tilemap_mark_tile_dirty(state->fg_tilemap,offset); } static VIDEO_START(spoker) { - bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 32, 128, 8); - fg_tilemap = tilemap_create(machine, get_fg_tile_info, tilemap_scan_rows, 8, 8, 128, 32); - tilemap_set_transparent_pen(fg_tilemap, 0); + spoker_state *state = (spoker_state *)machine->driver_data; + + state->bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 32, 128, 8); + state->fg_tilemap = tilemap_create(machine, get_fg_tile_info, tilemap_scan_rows, 8, 8, 128, 32); + tilemap_set_transparent_pen(state->fg_tilemap, 0); } static VIDEO_UPDATE(spoker) { + spoker_state *state = (spoker_state *)screen->machine->driver_data; + bitmap_fill(bitmap, cliprect, get_black_pen(screen->machine)); - - tilemap_draw(bitmap, cliprect, bg_tilemap, 0, 0); - - tilemap_draw(bitmap, cliprect, fg_tilemap, 0, 0); - + tilemap_draw(bitmap, cliprect, state->bg_tilemap, 0, 0); + tilemap_draw(bitmap, cliprect, state->fg_tilemap, 0, 0); return 0; } @@ -79,17 +95,16 @@ static VIDEO_UPDATE(spoker) Memory Maps ***************************************************************************/ -static int nmi_enable, hopper; - static CUSTOM_INPUT( hopper_r ) { - if (hopper) return !(video_screen_get_frame_number(field->port->machine->primary_screen)%10); - return input_code_pressed(field->port->machine, KEYCODE_H); + running_machine *machine = field->port->machine; + spoker_state *state = (spoker_state *)machine->driver_data; + + if (state->hopper) return !(video_screen_get_frame_number(machine->primary_screen)%10); + return input_code_pressed(machine, KEYCODE_H); } -static UINT8 out[3]; - -static void show_out(void) +static void show_out(UINT8 *out) { #ifdef MAME_DEBUG popmessage("%02x %02x %02x", out[0], out[1], out[2]); @@ -98,7 +113,9 @@ static void show_out(void) static WRITE8_HANDLER( spoker_nmi_and_coins_w ) { - if ((nmi_enable ^ data) & (~0xdd)) + spoker_state *state = (spoker_state *)space->machine->driver_data; + + if ((state->nmi_enable ^ data) & (~0xdd)) { logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(space->cpu),data); // popmessage("%02x",data); @@ -111,71 +128,77 @@ static WRITE8_HANDLER( spoker_nmi_and_coins_w ) set_led_status(space->machine, 6, data & 0x40); // led for coin out / hopper active - nmi_enable = data; // data & 0x80 // nmi enable? + state->nmi_enable = data; // data & 0x80 // nmi enable? - out[0] = data; - show_out(); + state->out[0] = data; + show_out(state->out); } static WRITE8_HANDLER( spoker_video_and_leds_w ) { + spoker_state *state = (spoker_state *)space->machine->driver_data; + set_led_status(space->machine, 4, data & 0x01); // start? set_led_status(space->machine, 5, data & 0x04); // l_bet? - video_enable = data & 0x40; - hopper = (~data)& 0x80; + state->video_enable = data & 0x40; + state->hopper = (~data)& 0x80; - out[1] = data; - show_out(); + state->out[1] = data; + show_out(state->out); } static WRITE8_HANDLER( spoker_leds_w ) { + spoker_state *state = (spoker_state *)space->machine->driver_data; + set_led_status(space->machine, 0, data & 0x01); // stop_1 set_led_status(space->machine, 1, data & 0x02); // stop_2 set_led_status(space->machine, 2, data & 0x04); // stop_3 set_led_status(space->machine, 3, data & 0x08); // stop // data & 0x10? - out[2] = data; - show_out(); + state->out[2] = data; + show_out(state->out); } -static UINT8 igs_magic[2]; - static WRITE8_HANDLER( spoker_magic_w ) { - igs_magic[offset] = data; + spoker_state *state = (spoker_state *)space->machine->driver_data; + + state->igs_magic[offset] = data; if (offset == 0) return; - switch(igs_magic[0]) + switch(state->igs_magic[0]) { case 0x01: break; default: // popmessage("magic %x <- %04x",igs_magic[0],data); - logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(space->cpu), igs_magic[0], data); + logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(space->cpu), state->igs_magic[0], data); } } static READ8_HANDLER( spoker_magic_r ) { - switch(igs_magic[0]) + spoker_state *state = (spoker_state *)space->machine->driver_data; + + switch(state->igs_magic[0]) { case 0x00: - if ( !(igs_magic[1] & 0x01) ) return input_port_read(space->machine, "DSW1"); - if ( !(igs_magic[1] & 0x02) ) return input_port_read(space->machine, "DSW2"); - if ( !(igs_magic[1] & 0x04) ) return input_port_read(space->machine, "DSW3"); - if ( !(igs_magic[1] & 0x08) ) return input_port_read(space->machine, "DSW4"); - if ( !(igs_magic[1] & 0x10) ) return input_port_read(space->machine, "DSW5"); - logerror("%06x: warning, reading dsw with igs_magic[1] = %02x\n", cpu_get_pc(space->cpu), igs_magic[1]); + if ( !(state->igs_magic[1] & 0x01) ) return input_port_read(space->machine, "DSW1"); + if ( !(state->igs_magic[1] & 0x02) ) return input_port_read(space->machine, "DSW2"); + if ( !(state->igs_magic[1] & 0x04) ) return input_port_read(space->machine, "DSW3"); + if ( !(state->igs_magic[1] & 0x08) ) return input_port_read(space->machine, "DSW4"); + if ( !(state->igs_magic[1] & 0x10) ) return input_port_read(space->machine, "DSW5"); + logerror("%06x: warning, reading dsw with igs_magic[1] = %02x\n", cpu_get_pc(space->cpu), state->igs_magic[1]); break; default: - logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(space->cpu), igs_magic[0]); + logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(space->cpu), state->igs_magic[0]); } return 0; @@ -195,9 +218,9 @@ static ADDRESS_MAP_START( spoker_portmap, ADDRESS_SPACE_IO, 8 ) AM_RANGE( 0x2000, 0x23ff ) AM_RAM_WRITE( paletteram_xBBBBBGGGGGRRRRR_split1_w ) AM_BASE_GENERIC( paletteram ) AM_RANGE( 0x2400, 0x27ff ) AM_RAM_WRITE( paletteram_xBBBBBGGGGGRRRRR_split2_w ) AM_BASE_GENERIC( paletteram2 ) - AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE( bg_tile_w ) AM_BASE( &bg_tile_ram ) + AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE( bg_tile_w ) AM_BASE_MEMBER( spoker_state,bg_tile_ram ) - AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE( fg_tile_w ) AM_BASE( &fg_tile_ram ) + AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE( fg_tile_w ) AM_BASE_MEMBER( spoker_state,fg_tile_ram ) AM_RANGE( 0x6480, 0x6480 ) AM_WRITE( spoker_nmi_and_coins_w ) @@ -214,7 +237,7 @@ static ADDRESS_MAP_START( spoker_portmap, ADDRESS_SPACE_IO, 8 ) AM_RANGE( 0x64d0, 0x64d1 ) AM_READWRITE( spoker_magic_r, spoker_magic_w ) // DSW1-5 - AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE( fg_color_w ) AM_BASE( &fg_color_ram ) + AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE( fg_color_w ) AM_BASE_MEMBER( spoker_state,fg_color_ram ) ADDRESS_MAP_END @@ -343,18 +366,25 @@ GFXDECODE_END static MACHINE_RESET( spoker ) { - nmi_enable = 0; - hopper = 0; - video_enable = 1; + spoker_state *state = (spoker_state *)machine->driver_data; + + state->nmi_enable = 0; + state->hopper = 0; + state->video_enable = 1; } static INTERRUPT_GEN( spoker_interrupt ) { - if (nmi_enable & 0x80) + spoker_state *state = (spoker_state *)device->machine->driver_data; + + if (state->nmi_enable & 0x80) cpu_set_input_line(device, INPUT_LINE_NMI, PULSE_LINE); } static MACHINE_DRIVER_START( spoker ) + + MDRV_DRIVER_DATA( spoker_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", Z180, XTAL_12MHz / 2) /* HD64180RP8, 8 MHz? */ MDRV_CPU_PROGRAM_MAP(spoker_map) diff --git a/src/mame/drivers/spool99.c b/src/mame/drivers/spool99.c index d7c29e7b284..5548e1a5503 100644 --- a/src/mame/drivers/spool99.c +++ b/src/mame/drivers/spool99.c @@ -92,15 +92,20 @@ Note #include "sound/okim6295.h" #include "machine/eeprom.h" -static UINT8 *spool99_main; -static tilemap_t *sc0_tilemap; -static UINT8 *spool99_cram; -static UINT8 *spool99_vram; +typedef struct _spool99_state spool99_state; +struct _spool99_state +{ + UINT8 *main; + tilemap_t *sc0_tilemap; + UINT8 *cram; + UINT8 *vram; +}; static TILE_GET_INFO( get_spool99_tile_info ) { - int code = ((spool99_vram[tile_index*2+1]<<8) | (spool99_vram[tile_index*2+0])); - int color = spool99_cram[tile_index*2+0]; + spool99_state *state = (spool99_state *)machine->driver_data; + int code = ((state->vram[tile_index*2+1]<<8) | (state->vram[tile_index*2+0])); + int color = state->cram[tile_index*2+0]; SET_TILE_INFO( 0, @@ -111,25 +116,33 @@ static TILE_GET_INFO( get_spool99_tile_info ) static VIDEO_START(spool99) { - sc0_tilemap = tilemap_create(machine, get_spool99_tile_info,tilemap_scan_rows,8,8,64,32); + spool99_state *state = (spool99_state *)machine->driver_data; + + state->sc0_tilemap = tilemap_create(machine, get_spool99_tile_info, tilemap_scan_rows, 8, 8, 64, 32); } static VIDEO_UPDATE(spool99) { - tilemap_draw(bitmap,cliprect,sc0_tilemap,0,0); + spool99_state *state = (spool99_state *)screen->machine->driver_data; + + tilemap_draw(bitmap,cliprect,state->sc0_tilemap,0,0); return 0; } static WRITE8_HANDLER( spool99_vram_w ) { - spool99_vram[offset] = data; - tilemap_mark_tile_dirty(sc0_tilemap,offset/2); + spool99_state *state = (spool99_state *)space->machine->driver_data; + + state->vram[offset] = data; + tilemap_mark_tile_dirty(state->sc0_tilemap,offset/2); } static WRITE8_HANDLER( spool99_cram_w ) { - spool99_cram[offset] = data; - tilemap_mark_tile_dirty(sc0_tilemap,offset/2); + spool99_state *state = (spool99_state *)space->machine->driver_data; + + state->cram[offset] = data; + tilemap_mark_tile_dirty(state->sc0_tilemap,offset/2); } @@ -185,7 +198,7 @@ static WRITE8_DEVICE_HANDLER( eeprom_dataline_w ) } static ADDRESS_MAP_START( spool99_map, ADDRESS_SPACE_PROGRAM, 8 ) - AM_RANGE(0x0000, 0xaeff) AM_RAM AM_BASE(&spool99_main) + AM_RANGE(0x0000, 0xaeff) AM_RAM AM_BASE_MEMBER(spool99_state,main) AM_RANGE(0xaf00, 0xafff) AM_READ(spool99_io_r) AM_RANGE(0xafed, 0xafed) AM_DEVWRITE("eeprom", eeprom_resetline_w ) AM_RANGE(0xafee, 0xafee) AM_DEVWRITE("eeprom", eeprom_clockline_w ) @@ -195,8 +208,8 @@ static ADDRESS_MAP_START( spool99_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0xb000, 0xb3ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_le_w) AM_BASE_GENERIC(paletteram) // palette AM_RANGE(0xb800, 0xdfff) AM_RAM - AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(spool99_vram_w) AM_BASE(&spool99_vram) - AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(spool99_cram_w) AM_BASE(&spool99_cram) + AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(spool99_vram_w) AM_BASE_MEMBER(spool99_state,vram) + AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(spool99_cram_w) AM_BASE_MEMBER(spool99_state,cram) ADDRESS_MAP_END @@ -267,6 +280,9 @@ INPUT_PORTS_END static MACHINE_DRIVER_START( spool99 ) + + MDRV_DRIVER_DATA( spool99_state ) + MDRV_CPU_ADD("maincpu", Z80, 24000000/8) MDRV_CPU_PROGRAM_MAP(spool99_map) MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) @@ -324,9 +340,11 @@ ROM_END static DRIVER_INIT( spool99 ) { + spool99_state *state = (spool99_state *)machine->driver_data; + UINT8 *ROM = memory_region(machine, "maincpu"); // vram = auto_alloc_array(machine, UINT8, 0x2000); - memcpy(spool99_main, ROM, 0xae00); + memcpy(state->main, ROM, 0xae00); } diff --git a/src/mame/drivers/srmp5.c b/src/mame/drivers/srmp5.c index 962cc5bd582..58c4d9cfff4 100644 --- a/src/mame/drivers/srmp5.c +++ b/src/mame/drivers/srmp5.c @@ -42,15 +42,6 @@ This is not a bug (real machine behaves the same). #include "includes/st0016.h" #define DEBUG_CHAR -static UINT32 databank; -static UINT32 srmp5_vidregs[0x120 / 4]; -static UINT16 *tileram, *palram; -static UINT16 *sprram; -static UINT8 cmd1 = 0, cmd2 = 0, cmd_stat = 0; - -#ifdef DEBUG_CHAR -static UINT8 tileduty[0x2000]; -#endif #define SPRITE_GLOBAL_X 0 #define SPRITE_GLOBAL_Y 1 @@ -71,20 +62,41 @@ static UINT8 tileduty[0x2000]; #define SPRITE_DATA_GRANULARITY 0x80 +typedef struct _srmp5_state srmp5_state; +struct _srmp5_state +{ + UINT32 databank; + UINT16 *tileram; + UINT16 *palram; + UINT16 *sprram; + + UINT8 input_select; + + UINT8 cmd1; + UINT8 cmd2; + UINT8 cmd_stat; + + UINT32 vidregs[0x120 / 4]; +#ifdef DEBUG_CHAR + UINT8 tileduty[0x2000]; +#endif +}; + static VIDEO_UPDATE( srmp5 ) { + srmp5_state *state = (srmp5_state *)screen->machine->driver_data; int x,y,address,xs,xs2,ys,ys2,height,width,xw,yw,xb,yb,sizex,sizey; - UINT16 *sprite_list=sprram; - UINT16 *sprite_list_end=&sprram[0x4000]; //guess - UINT8 *pixels=(UINT8 *)tileram; + UINT16 *sprite_list=state->sprram; + UINT16 *sprite_list_end=&state->sprram[0x4000]; //guess + UINT8 *pixels=(UINT8 *)state->tileram; const rectangle *visarea = video_screen_get_visible_area(screen); //Table surface seems to be tiles, but display corrupts when switching the scene if always ON. //Currently the tiles are OFF. #ifdef BG_ENABLE - UINT8 tile_width = (srmp5_vidregs[2] >> 0) & 0xFF; - UINT8 tile_height = (srmp5_vidregs[2] >> 8) & 0xFF; + UINT8 tile_width = (state->vidregs[2] >> 0) & 0xFF; + UINT8 tile_height = (state->vidregs[2] >> 8) & 0xFF; if(tile_width && tile_height) { // 16x16 tile @@ -104,7 +116,7 @@ static VIDEO_UPDATE( srmp5 ) UINT8 pen = pixels[address]; if(pen) { - UINT16 pixdata=palram[pen]; + UINT16 pixdata=state->palram[pen]; *BITMAP_ADDR32(bitmap, yw * 16 + y, xw * 16 + x) = ((pixdata&0x7c00)>>7) | ((pixdata&0x3e0)<<6) | ((pixdata&0x1f)<<19); } address++; @@ -119,7 +131,7 @@ static VIDEO_UPDATE( srmp5 ) while((sprite_list[SUBLIST_OFFSET]&SPRITE_LIST_END_MARKER)==0 && sprite_listsprram[sprite_list[SUBLIST_OFFSET]<max_x && xb+xs2>=visarea->min_x && yb+ys2<=visarea->max_y && yb+ys2>=visarea->min_y ) { - UINT16 pixdata=palram[pen+((sprite_sublist[SPRITE_PALETTE]&0xff)<<8)]; + UINT16 pixdata=state->palram[pen+((sprite_sublist[SPRITE_PALETTE]&0xff)<<8)]; *BITMAP_ADDR32(bitmap, yb+ys2, xb+xs2) = ((pixdata&0x7c00)>>7) | ((pixdata&0x3e0)<<6) | ((pixdata&0x1f)<<19); } } @@ -177,10 +189,10 @@ static VIDEO_UPDATE( srmp5 ) int i; for(i = 0; i < 0x2000; i++) { - if(tileduty[i] == 1) + if (state->tileduty[i] == 1) { - decodechar(screen->machine->gfx[0], i, (UINT8 *)tileram); - tileduty[i] = 0; + decodechar(screen->machine->gfx[0], i, (UINT8 *)state->tileram); + state->tileduty[i] = 0; } } } @@ -190,62 +202,80 @@ static VIDEO_UPDATE( srmp5 ) static READ32_HANDLER(srmp5_palette_r) { - return palram[offset]; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + return state->palram[offset]; } static WRITE32_HANDLER(srmp5_palette_w) { - COMBINE_DATA(&palram[offset]); + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + COMBINE_DATA(&state->palram[offset]); palette_set_color(space->machine, offset, MAKE_RGB(data << 3 & 0xFF, data >> 2 & 0xFF, data >> 7 & 0xFF)); } static WRITE32_HANDLER(bank_w) { - COMBINE_DATA(&databank); + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + COMBINE_DATA(&state->databank); } static READ32_HANDLER(tileram_r) { - return tileram[offset]; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + return state->tileram[offset]; } static WRITE32_HANDLER(tileram_w) { - tileram[offset] = data & 0xFFFF; //lower 16bit only + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + state->tileram[offset] = data & 0xFFFF; //lower 16bit only #ifdef DEBUG_CHAR - tileduty[offset >> 6] = 1; + state->tileduty[offset >> 6] = 1; #endif } static READ32_HANDLER(spr_r) { - return sprram[offset]; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + return state->sprram[offset]; } static WRITE32_HANDLER(spr_w) { - sprram[offset] = data & 0xFFFF; //lower 16bit only + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + state->sprram[offset] = data & 0xFFFF; //lower 16bit only } static READ32_HANDLER(data_r) { + srmp5_state *state = (srmp5_state *)space->machine->driver_data; UINT32 data; const UINT8 *usr = memory_region(space->machine, "user2"); - data=((databank>>4)&0xf)*0x100000; //guess + + data=((state->databank>>4)&0xf)*0x100000; //guess data=usr[data+offset*2]+usr[data+offset*2+1]*256; return data|(data<<16); } -static UINT8 input_select = 0; - static WRITE32_HANDLER(input_select_w) { - input_select = data & 0x0F; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + state->input_select = data & 0x0F; } static READ32_HANDLER(srmp5_inputs_r) { + srmp5_state *state = (srmp5_state *)space->machine->driver_data; UINT32 ret = 0; - switch(input_select) + + switch (state->input_select) { case 0x01: ret = input_port_read(space->machine, "IN0"); @@ -267,33 +297,43 @@ static READ32_HANDLER(srmp5_inputs_r) //almost all cmds are sound related static WRITE32_HANDLER(cmd1_w) { - cmd1 = data & 0xFF; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + state->cmd1 = data & 0xFF; logerror("cmd1_w %08X\n", data); } static WRITE32_HANDLER(cmd2_w) { - cmd2 = data & 0xFF; - cmd_stat = 5; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + state->cmd2 = data & 0xFF; + state->cmd_stat = 5; logerror("cmd2_w %08X\n", data); } static READ32_HANDLER(cmd_stat32_r) { - return cmd_stat; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + return state->cmd_stat; } static READ32_HANDLER(srmp5_vidregs_r) { - logerror("vidregs read %08X %08X\n", offset << 2, srmp5_vidregs[offset]); - return srmp5_vidregs[offset]; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + logerror("vidregs read %08X %08X\n", offset << 2, state->vidregs[offset]); + return state->vidregs[offset]; } static WRITE32_HANDLER(srmp5_vidregs_w) { - COMBINE_DATA(&srmp5_vidregs[offset]); + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + COMBINE_DATA(&state->vidregs[offset]); if(offset != 0x10C / 4) - logerror("vidregs write %08X %08X\n", offset << 2, srmp5_vidregs[offset]); + logerror("vidregs write %08X %08X\n", offset << 2, state->vidregs[offset]); } static ADDRESS_MAP_START( srmp5_mem, ADDRESS_SPACE_PROGRAM, 32 ) @@ -339,18 +379,24 @@ READ8_HANDLER(st0016_dma_r); static READ8_HANDLER(cmd1_r) { - cmd_stat = 0; - return cmd1; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + state->cmd_stat = 0; + return state->cmd1; } static READ8_HANDLER(cmd2_r) { - return cmd2; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + return state->cmd2; } static READ8_HANDLER(cmd_stat8_r) { - return cmd_stat; + srmp5_state *state = (srmp5_state *)space->machine->driver_data; + + return state->cmd_stat; } static ADDRESS_MAP_START( st0016_io, ADDRESS_SPACE_IO, 8 ) @@ -507,10 +553,13 @@ static const gfx_layout tile_16x16x8_layout = static GFXDECODE_START( srmp5 ) GFXDECODE_ENTRY( "gfx1", 0, tile_16x8x8_layout, 0x0, 0x800 ) -// GFXDECODE_ENTRY( "gfx1", 0, tile_16x16x8_layout, 0x0, 0x800 ) + //GFXDECODE_ENTRY( "gfx1", 0, tile_16x16x8_layout, 0x0, 0x800 ) GFXDECODE_END static MACHINE_DRIVER_START( srmp5 ) + + MDRV_DRIVER_DATA( srmp5_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu",Z80,8000000) MDRV_CPU_PROGRAM_MAP(st0016_mem) @@ -575,12 +624,14 @@ ROM_END static DRIVER_INIT(srmp5) { - st0016_game=9; - tileram = auto_alloc_array(machine, UINT16, 0x100000/2); - sprram = auto_alloc_array(machine, UINT16, 0x080000/2); - palram = auto_alloc_array(machine, UINT16, 0x040000/2); + srmp5_state *state = (srmp5_state *)machine->driver_data; + st0016_game = 9; + + state->tileram = auto_alloc_array(machine, UINT16, 0x100000/2); + state->sprram = auto_alloc_array(machine, UINT16, 0x080000/2); + state->palram = auto_alloc_array(machine, UINT16, 0x040000/2); #ifdef DEBUG_CHAR - memset(tileduty, 1, 0x2000); + memset(state->tileduty, 1, 0x2000); #endif } diff --git a/src/mame/drivers/srmp6.c b/src/mame/drivers/srmp6.c index b825244e4c6..a10eabfefac 100644 --- a/src/mame/drivers/srmp6.c +++ b/src/mame/drivers/srmp6.c @@ -71,12 +71,23 @@ Dumped 06/15/2000 #include "deprecat.h" #include "sound/nile.h" -static UINT16* tileram; -static UINT16* dmaram; +typedef struct _srmp6_state srmp6_state; +struct _srmp6_state +{ + UINT16* tileram; + UINT16* dmaram; -static UINT16 *sprram, *sprram_old; + UINT16 *sprram; + UINT16 *sprram_old; -static int brightness; + int brightness; + UINT16 input_select; + UINT16 *video_regs; + + unsigned short lastb; + unsigned short lastb2; + int destl; +}; #define VERBOSE 0 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) @@ -94,8 +105,9 @@ static const gfx_layout tiles8x8_layout = static void update_palette(running_machine *machine) { + srmp6_state *state = (srmp6_state *)machine->driver_data; INT8 r, g ,b; - int brg = brightness - 0x60; + int brg = state->brightness - 0x60; int i; for(i = 0; i < 0x800; i++) @@ -126,19 +138,17 @@ static void update_palette(running_machine *machine) static VIDEO_START(srmp6) { - tileram = auto_alloc_array(machine, UINT16, 0x100000*16/2); - memset(tileram,0x00,(0x100000*16)); + srmp6_state *state = (srmp6_state *)machine->driver_data; - dmaram = auto_alloc_array(machine, UINT16, 0x100/2); - - sprram_old = auto_alloc_array(machine, UINT16, 0x80000/2); - memset(sprram_old, 0, 0x80000); + state->tileram = auto_alloc_array_clear(machine, UINT16, 0x100000*16/2); + state->dmaram = auto_alloc_array(machine, UINT16, 0x100/2); + state->sprram_old = auto_alloc_array_clear(machine, UINT16, 0x80000/2); /* create the char set (gfx will then be updated dynamically from RAM) */ - machine->gfx[0] = gfx_element_alloc(machine, &tiles8x8_layout, (UINT8*)tileram, machine->config->total_colors / 256, 0); + machine->gfx[0] = gfx_element_alloc(machine, &tiles8x8_layout, (UINT8*)state->tileram, machine->config->total_colors / 256, 0); machine->gfx[0]->color_granularity=256; - brightness = 0x60; + state->brightness = 0x60; } #if 0 @@ -147,9 +157,10 @@ static int xixi=0; static VIDEO_UPDATE(srmp6) { + srmp6_state *state = (srmp6_state *)screen->machine->driver_data; int alpha; int x,y,tileno,height,width,xw,yw,sprite,xb,yb; - UINT16 *sprite_list=sprram_old; + UINT16 *sprite_list = state->sprram_old; UINT16 mainlist_offset = 0; union @@ -179,7 +190,7 @@ static VIDEO_UPDATE(srmp6) while (mainlist_offset<0x2000/2) { - UINT16 *sprite_sublist=&sprram_old[sprite_list[mainlist_offset+1]<<3]; + UINT16 *sprite_sublist = &state->sprram_old[sprite_list[mainlist_offset+1]<<3]; UINT16 sublist_length=sprite_list[mainlist_offset+0]&0x7fff; //+1 ? INT16 global_x,global_y, flip_x, flip_y; UINT16 global_pal; @@ -206,7 +217,7 @@ static VIDEO_UPDATE(srmp6) { alpha = 255; } - // printf("%x %x \n",sprite_list[mainlist_offset+1],sublist_length); + // printf("%x %x \n",sprite_list[mainlist_offset+1],sublist_length); while(sublist_length) { @@ -257,12 +268,12 @@ static VIDEO_UPDATE(srmp6) mainlist_offset+=8; } - memcpy(sprram_old, sprram, 0x80000); + memcpy(state->sprram_old, state->sprram, 0x80000); if(input_code_pressed_once(screen->machine, KEYCODE_Q)) { FILE *p=fopen("tileram.bin","wb"); - fwrite(tileram,1,0x100000*16,p); + fwrite(state->tileram, 1, 0x100000*16, p); fclose(p); } @@ -274,19 +285,21 @@ static VIDEO_UPDATE(srmp6) Main CPU memory handlers ***************************************************************************/ -static UINT16 srmp6_input_select = 0; - static WRITE16_HANDLER( srmp6_input_select_w ) { - srmp6_input_select = data & 0x0f; + srmp6_state *state = (srmp6_state *)space->machine->driver_data; + + state->input_select = data & 0x0f; } static READ16_HANDLER( srmp6_inputs_r ) { + srmp6_state *state = (srmp6_state *)space->machine->driver_data; + if (offset == 0) // DSW return input_port_read(space->machine, "DSW"); - switch(srmp6_input_select) // inputs + switch (state->input_select) // inputs { case 1<<0: return input_port_read(space->machine, "KEY0"); case 1<<1: return input_port_read(space->machine, "KEY1"); @@ -298,10 +311,10 @@ static READ16_HANDLER( srmp6_inputs_r ) } -static UINT16 *video_regs; - static WRITE16_HANDLER( video_regs_w ) { + srmp6_state *state = (srmp6_state *)space->machine->driver_data; + switch(offset) { @@ -315,8 +328,8 @@ static WRITE16_HANDLER( video_regs_w ) case 0x5c/2: // either 0x40 explicitely in many places, or according $2083b0 (IT4) //Fade in/out (0x40(dark)-0x60(normal)-0x7e?(bright) reset by 0x00? data = (!data)?0x60:(data == 0x5e)?0x60:data; - if(brightness != data) { - brightness = data; + if (state->brightness != data) { + state->brightness = data; update_palette(space->machine); } break; @@ -335,51 +348,49 @@ static WRITE16_HANDLER( video_regs_w ) logerror("video_regs_w (PC=%06X): %04x = %04x & %04x\n", cpu_get_previouspc(space->cpu), offset*2, data, mem_mask); break; } - COMBINE_DATA(&video_regs[offset]); + COMBINE_DATA(&state->video_regs[offset]); } static READ16_HANDLER( video_regs_r ) { + srmp6_state *state = (srmp6_state *)space->machine->driver_data; + logerror("video_regs_r (PC=%06X): %04x\n", cpu_get_previouspc(space->cpu), offset*2); - return video_regs[offset]; + return state->video_regs[offset]; } /* DMA RLE stuff - the same as CPS3 */ -static unsigned short lastb; -static unsigned short lastb2; -static int destl; - static UINT32 process(running_machine *machine,UINT8 b,UINT32 dst_offset) { - + srmp6_state *state = (srmp6_state *)machine->driver_data; int l=0; - UINT8 *tram=(UINT8*)tileram; + UINT8 *tram=(UINT8*)state->tileram; - if(lastb==lastb2) //rle + if (state->lastb == state->lastb2) //rle { int i; int rle=(b+1)&0xff; for(i=0;igfx[0], (dst_offset+destl)/0x40); + tram[dst_offset + state->destl] = state->lastb; + gfx_element_mark_dirty(machine->gfx[0], (dst_offset + state->destl)/0x40); dst_offset++; ++l; } - lastb2=0xffff; + state->lastb2 = 0xffff; return l; } else { - lastb2=lastb; - lastb=b; - tram[dst_offset+destl] = b; - gfx_element_mark_dirty(machine->gfx[0], (dst_offset+destl)/0x40); + state->lastb2 = state->lastb; + state->lastb = b; + tram[dst_offset + state->destl] = b; + gfx_element_mark_dirty(machine->gfx[0], (dst_offset + state->destl)/0x40); return 1; } @@ -388,8 +399,11 @@ static UINT32 process(running_machine *machine,UINT8 b,UINT32 dst_offset) static WRITE16_HANDLER(srmp6_dma_w) { + srmp6_state *state = (srmp6_state *)space->machine->driver_data; + UINT16* dmaram = state->dmaram; + COMBINE_DATA(&dmaram[offset]); - if(offset==13 && dmaram[offset]==0x40) + if (offset==13 && dmaram[offset]==0x40) { const UINT8 *rom = memory_region(space->machine, "nile"); UINT32 srctab=2*((((UINT32)dmaram[5])<<16)|dmaram[4]); @@ -414,10 +428,10 @@ static WRITE16_HANDLER(srmp6_dma_w) dmaram[0x18/2], dmaram[0x1a/2])); - destl=dmaram[9]*0x40000; + state->destl = dmaram[9]*0x40000; - lastb=0xfffe; - lastb2=0xffff; + state->lastb = 0xfffe; + state->lastb2 = 0xffff; while(1) { @@ -459,14 +473,14 @@ static WRITE16_HANDLER(srmp6_dma_w) /* if tileram is actually bigger than the mapped area, how do we access the rest? */ static READ16_HANDLER(tileram_r) { -// return tileram[offset]; + //return state->tileram[offset]; return 0x0000; } static WRITE16_HANDLER(tileram_w) { //UINT16 tmp; -// COMBINE_DATA(&tileram[offset]); + //COMBINE_DATA(&state->tileram[offset]); /* are the DMA registers enabled some other way, or always mapped here, over RAM? */ if (offset >= 0xfff00/2 && offset <= 0xfff1a/2 ) @@ -478,8 +492,9 @@ static WRITE16_HANDLER(tileram_w) static WRITE16_HANDLER(paletteram_w) { + srmp6_state *state = (srmp6_state *)space->machine->driver_data; INT8 r, g, b; - int brg = brightness - 0x60; + int brg = state->brightness - 0x60; paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset, data, mem_mask); @@ -521,20 +536,20 @@ static ADDRESS_MAP_START( srmp6, ADDRESS_SPACE_PROGRAM, 16 ) AM_RANGE(0x4d0000, 0x4d0001) AM_READWRITE(watchdog_reset16_r, watchdog_reset16_w) // watchdog // OBJ RAM: checked [$400000-$47dfff] - AM_RANGE(0x400000, 0x47ffff) AM_RAM AM_BASE(&sprram) + AM_RANGE(0x400000, 0x47ffff) AM_RAM AM_BASE_MEMBER(srmp6_state,sprram) // CHR RAM: checked [$500000-$5fffff] - AM_RANGE(0x500000, 0x5fffff) AM_READWRITE(tileram_r,tileram_w)//AM_RAM AM_BASE(&tileram) -// AM_RANGE(0x5fff00, 0x5fffff) AM_WRITE(dma_w) AM_BASE(&dmaram) + AM_RANGE(0x500000, 0x5fffff) AM_READWRITE(tileram_r,tileram_w)//AM_RAM AM_BASE_MEMBER(srmp6_state,tileram) + //AM_RANGE(0x5fff00, 0x5fffff) AM_WRITE(dma_w) AM_BASE_MEMBER(srmp6_state,dmaram) - AM_RANGE(0x4c0000, 0x4c006f) AM_READWRITE(video_regs_r, video_regs_w) AM_BASE(&video_regs) // ? gfx regs ST-0026 NiLe + AM_RANGE(0x4c0000, 0x4c006f) AM_READWRITE(video_regs_r, video_regs_w) AM_BASE_MEMBER(srmp6_state,video_regs) // ? gfx regs ST-0026 NiLe AM_RANGE(0x4e0000, 0x4e00ff) AM_DEVREADWRITE("nile", nile_snd_r, nile_snd_w) AM_BASE(&nile_sound_regs) AM_RANGE(0x4e0100, 0x4e0101) AM_DEVREADWRITE("nile", nile_sndctrl_r, nile_sndctrl_w) -// AM_RANGE(0x4e0110, 0x4e0111) AM_NOP // ? accessed once ($268dc, written $b.w) -// AM_RANGE(0x5fff00, 0x5fff1f) AM_RAM // ? see routine $5ca8, video_regs related ??? + //AM_RANGE(0x4e0110, 0x4e0111) AM_NOP // ? accessed once ($268dc, written $b.w) + //AM_RANGE(0x5fff00, 0x5fff1f) AM_RAM // ? see routine $5ca8, video_regs related ??? -// AM_RANGE(0xf00004, 0xf00005) AM_RAM // ? -// AM_RANGE(0xf00006, 0xf00007) AM_RAM // ? + //AM_RANGE(0xf00004, 0xf00005) AM_RAM // ? + //AM_RANGE(0xf00006, 0xf00007) AM_RAM // ? ADDRESS_MAP_END @@ -644,6 +659,9 @@ static INTERRUPT_GEN(srmp6_interrupt) } static MACHINE_DRIVER_START( srmp6 ) + + MDRV_DRIVER_DATA( srmp6_state ) + MDRV_CPU_ADD("maincpu", M68000, 16000000) MDRV_CPU_PROGRAM_MAP(srmp6) MDRV_CPU_VBLANK_INT_HACK(srmp6_interrupt,2) diff --git a/src/mame/drivers/ssingles.c b/src/mame/drivers/ssingles.c index 588b8b83fd6..cadddfbc877 100644 --- a/src/mame/drivers/ssingles.c +++ b/src/mame/drivers/ssingles.c @@ -147,13 +147,17 @@ Dumped by Chack'n #include "sound/ay8910.h" #include "video/mc6845.h" -static UINT8 *ssingles_videoram; -static UINT8 *ssingles_colorram; -static UINT8 prot_data; - #define NUM_PENS (4*8) #define VMEM_SIZE 0x100 -static pen_t pens[NUM_PENS]; + +typedef struct _ssingles_state ssingles_state; +struct _ssingles_state +{ + UINT8 *videoram; + UINT8 *colorram; + UINT8 prot_data; + pen_t pens[NUM_PENS]; +}; //fake palette static const UINT8 ssingles_colors[NUM_PENS*3]= @@ -170,6 +174,7 @@ static const UINT8 ssingles_colors[NUM_PENS*3]= static MC6845_UPDATE_ROW( update_row ) { + ssingles_state *state = (ssingles_state *)device->machine->driver_data; int cx,x; UINT32 tile_address; UINT16 cell,palette; @@ -180,7 +185,7 @@ static MC6845_UPDATE_ROW( update_row ) { int address=((ma>>1)+(cx>>1))&0xff; - cell=ssingles_videoram[address]+(ssingles_colorram[address]<<8); + cell=state->videoram[address]+(state->colorram[address]<<8); tile_address=((cell&0x3ff)<<4)+ra; palette=(cell>>10)&0x1c; @@ -198,7 +203,7 @@ static MC6845_UPDATE_ROW( update_row ) for(x=7;x>=0;--x) { - *BITMAP_ADDR32(bitmap, y, (cx<<3)|(x)) = pens[palette+((b1&1)|((b0&1)<<1))]; + *BITMAP_ADDR32(bitmap, y, (cx<<3)|(x)) = state->pens[palette+((b1&1)|((b0&1)<<1))]; b0>>=1; b1>>=1; } @@ -221,22 +226,26 @@ static const mc6845_interface mc6845_intf = static WRITE8_HANDLER(ssingles_videoram_w) { - ssingles_videoram[offset]=data; + ssingles_state *state = (ssingles_state *)space->machine->driver_data; + state->videoram[offset]=data; } static WRITE8_HANDLER(ssingles_colorram_w) { - ssingles_colorram[offset]=data; + ssingles_state *state = (ssingles_state *)space->machine->driver_data; + state->colorram[offset]=data; } static VIDEO_START(ssingles) { + ssingles_state *state = (ssingles_state *)machine->driver_data; + { int i; for(i=0;ipens[i]=MAKE_RGB(ssingles_colors[3*i], ssingles_colors[3*i+1], ssingles_colors[3*i+2]); } } } @@ -253,18 +262,24 @@ static VIDEO_UPDATE( ssingles ) static READ8_HANDLER(c000_r) { - return prot_data; + ssingles_state *state = (ssingles_state *)space->machine->driver_data; + + return state->prot_data; } static READ8_HANDLER(c001_r) { - prot_data=0xc4; + ssingles_state *state = (ssingles_state *)space->machine->driver_data; + + state->prot_data=0xc4; return 0; } static WRITE8_HANDLER(c001_w) { - prot_data^=data^0x11; + ssingles_state *state = (ssingles_state *)space->machine->driver_data; + + state->prot_data^=data^0x11; } static CUSTOM_INPUT(controls_r) @@ -392,6 +407,9 @@ static INPUT_PORTS_START( ssingles ) INPUT_PORTS_END static MACHINE_DRIVER_START( ssingles ) + + MDRV_DRIVER_DATA( ssingles_state ) + MDRV_CPU_ADD("maincpu", Z80,4000000) /* ? MHz */ MDRV_CPU_PROGRAM_MAP(ssingles_map) MDRV_CPU_IO_MAP(ssingles_io_map) @@ -529,10 +547,12 @@ ROM_END static DRIVER_INIT(ssingles) { - ssingles_videoram=auto_alloc_array_clear(machine, UINT8, VMEM_SIZE); - ssingles_colorram=auto_alloc_array_clear(machine, UINT8, VMEM_SIZE); - state_save_register_global_pointer(machine, ssingles_videoram, VMEM_SIZE); - state_save_register_global_pointer(machine, ssingles_colorram, VMEM_SIZE); + ssingles_state *state = (ssingles_state *)machine->driver_data; + + state->videoram=auto_alloc_array_clear(machine, UINT8, VMEM_SIZE); + state->colorram=auto_alloc_array_clear(machine, UINT8, VMEM_SIZE); + state_save_register_global_pointer(machine, state->videoram, VMEM_SIZE); + state_save_register_global_pointer(machine, state->colorram, VMEM_SIZE); } GAME( 1983, ssingles, 0, ssingles, ssingles, ssingles, ROT90, "Ent. Ent. Ltd", "Swinging Singles", GAME_SUPPORTS_SAVE | GAME_WRONG_COLORS | GAME_IMPERFECT_SOUND ) diff --git a/src/mame/drivers/sstrangr.c b/src/mame/drivers/sstrangr.c index 88d9dff4599..312f94fbc0a 100644 --- a/src/mame/drivers/sstrangr.c +++ b/src/mame/drivers/sstrangr.c @@ -12,10 +12,13 @@ #define NUM_PENS (8) - -static UINT8 *sstrngr_ram; -static size_t sstrngr_ram_size; -static UINT8 sstrngr_flip_screen; +typedef struct _sstrangr_state sstrangr_state; +struct _sstrangr_state +{ + UINT8 *ram; + UINT8 flip_screen; + UINT8 *proms; +}; @@ -27,21 +30,22 @@ static UINT8 sstrngr_flip_screen; static VIDEO_UPDATE( sstrangr ) { + sstrangr_state *state = (sstrangr_state *)screen->machine->driver_data; offs_t offs; - for (offs = 0; offs < sstrngr_ram_size; offs++) + for (offs = 0; offs < 0x2000; offs++) { int i; UINT8 x = offs << 3; int y = offs >> 5; - UINT8 data = sstrngr_ram[offs]; + UINT8 data = state->ram[offs]; for (i = 0; i < 8; i++) { pen_t pen; - if (sstrngr_flip_screen) + if (state->flip_screen) { pen = (data & 0x80) ? RGB_WHITE : RGB_BLACK; data = data << 1; @@ -75,15 +79,16 @@ static void get_pens(pen_t *pens) static VIDEO_UPDATE( sstrngr2 ) { + sstrangr_state *state = (sstrangr_state *)screen->machine->driver_data; pen_t pens[NUM_PENS]; offs_t offs; UINT8 *color_map_base; get_pens(pens); - color_map_base = &memory_region(screen->machine, "proms")[sstrngr_flip_screen ? 0x0000 : 0x0200]; + color_map_base = &memory_region(screen->machine, "proms")[state->flip_screen ? 0x0000 : 0x0200]; - for (offs = 0; offs < sstrngr_ram_size; offs++) + for (offs = 0; offs < 0x2000; offs++) { int i; @@ -92,14 +97,14 @@ static VIDEO_UPDATE( sstrngr2 ) offs_t color_address = (offs >> 9 << 5) | (offs & 0x1f); - UINT8 data = sstrngr_ram[offs]; + UINT8 data = state->ram[offs]; UINT8 fore_color = color_map_base[color_address] & 0x07; for (i = 0; i < 8; i++) { UINT8 color; - if (sstrngr_flip_screen) + if (state->flip_screen) { color = (data & 0x80) ? fore_color : 0; data = data << 1; @@ -122,7 +127,9 @@ static VIDEO_UPDATE( sstrngr2 ) static WRITE8_HANDLER( port_w ) { - sstrngr_flip_screen = data & 0x20; + sstrangr_state *state = (sstrangr_state *)space->machine->driver_data; + + state->flip_screen = data & 0x20; } @@ -130,7 +137,7 @@ static WRITE8_HANDLER( port_w ) static ADDRESS_MAP_START( sstrangr_map, ADDRESS_SPACE_PROGRAM, 8 ) ADDRESS_MAP_GLOBAL_MASK(0x7fff) AM_RANGE(0x0000, 0x1fff) AM_ROM - AM_RANGE(0x2000, 0x3fff) AM_RAM AM_BASE(&sstrngr_ram) AM_SIZE(&sstrngr_ram_size) + AM_RANGE(0x2000, 0x3fff) AM_RAM AM_BASE_MEMBER(sstrangr_state,ram) AM_RANGE(0x6000, 0x63ff) AM_ROM ADDRESS_MAP_END @@ -181,6 +188,8 @@ INPUT_PORTS_END static MACHINE_DRIVER_START( sstrangr ) + MDRV_DRIVER_DATA( sstrangr_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu",8080,1996800) /* clock is a guess, taken from mw8080bw */ MDRV_CPU_PROGRAM_MAP(sstrangr_map) diff --git a/src/mame/drivers/sub.c b/src/mame/drivers/sub.c index dc36dab26eb..81e4e11f99e 100644 --- a/src/mame/drivers/sub.c +++ b/src/mame/drivers/sub.c @@ -112,9 +112,16 @@ PCB2 (Top board, CPU board) #define MASTER_CLOCK XTAL_18_432MHz -static UINT8* sub_vid; -static UINT8* sub_attr; -static UINT8* sub_scrolly; +typedef struct _sub_state sub_state; +struct _sub_state +{ + UINT8* vid; + UINT8* attr; + UINT8* scrolly; + UINT8* spriteram; + UINT8* spriteram2; + UINT8 nmi_en; +}; static VIDEO_START(sub) { @@ -122,7 +129,9 @@ static VIDEO_START(sub) static VIDEO_UPDATE(sub) { + sub_state *state = (sub_state *)screen->machine->driver_data; const gfx_element *gfx = screen->machine->gfx[0]; + const gfx_element *gfx_1 = screen->machine->gfx[1]; int y,x; int count = 0; @@ -130,12 +139,12 @@ static VIDEO_UPDATE(sub) { for (x=0;x<32;x++) { - UINT16 tile = sub_vid[count]; + UINT16 tile = state->vid[count]; UINT8 col; - UINT8 y_offs = sub_scrolly[x]; + UINT8 y_offs = state->scrolly[x]; - tile += (sub_attr[count]&0xe0)<<3; - col = (sub_attr[count]&0x1f); + tile += (state->attr[count]&0xe0)<<3; + col = (state->attr[count]&0x1f); drawgfx_opaque(bitmap,cliprect,gfx,tile,col+0x40,0,0,x*8,(y*8)-y_offs); drawgfx_opaque(bitmap,cliprect,gfx,tile,col+0x40,0,0,x*8,(y*8)-y_offs+256); @@ -156,8 +165,8 @@ static VIDEO_UPDATE(sub) 1 --cc cccc color */ { - UINT8 *spriteram = screen->machine->generic.spriteram.u8; - UINT8 *spriteram_2 = screen->machine->generic.spriteram2.u8; + UINT8 *spriteram = state->spriteram; + UINT8 *spriteram_2 = state->spriteram2; UINT8 x,y,spr_offs,i,col,fx,fy; for(i=0;i<0x40;i+=2) @@ -170,7 +179,7 @@ static VIDEO_UPDATE(sub) if(fx) { x = 0xe0 - x; } fy = (spriteram_2[i+0] & 0x40) ? 0 : 1; - drawgfx_transpen(bitmap,cliprect,screen->machine->gfx[1],spr_offs,col,0,fy,x,y,0); + drawgfx_transpen(bitmap,cliprect,gfx_1,spr_offs,col,0,fy,x,y,0); } } @@ -181,12 +190,12 @@ static VIDEO_UPDATE(sub) { for (x=0;x<32;x++) { - UINT16 tile = sub_vid[count]; + UINT16 tile = state->vid[count]; UINT8 col; - UINT8 y_offs = sub_scrolly[x]; + UINT8 y_offs = state->scrolly[x]; - tile += (sub_attr[count]&0xe0)<<3; - col = (sub_attr[count]&0x1f); + tile += (state->attr[count]&0xe0)<<3; + col = (state->attr[count]&0x1f); if(x >= 28) { @@ -204,11 +213,11 @@ static VIDEO_UPDATE(sub) static ADDRESS_MAP_START( subm_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0xafff) AM_ROM AM_RANGE(0xb000, 0xbfff) AM_RAM - AM_RANGE(0xc000, 0xc3ff) AM_RAM AM_BASE(&sub_attr) - AM_RANGE(0xc400, 0xc7ff) AM_RAM AM_BASE(&sub_vid) - AM_RANGE(0xd000, 0xd03f) AM_RAM AM_BASE_GENERIC(spriteram) - AM_RANGE(0xd800, 0xd83f) AM_RAM AM_BASE_GENERIC(spriteram2) - AM_RANGE(0xd840, 0xd85f) AM_RAM AM_BASE(&sub_scrolly) + AM_RANGE(0xc000, 0xc3ff) AM_RAM AM_BASE_MEMBER(sub_state,attr) + AM_RANGE(0xc400, 0xc7ff) AM_RAM AM_BASE_MEMBER(sub_state,vid) + AM_RANGE(0xd000, 0xd03f) AM_RAM AM_BASE_MEMBER(sub_state,spriteram) + AM_RANGE(0xd800, 0xd83f) AM_RAM AM_BASE_MEMBER(sub_state,spriteram2) + AM_RANGE(0xd840, 0xd85f) AM_RAM AM_BASE_MEMBER(sub_state,scrolly) AM_RANGE(0xe000, 0xe000) AM_NOP AM_RANGE(0xe800, 0xe800) AM_NOP @@ -229,11 +238,11 @@ static WRITE8_HANDLER( subm_to_sound_w ) cputag_set_input_line(space->machine, "soundcpu", 0, HOLD_LINE); } -static UINT8 nmi_en; - static WRITE8_HANDLER( nmi_mask_w ) { - nmi_en = data & 1; + sub_state *state = (sub_state *)space->machine->driver_data; + + state->nmi_en = data & 1; } static ADDRESS_MAP_START( subm_io, ADDRESS_SPACE_IO, 8 ) @@ -348,14 +357,17 @@ static const gfx_layout tiles8x8_layout = }; static const gfx_layout tiles16x32_layout = { - 16,32, - RGN_FRAC(1,3), - 3, - { RGN_FRAC(2,3), RGN_FRAC(1,3), RGN_FRAC(0,3) }, - { 64+0, 64+1, 64+2, 64+3, 64+4, 64+5, 64+6, 64+7, 0, 1, 2, 3, 4, 5, 6, 7 }, - { 55*8, 54*8, 53*8, 52*8, 51*8, 50*8, 49*8, 48*8, 39*8,38*8,37*8,36*8,35*8,34*8,33*8,32*8,23*8,22*8,21*8,20*8,19*8,18*8,17*8,16*8,7*8, -6*8, 5*8, 4*8, 3*8, 2*8, 1*8, 0*8 }, - 64*8 + 16,32, + RGN_FRAC(1,3), + 3, + { RGN_FRAC(2,3), RGN_FRAC(1,3), RGN_FRAC(0,3) }, + { 64+0, 64+1, 64+2, 64+3, 64+4, 64+5, 64+6, 64+7, 0, 1, 2, 3, 4, 5, 6, 7 }, + { 55*8, 54*8, 53*8, 52*8, 51*8, 50*8, 49*8, 48*8, + 39*8, 38*8, 37*8, 36*8, 35*8, 34*8, 33*8, 32*8, + 23*8, 22*8, 21*8, 20*8, 19*8, 18*8, 17*8, 16*8, + 7*8, 6*8, 5*8, 4*8, 3*8, 2*8, 1*8, 0*8 + }, + 64*8 }; static GFXDECODE_START( sub ) @@ -396,11 +408,16 @@ static PALETTE_INIT( sub ) static INTERRUPT_GEN( subm_sound_irq ) { - if(nmi_en) + sub_state *state = (sub_state *)device->machine->driver_data; + + if(state->nmi_en) cputag_set_input_line(device->machine, "soundcpu", INPUT_LINE_NMI, PULSE_LINE); } static MACHINE_DRIVER_START( sub ) + + MDRV_DRIVER_DATA( sub_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", Z80,MASTER_CLOCK/6) /* ? MHz */ MDRV_CPU_PROGRAM_MAP(subm_map) diff --git a/src/mame/drivers/supdrapo.c b/src/mame/drivers/supdrapo.c index 71d9b3b8613..0c6ea48e048 100644 --- a/src/mame/drivers/supdrapo.c +++ b/src/mame/drivers/supdrapo.c @@ -32,7 +32,14 @@ A3-1J #include "cpu/z80/z80.h" #include "sound/ay8910.h" -static UINT8 *char_bank,*col_line; + +typedef struct _supdrapo_state supdrapo_state; +struct _supdrapo_state +{ + UINT8 *char_bank; + UINT8 *col_line; + UINT8 *videoram; +}; static READ8_HANDLER( sdpoker_rng_r ) { @@ -43,10 +50,10 @@ static ADDRESS_MAP_START( sdpoker_mem, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0x4fff) AM_ROM AM_RANGE(0x5000, 0x50ff) AM_RAM AM_SHARE("share1") AM_RANGE(0x57ff, 0x57ff) AM_RAM AM_SHARE("share1") - AM_RANGE(0x5800, 0x58ff) AM_RAM AM_SHARE("share1") AM_BASE(&col_line) + AM_RANGE(0x5800, 0x58ff) AM_RAM AM_SHARE("share1") AM_BASE_MEMBER(supdrapo_state,col_line) AM_RANGE(0x6000, 0x67ff) AM_RAM //work ram - AM_RANGE(0x6800, 0x6bff) AM_RAM AM_BASE_GENERIC(videoram) - AM_RANGE(0x6c00, 0x6fff) AM_RAM AM_BASE(&char_bank) + AM_RANGE(0x6800, 0x6bff) AM_RAM AM_BASE_MEMBER(supdrapo_state,videoram) + AM_RANGE(0x6c00, 0x6fff) AM_RAM AM_BASE_MEMBER(supdrapo_state,char_bank) AM_RANGE(0x7000, 0x7bff) AM_RAM //$7600 seems watchdog AM_RANGE(0x7c00, 0x7c00) AM_WRITENOP //? AM_RANGE(0x8000, 0x8000) AM_READ_PORT("IN4") AM_WRITENOP @@ -194,6 +201,7 @@ static VIDEO_START( supdrapo ) static VIDEO_UPDATE( supdrapo ) { + supdrapo_state *state = (supdrapo_state *)screen->machine->driver_data; int x,y; int count; int color; @@ -204,9 +212,9 @@ static VIDEO_UPDATE( supdrapo ) { for(x=0;x<32;x++) { - int tile = screen->machine->generic.videoram.u8[count] + char_bank[count] * 0x100; + int tile = state->videoram[count] + state->char_bank[count] * 0x100; /* Global Column Coloring, GUESS! */ - color = col_line[(x*2)+1] ? (col_line[(x*2)+1]-1) & 0x7 : 0; + color = state->col_line[(x*2)+1] ? (state->col_line[(x*2)+1]-1) & 0x7 : 0; drawgfx_opaque(bitmap,cliprect,screen->machine->gfx[0],tile,color,0,0,x*8,y*8); @@ -245,6 +253,9 @@ static PALETTE_INIT( sdpoker ) } static MACHINE_DRIVER_START( supdrapo ) + + MDRV_DRIVER_DATA( supdrapo_state ) + MDRV_CPU_ADD("maincpu", Z80,8000000/2) /* ??? */ MDRV_CPU_PROGRAM_MAP(sdpoker_mem) MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) diff --git a/src/mame/drivers/superdq.c b/src/mame/drivers/superdq.c index e385acb883c..aee42ddc7cb 100644 --- a/src/mame/drivers/superdq.c +++ b/src/mame/drivers/superdq.c @@ -27,28 +27,38 @@ #include "machine/laserdsc.h" #include "video/resnet.h" -static running_device *laserdisc; -static UINT8 superdq_ld_in_latch; -static UINT8 superdq_ld_out_latch; +typedef struct _superdq_state superdq_state; +struct _superdq_state +{ + running_device *laserdisc; + UINT8 ld_in_latch; + UINT8 ld_out_latch; -static tilemap_t *superdq_tilemap; -static int superdq_color_bank = 0; + UINT8 *videoram; + tilemap_t *tilemap; + int color_bank; +}; static TILE_GET_INFO( get_tile_info ) { - int tile = machine->generic.videoram.u8[tile_index]; + superdq_state *state = (superdq_state *)machine->driver_data; + int tile = state->videoram[tile_index]; - SET_TILE_INFO(0,tile,superdq_color_bank,0); + SET_TILE_INFO(0, tile, state->color_bank, 0); } static VIDEO_START( superdq ) { - superdq_tilemap = tilemap_create(machine, get_tile_info,tilemap_scan_rows, 8, 8, 32, 32); + superdq_state *state = (superdq_state *)machine->driver_data; + + state->tilemap = tilemap_create(machine, get_tile_info, tilemap_scan_rows, 8, 8, 32, 32); } static VIDEO_UPDATE( superdq ) { - tilemap_draw(bitmap,cliprect,superdq_tilemap,0,0); + superdq_state *state = (superdq_state *)screen->machine->driver_data; + + tilemap_draw(bitmap, cliprect, state->tilemap, 0, 0); return 0; } @@ -102,33 +112,40 @@ static PALETTE_INIT( superdq ) static MACHINE_RESET( superdq ) { - superdq_ld_in_latch = 0; - superdq_ld_out_latch = 0xff; - superdq_color_bank = 0; + superdq_state *state = (superdq_state *)machine->driver_data; + + state->ld_in_latch = 0; + state->ld_out_latch = 0xff; + state->color_bank = 0; } static INTERRUPT_GEN( superdq_vblank ) { + superdq_state *state = (superdq_state *)device->machine->driver_data; + /* status is read when the STATUS line from the laserdisc toggles (600usec after the vblank). We could set up a timer to do that, but this works as well */ - superdq_ld_in_latch = laserdisc_data_r(laserdisc); + state->ld_in_latch = laserdisc_data_r(state->laserdisc); /* command is written when the COMMAND line from the laserdisc toggles (680usec after the vblank). We could set up a timer to do that, but this works as well */ - laserdisc_data_w(laserdisc, superdq_ld_out_latch); + laserdisc_data_w(state->laserdisc, state->ld_out_latch); cpu_set_input_line(device, 0, ASSERT_LINE); } static WRITE8_HANDLER( superdq_videoram_w ) { - space->machine->generic.videoram.u8[offset] = data; - tilemap_mark_tile_dirty(superdq_tilemap,offset); + superdq_state *state = (superdq_state *)space->machine->driver_data; + + state->videoram[offset] = data; + tilemap_mark_tile_dirty(state->tilemap,offset); } static WRITE8_HANDLER( superdq_io_w ) { + superdq_state *state = (superdq_state *)space->machine->driver_data; int i; static const UINT8 black_color_entries[] = {7,15,16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; @@ -138,7 +155,7 @@ static WRITE8_HANDLER( superdq_io_w ) coin_counter_w( space->machine, 0, data & 0x08 ); coin_counter_w( space->machine, 1, data & 0x04 ); - superdq_color_bank = ( data & 2 ) ? 1 : 0; + state->color_bank = ( data & 2 ) ? 1 : 0; for( i = 0; i < ARRAY_LENGTH( black_color_entries ); i++ ) { @@ -158,12 +175,16 @@ static WRITE8_HANDLER( superdq_io_w ) static READ8_HANDLER( superdq_ld_r ) { - return superdq_ld_in_latch; + superdq_state *state = (superdq_state *)space->machine->driver_data; + + return state->ld_in_latch; } static WRITE8_HANDLER( superdq_ld_w ) { - superdq_ld_out_latch = data; + superdq_state *state = (superdq_state *)space->machine->driver_data; + + state->ld_out_latch = data; } @@ -177,7 +198,7 @@ static WRITE8_HANDLER( superdq_ld_w ) static ADDRESS_MAP_START( superdq_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0x3fff) AM_ROM AM_RANGE(0x4000, 0x47ff) AM_RAM - AM_RANGE(0x5c00, 0x5fff) AM_RAM_WRITE(superdq_videoram_w) AM_BASE_GENERIC(videoram) + AM_RANGE(0x5c00, 0x5fff) AM_RAM_WRITE(superdq_videoram_w) AM_BASE_MEMBER(superdq_state,videoram) ADDRESS_MAP_END static ADDRESS_MAP_START( superdq_io, ADDRESS_SPACE_IO, 8 ) @@ -292,12 +313,16 @@ GFXDECODE_END static MACHINE_START( superdq ) { - laserdisc = devtag_get_device(machine, "laserdisc"); + superdq_state *state = (superdq_state *)machine->driver_data; + + state->laserdisc = devtag_get_device(machine, "laserdisc"); } static MACHINE_DRIVER_START( superdq ) + MDRV_DRIVER_DATA( superdq_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", Z80, MASTER_CLOCK/8) MDRV_CPU_PROGRAM_MAP(superdq_map) diff --git a/src/mame/drivers/supertnk.c b/src/mame/drivers/supertnk.c index 999d85a18fc..10486b42156 100644 --- a/src/mame/drivers/supertnk.c +++ b/src/mame/drivers/supertnk.c @@ -105,11 +105,14 @@ CRU lines: every 8 bytes */ #define NUM_PENS (8) - -static UINT8 *supertnk_videoram[3]; -static size_t supertnk_videoram_size; -static UINT8 supertnk_rom_bank; -static UINT8 supertnk_bitplane_select; +typedef struct _supertnk_state supertnk_state; +struct _supertnk_state +{ + UINT8 *videoram[3]; + UINT8 rom_bank; + UINT8 bitplane_select; + pen_t pens[NUM_PENS]; +}; @@ -121,11 +124,12 @@ static UINT8 supertnk_bitplane_select; static WRITE8_HANDLER( supertnk_bankswitch_0_w ) { + supertnk_state *state = (supertnk_state *)space->machine->driver_data; offs_t bank_address; - supertnk_rom_bank = (supertnk_rom_bank & 0x02) | ((data << 0) & 0x01); + state->rom_bank = (state->rom_bank & 0x02) | ((data << 0) & 0x01); - bank_address = 0x10000 + (supertnk_rom_bank * 0x1000); + bank_address = 0x10000 + (state->rom_bank * 0x1000); memory_set_bankptr(space->machine, "bank1", &memory_region(space->machine, "maincpu")[bank_address]); } @@ -133,11 +137,12 @@ static WRITE8_HANDLER( supertnk_bankswitch_0_w ) static WRITE8_HANDLER( supertnk_bankswitch_1_w ) { + supertnk_state *state = (supertnk_state *)space->machine->driver_data; offs_t bank_address; - supertnk_rom_bank = (supertnk_rom_bank & 0x01) | ((data << 1) & 0x02); + state->rom_bank = (state->rom_bank & 0x01) | ((data << 1) & 0x02); - bank_address = 0x10000 + (supertnk_rom_bank * 0x1000); + bank_address = 0x10000 + (state->rom_bank * 0x1000); memory_set_bankptr(space->machine, "bank1", &memory_region(space->machine, "maincpu")[bank_address]); } @@ -172,52 +177,7 @@ static WRITE8_HANDLER( supertnk_interrupt_ack_w ) static VIDEO_START( supertnk ) { - supertnk_videoram[0] = auto_alloc_array(machine, UINT8, supertnk_videoram_size); - supertnk_videoram[1] = auto_alloc_array(machine, UINT8, supertnk_videoram_size); - supertnk_videoram[2] = auto_alloc_array(machine, UINT8, supertnk_videoram_size); -} - - -static WRITE8_HANDLER( supertnk_videoram_w ) -{ - if (supertnk_bitplane_select > 2) - { - supertnk_videoram[0][offset] = 0; - supertnk_videoram[1][offset] = 0; - supertnk_videoram[2][offset] = 0; - } - else - { - supertnk_videoram[supertnk_bitplane_select][offset] = data; - } -} - - -static READ8_HANDLER( supertnk_videoram_r ) -{ - UINT8 ret = 0x00; - - if (supertnk_bitplane_select < 3) - ret = supertnk_videoram[supertnk_bitplane_select][offset]; - - return ret; -} - - -static WRITE8_HANDLER( supertnk_bitplane_select_0_w ) -{ - supertnk_bitplane_select = (supertnk_bitplane_select & 0x02) | ((data << 0) & 0x01); -} - - -static WRITE8_HANDLER( supertnk_bitplane_select_1_w ) -{ - supertnk_bitplane_select = (supertnk_bitplane_select & 0x01) | ((data << 1) & 0x02); -} - - -static void get_pens(running_machine *machine, pen_t *pens) -{ + supertnk_state *state = (supertnk_state *)machine->driver_data; offs_t i; const UINT8 *prom = memory_region(machine, "proms"); @@ -225,33 +185,80 @@ static void get_pens(running_machine *machine, pen_t *pens) { UINT8 data = prom[i]; - pens[i] = MAKE_RGB(pal1bit(data >> 2), pal1bit(data >> 5), pal1bit(data >> 6)); + state->pens[i] = MAKE_RGB(pal1bit(data >> 2), pal1bit(data >> 5), pal1bit(data >> 6)); } + + state->videoram[0] = auto_alloc_array(machine, UINT8, 0x2000); + state->videoram[1] = auto_alloc_array(machine, UINT8, 0x2000); + state->videoram[2] = auto_alloc_array(machine, UINT8, 0x2000); +} + + +static WRITE8_HANDLER( supertnk_videoram_w ) +{ + supertnk_state *state = (supertnk_state *)space->machine->driver_data; + + if (state->bitplane_select > 2) + { + state->videoram[0][offset] = 0; + state->videoram[1][offset] = 0; + state->videoram[2][offset] = 0; + } + else + { + state->videoram[state->bitplane_select][offset] = data; + } +} + + +static READ8_HANDLER( supertnk_videoram_r ) +{ + supertnk_state *state = (supertnk_state *)space->machine->driver_data; + UINT8 ret = 0x00; + + if (state->bitplane_select < 3) + ret = state->videoram[state->bitplane_select][offset]; + + return ret; +} + + +static WRITE8_HANDLER( supertnk_bitplane_select_0_w ) +{ + supertnk_state *state = (supertnk_state *)space->machine->driver_data; + + state->bitplane_select = (state->bitplane_select & 0x02) | ((data << 0) & 0x01); +} + + +static WRITE8_HANDLER( supertnk_bitplane_select_1_w ) +{ + supertnk_state *state = (supertnk_state *)space->machine->driver_data; + + state->bitplane_select = (state->bitplane_select & 0x01) | ((data << 1) & 0x02); } static VIDEO_UPDATE( supertnk ) { - pen_t pens[NUM_PENS]; + supertnk_state *state = (supertnk_state *)screen->machine->driver_data; offs_t offs; - get_pens(screen->machine, pens); - - for (offs = 0; offs < supertnk_videoram_size; offs++) + for (offs = 0; offs < 0x2000; offs++) { int i; UINT8 y = offs >> 5; UINT8 x = offs << 3; - UINT8 data0 = supertnk_videoram[0][offs]; - UINT8 data1 = supertnk_videoram[1][offs]; - UINT8 data2 = supertnk_videoram[2][offs]; + UINT8 data0 = state->videoram[0][offs]; + UINT8 data1 = state->videoram[1][offs]; + UINT8 data2 = state->videoram[2][offs]; for (i = 0; i < 8; i++) { UINT8 color = ((data0 & 0x80) >> 5) | ((data1 & 0x80) >> 6) | ((data2 & 0x80) >> 7); - *BITMAP_ADDR32(bitmap, y, x) = pens[color]; + *BITMAP_ADDR32(bitmap, y, x) = state->pens[color]; data0 = data0 << 1; data1 = data1 << 1; @@ -299,7 +306,7 @@ static ADDRESS_MAP_START( supertnk_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x1efe, 0x1eff) AM_DEVWRITE("aysnd", ay8910_address_data_w) AM_RANGE(0x1efe, 0x1efe) AM_READ_PORT("DSW") AM_RANGE(0x1eff, 0x1eff) AM_READ_PORT("UNK") - AM_RANGE(0x2000, 0x3fff) AM_READWRITE(supertnk_videoram_r, supertnk_videoram_w) AM_SIZE(&supertnk_videoram_size) + AM_RANGE(0x2000, 0x3fff) AM_READWRITE(supertnk_videoram_r, supertnk_videoram_w) ADDRESS_MAP_END @@ -412,6 +419,8 @@ INPUT_PORTS_END static MACHINE_DRIVER_START( supertnk ) + MDRV_DRIVER_DATA( supertnk_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", TMS9980, 2598750) /* ? to which frequency is the 20.79 Mhz crystal mapped down? */ MDRV_CPU_PROGRAM_MAP(supertnk_map) @@ -485,7 +494,7 @@ static DRIVER_INIT( supertnk ) for (offs = 0; offs < len; offs++) { rom[offs] = BITSWAP8(rom[offs],0,1,2,3,4,5,6,7); - }; + } } diff --git a/src/mame/drivers/suprgolf.c b/src/mame/drivers/suprgolf.c index 30c32cd88f3..d14c34d1929 100644 --- a/src/mame/drivers/suprgolf.c +++ b/src/mame/drivers/suprgolf.c @@ -24,19 +24,31 @@ #include "sound/2203intf.h" #include "sound/msm5205.h" -static tilemap_t *suprgolf_tilemap; -static UINT8 *suprgolf_bg_vram; -static UINT16 *suprgolf_bg_fb,*suprgolf_fg_fb; -static int suprgolf_rom_bank; -static UINT8 suprgolf_bg_bank; -static UINT8 suprgolf_vreg_bank; -static UINT8 msm5205next,msm_nmi_mask; -static UINT8 suprgolf_vreg_pen; +typedef struct _suprgolf_state suprgolf_state; +struct _suprgolf_state +{ + tilemap_t *tilemap; + UINT8 *videoram; + UINT8 *paletteram; + UINT8 *bg_vram; + UINT16 *bg_fb; + UINT16 *fg_fb; + int rom_bank; + UINT8 bg_bank; + UINT8 vreg_bank; + UINT8 msm5205next; + UINT8 msm_nmi_mask; + UINT8 vreg_pen; + UINT8 palette_switch; + UINT8 bg_vreg_test; + int toggle; +}; static TILE_GET_INFO( get_tile_info ) { - int code = machine->generic.videoram.u8[tile_index*2]+256*(machine->generic.videoram.u8[tile_index*2+1]); - int color = machine->generic.videoram.u8[tile_index*2+0x800] & 0x7f; + suprgolf_state *state = (suprgolf_state *)machine->driver_data; + int code = state->videoram[tile_index*2]+256*(state->videoram[tile_index*2+1]); + int color = state->videoram[tile_index*2+0x800] & 0x7f; SET_TILE_INFO( 0, @@ -47,17 +59,20 @@ static TILE_GET_INFO( get_tile_info ) static VIDEO_START( suprgolf ) { - suprgolf_tilemap = tilemap_create( machine, get_tile_info,tilemap_scan_rows,8,8,32,32 ); - machine->generic.paletteram.u8 = auto_alloc_array(machine, UINT8, 0x1000); - suprgolf_bg_vram = auto_alloc_array(machine, UINT8, 0x2000*0x20); - suprgolf_bg_fb = auto_alloc_array(machine, UINT16, 0x2000*0x20); - suprgolf_fg_fb = auto_alloc_array(machine, UINT16, 0x2000*0x20); + suprgolf_state *state = (suprgolf_state *)machine->driver_data; - tilemap_set_transparent_pen(suprgolf_tilemap,15); + state->tilemap = tilemap_create( machine, get_tile_info,tilemap_scan_rows,8,8,32,32 ); + state->paletteram = auto_alloc_array(machine, UINT8, 0x1000); + state->bg_vram = auto_alloc_array(machine, UINT8, 0x2000*0x20); + state->bg_fb = auto_alloc_array(machine, UINT16, 0x2000*0x20); + state->fg_fb = auto_alloc_array(machine, UINT16, 0x2000*0x20); + + tilemap_set_transparent_pen(state->tilemap,15); } static VIDEO_UPDATE( suprgolf ) { + suprgolf_state *state = (suprgolf_state *)screen->machine->driver_data; int x,y,count,color; bitmap_fill(bitmap, cliprect, get_black_pen(screen->machine)); @@ -68,7 +83,7 @@ static VIDEO_UPDATE( suprgolf ) { for(x=0;x<512;x++) { - color = suprgolf_bg_fb[count]; + color = state->bg_fb[count]; if(x <= cliprect->max_x && y <= cliprect->max_y) *BITMAP_ADDR16(bitmap, y, x) = screen->machine->pens[(color & 0x7ff)]; @@ -85,9 +100,9 @@ static VIDEO_UPDATE( suprgolf ) { for(x=0;x<512;x++) { - color = suprgolf_fg_fb[count]; + color = state->fg_fb[count]; - if(((suprgolf_fg_fb[count] & 0x0f) != 0x0f) && (x <= cliprect->max_x && y <= cliprect->max_y)) + if(((state->fg_fb[count] & 0x0f) != 0x0f) && (x <= cliprect->max_x && y <= cliprect->max_y)) *BITMAP_ADDR16(bitmap, y, x) = screen->machine->pens[(color & 0x7ff)]; count++; @@ -95,29 +110,31 @@ static VIDEO_UPDATE( suprgolf ) } } - tilemap_draw(bitmap,cliprect,suprgolf_tilemap,0,0); + tilemap_draw(bitmap,cliprect,state->tilemap,0,0); return 0; } -static UINT8 palette_switch; - static READ8_HANDLER( suprgolf_videoram_r ) { - if(palette_switch) - return space->machine->generic.paletteram.u8[offset]; + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + + if (state->palette_switch) + return state->paletteram[offset]; else - return space->machine->generic.videoram.u8[offset]; + return state->videoram[offset]; } static WRITE8_HANDLER( suprgolf_videoram_w ) { - if(palette_switch) + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + + if(state->palette_switch) { int r,g,b,datax; - space->machine->generic.paletteram.u8[offset] = data; + state->paletteram[offset] = data; offset>>=1; - datax=space->machine->generic.paletteram.u8[offset*2]+256*space->machine->generic.paletteram.u8[offset*2+1]; + datax = state->paletteram[offset*2] + 256*state->paletteram[offset*2 + 1]; b = (datax & 0x8000) ? 0 : ((datax)&0x001f)>>0; g = (datax & 0x8000) ? 0 : ((datax)&0x03e0)>>5; @@ -127,26 +144,28 @@ static WRITE8_HANDLER( suprgolf_videoram_w ) } else { - space->machine->generic.videoram.u8[offset] = data; - tilemap_mark_tile_dirty(suprgolf_tilemap, (offset & 0x7fe) >> 1); + state->videoram[offset] = data; + tilemap_mark_tile_dirty(state->tilemap, (offset & 0x7fe) >> 1); } } static READ8_HANDLER( suprgolf_vregs_r ) { - return suprgolf_vreg_bank; -} + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; -static UINT8 suprgolf_bg_vreg_test; + return state->vreg_bank; +} static WRITE8_HANDLER( suprgolf_vregs_w ) { - //bits 0,1,2 and probably 3 controls the background vram banking - suprgolf_vreg_bank = data; - palette_switch = (data & 0x80); - suprgolf_bg_bank = (data & 0x1f); + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; - suprgolf_bg_vreg_test = data & 0x20; + //bits 0,1,2 and probably 3 controls the background vram banking + state->vreg_bank = data; + state->palette_switch = (data & 0x80); + state->bg_bank = (data & 0x1f); + + state->bg_vreg_test = data & 0x20; //if(data & 0x60) // printf("Video regs with data %02x activated\n",data); @@ -154,13 +173,16 @@ static WRITE8_HANDLER( suprgolf_vregs_w ) static READ8_HANDLER( suprgolf_bg_vram_r ) { - return suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000]; + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + + return state->bg_vram[offset+state->bg_bank*0x2000]; } static WRITE8_HANDLER( suprgolf_bg_vram_w ) { - static UINT8 hi_nibble,lo_nibble; - static UINT8 hi_dirty_dot,lo_dirty_dot; // helpers + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + UINT8 hi_nibble,lo_nibble; + UINT8 hi_dirty_dot,lo_dirty_dot; // helpers hi_nibble = data & 0xf0; lo_nibble = data & 0x0f; @@ -169,66 +191,73 @@ static WRITE8_HANDLER( suprgolf_bg_vram_w ) if(hi_nibble == 0xf0) { - hi_nibble = suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] & 0xf0; - if(!(suprgolf_vreg_pen & 0x80) && (!(suprgolf_bg_bank & 0x10))) + hi_nibble = state->bg_vram[offset+state->bg_bank*0x2000] & 0xf0; + if(!(state->vreg_pen & 0x80) && (!(state->bg_bank & 0x10))) hi_dirty_dot = 0; } if(lo_nibble == 0x0f) { - lo_nibble = suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] & 0x0f; - if(!(suprgolf_vreg_pen & 0x80) && (!(suprgolf_bg_bank & 0x10))) + lo_nibble = state->bg_vram[offset+state->bg_bank*0x2000] & 0x0f; + if(!(state->vreg_pen & 0x80) && (!(state->bg_bank & 0x10))) lo_dirty_dot = 0; } - if(suprgolf_vreg_pen & 0x80 || suprgolf_bg_bank & 0x10) - suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] = data; + if(state->vreg_pen & 0x80 || state->bg_bank & 0x10) + state->bg_vram[offset+state->bg_bank*0x2000] = data; else - suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] = hi_nibble|lo_nibble; + state->bg_vram[offset+state->bg_bank*0x2000] = hi_nibble|lo_nibble; - if(suprgolf_bg_bank & 0x10) + if(state->bg_bank & 0x10) { if(hi_dirty_dot) - suprgolf_fg_fb[(offset+(suprgolf_bg_bank & 0x0f)*0x2000)*2+1] = (suprgolf_vreg_pen & 0x7f)<<4 | ((suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] & 0xf0)>>4); + state->fg_fb[(offset+(state->bg_bank & 0x0f)*0x2000)*2+1] = (state->vreg_pen & 0x7f)<<4 | ((state->bg_vram[offset+state->bg_bank*0x2000] & 0xf0)>>4); if(lo_dirty_dot) - suprgolf_fg_fb[(offset+(suprgolf_bg_bank & 0x0f)*0x2000)*2+0] = (suprgolf_vreg_pen & 0x7f)<<4 | ((suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] & 0x0f)>>0); + state->fg_fb[(offset+(state->bg_bank & 0x0f)*0x2000)*2+0] = (state->vreg_pen & 0x7f)<<4 | ((state->bg_vram[offset+state->bg_bank*0x2000] & 0x0f)>>0); } else { if(hi_dirty_dot) - suprgolf_bg_fb[(offset+(suprgolf_bg_bank & 0x0f)*0x2000)*2+1] = (suprgolf_vreg_pen & 0x7f)<<4 | ((suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] & 0xf0)>>4); + state->bg_fb[(offset+(state->bg_bank & 0x0f)*0x2000)*2+1] = (state->vreg_pen & 0x7f)<<4 | ((state->bg_vram[offset+state->bg_bank*0x2000] & 0xf0)>>4); if(lo_dirty_dot) - suprgolf_bg_fb[(offset+(suprgolf_bg_bank & 0x0f)*0x2000)*2+0] = (suprgolf_vreg_pen & 0x7f)<<4 | ((suprgolf_bg_vram[offset+suprgolf_bg_bank*0x2000] & 0x0f)>>0); + state->bg_fb[(offset+(state->bg_bank & 0x0f)*0x2000)*2+0] = (state->vreg_pen & 0x7f)<<4 | ((state->bg_vram[offset+state->bg_bank*0x2000] & 0x0f)>>0); } } static WRITE8_HANDLER( suprgolf_pen_w ) { - suprgolf_vreg_pen = data; + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + + state->vreg_pen = data; } static WRITE8_HANDLER( adpcm_data_w ) { - msm5205next = data; + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + + state->msm5205next = data; } static READ8_HANDLER( rom_bank_select_r ) { - return suprgolf_rom_bank; + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; + + return state->rom_bank; } static WRITE8_HANDLER( rom_bank_select_w ) { + suprgolf_state *state = (suprgolf_state *)space->machine->driver_data; UINT8 *region_base = memory_region(space->machine, "user1"); - suprgolf_rom_bank = data; + state->rom_bank = data; //popmessage("%08x %02x",((data & 0x3f) * 0x4000),data); mame_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,cpu_get_previouspc(space->cpu)); memory_set_bankptr(space->machine, "bank2", region_base + (data&0x3f ) * 0x4000); - msm_nmi_mask = data & 0x40; + state->msm_nmi_mask = data & 0x40; flip_screen_set(space->machine, data & 0x80); } @@ -245,7 +274,7 @@ static WRITE8_HANDLER( rom2_bank_select_w ) static READ8_HANDLER( pedal_extra_bits_r ) { - static UINT8 p1_sht_sw,p2_sht_sw; + UINT8 p1_sht_sw,p2_sht_sw; p1_sht_sw = (input_port_read(space->machine, "P1_RELEASE") & 0x80)>>7; p2_sht_sw = (input_port_read(space->machine, "P2_RELEASE") & 0x80)>>6; @@ -269,7 +298,7 @@ static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x4000, 0x4000) AM_WRITE( rom2_bank_select_w ) AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2") AM_RANGE(0xc000, 0xdfff) AM_READWRITE( suprgolf_bg_vram_r, suprgolf_bg_vram_w ) // banked background vram - AM_RANGE(0xe000, 0xefff) AM_READWRITE( suprgolf_videoram_r, suprgolf_videoram_w ) AM_BASE_GENERIC(videoram) //foreground vram + paletteram + AM_RANGE(0xe000, 0xefff) AM_READWRITE( suprgolf_videoram_r, suprgolf_videoram_w ) AM_BASE_MEMBER(suprgolf_state,videoram) //foreground vram + paletteram AM_RANGE(0xf000, 0xf000) AM_WRITE( suprgolf_pen_w ) AM_RANGE(0xf800, 0xffff) AM_RAM ADDRESS_MAP_END @@ -404,19 +433,19 @@ static const ym2203_interface ym2203_config = static void adpcm_int(running_device *device) { - static int toggle = 0; + suprgolf_state *state = (suprgolf_state *)device->machine->driver_data; { msm5205_reset_w(device,0); - toggle ^= 1; - if(toggle) + state->toggle ^= 1; + if(state->toggle) { - msm5205_data_w(device, (msm5205next & 0xf0) >> 4); - if(msm_nmi_mask) { cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE); } + msm5205_data_w(device, (state->msm5205next & 0xf0) >> 4); + if(state->msm_nmi_mask) { cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE); } } else { - msm5205_data_w(device, (msm5205next & 0x0f) >> 0); + msm5205_data_w(device, (state->msm5205next & 0x0f) >> 0); } } } @@ -429,13 +458,13 @@ static const msm5205_interface msm5205_config = static const gfx_layout gfxlayout = { - 8,8, - RGN_FRAC(1,1), - 4, - { 0, 1, 2, 3 }, - { 1*4, 0*4, 3*4, 2*4, 5*4, 4*4, 7*4, 6*4 }, - { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 }, - 8*8*4 + 8,8, + RGN_FRAC(1,1), + 4, + { 0, 1, 2, 3 }, + { 1*4, 0*4, 3*4, 2*4, 5*4, 4*4, 7*4, 6*4 }, + { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 }, + 8*8*4 }; static GFXDECODE_START( suprgolf ) @@ -444,10 +473,15 @@ GFXDECODE_END static MACHINE_RESET( suprgolf ) { - msm_nmi_mask = 0; + suprgolf_state *state = (suprgolf_state *)machine->driver_data; + + state->msm_nmi_mask = 0; } static MACHINE_DRIVER_START( suprgolf ) + + MDRV_DRIVER_DATA( suprgolf_state ) + /* basic machine hardware */ MDRV_CPU_ADD("maincpu", Z80,4000000) /* guess */ MDRV_CPU_PROGRAM_MAP(main_map) diff --git a/src/osd/windows/winmain.c b/src/osd/windows/winmain.c index 0e7684ed4e2..15fb9f6cb62 100644 --- a/src/osd/windows/winmain.c +++ b/src/osd/windows/winmain.c @@ -94,7 +94,7 @@ typedef BOOL (WINAPI *av_revert_mm_thread_characteristics_ptr)(HANDLE AvrtHandle // from dbghelp.dll typedef PIMAGE_NT_HEADERS (WINAPI *image_nt_header_ptr)(PVOID ImageBase); typedef BOOL (WINAPI *stack_walk_64_ptr)(DWORD MachineType, HANDLE hProcess, HANDLE hThread, LPSTACKFRAME64 StackFrame, PVOID ContextRecord, PREAD_PROCESS_MEMORY_ROUTINE64 ReadMemoryRoutine, PFUNCTION_TABLE_ACCESS_ROUTINE64 FunctionTableAccessRoutine, PGET_MODULE_BASE_ROUTINE64 GetModuleBaseRoutine, PTRANSLATE_ADDRESS_ROUTINE64 TranslateAddress); -typedef BOOL (WINAPI *sym_initialize_ptr)(HANDLE hProcess, PCTSTR UserSearchPath, BOOL fInvadeProcess); +typedef BOOL (WINAPI *sym_initialize_ptr)(HANDLE hProcess, LPCTSTR UserSearchPath, BOOL fInvadeProcess); typedef PVOID (WINAPI *sym_function_table_access_64_ptr)(HANDLE hProcess, DWORD64 AddrBase); typedef DWORD64 (WINAPI *sym_get_module_base_64_ptr)(HANDLE hProcess, DWORD64 dwAddr); typedef BOOL (WINAPI *sym_from_addr_ptr)(HANDLE hProcess, DWORD64 Address, PDWORD64 Displacement, PSYMBOL_INFO Symbol);