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jubilee.c: Switched to new TMS9980 implementation and tried to bring the
driver in better shape. [Michael Zapf]
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@ -82,16 +82,10 @@
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*******************************************************************************/
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#define MODERN 0
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#define MASTER_CLOCK XTAL_8MHz /* guess */
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#include "emu.h"
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#if MODERN
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#include "cpu/tms9900/tms9980a.h"
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#else
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#include "cpu/tms9900/tms9900l.h"
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#endif
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#include "video/mc6845.h"
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@ -107,6 +101,7 @@ public:
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tilemap_t *m_bg_tilemap;
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DECLARE_WRITE8_MEMBER(jubileep_videoram_w);
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DECLARE_READ8_MEMBER(unk_r);
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DECLARE_WRITE8_MEMBER(unk_w);
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TILE_GET_INFO_MEMBER(get_bg_tile_info);
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virtual void video_start();
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virtual void palette_init();
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@ -161,13 +156,7 @@ void jubilee_state::palette_init()
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INTERRUPT_GEN_MEMBER(jubilee_state::jubileep_interrupt)
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{
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/* doesn't seems to work properly. need to set level1 interrupts */
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#if MODERN
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m_maincpu->set_input_line(INT_9980A_LEVEL1, ASSERT_LINE);
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m_maincpu->set_input_line(INT_9980A_LEVEL1, CLEAR_LINE);
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#else
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device.execute().set_input_line_and_vector(0, ASSERT_LINE, 3);//2=nmi 3,4,5,6
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#endif
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}
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@ -191,17 +180,41 @@ ADDRESS_MAP_END
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*/
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/*
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TODO: I/O lines handling. This is still work to be done; someone needs to
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check the schematics. Here, we need to deliver some reasonable return values
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instead of the 0. Returning a random number will create a nondeterministic
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behavior at best.
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*/
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READ8_MEMBER(jubilee_state::unk_r)
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{
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return (machine().rand() & 0xff);
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// return (machine().rand() & 0xff);
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logerror("CRU read from address %04x\n", offset<<4);
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return 0;
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}
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WRITE8_MEMBER(jubilee_state::unk_w)
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{
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// return (machine().rand() & 0xff);
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logerror("CRU write to address %04x: %d\n", offset<<1, data & 1);
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// In particular, the interrupt from above must be cleared. We assume that
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// this is done by one of the output lines, and from the 32 lines that are
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// set right after an interrupt is serviced, all are set to 0, and only one
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// is set to one. Maybe this one clears the interrupt.
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// TODO: Check the schematics.
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if (((offset<<1)==0x0ce2)&&(data==1))
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{
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m_maincpu->set_input_line(INT_9980A_LEVEL1, CLEAR_LINE);
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}
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}
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static ADDRESS_MAP_START( jubileep_cru_map, AS_IO, 8, jubilee_state )
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// AM_RANGE(0x0000, 0xffff) AM_READ(unk_r)
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AM_RANGE(0x0000, 0x01ff) AM_READ(unk_r)
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AM_RANGE(0x0000, 0x0fff) AM_WRITE(unk_w)
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// AM_RANGE(0x00, 0x00) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
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// AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
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AM_RANGE(0xc8, 0xc8) AM_READ(unk_r)
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// AM_RANGE(0xc8, 0xc8) AM_READ(unk_r)
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ADDRESS_MAP_END
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/* I/O byte R/W
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@ -418,7 +431,6 @@ static MC6845_INTERFACE( mc6845_intf )
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NULL /* update address callback */
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};
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#if MODERN
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static TMS9980A_CONFIG( cpuconf )
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{
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DEVCB_NULL,
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@ -427,7 +439,6 @@ static TMS9980A_CONFIG( cpuconf )
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DEVCB_NULL, // Hold acknowledge
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DEVCB_NULL // DBIN
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};
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#endif
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/*************************
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* Machine Drivers *
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@ -436,13 +447,7 @@ static TMS9980A_CONFIG( cpuconf )
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static MACHINE_CONFIG_START( jubileep, jubilee_state )
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/* basic machine hardware */
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#if MODERN
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MCFG_TMS99xx_ADD("maincpu", TMS9980A, MASTER_CLOCK/2, jubileep_map, jubileep_cru_map, cpuconf)
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#else
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MCFG_CPU_ADD("maincpu", TMS9980L, MASTER_CLOCK/2) /* guess */
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MCFG_CPU_PROGRAM_MAP(jubileep_map)
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MCFG_CPU_IO_MAP(jubileep_cru_map)
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#endif
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MCFG_CPU_VBLANK_INT_DRIVER("screen", jubilee_state, jubileep_interrupt)
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/* video hardware */
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