Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-26 18:23:08 +03:00
Code Issues Actions 29 Packages Projects Releases Wiki Activity

nec.c: Modernized cpu core (bw)

Browse Source
This commit is contained in:
Wilbert Pol 2013-10-07 18:35:50 +00:00
parent cd3c763e6e
commit ffb7377f8f
23 changed files with 2664 additions and 2690 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitattributes vendored
View File

@ -715,6 +715,7 @@ src/emu/cpu/nec/necmacro.h svneol=native#text/plain
src/emu/cpu/nec/necmodrm.h svneol=native#text/plain
src/emu/cpu/nec/necpriv.h svneol=native#text/plain
src/emu/cpu/nec/v25.c svneol=native#text/plain
src/emu/cpu/nec/v25.h svneol=native#text/plain
src/emu/cpu/nec/v25instr.c svneol=native#text/plain
src/emu/cpu/nec/v25instr.h svneol=native#text/plain
src/emu/cpu/nec/v25priv.h svneol=native#text/plain

593
src/emu/cpu/nec/nec.c
View File

@ -114,25 +114,59 @@ typedef UINT32 DWORD;
#include "nec.h"
#include "necpriv.h"
extern CPU_DISASSEMBLE( nec );
const device_type V20 = &device_creator<v20_device>;
const device_type V30 = &device_creator<v30_device>;
const device_type V33 = &device_creator<v33_device>;
INLINE nec_state_t *get_safe_token(device_t *device)
nec_common_device::nec_common_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, bool is_16bit, offs_t fetch_xor, UINT8 prefetch_size, UINT8 prefetch_cycles, UINT32 chip_type)
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
, m_program_config("program", ENDIANNESS_LITTLE, is_16bit ? 16 : 8, 20, 0)
, m_io_config("io", ENDIANNESS_LITTLE, is_16bit ? 16 : 8, 16, 0)
, m_fetch_xor(fetch_xor)
, m_prefetch_size(prefetch_size)
, m_prefetch_cycles(prefetch_cycles)
, m_chip_type(chip_type)
{
assert(device != NULL);
assert(device->type() == V20 ||
device->type() == V30 ||
device->type() == V33);
return (nec_state_t *)downcast<legacy_cpu_device *>(device)->token();
}
INLINE void prefetch(nec_state_t *nec_state)
v20_device::v20_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: nec_common_device(mconfig, V20, "V20", tag, owner, clock, "v20", false, 0, 4, 4, V20_TYPE)
{
nec_state->prefetch_count--;
}
static void do_prefetch(nec_state_t *nec_state, int previous_ICount)
v30_device::v30_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: nec_common_device(mconfig, V30, "V30", tag, owner, clock, "v30", true, BYTE_XOR_LE(0), 6, 2, V30_TYPE)
{
int diff = previous_ICount - (int) nec_state->icount;
}
/* FIXME: Need information about prefetch size and cycles for V33.
* complete guess below, nbbatman will not work
* properly without. */
v33_device::v33_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: nec_common_device(mconfig, V33, "V33", tag, owner, clock, "v33", true, BYTE_XOR_LE(0), 6, 1, V33_TYPE)
{
}
offs_t nec_common_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
extern CPU_DISASSEMBLE( nec );
return CPU_DISASSEMBLE_NAME(nec)(this, buffer, pc, oprom, opram, options);
}
void nec_common_device::prefetch()
{
m_prefetch_count--;
}
void nec_common_device::do_prefetch(int previous_ICount)
{
int diff = previous_ICount - (int) m_icount;
/* The implementation is not accurate, but comes close.
* It does not respect that the V30 will fetch two bytes
@ -140,37 +174,37 @@ static void do_prefetch(nec_state_t *nec_state, int previous_ICount)
* of 4. There are however only very few sources publicly
* available and they are vague.
*/
while (nec_state->prefetch_count<0)
while (m_prefetch_count<0)
{
nec_state->prefetch_count++;
if (diff>nec_state->prefetch_cycles)
diff -= nec_state->prefetch_cycles;
m_prefetch_count++;
if (diff>m_prefetch_cycles)
diff -= m_prefetch_cycles;
else
nec_state->icount -= nec_state->prefetch_cycles;
m_icount -= m_prefetch_cycles;
}
if (nec_state->prefetch_reset)
if (m_prefetch_reset)
{
nec_state->prefetch_count = 0;
nec_state->prefetch_reset = 0;
m_prefetch_count = 0;
m_prefetch_reset = 0;
return;
}
while (diff>=nec_state->prefetch_cycles && nec_state->prefetch_count < nec_state->prefetch_size)
while (diff>=m_prefetch_cycles && m_prefetch_count < m_prefetch_size)
{
diff -= nec_state->prefetch_cycles;
nec_state->prefetch_count++;
diff -= m_prefetch_cycles;
m_prefetch_count++;
}
}
INLINE UINT8 fetch(nec_state_t *nec_state)
UINT8 nec_common_device::fetch()
{
prefetch(nec_state);
return nec_state->direct->read_raw_byte((Sreg(PS)<<4)+nec_state->ip++, nec_state->fetch_xor);
prefetch();
return m_direct->read_raw_byte((Sreg(PS)<<4)+m_ip++, m_fetch_xor);
}
INLINE UINT16 fetchword(nec_state_t *nec_state)
UINT16 nec_common_device::fetchword()
{
UINT16 r = FETCH();
r |= (FETCH()<<8);
@ -184,38 +218,36 @@ INLINE UINT16 fetchword(nec_state_t *nec_state)
static UINT8 parity_table[256];
static UINT8 fetchop(nec_state_t *nec_state)
UINT8 nec_common_device::fetchop()
{
prefetch(nec_state);
return nec_state->direct->read_decrypted_byte(( Sreg(PS)<<4)+nec_state->ip++, nec_state->fetch_xor);
prefetch();
return m_direct->read_decrypted_byte(( Sreg(PS)<<4)+m_ip++, m_fetch_xor);
}
/***************************************************************************/
static CPU_RESET( nec )
void nec_common_device::device_reset()
{
nec_state_t *nec_state = get_safe_token(device);
memset( &m_regs.w, 0, sizeof(m_regs.w));
memset( &nec_state->regs.w, 0, sizeof(nec_state->regs.w));
nec_state->ip = 0;
nec_state->TF = 0;
nec_state->IF = 0;
nec_state->DF = 0;
nec_state->MF = 1; // brkem should set to 0 when implemented
nec_state->SignVal = 0;
nec_state->AuxVal = 0;
nec_state->OverVal = 0;
nec_state->ZeroVal = 1;
nec_state->CarryVal = 0;
nec_state->ParityVal = 1;
nec_state->pending_irq = 0;
nec_state->nmi_state = 0;
nec_state->irq_state = 0;
nec_state->poll_state = 1;
nec_state->halted = 0;
m_ip = 0;
m_TF = 0;
m_IF = 0;
m_DF = 0;
m_MF = 1; // brkem should set to 0 when implemented
m_SignVal = 0;
m_AuxVal = 0;
m_OverVal = 0;
m_ZeroVal = 1;
m_CarryVal = 0;
m_ParityVal = 1;
m_pending_irq = 0;
m_nmi_state = 0;
m_irq_state = 0;
m_poll_state = 1;
m_halted = 0;
Sreg(PS) = 0xffff;
Sreg(SS) = 0;
@ -225,50 +257,47 @@ static CPU_RESET( nec )
CHANGE_PC;
}
static CPU_EXIT( nec )
{
}
static void nec_interrupt(nec_state_t *nec_state, unsigned int_num, INTSOURCES source)
void nec_common_device::nec_interrupt(unsigned int_num, int/*INTSOURCES*/ source)
{
UINT32 dest_seg, dest_off;
i_pushf(nec_state);
nec_state->TF = nec_state->IF = 0;
i_pushf();
m_TF = m_IF = 0;
if (source == INT_IRQ) /* get vector */
int_num = (*nec_state->irq_callback)(nec_state->device, 0);
int_num = (standard_irq_callback)(0);
dest_off = read_mem_word(int_num*4);
dest_seg = read_mem_word(int_num*4+2);
PUSH(Sreg(PS));
PUSH(nec_state->ip);
nec_state->ip = (WORD)dest_off;
PUSH(m_ip);
m_ip = (WORD)dest_off;
Sreg(PS) = (WORD)dest_seg;
CHANGE_PC;
}
static void nec_trap(nec_state_t *nec_state)
void nec_common_device::nec_trap()
{
nec_instruction[fetchop(nec_state)](nec_state);
nec_interrupt(nec_state, NEC_TRAP_VECTOR, BRK);
(this->*s_nec_instruction[fetchop()])();
nec_interrupt(NEC_TRAP_VECTOR, BRK);
}
static void external_int(nec_state_t *nec_state)
void nec_common_device::external_int()
{
if (nec_state->pending_irq & NMI_IRQ)
if (m_pending_irq & NMI_IRQ)
{
nec_interrupt(nec_state, NEC_NMI_VECTOR, NMI_IRQ);
nec_state->pending_irq &= ~NMI_IRQ;
nec_interrupt(NEC_NMI_VECTOR, NMI_IRQ);
m_pending_irq &= ~NMI_IRQ;
}
else if (nec_state->pending_irq)
else if (m_pending_irq)
{
/* the actual vector is retrieved after pushing flags */
/* and clearing the IF */
nec_interrupt(nec_state, (UINT32)-1, INT_IRQ);
nec_state->irq_state = CLEAR_LINE;
nec_state->pending_irq &= ~INT_IRQ;
nec_interrupt((UINT32)-1, INT_IRQ);
m_irq_state = CLEAR_LINE;
m_pending_irq &= ~INT_IRQ;
}
}
@ -280,39 +309,37 @@ static void external_int(nec_state_t *nec_state)
/*****************************************************************************/
static void set_irq_line(nec_state_t *nec_state, int irqline, int state)
void nec_common_device::execute_set_input(int irqline, int state)
{
switch (irqline)
{
case 0:
nec_state->irq_state = state;
m_irq_state = state;
if (state == CLEAR_LINE)
nec_state->pending_irq &= ~INT_IRQ;
m_pending_irq &= ~INT_IRQ;
else
{
nec_state->pending_irq |= INT_IRQ;
nec_state->halted = 0;
m_pending_irq |= INT_IRQ;
m_halted = 0;
}
break;
case INPUT_LINE_NMI:
if (nec_state->nmi_state == state) return;
nec_state->nmi_state = state;
if (m_nmi_state == state) return;
m_nmi_state = state;
if (state != CLEAR_LINE)
{
nec_state->pending_irq |= NMI_IRQ;
nec_state->halted = 0;
m_pending_irq |= NMI_IRQ;
m_halted = 0;
}
break;
case NEC_INPUT_LINE_POLL:
nec_state->poll_state = state;
m_poll_state = state;
break;
}
}
static void nec_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback)
void nec_common_device::device_start()
{
nec_state_t *nec_state = get_safe_token(device);
unsigned int i, j, c;
static const WREGS wreg_name[8]={ AW, CW, DW, BW, SP, BP, IX, IY };
@ -337,246 +364,70 @@ static void nec_init(legacy_cpu_device *device, device_irq_acknowledge_callback
Mod_RM.RM.b[i] = breg_name[i & 7];
}
memset(nec_state, 0, sizeof(*nec_state));
m_no_interrupt = 0;
m_prefetch_count = 0;
m_prefetch_reset = 0;
m_prefix_base = 0;
m_seg_prefix = 0;
m_EA = 0;
m_EO = 0;
m_E16 = 0;
device->save_item(NAME(nec_state->regs.w));
device->save_item(NAME(nec_state->sregs));
save_item(NAME(m_regs.w));
save_item(NAME(m_sregs));
device->save_item(NAME(nec_state->ip));
device->save_item(NAME(nec_state->TF));
device->save_item(NAME(nec_state->IF));
device->save_item(NAME(nec_state->DF));
device->save_item(NAME(nec_state->MF));
device->save_item(NAME(nec_state->SignVal));
device->save_item(NAME(nec_state->AuxVal));
device->save_item(NAME(nec_state->OverVal));
device->save_item(NAME(nec_state->ZeroVal));
device->save_item(NAME(nec_state->CarryVal));
device->save_item(NAME(nec_state->ParityVal));
device->save_item(NAME(nec_state->pending_irq));
device->save_item(NAME(nec_state->nmi_state));
device->save_item(NAME(nec_state->irq_state));
device->save_item(NAME(nec_state->poll_state));
device->save_item(NAME(nec_state->halted));
save_item(NAME(m_ip));
save_item(NAME(m_TF));
save_item(NAME(m_IF));
save_item(NAME(m_DF));
save_item(NAME(m_MF));
save_item(NAME(m_SignVal));
save_item(NAME(m_AuxVal));
save_item(NAME(m_OverVal));
save_item(NAME(m_ZeroVal));
save_item(NAME(m_CarryVal));
save_item(NAME(m_ParityVal));
save_item(NAME(m_pending_irq));
save_item(NAME(m_nmi_state));
save_item(NAME(m_irq_state));
save_item(NAME(m_poll_state));
save_item(NAME(m_halted));
nec_state->irq_callback = irqcallback;
nec_state->device = device;
nec_state->program = &device->space(AS_PROGRAM);
nec_state->direct = &nec_state->program->direct();
nec_state->io = &device->space(AS_IO);
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_io = &space(AS_IO);
state_add( NEC_PC, "PC", m_debugger_temp).callimport().callexport().formatstr("%5X");
state_add( NEC_IP, "IP", m_ip).formatstr("%4X");
state_add( NEC_SP, "SP", Wreg(SP)).formatstr("%4X");
state_add( NEC_FLAGS, "F", m_debugger_temp).callimport().callexport().formatstr("%4X");
state_add( NEC_AW, "AW", Wreg(AW)).formatstr("%4X");
state_add( NEC_CW, "CW", Wreg(CW)).formatstr("%4X");
state_add( NEC_DW, "DW", Wreg(DW)).formatstr("%4X");
state_add( NEC_BW, "BW", Wreg(BW)).formatstr("%4X");
state_add( NEC_BP, "BP", Wreg(BP)).formatstr("%4X");
state_add( NEC_IX, "IX", Wreg(IX)).formatstr("%4X");
state_add( NEC_IY, "IY", Wreg(IY)).formatstr("%4X");
state_add( NEC_ES, "DS1", Sreg(DS1)).formatstr("%4X");
state_add( NEC_CS, "PS", Sreg(PS)).formatstr("%4X");
state_add( NEC_SS, "SS", Sreg(SS)).formatstr("%4X");
state_add( NEC_DS, "DS0", Sreg(DS0)).formatstr("%4X");
state_add( STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow();
state_add( STATE_GENSP, "GENSP", m_debugger_temp).callimport().callexport().noshow();
state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).formatstr("%16s").noshow();
m_icountptr = &m_icount;
}
static CPU_EXECUTE( necv )
void nec_common_device::state_string_export(const device_state_entry &entry, astring &string)
{
nec_state_t *nec_state = get_safe_token(device);
int prev_ICount;
UINT16 flags = CompressFlags();
if (nec_state->halted)
switch (entry.index())
{
nec_state->icount = 0;
debugger_instruction_hook(device, (Sreg(PS)<<4) + nec_state->ip);
return;
}
while(nec_state->icount>0) {
/* Dispatch IRQ */
if (nec_state->pending_irq && nec_state->no_interrupt==0)
{
if (nec_state->pending_irq & NMI_IRQ)
external_int(nec_state);
else if (nec_state->IF)
external_int(nec_state);
}
/* No interrupt allowed between last instruction and this one */
if (nec_state->no_interrupt)
nec_state->no_interrupt--;
debugger_instruction_hook(device, (Sreg(PS)<<4) + nec_state->ip);
prev_ICount = nec_state->icount;
nec_instruction[fetchop(nec_state)](nec_state);
do_prefetch(nec_state, prev_ICount);
}
}
/* Wrappers for the different CPU types */
static CPU_INIT( v20 )
{
nec_state_t *nec_state = get_safe_token(device);
nec_init(device, irqcallback);
nec_state->fetch_xor = 0;
nec_state->chip_type=V20_TYPE;
nec_state->prefetch_size = 4; /* 3 words */
nec_state->prefetch_cycles = 4; /* four cycles per byte */
}
static CPU_INIT( v30 )
{
nec_state_t *nec_state = get_safe_token(device);
nec_init(device, irqcallback);
nec_state->fetch_xor = BYTE_XOR_LE(0);
nec_state->chip_type=V30_TYPE;
nec_state->prefetch_size = 6; /* 3 words */
nec_state->prefetch_cycles = 2; /* two cycles per byte / four per word */
}
static CPU_INIT( v33 )
{
nec_state_t *nec_state = get_safe_token(device);
nec_init(device, irqcallback);
nec_state->chip_type=V33_TYPE;
nec_state->prefetch_size = 6;
/* FIXME: Need information about prefetch size and cycles for V33.
* complete guess below, nbbatman will not work
* properly without. */
nec_state->prefetch_cycles = 1; /* two cycles per byte / four per word */
nec_state->fetch_xor = BYTE_XOR_LE(0);
}
/**************************************************************************
* Generic set_info
**************************************************************************/
static CPU_SET_INFO( nec )
{
nec_state_t *nec_state = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(nec_state, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(nec_state, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + NEC_INPUT_LINE_POLL: set_irq_line(nec_state, NEC_INPUT_LINE_POLL, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + NEC_PC:
if( info->i - (Sreg(PS)<<4) < 0x10000 )
{
nec_state->ip = info->i - (Sreg(PS)<<4);
}
else
{
Sreg(PS) = info->i >> 4;
nec_state->ip = info->i & 0x0000f;
}
break;
case CPUINFO_INT_REGISTER + NEC_IP: nec_state->ip = info->i; break;
case CPUINFO_INT_SP:
if( info->i - (Sreg(SS)<<4) < 0x10000 )
{
Wreg(SP) = info->i - (Sreg(SS)<<4);
}
else
{
Sreg(SS) = info->i >> 4;
Wreg(SP) = info->i & 0x0000f;
}
break;
case CPUINFO_INT_REGISTER + NEC_SP: Wreg(SP) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_FLAGS: ExpandFlags(info->i); break;
case CPUINFO_INT_REGISTER + NEC_AW: Wreg(AW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_CW: Wreg(CW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_DW: Wreg(DW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_BW: Wreg(BW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_BP: Wreg(BP) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_IX: Wreg(IX) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_IY: Wreg(IY) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_ES: Sreg(DS1) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_CS: Sreg(PS) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_SS: Sreg(SS) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_DS: Sreg(DS0) = info->i; break;
}
}
/**************************************************************************
* Generic get_info
**************************************************************************/
static CPU_GET_INFO( nec )
{
nec_state_t *nec_state = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
int flags;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(nec_state_t); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 80; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = (nec_state->pending_irq & INT_IRQ) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = nec_state->nmi_state; break;
case CPUINFO_INT_INPUT_STATE + NEC_INPUT_LINE_POLL: info->i = nec_state->poll_state; break;
case CPUINFO_INT_PREVIOUSPC: /* not supported */ break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + NEC_PC: info->i = ((Sreg(PS)<<4) + nec_state->ip); break;
case CPUINFO_INT_REGISTER + NEC_IP: info->i = nec_state->ip; break;
case CPUINFO_INT_SP: info->i = (Sreg(SS)<<4) + Wreg(SP); break;
case CPUINFO_INT_REGISTER + NEC_SP: info->i = Wreg(SP); break;
case CPUINFO_INT_REGISTER + NEC_FLAGS: info->i = CompressFlags(); break;
case CPUINFO_INT_REGISTER + NEC_AW: info->i = Wreg(AW); break;
case CPUINFO_INT_REGISTER + NEC_CW: info->i = Wreg(CW); break;
case CPUINFO_INT_REGISTER + NEC_DW: info->i = Wreg(DW); break;
case CPUINFO_INT_REGISTER + NEC_BW: info->i = Wreg(BW); break;
case CPUINFO_INT_REGISTER + NEC_BP: info->i = Wreg(BP); break;
case CPUINFO_INT_REGISTER + NEC_IX: info->i = Wreg(IX); break;
case CPUINFO_INT_REGISTER + NEC_IY: info->i = Wreg(IY); break;
case CPUINFO_INT_REGISTER + NEC_ES: info->i = Sreg(DS1); break;
case CPUINFO_INT_REGISTER + NEC_CS: info->i = Sreg(PS); break;
case CPUINFO_INT_REGISTER + NEC_SS: info->i = Sreg(SS); break;
case CPUINFO_INT_REGISTER + NEC_DS: info->i = Sreg(DS0); break;
case CPUINFO_INT_REGISTER + NEC_PENDING: info->i = nec_state->pending_irq; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(nec); break;
case CPUINFO_FCT_INIT: /* set per-CPU */ break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(nec); break;
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(nec); break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(necv); break;
case CPUINFO_FCT_BURN: info->burn = NULL; break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(nec); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &nec_state->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "NEC"); break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC V-Series"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CREDITS: strcpy(info->s, "Bryan McPhail (V25/V35 support added by Alex W. Jackson)"); break;
case CPUINFO_STR_FLAGS:
flags = CompressFlags();
sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
case STATE_GENFLAGS:
string.printf("%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
flags & 0x8000 ? 'N':'E',
flags & 0x4000 ? '?':'.',
flags & 0x2000 ? '?':'.',
@ -594,89 +445,81 @@ static CPU_GET_INFO( nec )
flags & 0x0002 ? '.':'?',
flags & 0x0001 ? 'C':'.');
break;
case CPUINFO_STR_REGISTER + NEC_PC: sprintf(info->s, "PC:%05X", (Sreg(PS)<<4) + nec_state->ip); break;
case CPUINFO_STR_REGISTER + NEC_IP: sprintf(info->s, "IP:%04X", nec_state->ip); break;
case CPUINFO_STR_REGISTER + NEC_SP: sprintf(info->s, "SP:%04X", Wreg(SP)); break;
case CPUINFO_STR_REGISTER + NEC_FLAGS: sprintf(info->s, "F:%04X", CompressFlags()); break;
case CPUINFO_STR_REGISTER + NEC_AW: sprintf(info->s, "AW:%04X", Wreg(AW)); break;
case CPUINFO_STR_REGISTER + NEC_CW: sprintf(info->s, "CW:%04X", Wreg(CW)); break;
case CPUINFO_STR_REGISTER + NEC_DW: sprintf(info->s, "DW:%04X", Wreg(DW)); break;
case CPUINFO_STR_REGISTER + NEC_BW: sprintf(info->s, "BW:%04X", Wreg(BW)); break;
case CPUINFO_STR_REGISTER + NEC_BP: sprintf(info->s, "BP:%04X", Wreg(BP)); break;
case CPUINFO_STR_REGISTER + NEC_IX: sprintf(info->s, "IX:%04X", Wreg(IX)); break;
case CPUINFO_STR_REGISTER + NEC_IY: sprintf(info->s, "IY:%04X", Wreg(IY)); break;
case CPUINFO_STR_REGISTER + NEC_ES: sprintf(info->s, "DS1:%04X", Sreg(DS1)); break;
case CPUINFO_STR_REGISTER + NEC_CS: sprintf(info->s, "PS:%04X", Sreg(PS)); break;
case CPUINFO_STR_REGISTER + NEC_SS: sprintf(info->s, "SS:%04X", Sreg(SS)); break;
case CPUINFO_STR_REGISTER + NEC_DS: sprintf(info->s, "DS0:%04X", Sreg(DS0)); break;
}
}
/**************************************************************************
* CPU-specific set_info
**************************************************************************/
CPU_GET_INFO( v20 )
void nec_common_device::state_import(const device_state_entry &entry)
{
switch (state)
switch (entry.index())
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
case NEC_PC:
if( m_debugger_temp - (Sreg(PS)<<4) < 0x10000 )
{
m_ip = m_debugger_temp - (Sreg(PS)<<4);
}
else
{
Sreg(PS) = m_debugger_temp >> 4;
m_ip = m_debugger_temp & 0x0000f;
}
break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v20); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "V20"); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "v20"); break;
default: CPU_GET_INFO_CALL(nec); break;
case NEC_FLAGS:
ExpandFlags(m_debugger_temp);
break;
}
}
/**************************************************************************
* CPU-specific set_info
**************************************************************************/
CPU_GET_INFO( v30 )
void nec_common_device::state_export(const device_state_entry &entry)
{
switch (state)
switch (entry.index())
{
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v30); break;
case STATE_GENPC:
case NEC_PC:
m_debugger_temp = (Sreg(PS)<<4) + m_ip;
break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "V30"); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "v30"); break;
case STATE_GENSP:
m_debugger_temp = (Sreg(SS)<<4) + Wreg(SP);
break;
default: CPU_GET_INFO_CALL(nec); break;
case NEC_FLAGS:
m_debugger_temp = CompressFlags();
break;
}
}
/**************************************************************************
* CPU-specific set_info
**************************************************************************/
CPU_GET_INFO( v33 )
void nec_common_device::execute_run()
{
switch (state)
int prev_ICount;
if (m_halted)
{
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v33); break;
m_icount = 0;
debugger_instruction_hook(this, (Sreg(PS)<<4) + m_ip);
return;
}
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "V33"); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "v33"); break;
while(m_icount>0) {
/* Dispatch IRQ */
if (m_pending_irq && m_no_interrupt==0)
{
if (m_pending_irq & NMI_IRQ)
external_int();
else if (m_IF)
external_int();
}
default: CPU_GET_INFO_CALL(nec); break;
/* No interrupt allowed between last instruction and this one */
if (m_no_interrupt)
m_no_interrupt--;
debugger_instruction_hook(this, (Sreg(PS)<<4) + m_ip);
prev_ICount = m_icount;
(this->*s_nec_instruction[fetchop()])();
do_prefetch(prev_ICount);
}
}
DEFINE_LEGACY_CPU_DEVICE(V20, v20);
DEFINE_LEGACY_CPU_DEVICE(V30, v30);
DEFINE_LEGACY_CPU_DEVICE(V33, v33);

419
src/emu/cpu/nec/nec.h
View File

@ -3,21 +3,11 @@
#define __NEC_H_
struct nec_config
{
const UINT8* v25v35_decryptiontable; // internal decryption table
};
#define NEC_INPUT_LINE_INTP0 10
#define NEC_INPUT_LINE_INTP1 11
#define NEC_INPUT_LINE_INTP2 12
#define NEC_INPUT_LINE_POLL 20
#define V25_PORT_P0 0x10000
#define V25_PORT_P1 0x10002
#define V25_PORT_P2 0x10004
#define V25_PORT_PT 0x10006
enum
{
NEC_PC=0,
@ -26,11 +16,408 @@ enum
NEC_PENDING
};
/* Public functions */
DECLARE_LEGACY_CPU_DEVICE(V20, v20);
DECLARE_LEGACY_CPU_DEVICE(V25, v25);
DECLARE_LEGACY_CPU_DEVICE(V30, v30);
DECLARE_LEGACY_CPU_DEVICE(V33, v33);
DECLARE_LEGACY_CPU_DEVICE(V35, v35);
class nec_common_device : public cpu_device
{
public:
// construction/destruction
nec_common_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, bool is_16bit, offs_t fetch_xor, UINT8 prefetch_size, UINT8 prefetch_cycles, UINT32 chip_type);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 80; }
virtual UINT32 execute_input_lines() const { return 1; }
virtual UINT32 execute_default_irq_vector() const { return 0xff; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL); }
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
virtual void state_import(const device_state_entry &entry);
virtual void state_export(const device_state_entry &entry);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
virtual UINT32 disasm_max_opcode_bytes() const { return 8; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
address_space_config m_io_config;
/* NEC registers */
union necbasicregs
{ /* eight general registers */
UINT16 w[8]; /* viewed as 16 bits registers */
UINT8 b[16]; /* or as 8 bit registers */
};
necbasicregs m_regs;
offs_t m_fetch_xor;
UINT16 m_sregs[4];
UINT16 m_ip;
/* PSW flags */
INT32 m_SignVal;
UINT32 m_AuxVal; /* 0 or non-0 valued flags */
UINT32 m_OverVal;
UINT32 m_ZeroVal;
UINT32 m_CarryVal;
UINT32 m_ParityVal;
UINT8 m_TF; /* 0 or 1 valued flags */
UINT8 m_IF;
UINT8 m_DF;
UINT8 m_MF;
/* interrupt related */
UINT32 m_pending_irq;
UINT32 m_nmi_state;
UINT32 m_irq_state;
UINT32 m_poll_state;
UINT8 m_no_interrupt;
UINT8 m_halted;
address_space *m_program;
direct_read_data *m_direct;
address_space *m_io;
int m_icount;
UINT8 m_prefetch_size;
UINT8 m_prefetch_cycles;
INT8 m_prefetch_count;
UINT8 m_prefetch_reset;
UINT32 m_chip_type;
UINT32 m_prefix_base; /* base address of the latest prefix segment */
UINT8 m_seg_prefix; /* prefix segment indicator */
UINT32 m_EA;
UINT16 m_EO;
UINT16 m_E16;
UINT32 m_debugger_temp;
typedef void (nec_common_device::*nec_ophandler)();
typedef UINT32 (nec_common_device::*nec_eahandler)();
static const nec_ophandler s_nec_instruction[256];
static const nec_eahandler s_GetEA[192];
inline void prefetch();
void do_prefetch(int previous_ICount);
inline UINT8 fetch();
inline UINT16 fetchword();
UINT8 fetchop();
void nec_interrupt(unsigned int_num, int source);
void nec_trap();
void external_int();
void i_add_br8();
void i_add_wr16();
void i_add_r8b();
void i_add_r16w();
void i_add_ald8();
void i_add_axd16();
void i_push_es();
void i_pop_es();
void i_or_br8();
void i_or_r8b();
void i_or_wr16();
void i_or_r16w();
void i_or_ald8();
void i_or_axd16();
void i_push_cs();
void i_pre_nec();
void i_adc_br8();
void i_adc_wr16();
void i_adc_r8b();
void i_adc_r16w();
void i_adc_ald8();
void i_adc_axd16();
void i_push_ss();
void i_pop_ss();
void i_sbb_br8();
void i_sbb_wr16();
void i_sbb_r8b();
void i_sbb_r16w();
void i_sbb_ald8();
void i_sbb_axd16();
void i_push_ds();
void i_pop_ds();
void i_and_br8();
void i_and_r8b();
void i_and_wr16();
void i_and_r16w();
void i_and_ald8();
void i_and_axd16();
void i_es();
void i_daa();
void i_sub_br8();
void i_sub_wr16();
void i_sub_r8b();
void i_sub_r16w();
void i_sub_ald8();
void i_sub_axd16();
void i_cs();
void i_das();
void i_xor_br8();
void i_xor_r8b();
void i_xor_wr16();
void i_xor_r16w();
void i_xor_ald8();
void i_xor_axd16();
void i_ss();
void i_aaa();
void i_cmp_br8();
void i_cmp_wr16();
void i_cmp_r8b();
void i_cmp_r16w();
void i_cmp_ald8();
void i_cmp_axd16();
void i_ds();
void i_aas();
void i_inc_ax();
void i_inc_cx();
void i_inc_dx();
void i_inc_bx();
void i_inc_sp();
void i_inc_bp();
void i_inc_si();
void i_inc_di();
void i_dec_ax();
void i_dec_cx();
void i_dec_dx();
void i_dec_bx();
void i_dec_sp();
void i_dec_bp();
void i_dec_si();
void i_dec_di();
void i_push_ax();
void i_push_cx();
void i_push_dx();
void i_push_bx();
void i_push_sp();
void i_push_bp();
void i_push_si();
void i_push_di();
void i_pop_ax();
void i_pop_cx();
void i_pop_dx();
void i_pop_bx();
void i_pop_sp();
void i_pop_bp();
void i_pop_si();
void i_pop_di();
void i_pusha();
void i_popa();
void i_chkind();
void i_repnc();
void i_repc();
void i_push_d16();
void i_imul_d16();
void i_push_d8();
void i_imul_d8();
void i_insb();
void i_insw();
void i_outsb();
void i_outsw();
void i_jo();
void i_jno();
void i_jc();
void i_jnc();
void i_jz();
void i_jnz();
void i_jce();
void i_jnce();
void i_js();
void i_jns();
void i_jp();
void i_jnp();
void i_jl();
void i_jnl();
void i_jle();
void i_jnle();
void i_80pre();
void i_82pre();
void i_81pre();
void i_83pre();
void i_test_br8();
void i_test_wr16();
void i_xchg_br8();
void i_xchg_wr16();
void i_mov_br8();
void i_mov_r8b();
void i_mov_wr16();
void i_mov_r16w();
void i_mov_wsreg();
void i_lea();
void i_mov_sregw();
void i_invalid();
void i_popw();
void i_nop();
void i_xchg_axcx();
void i_xchg_axdx();
void i_xchg_axbx();
void i_xchg_axsp();
void i_xchg_axbp();
void i_xchg_axsi();
void i_xchg_axdi();
void i_cbw();
void i_cwd();
void i_call_far();
void i_pushf();
void i_popf();
void i_sahf();
void i_lahf();
void i_mov_aldisp();
void i_mov_axdisp();
void i_mov_dispal();
void i_mov_dispax();
void i_movsb();
void i_movsw();
void i_cmpsb();
void i_cmpsw();
void i_test_ald8();
void i_test_axd16();
void i_stosb();
void i_stosw();
void i_lodsb();
void i_lodsw();
void i_scasb();
void i_scasw();
void i_mov_ald8();
void i_mov_cld8();
void i_mov_dld8();
void i_mov_bld8();
void i_mov_ahd8();
void i_mov_chd8();
void i_mov_dhd8();
void i_mov_bhd8();
void i_mov_axd16();
void i_mov_cxd16();
void i_mov_dxd16();
void i_mov_bxd16();
void i_mov_spd16();
void i_mov_bpd16();
void i_mov_sid16();
void i_mov_did16();
void i_rotshft_bd8();
void i_rotshft_wd8();
void i_ret_d16();
void i_ret();
void i_les_dw();
void i_lds_dw();
void i_mov_bd8();
void i_mov_wd16();
void i_enter();
void i_leave();
void i_retf_d16();
void i_retf();
void i_int3();
void i_int();
void i_into();
void i_iret();
void i_rotshft_b();
void i_rotshft_w();
void i_rotshft_bcl();
void i_rotshft_wcl();
void i_aam();
void i_aad();
void i_setalc();
void i_trans();
void i_fpo();
void i_loopne();
void i_loope();
void i_loop();
void i_jcxz();
void i_inal();
void i_inax();
void i_outal();
void i_outax();
void i_call_d16();
void i_jmp_d16();
void i_jmp_far();
void i_jmp_d8();
void i_inaldx();
void i_inaxdx();
void i_outdxal();
void i_outdxax();
void i_lock();
void i_repne();
void i_repe();
void i_hlt();
void i_cmc();
void i_f6pre();
void i_f7pre();
void i_clc();
void i_stc();
void i_di();
void i_ei();
void i_cld();
void i_std();
void i_fepre();
void i_ffpre();
void i_wait();
UINT32 EA_000();
UINT32 EA_001();
UINT32 EA_002();
UINT32 EA_003();
UINT32 EA_004();
UINT32 EA_005();
UINT32 EA_006();
UINT32 EA_007();
UINT32 EA_100();
UINT32 EA_101();
UINT32 EA_102();
UINT32 EA_103();
UINT32 EA_104();
UINT32 EA_105();
UINT32 EA_106();
UINT32 EA_107();
UINT32 EA_200();
UINT32 EA_201();
UINT32 EA_202();
UINT32 EA_203();
UINT32 EA_204();
UINT32 EA_205();
UINT32 EA_206();
UINT32 EA_207();
};
class v20_device : public nec_common_device
{
public:
v20_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class v30_device : public nec_common_device
{
public:
v30_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class v33_device : public nec_common_device
{
public:
v33_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
extern const device_type V20;
extern const device_type V30;
extern const device_type V33;
#endif

24
src/emu/cpu/nec/necdasm.c
View File

@ -7,18 +7,7 @@
#include "emu.h"
struct nec_config
{
const UINT8* v25v35_decryptiontable; // internal decryption table
};
/* default configuration */
static const nec_config default_config =
{
NULL
};
static const nec_config *Iconfig;
static const UINT8 *Iconfig;
enum
{
@ -1532,14 +1521,14 @@ static void decode_opcode(char *s, const I386_OPCODE *op, UINT8 op1 )
case SEG_SS:
segment = op->flags;
op2 = FETCH();
if (Iconfig->v25v35_decryptiontable) op2 = Iconfig->v25v35_decryptiontable[op2];
if (Iconfig) op2 = Iconfig[op2];
decode_opcode( s, &necv_opcode_table1[op2], op1 );
return;
case PREFIX:
s += sprintf( s, "%-8s", op->mnemonic );
op2 = FETCH();
if (Iconfig->v25v35_decryptiontable) op2 = Iconfig->v25v35_decryptiontable[op2];
if (Iconfig) op2 = Iconfig[op2];
decode_opcode( s, &necv_opcode_table1[op2], op1 );
return;
@ -1586,11 +1575,10 @@ handle_unknown:
sprintf(s, "???");
}
int necv_dasm_one(char *buffer, UINT32 eip, const UINT8 *oprom, const nec_config *_config)
int necv_dasm_one(char *buffer, UINT32 eip, const UINT8 *oprom, const UINT8 *decryption_table)
{
UINT8 op;
const nec_config *config = _config ? _config : &default_config;
Iconfig = config;
Iconfig = decryption_table;
opcode_ptr = opcode_ptr_base = oprom;
pc = eip;
@ -1599,7 +1587,7 @@ int necv_dasm_one(char *buffer, UINT32 eip, const UINT8 *oprom, const nec_config
op = FETCH();
if (Iconfig->v25v35_decryptiontable) op = Iconfig->v25v35_decryptiontable[op];
if (Iconfig) op = Iconfig[op];
decode_opcode( buffer, &necv_opcode_table1[op], op );
return (pc-eip) | dasm_flags | DASMFLAG_SUPPORTED;

103
src/emu/cpu/nec/necea.h
View File

@ -1,60 +1,57 @@
static UINT32 EA;
static UINT16 EO;
static UINT16 E16;
UINT32 nec_common_device::EA_000() { m_EO=Wreg(BW)+Wreg(IX); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_001() { m_EO=Wreg(BW)+Wreg(IY); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_002() { m_EO=Wreg(BP)+Wreg(IX); m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_003() { m_EO=Wreg(BP)+Wreg(IY); m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_004() { m_EO=Wreg(IX); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_005() { m_EO=Wreg(IY); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_006() { m_EO=FETCH(); m_EO+=FETCH()<<8; m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_007() { m_EO=Wreg(BW); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
static unsigned EA_000(nec_state_t *nec_state) { EO=Wreg(BW)+Wreg(IX); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_001(nec_state_t *nec_state) { EO=Wreg(BW)+Wreg(IY); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_002(nec_state_t *nec_state) { EO=Wreg(BP)+Wreg(IX); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_003(nec_state_t *nec_state) { EO=Wreg(BP)+Wreg(IY); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_004(nec_state_t *nec_state) { EO=Wreg(IX); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_005(nec_state_t *nec_state) { EO=Wreg(IY); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_006(nec_state_t *nec_state) { EO=FETCH(); EO+=FETCH()<<8; EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_007(nec_state_t *nec_state) { EO=Wreg(BW); EA=DefaultBase(DS0)+EO; return EA; }
UINT32 nec_common_device::EA_100() { m_EO=(Wreg(BW)+Wreg(IX)+(INT8)FETCH()); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_101() { m_EO=(Wreg(BW)+Wreg(IY)+(INT8)FETCH()); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_102() { m_EO=(Wreg(BP)+Wreg(IX)+(INT8)FETCH()); m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_103() { m_EO=(Wreg(BP)+Wreg(IY)+(INT8)FETCH()); m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_104() { m_EO=(Wreg(IX)+(INT8)FETCH()); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_105() { m_EO=(Wreg(IY)+(INT8)FETCH()); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_106() { m_EO=(Wreg(BP)+(INT8)FETCH()); m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_107() { m_EO=(Wreg(BW)+(INT8)FETCH()); m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
static unsigned EA_100(nec_state_t *nec_state) { EO=(Wreg(BW)+Wreg(IX)+(INT8)FETCH()); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_101(nec_state_t *nec_state) { EO=(Wreg(BW)+Wreg(IY)+(INT8)FETCH()); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_102(nec_state_t *nec_state) { EO=(Wreg(BP)+Wreg(IX)+(INT8)FETCH()); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_103(nec_state_t *nec_state) { EO=(Wreg(BP)+Wreg(IY)+(INT8)FETCH()); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_104(nec_state_t *nec_state) { EO=(Wreg(IX)+(INT8)FETCH()); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_105(nec_state_t *nec_state) { EO=(Wreg(IY)+(INT8)FETCH()); EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_106(nec_state_t *nec_state) { EO=(Wreg(BP)+(INT8)FETCH()); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_107(nec_state_t *nec_state) { EO=(Wreg(BW)+(INT8)FETCH()); EA=DefaultBase(DS0)+EO; return EA; }
UINT32 nec_common_device::EA_200() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(BW)+Wreg(IX)+(INT16)m_E16; m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_201() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(BW)+Wreg(IY)+(INT16)m_E16; m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_202() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(BP)+Wreg(IX)+(INT16)m_E16; m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_203() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(BP)+Wreg(IY)+(INT16)m_E16; m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_204() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(IX)+(INT16)m_E16; m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_205() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(IY)+(INT16)m_E16; m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_206() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(BP)+(INT16)m_E16; m_EA=DefaultBase(SS)+m_EO; return m_EA; }
UINT32 nec_common_device::EA_207() { m_E16=FETCH(); m_E16+=FETCH()<<8; m_EO=Wreg(BW)+(INT16)m_E16; m_EA=DefaultBase(DS0)+m_EO; return m_EA; }
static unsigned EA_200(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(BW)+Wreg(IX)+(INT16)E16; EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_201(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(BW)+Wreg(IY)+(INT16)E16; EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_202(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(BP)+Wreg(IX)+(INT16)E16; EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_203(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(BP)+Wreg(IY)+(INT16)E16; EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_204(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(IX)+(INT16)E16; EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_205(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(IY)+(INT16)E16; EA=DefaultBase(DS0)+EO; return EA; }
static unsigned EA_206(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(BP)+(INT16)E16; EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_207(nec_state_t *nec_state) { E16=FETCH(); E16+=FETCH()<<8; EO=Wreg(BW)+(INT16)E16; EA=DefaultBase(DS0)+EO; return EA; }
const nec_common_device::nec_eahandler nec_common_device::s_GetEA[192]=
{
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
&nec_common_device::EA_000, &nec_common_device::EA_001, &nec_common_device::EA_002, &nec_common_device::EA_003, &nec_common_device::EA_004, &nec_common_device::EA_005, &nec_common_device::EA_006, &nec_common_device::EA_007,
static unsigned (*const GetEA[192])(nec_state_t *)={
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
&nec_common_device::EA_100, &nec_common_device::EA_101, &nec_common_device::EA_102, &nec_common_device::EA_103, &nec_common_device::EA_104, &nec_common_device::EA_105, &nec_common_device::EA_106, &nec_common_device::EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207,
&nec_common_device::EA_200, &nec_common_device::EA_201, &nec_common_device::EA_202, &nec_common_device::EA_203, &nec_common_device::EA_204, &nec_common_device::EA_205, &nec_common_device::EA_206, &nec_common_device::EA_207
};

470
src/emu/cpu/nec/necinstr.c
View File

@ -1,25 +1,25 @@
#define OP(num,func_name) static void func_name(nec_state_t *nec_state)
#define OP(num,func_name) void nec_common_device::func_name()
OP( 0x00, i_add_br8 ) { DEF_br8; ADDB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x01, i_add_wr16 ) { DEF_wr16; ADDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x01, i_add_wr16 ) { DEF_wr16; ADDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x02, i_add_r8b ) { DEF_r8b; ADDB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x03, i_add_r16w ) { DEF_r16w; ADDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x03, i_add_r16w ) { DEF_r16w; ADDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x04, i_add_ald8 ) { DEF_ald8; ADDB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x05, i_add_axd16) { DEF_axd16; ADDW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x06, i_push_es ) { PUSH(Sreg(DS1)); CLKS(12,8,3); }
OP( 0x07, i_pop_es ) { POP(Sreg(DS1)); CLKS(12,8,5); }
OP( 0x08, i_or_br8 ) { DEF_br8; ORB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x09, i_or_wr16 ) { DEF_wr16; ORW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x09, i_or_wr16 ) { DEF_wr16; ORW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x0a, i_or_r8b ) { DEF_r8b; ORB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x0b, i_or_r16w ) { DEF_r16w; ORW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x0b, i_or_r16w ) { DEF_r16w; ORW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x0c, i_or_ald8 ) { DEF_ald8; ORB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x0d, i_or_axd16 ) { DEF_axd16; ORW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x0e, i_push_cs ) { PUSH(Sreg(PS)); CLKS(12,8,3); }
OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2;
switch (FETCH()) {
case 0x10 : BITOP_BYTE; CLKS(3,3,4); tmp2 = Breg(CL) & 0x7; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x11 : BITOP_WORD; CLKS(3,3,4); tmp2 = Breg(CL) & 0xf; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x10 : BITOP_BYTE; CLKS(3,3,4); tmp2 = Breg(CL) & 0x7; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x11 : BITOP_WORD; CLKS(3,3,4); tmp2 = Breg(CL) & 0xf; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x12 : BITOP_BYTE; CLKS(5,5,4); tmp2 = Breg(CL) & 0x7; tmp &= ~(1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Clr */
case 0x13 : BITOP_WORD; CLKS(5,5,4); tmp2 = Breg(CL) & 0xf; tmp &= ~(1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Clr */
case 0x14 : BITOP_BYTE; CLKS(4,4,4); tmp2 = Breg(CL) & 0x7; tmp |= (1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Set */
@ -27,8 +27,8 @@ OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2;
case 0x16 : BITOP_BYTE; CLKS(4,4,4); tmp2 = Breg(CL) & 0x7; BIT_NOT; PutbackRMByte(ModRM,tmp); break; /* Not */
case 0x17 : BITOP_WORD; CLKS(4,4,4); tmp2 = Breg(CL) & 0xf; BIT_NOT; PutbackRMWord(ModRM,tmp); break; /* Not */
case 0x18 : BITOP_BYTE; CLKS(4,4,4); tmp2 = (FETCH()) & 0x7; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x19 : BITOP_WORD; CLKS(4,4,4); tmp2 = (FETCH()) & 0xf; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x18 : BITOP_BYTE; CLKS(4,4,4); tmp2 = (FETCH()) & 0x7; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x19 : BITOP_WORD; CLKS(4,4,4); tmp2 = (FETCH()) & 0xf; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x1a : BITOP_BYTE; CLKS(6,6,4); tmp2 = (FETCH()) & 0x7; tmp &= ~(1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Clr */
case 0x1b : BITOP_WORD; CLKS(6,6,4); tmp2 = (FETCH()) & 0xf; tmp &= ~(1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Clr */
case 0x1c : BITOP_BYTE; CLKS(5,5,4); tmp2 = (FETCH()) & 0x7; tmp |= (1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Set */
@ -41,67 +41,67 @@ OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2;
case 0x26 : CMP4S; CLKS(7,7,2); break;
case 0x28 : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= Breg(AL) & 0xf; Breg(AL) = (Breg(AL) & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(13,13,9,28,28,15); break;
case 0x2a : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp2 = (Breg(AL) & 0xf)<<4; Breg(AL) = (Breg(AL) & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(17,17,13,32,32,19); break;
case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC(nec_state)); break;
case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC(nec_state)); break;
case 0xe0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",PC(nec_state)); break;
case 0xf0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",PC(nec_state)); break;
case 0xff : ModRM = FETCH(); ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",PC(nec_state)); break;
default: logerror("%06x: Unknown V20 instruction\n",PC(nec_state)); break;
case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC()); break;
case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC()); break;
case 0xe0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",PC()); break;
case 0xf0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",PC()); break;
case 0xff : ModRM = FETCH(); ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",PC()); break;
default: logerror("%06x: Unknown V20 instruction\n",PC()); break;
}
}
OP( 0x10, i_adc_br8 ) { DEF_br8; src+=CF; ADDB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x11, i_adc_wr16 ) { DEF_wr16; src+=CF; ADDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x11, i_adc_wr16 ) { DEF_wr16; src+=CF; ADDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x12, i_adc_r8b ) { DEF_r8b; src+=CF; ADDB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x13, i_adc_r16w ) { DEF_r16w; src+=CF; ADDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x13, i_adc_r16w ) { DEF_r16w; src+=CF; ADDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x14, i_adc_ald8 ) { DEF_ald8; src+=CF; ADDB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x15, i_adc_axd16) { DEF_axd16; src+=CF; ADDW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x16, i_push_ss ) { PUSH(Sreg(SS)); CLKS(12,8,3); }
OP( 0x17, i_pop_ss ) { POP(Sreg(SS)); CLKS(12,8,5); nec_state->no_interrupt=1; }
OP( 0x17, i_pop_ss ) { POP(Sreg(SS)); CLKS(12,8,5); m_no_interrupt=1; }
OP( 0x18, i_sbb_br8 ) { DEF_br8; src+=CF; SUBB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x19, i_sbb_wr16 ) { DEF_wr16; src+=CF; SUBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x19, i_sbb_wr16 ) { DEF_wr16; src+=CF; SUBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x1a, i_sbb_r8b ) { DEF_r8b; src+=CF; SUBB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x1b, i_sbb_r16w ) { DEF_r16w; src+=CF; SUBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x1b, i_sbb_r16w ) { DEF_r16w; src+=CF; SUBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x1c, i_sbb_ald8 ) { DEF_ald8; src+=CF; SUBB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x1d, i_sbb_axd16) { DEF_axd16; src+=CF; SUBW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x1e, i_push_ds ) { PUSH(Sreg(DS0)); CLKS(12,8,3); }
OP( 0x1f, i_pop_ds ) { POP(Sreg(DS0)); CLKS(12,8,5); }
OP( 0x20, i_and_br8 ) { DEF_br8; ANDB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x21, i_and_wr16 ) { DEF_wr16; ANDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x21, i_and_wr16 ) { DEF_wr16; ANDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x22, i_and_r8b ) { DEF_r8b; ANDB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x23, i_and_r16w ) { DEF_r16w; ANDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x23, i_and_r16w ) { DEF_r16w; ANDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x24, i_and_ald8 ) { DEF_ald8; ANDB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x25, i_and_axd16) { DEF_axd16; ANDW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x26, i_es ) { nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS1)<<4; CLK(2); nec_instruction[fetchop(nec_state)](nec_state); nec_state->seg_prefix=FALSE; }
OP( 0x26, i_es ) { m_seg_prefix=TRUE; m_prefix_base=Sreg(DS1)<<4; CLK(2); (this->*s_nec_instruction[fetchop()])(); m_seg_prefix=FALSE; }
OP( 0x27, i_daa ) { ADJ4(6,0x60); CLKS(3,3,2); }
OP( 0x28, i_sub_br8 ) { DEF_br8; SUBB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x29, i_sub_wr16 ) { DEF_wr16; SUBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x29, i_sub_wr16 ) { DEF_wr16; SUBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x2a, i_sub_r8b ) { DEF_r8b; SUBB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x2b, i_sub_r16w ) { DEF_r16w; SUBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x2b, i_sub_r16w ) { DEF_r16w; SUBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x2c, i_sub_ald8 ) { DEF_ald8; SUBB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x2d, i_sub_axd16) { DEF_axd16; SUBW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x2e, i_cs ) { nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(PS)<<4; CLK(2); nec_instruction[fetchop(nec_state)](nec_state); nec_state->seg_prefix=FALSE; }
OP( 0x2e, i_cs ) { m_seg_prefix=TRUE; m_prefix_base=Sreg(PS)<<4; CLK(2); (this->*s_nec_instruction[fetchop()])(); m_seg_prefix=FALSE; }
OP( 0x2f, i_das ) { ADJ4(-6,-0x60); CLKS(3,3,2); }
OP( 0x30, i_xor_br8 ) { DEF_br8; XORB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
OP( 0x31, i_xor_wr16 ) { DEF_wr16; XORW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,EA);}
OP( 0x31, i_xor_wr16 ) { DEF_wr16; XORW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
OP( 0x32, i_xor_r8b ) { DEF_r8b; XORB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
OP( 0x33, i_xor_r16w ) { DEF_r16w; XORW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x33, i_xor_r16w ) { DEF_r16w; XORW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x34, i_xor_ald8 ) { DEF_ald8; XORB; Breg(AL)=dst; CLKS(4,4,2); }
OP( 0x35, i_xor_axd16) { DEF_axd16; XORW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x36, i_ss ) { nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(SS)<<4; CLK(2); nec_instruction[fetchop(nec_state)](nec_state); nec_state->seg_prefix=FALSE; }
OP( 0x36, i_ss ) { m_seg_prefix=TRUE; m_prefix_base=Sreg(SS)<<4; CLK(2); (this->*s_nec_instruction[fetchop()])(); m_seg_prefix=FALSE; }
OP( 0x37, i_aaa ) { ADJB(6, (Breg(AL) > 0xf9) ? 2 : 1); CLKS(7,7,4); }
OP( 0x38, i_cmp_br8 ) { DEF_br8; SUBB; CLKM(2,2,2,11,11,6); }
OP( 0x39, i_cmp_wr16 ) { DEF_wr16; SUBW; CLKR(15,15,8,15,11,6,2,EA);}
OP( 0x39, i_cmp_wr16 ) { DEF_wr16; SUBW; CLKR(15,15,8,15,11,6,2,m_EA);}
OP( 0x3a, i_cmp_r8b ) { DEF_r8b; SUBB; CLKM(2,2,2,11,11,6); }
OP( 0x3b, i_cmp_r16w ) { DEF_r16w; SUBW; CLKR(15,15,8,15,11,6,2,EA); }
OP( 0x3b, i_cmp_r16w ) { DEF_r16w; SUBW; CLKR(15,15,8,15,11,6,2,m_EA); }
OP( 0x3c, i_cmp_ald8 ) { DEF_ald8; SUBB; CLKS(4,4,2); }
OP( 0x3d, i_cmp_axd16) { DEF_axd16; SUBW; CLKS(4,4,2); }
OP( 0x3e, i_ds ) { nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS0)<<4; CLK(2); nec_instruction[fetchop(nec_state)](nec_state); nec_state->seg_prefix=FALSE; }
OP( 0x3e, i_ds ) { m_seg_prefix=TRUE; m_prefix_base=Sreg(DS0)<<4; CLK(2); (this->*s_nec_instruction[fetchop()])(); m_seg_prefix=FALSE; }
OP( 0x3f, i_aas ) { ADJB(-6, (Breg(AL) < 6) ? -2 : -1); CLKS(7,7,4); }
OP( 0x40, i_inc_ax ) { IncWordReg(AW); CLK(2); }
@ -171,75 +171,75 @@ OP( 0x62, i_chkind ) {
high= GetnextRMWord;
tmp= RegWord(ModRM);
if (tmp<low || tmp>high) {
nec_interrupt(nec_state, NEC_CHKIND_VECTOR, BRK);
nec_interrupt(NEC_CHKIND_VECTOR, BRK);
}
nec_state->icount-=20;
logerror("%06x: bound %04x high %04x low %04x tmp\n",PC(nec_state),high,low,tmp);
m_icount-=20;
logerror("%06x: bound %04x high %04x low %04x tmp\n",PC(),high,low,tmp);
}
OP( 0x64, i_repnc ) { UINT32 next = fetchop(nec_state); UINT16 c = Wreg(CW);
OP( 0x64, i_repnc ) { UINT32 next = fetchop(); UINT16 c = Wreg(CW);
switch(next) { /* Segments */
case 0x26: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS1)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x2e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(PS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x36: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(SS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x3e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS0)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x26: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS1)<<4; next = fetchop(); CLK(2); break;
case 0x2e: m_seg_prefix=TRUE; m_prefix_base=Sreg(PS)<<4; next = fetchop(); CLK(2); break;
case 0x36: m_seg_prefix=TRUE; m_prefix_base=Sreg(SS)<<4; next = fetchop(); CLK(2); break;
case 0x3e: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS0)<<4; next = fetchop(); CLK(2); break;
}
switch(next) {
case 0x6c: CLK(2); if (c) do { i_insb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
default: logerror("%06x: REPNC invalid\n",PC(nec_state)); nec_instruction[next](nec_state);
case 0x6c: CLK(2); if (c) do { i_insb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && !CF); Wreg(CW)=c; break;
default: logerror("%06x: REPNC invalid\n",PC()); (this->*s_nec_instruction[next])();
}
nec_state->seg_prefix=FALSE;
m_seg_prefix=FALSE;
}
OP( 0x65, i_repc ) { UINT32 next = fetchop(nec_state); UINT16 c = Wreg(CW);
OP( 0x65, i_repc ) { UINT32 next = fetchop(); UINT16 c = Wreg(CW);
switch(next) { /* Segments */
case 0x26: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS1)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x2e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(PS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x36: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(SS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x3e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS0)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x26: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS1)<<4; next = fetchop(); CLK(2); break;
case 0x2e: m_seg_prefix=TRUE; m_prefix_base=Sreg(PS)<<4; next = fetchop(); CLK(2); break;
case 0x36: m_seg_prefix=TRUE; m_prefix_base=Sreg(SS)<<4; next = fetchop(); CLK(2); break;
case 0x3e: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS0)<<4; next = fetchop(); CLK(2); break;
}
switch(next) {
case 0x6c: CLK(2); if (c) do { i_insb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && CF); Wreg(CW)=c; break;
default: logerror("%06x: REPC invalid\n",PC(nec_state)); nec_instruction[next](nec_state);
case 0x6c: CLK(2); if (c) do { i_insb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && CF); Wreg(CW)=c; break;
default: logerror("%06x: REPC invalid\n",PC()); (this->*s_nec_instruction[next])();
}
nec_state->seg_prefix=FALSE;
m_seg_prefix=FALSE;
}
OP( 0x68, i_push_d16 ) { UINT32 tmp; tmp = FETCHWORD(); PUSH(tmp); CLKW(12,12,5,12,8,5,Wreg(SP)); }
OP( 0x69, i_imul_d16 ) { UINT32 tmp; DEF_r16w; tmp = FETCHWORD(); dst = (INT32)((INT16)src)*(INT32)((INT16)tmp); nec_state->CarryVal = nec_state->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1); RegWord(ModRM)=(WORD)dst; nec_state->icount-=(ModRM >=0xc0 )?38:47;}
OP( 0x69, i_imul_d16 ) { UINT32 tmp; DEF_r16w; tmp = FETCHWORD(); dst = (INT32)((INT16)src)*(INT32)((INT16)tmp); m_CarryVal = m_OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1); RegWord(ModRM)=(WORD)dst; m_icount-=(ModRM >=0xc0 )?38:47;}
OP( 0x6a, i_push_d8 ) { UINT32 tmp = (WORD)((INT16)((INT8)FETCH())); PUSH(tmp); CLKW(11,11,5,11,7,3,Wreg(SP)); }
OP( 0x6b, i_imul_d8 ) { UINT32 src2; DEF_r16w; src2= (WORD)((INT16)((INT8)FETCH())); dst = (INT32)((INT16)src)*(INT32)((INT16)src2); nec_state->CarryVal = nec_state->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1); RegWord(ModRM)=(WORD)dst; nec_state->icount-=(ModRM >=0xc0 )?31:39; }
OP( 0x6c, i_insb ) { PutMemB(DS1,Wreg(IY),read_port_byte(Wreg(DW))); Wreg(IY)+= -2 * nec_state->DF + 1; CLK(8); }
OP( 0x6d, i_insw ) { PutMemW(DS1,Wreg(IY),read_port_word(Wreg(DW))); Wreg(IY)+= -4 * nec_state->DF + 2; CLKS(18,10,8); }
OP( 0x6e, i_outsb ) { write_port_byte(Wreg(DW),GetMemB(DS0,Wreg(IX))); Wreg(IX)+= -2 * nec_state->DF + 1; CLK(8); }
OP( 0x6f, i_outsw ) { write_port_word(Wreg(DW),GetMemW(DS0,Wreg(IX))); Wreg(IX)+= -4 * nec_state->DF + 2; CLKS(18,10,8); }
OP( 0x6b, i_imul_d8 ) { UINT32 src2; DEF_r16w; src2= (WORD)((INT16)((INT8)FETCH())); dst = (INT32)((INT16)src)*(INT32)((INT16)src2); m_CarryVal = m_OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1); RegWord(ModRM)=(WORD)dst; m_icount-=(ModRM >=0xc0 )?31:39; }
OP( 0x6c, i_insb ) { PutMemB(DS1,Wreg(IY),read_port_byte(Wreg(DW))); Wreg(IY)+= -2 * m_DF + 1; CLK(8); }
OP( 0x6d, i_insw ) { PutMemW(DS1,Wreg(IY),read_port_word(Wreg(DW))); Wreg(IY)+= -4 * m_DF + 2; CLKS(18,10,8); }
OP( 0x6e, i_outsb ) { write_port_byte(Wreg(DW),GetMemB(DS0,Wreg(IX))); Wreg(IX)+= -2 * m_DF + 1; CLK(8); }
OP( 0x6f, i_outsw ) { write_port_word(Wreg(DW),GetMemW(DS0,Wreg(IX))); Wreg(IX)+= -4 * m_DF + 2; CLKS(18,10,8); }
OP( 0x70, i_jo ) { JMP( OF); CLKS(4,4,3); }
OP( 0x71, i_jno ) { JMP(!OF); CLKS(4,4,3); }
@ -273,7 +273,7 @@ OP( 0x80, i_80pre ) { UINT32 dst, src; GetModRM; dst = GetRMByte(ModRM); src =
}
OP( 0x81, i_81pre ) { UINT32 dst, src; GetModRM; dst = GetRMWord(ModRM); src = FETCH(); src+= (FETCH() << 8);
if (ModRM >=0xc0 ) CLKS(4,4,2) else if ((ModRM & 0x38)==0x38) CLKW(17,17,8,17,13,6,EA) else CLKW(26,26,11,26,18,7,EA)
if (ModRM >=0xc0 ) CLKS(4,4,2) else if ((ModRM & 0x38)==0x38) CLKW(17,17,8,17,13,6,m_EA) else CLKW(26,26,11,26,18,7,m_EA)
switch (ModRM & 0x38) {
case 0x00: ADDW; PutbackRMWord(ModRM,dst); break;
case 0x08: ORW; PutbackRMWord(ModRM,dst); break;
@ -301,7 +301,7 @@ OP( 0x82, i_82pre ) { UINT32 dst, src; GetModRM; dst = GetRMByte(ModRM); src =
}
OP( 0x83, i_83pre ) { UINT32 dst, src; GetModRM; dst = GetRMWord(ModRM); src = (WORD)((INT16)((INT8)FETCH()));
if (ModRM >=0xc0 ) CLKS(4,4,2) else if ((ModRM & 0x38)==0x38) CLKW(17,17,8,17,13,6,EA) else CLKW(26,26,11,26,18,7,EA)
if (ModRM >=0xc0 ) CLKS(4,4,2) else if ((ModRM & 0x38)==0x38) CLKW(17,17,8,17,13,6,m_EA) else CLKW(26,26,11,26,18,7,m_EA)
switch (ModRM & 0x38) {
case 0x00: ADDW; PutbackRMWord(ModRM,dst); break;
case 0x08: ORW; PutbackRMWord(ModRM,dst); break;
@ -315,36 +315,36 @@ OP( 0x83, i_83pre ) { UINT32 dst, src; GetModRM; dst = GetRMWord(ModRM); src =
}
OP( 0x84, i_test_br8 ) { DEF_br8; ANDB; CLKM(2,2,2,10,10,6); }
OP( 0x85, i_test_wr16 ) { DEF_wr16; ANDW; CLKR(14,14,8,14,10,6,2,EA); }
OP( 0x85, i_test_wr16 ) { DEF_wr16; ANDW; CLKR(14,14,8,14,10,6,2,m_EA); }
OP( 0x86, i_xchg_br8 ) { DEF_br8; RegByte(ModRM)=dst; PutbackRMByte(ModRM,src); CLKM(3,3,3,16,18,8); }
OP( 0x87, i_xchg_wr16 ) { DEF_wr16; RegWord(ModRM)=dst; PutbackRMWord(ModRM,src); CLKR(24,24,12,24,16,8,3,EA); }
OP( 0x87, i_xchg_wr16 ) { DEF_wr16; RegWord(ModRM)=dst; PutbackRMWord(ModRM,src); CLKR(24,24,12,24,16,8,3,m_EA); }
OP( 0x88, i_mov_br8 ) { UINT8 src; GetModRM; src = RegByte(ModRM); PutRMByte(ModRM,src); CLKM(2,2,2,9,9,3); }
OP( 0x89, i_mov_wr16 ) { UINT16 src; GetModRM; src = RegWord(ModRM); PutRMWord(ModRM,src); CLKR(13,13,5,13,9,3,2,EA); }
OP( 0x89, i_mov_wr16 ) { UINT16 src; GetModRM; src = RegWord(ModRM); PutRMWord(ModRM,src); CLKR(13,13,5,13,9,3,2,m_EA); }
OP( 0x8a, i_mov_r8b ) { UINT8 src; GetModRM; src = GetRMByte(ModRM); RegByte(ModRM)=src; CLKM(2,2,2,11,11,5); }
OP( 0x8b, i_mov_r16w ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); RegWord(ModRM)=src; CLKR(15,15,7,15,11,5,2,EA); }
OP( 0x8b, i_mov_r16w ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); RegWord(ModRM)=src; CLKR(15,15,7,15,11,5,2,m_EA); }
OP( 0x8c, i_mov_wsreg ) { GetModRM;
switch (ModRM & 0x38) {
case 0x00: PutRMWord(ModRM,Sreg(DS1)); CLKR(14,14,5,14,10,3,2,EA); break;
case 0x08: PutRMWord(ModRM,Sreg(PS)); CLKR(14,14,5,14,10,3,2,EA); break;
case 0x10: PutRMWord(ModRM,Sreg(SS)); CLKR(14,14,5,14,10,3,2,EA); break;
case 0x18: PutRMWord(ModRM,Sreg(DS0)); CLKR(14,14,5,14,10,3,2,EA); break;
default: logerror("%06x: MOV Sreg - Invalid register\n",PC(nec_state));
case 0x00: PutRMWord(ModRM,Sreg(DS1)); CLKR(14,14,5,14,10,3,2,m_EA); break;
case 0x08: PutRMWord(ModRM,Sreg(PS)); CLKR(14,14,5,14,10,3,2,m_EA); break;
case 0x10: PutRMWord(ModRM,Sreg(SS)); CLKR(14,14,5,14,10,3,2,m_EA); break;
case 0x18: PutRMWord(ModRM,Sreg(DS0)); CLKR(14,14,5,14,10,3,2,m_EA); break;
default: logerror("%06x: MOV Sreg - Invalid register\n",PC());
}
}
OP( 0x8d, i_lea ) { UINT16 ModRM = FETCH(); (void)(*GetEA[ModRM])(nec_state); RegWord(ModRM)=EO; CLKS(4,4,2); }
OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKR(15,15,7,15,11,5,2,EA);
OP( 0x8d, i_lea ) { UINT16 ModRM = FETCH(); (void)(this->*s_GetEA[ModRM])(); RegWord(ModRM)=m_EO; CLKS(4,4,2); }
OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKR(15,15,7,15,11,5,2,m_EA);
switch (ModRM & 0x38) {
case 0x00: Sreg(DS1) = src; break; /* mov es,ew */
case 0x08: Sreg(PS) = src; break; /* mov cs,ew */
case 0x10: Sreg(SS) = src; break; /* mov ss,ew */
case 0x18: Sreg(DS0) = src; break; /* mov ds,ew */
default: logerror("%06x: MOV Sreg - Invalid register\n",PC(nec_state));
default: logerror("%06x: MOV Sreg - Invalid register\n",PC());
}
nec_state->no_interrupt=1;
m_no_interrupt=1;
}
OP( 0x8f, i_popw ) { UINT16 tmp; GetModRM; POP(tmp); PutRMWord(ModRM,tmp); nec_state->icount-=21; }
OP( 0x90, i_nop ) { CLK(3); /* { if (nec_state->MF == 0) printf("90 -> %06x: \n",PC(nec_state)); } */ }
OP( 0x8f, i_popw ) { UINT16 tmp; GetModRM; POP(tmp); PutRMWord(ModRM,tmp); m_icount-=21; }
OP( 0x90, i_nop ) { CLK(3); /* { if (m_MF == 0) printf("90 -> %06x: \n",PC()); } */ }
OP( 0x91, i_xchg_axcx ) { XchgAWReg(CW); CLK(3); }
OP( 0x92, i_xchg_axdx ) { XchgAWReg(DW); CLK(3); }
OP( 0x93, i_xchg_axbx ) { XchgAWReg(BW); CLK(3); }
@ -355,10 +355,10 @@ OP( 0x97, i_xchg_axdi ) { XchgAWReg(IY); CLK(3); }
OP( 0x98, i_cbw ) { Breg(AH) = (Breg(AL) & 0x80) ? 0xff : 0; CLK(2); }
OP( 0x99, i_cwd ) { Wreg(DW) = (Breg(AH) & 0x80) ? 0xffff : 0; CLK(4); }
OP( 0x9a, i_call_far ) { UINT32 tmp, tmp2; tmp = FETCHWORD(); tmp2 = FETCHWORD(); PUSH(Sreg(PS)); PUSH(nec_state->ip); nec_state->ip = (WORD)tmp; Sreg(PS) = (WORD)tmp2; CHANGE_PC; CLKW(29,29,13,29,21,9,Wreg(SP)); }
OP( 0x9b, i_wait ) { if (!nec_state->poll_state) nec_state->ip--; CLK(5); }
OP( 0x9a, i_call_far ) { UINT32 tmp, tmp2; tmp = FETCHWORD(); tmp2 = FETCHWORD(); PUSH(Sreg(PS)); PUSH(m_ip); m_ip = (WORD)tmp; Sreg(PS) = (WORD)tmp2; CHANGE_PC; CLKW(29,29,13,29,21,9,Wreg(SP)); }
OP( 0x9b, i_wait ) { if (!m_poll_state) m_ip--; CLK(5); }
OP( 0x9c, i_pushf ) { UINT16 tmp = CompressFlags(); PUSH( tmp ); CLKS(12,8,3); }
OP( 0x9d, i_popf ) { UINT32 tmp; POP(tmp); ExpandFlags(tmp); CLKS(12,8,5); if (nec_state->TF) nec_trap(nec_state); }
OP( 0x9d, i_popf ) { UINT32 tmp; POP(tmp); ExpandFlags(tmp); CLKS(12,8,5); if (m_TF) nec_trap(); }
OP( 0x9e, i_sahf ) { UINT32 tmp = (CompressFlags() & 0xff00) | (Breg(AH) & 0xd5); ExpandFlags(tmp); CLKS(3,3,2); }
OP( 0x9f, i_lahf ) { Breg(AH) = CompressFlags() & 0xff; CLKS(3,3,2); }
@ -366,19 +366,19 @@ OP( 0xa0, i_mov_aldisp ) { UINT32 addr; addr = FETCHWORD(); Breg(AL) = GetMemB(D
OP( 0xa1, i_mov_axdisp ) { UINT32 addr; addr = FETCHWORD(); Wreg(AW) = GetMemW(DS0, addr); CLKW(14,14,7,14,10,5,addr); }
OP( 0xa2, i_mov_dispal ) { UINT32 addr; addr = FETCHWORD(); PutMemB(DS0, addr, Breg(AL)); CLKS(9,9,3); }
OP( 0xa3, i_mov_dispax ) { UINT32 addr; addr = FETCHWORD(); PutMemW(DS0, addr, Wreg(AW)); CLKW(13,13,5,13,9,3,addr); }
OP( 0xa4, i_movsb ) { UINT32 tmp = GetMemB(DS0,Wreg(IX)); PutMemB(DS1,Wreg(IY), tmp); Wreg(IY) += -2 * nec_state->DF + 1; Wreg(IX) += -2 * nec_state->DF + 1; CLKS(8,8,6); }
OP( 0xa5, i_movsw ) { UINT32 tmp = GetMemW(DS0,Wreg(IX)); PutMemW(DS1,Wreg(IY), tmp); Wreg(IY) += -4 * nec_state->DF + 2; Wreg(IX) += -4 * nec_state->DF + 2; CLKS(16,16,10); }
OP( 0xa6, i_cmpsb ) { UINT32 src = GetMemB(DS1, Wreg(IY)); UINT32 dst = GetMemB(DS0, Wreg(IX)); SUBB; Wreg(IY) += -2 * nec_state->DF + 1; Wreg(IX) += -2 * nec_state->DF + 1; CLKS(14,14,14); }
OP( 0xa7, i_cmpsw ) { UINT32 src = GetMemW(DS1, Wreg(IY)); UINT32 dst = GetMemW(DS0, Wreg(IX)); SUBW; Wreg(IY) += -4 * nec_state->DF + 2; Wreg(IX) += -4 * nec_state->DF + 2; CLKS(14,14,14); }
OP( 0xa4, i_movsb ) { UINT32 tmp = GetMemB(DS0,Wreg(IX)); PutMemB(DS1,Wreg(IY), tmp); Wreg(IY) += -2 * m_DF + 1; Wreg(IX) += -2 * m_DF + 1; CLKS(8,8,6); }
OP( 0xa5, i_movsw ) { UINT32 tmp = GetMemW(DS0,Wreg(IX)); PutMemW(DS1,Wreg(IY), tmp); Wreg(IY) += -4 * m_DF + 2; Wreg(IX) += -4 * m_DF + 2; CLKS(16,16,10); }
OP( 0xa6, i_cmpsb ) { UINT32 src = GetMemB(DS1, Wreg(IY)); UINT32 dst = GetMemB(DS0, Wreg(IX)); SUBB; Wreg(IY) += -2 * m_DF + 1; Wreg(IX) += -2 * m_DF + 1; CLKS(14,14,14); }
OP( 0xa7, i_cmpsw ) { UINT32 src = GetMemW(DS1, Wreg(IY)); UINT32 dst = GetMemW(DS0, Wreg(IX)); SUBW; Wreg(IY) += -4 * m_DF + 2; Wreg(IX) += -4 * m_DF + 2; CLKS(14,14,14); }
OP( 0xa8, i_test_ald8 ) { DEF_ald8; ANDB; CLKS(4,4,2); }
OP( 0xa9, i_test_axd16 ) { DEF_axd16; ANDW; CLKS(4,4,2); }
OP( 0xaa, i_stosb ) { PutMemB(DS1,Wreg(IY),Breg(AL)); Wreg(IY) += -2 * nec_state->DF + 1; CLKS(4,4,3); }
OP( 0xab, i_stosw ) { PutMemW(DS1,Wreg(IY),Wreg(AW)); Wreg(IY) += -4 * nec_state->DF + 2; CLKW(8,8,5,8,4,3,Wreg(IY)); }
OP( 0xac, i_lodsb ) { Breg(AL) = GetMemB(DS0,Wreg(IX)); Wreg(IX) += -2 * nec_state->DF + 1; CLKS(4,4,3); }
OP( 0xad, i_lodsw ) { Wreg(AW) = GetMemW(DS0,Wreg(IX)); Wreg(IX) += -4 * nec_state->DF + 2; CLKW(8,8,5,8,4,3,Wreg(IX)); }
OP( 0xae, i_scasb ) { UINT32 src = GetMemB(DS1, Wreg(IY)); UINT32 dst = Breg(AL); SUBB; Wreg(IY) += -2 * nec_state->DF + 1; CLKS(4,4,3); }
OP( 0xaf, i_scasw ) { UINT32 src = GetMemW(DS1, Wreg(IY)); UINT32 dst = Wreg(AW); SUBW; Wreg(IY) += -4 * nec_state->DF + 2; CLKW(8,8,5,8,4,3,Wreg(IY)); }
OP( 0xaa, i_stosb ) { PutMemB(DS1,Wreg(IY),Breg(AL)); Wreg(IY) += -2 * m_DF + 1; CLKS(4,4,3); }
OP( 0xab, i_stosw ) { PutMemW(DS1,Wreg(IY),Wreg(AW)); Wreg(IY) += -4 * m_DF + 2; CLKW(8,8,5,8,4,3,Wreg(IY)); }
OP( 0xac, i_lodsb ) { Breg(AL) = GetMemB(DS0,Wreg(IX)); Wreg(IX) += -2 * m_DF + 1; CLKS(4,4,3); }
OP( 0xad, i_lodsw ) { Wreg(AW) = GetMemW(DS0,Wreg(IX)); Wreg(IX) += -4 * m_DF + 2; CLKW(8,8,5,8,4,3,Wreg(IX)); }
OP( 0xae, i_scasb ) { UINT32 src = GetMemB(DS1, Wreg(IY)); UINT32 dst = Breg(AL); SUBB; Wreg(IY) += -2 * m_DF + 1; CLKS(4,4,3); }
OP( 0xaf, i_scasw ) { UINT32 src = GetMemW(DS1, Wreg(IY)); UINT32 dst = Wreg(AW); SUBW; Wreg(IY) += -4 * m_DF + 2; CLKW(8,8,5,8,4,3,Wreg(IY)); }
OP( 0xb0, i_mov_ald8 ) { Breg(AL) = FETCH(); CLKS(4,4,2); }
OP( 0xb1, i_mov_cld8 ) { Breg(CL) = FETCH(); CLKS(4,4,2); }
@ -410,7 +410,7 @@ OP( 0xc0, i_rotshft_bd8 ) {
case 0x18: do { RORC_BYTE; c--; CLK(1); } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break;
case 0x20: SHL_BYTE(c); break;
case 0x28: SHR_BYTE(c); break;
case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",PC(nec_state)); break;
case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",PC()); break;
case 0x38: SHRA_BYTE(c); break;
}
}
@ -427,23 +427,23 @@ OP( 0xc1, i_rotshft_wd8 ) {
case 0x18: do { RORC_WORD; c--; CLK(1); } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break;
case 0x20: SHL_WORD(c); break;
case 0x28: SHR_WORD(c); break;
case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",PC(nec_state)); break;
case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",PC()); break;
case 0x38: SHRA_WORD(c); break;
}
}
OP( 0xc2, i_ret_d16 ) { UINT32 count = FETCH(); count += FETCH() << 8; POP(nec_state->ip); Wreg(SP)+=count; CHANGE_PC; CLKS(24,24,10); }
OP( 0xc3, i_ret ) { POP(nec_state->ip); CHANGE_PC; CLKS(19,19,10); }
OP( 0xc4, i_les_dw ) { GetModRM; WORD tmp = GetRMWord(ModRM); RegWord(ModRM)=tmp; Sreg(DS1) = GetnextRMWord; CLKW(26,26,14,26,18,10,EA); }
OP( 0xc5, i_lds_dw ) { GetModRM; WORD tmp = GetRMWord(ModRM); RegWord(ModRM)=tmp; Sreg(DS0) = GetnextRMWord; CLKW(26,26,14,26,18,10,EA); }
OP( 0xc6, i_mov_bd8 ) { GetModRM; PutImmRMByte(ModRM); nec_state->icount-=(ModRM >=0xc0 )?4:11; }
OP( 0xc7, i_mov_wd16 ) { GetModRM; PutImmRMWord(ModRM); nec_state->icount-=(ModRM >=0xc0 )?4:15; }
OP( 0xc2, i_ret_d16 ) { UINT32 count = FETCH(); count += FETCH() << 8; POP(m_ip); Wreg(SP)+=count; CHANGE_PC; CLKS(24,24,10); }
OP( 0xc3, i_ret ) { POP(m_ip); CHANGE_PC; CLKS(19,19,10); }
OP( 0xc4, i_les_dw ) { GetModRM; WORD tmp = GetRMWord(ModRM); RegWord(ModRM)=tmp; Sreg(DS1) = GetnextRMWord; CLKW(26,26,14,26,18,10,m_EA); }
OP( 0xc5, i_lds_dw ) { GetModRM; WORD tmp = GetRMWord(ModRM); RegWord(ModRM)=tmp; Sreg(DS0) = GetnextRMWord; CLKW(26,26,14,26,18,10,m_EA); }
OP( 0xc6, i_mov_bd8 ) { GetModRM; PutImmRMByte(ModRM); m_icount-=(ModRM >=0xc0 )?4:11; }
OP( 0xc7, i_mov_wd16 ) { GetModRM; PutImmRMWord(ModRM); m_icount-=(ModRM >=0xc0 )?4:15; }
OP( 0xc8, i_enter ) {
UINT32 nb = FETCH();
UINT32 i,level;
nec_state->icount-=23;
m_icount-=23;
nb += FETCH() << 8;
level = FETCH();
PUSH(Wreg(BP));
@ -451,34 +451,34 @@ OP( 0xc8, i_enter ) {
Wreg(SP) -= nb;
for (i=1;i<level;i++) {
PUSH(GetMemW(SS,Wreg(BP)-i*2));
nec_state->icount-=16;
m_icount-=16;
}
if (level) PUSH(Wreg(BP));
}
OP( 0xc9, i_leave ) {
Wreg(SP)=Wreg(BP);
POP(Wreg(BP));
nec_state->icount-=8;
m_icount-=8;
}
OP( 0xca, i_retf_d16 ) { UINT32 count = FETCH(); count += FETCH() << 8; POP(nec_state->ip); POP(Sreg(PS)); Wreg(SP)+=count; CHANGE_PC; CLKS(32,32,16); }
OP( 0xcb, i_retf ) { POP(nec_state->ip); POP(Sreg(PS)); CHANGE_PC; CLKS(29,29,16); }
OP( 0xcc, i_int3 ) { nec_interrupt(nec_state, 3, BRK); CLKS(50,50,24); }
OP( 0xcd, i_int ) { nec_interrupt(nec_state, FETCH(), BRK); CLKS(50,50,24); }
OP( 0xce, i_into ) { if (OF) { nec_interrupt(nec_state, NEC_BRKV_VECTOR, BRK); CLKS(52,52,26); } else CLK(3); }
OP( 0xcf, i_iret ) { POP(nec_state->ip); POP(Sreg(PS)); i_popf(nec_state); CHANGE_PC; CLKS(39,39,19); }
OP( 0xca, i_retf_d16 ) { UINT32 count = FETCH(); count += FETCH() << 8; POP(m_ip); POP(Sreg(PS)); Wreg(SP)+=count; CHANGE_PC; CLKS(32,32,16); }
OP( 0xcb, i_retf ) { POP(m_ip); POP(Sreg(PS)); CHANGE_PC; CLKS(29,29,16); }
OP( 0xcc, i_int3 ) { nec_interrupt(3, BRK); CLKS(50,50,24); }
OP( 0xcd, i_int ) { nec_interrupt(FETCH(), BRK); CLKS(50,50,24); }
OP( 0xce, i_into ) { if (OF) { nec_interrupt(NEC_BRKV_VECTOR, BRK); CLKS(52,52,26); } else CLK(3); }
OP( 0xcf, i_iret ) { POP(m_ip); POP(Sreg(PS)); i_popf(); CHANGE_PC; CLKS(39,39,19); }
OP( 0xd0, i_rotshft_b ) {
UINT32 src, dst; GetModRM; src = (UINT32)GetRMByte(ModRM); dst=src;
CLKM(6,6,2,16,16,7);
switch (ModRM & 0x38) {
case 0x00: ROL_BYTE; PutbackRMByte(ModRM,(BYTE)dst); nec_state->OverVal = (src^dst)&0x80; break;
case 0x08: ROR_BYTE; PutbackRMByte(ModRM,(BYTE)dst); nec_state->OverVal = (src^dst)&0x80; break;
case 0x10: ROLC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); nec_state->OverVal = (src^dst)&0x80; break;
case 0x18: RORC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); nec_state->OverVal = (src^dst)&0x80; break;
case 0x20: SHL_BYTE(1); nec_state->OverVal = (src^dst)&0x80; break;
case 0x28: SHR_BYTE(1); nec_state->OverVal = (src^dst)&0x80; break;
case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",PC(nec_state)); break;
case 0x38: SHRA_BYTE(1); nec_state->OverVal = 0; break;
case 0x00: ROL_BYTE; PutbackRMByte(ModRM,(BYTE)dst); m_OverVal = (src^dst)&0x80; break;
case 0x08: ROR_BYTE; PutbackRMByte(ModRM,(BYTE)dst); m_OverVal = (src^dst)&0x80; break;
case 0x10: ROLC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); m_OverVal = (src^dst)&0x80; break;
case 0x18: RORC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); m_OverVal = (src^dst)&0x80; break;
case 0x20: SHL_BYTE(1); m_OverVal = (src^dst)&0x80; break;
case 0x28: SHR_BYTE(1); m_OverVal = (src^dst)&0x80; break;
case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",PC()); break;
case 0x38: SHRA_BYTE(1); m_OverVal = 0; break;
}
}
@ -486,14 +486,14 @@ OP( 0xd1, i_rotshft_w ) {
UINT32 src, dst; GetModRM; src = (UINT32)GetRMWord(ModRM); dst=src;
CLKM(6,6,2,24,16,7);
switch (ModRM & 0x38) {
case 0x00: ROL_WORD; PutbackRMWord(ModRM,(WORD)dst); nec_state->OverVal = (src^dst)&0x8000; break;
case 0x08: ROR_WORD; PutbackRMWord(ModRM,(WORD)dst); nec_state->OverVal = (src^dst)&0x8000; break;
case 0x10: ROLC_WORD; PutbackRMWord(ModRM,(WORD)dst); nec_state->OverVal = (src^dst)&0x8000; break;
case 0x18: RORC_WORD; PutbackRMWord(ModRM,(WORD)dst); nec_state->OverVal = (src^dst)&0x8000; break;
case 0x20: SHL_WORD(1); nec_state->OverVal = (src^dst)&0x8000; break;
case 0x28: SHR_WORD(1); nec_state->OverVal = (src^dst)&0x8000; break;
case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",PC(nec_state)); break;
case 0x38: SHRA_WORD(1); nec_state->OverVal = 0; break;
case 0x00: ROL_WORD; PutbackRMWord(ModRM,(WORD)dst); m_OverVal = (src^dst)&0x8000; break;
case 0x08: ROR_WORD; PutbackRMWord(ModRM,(WORD)dst); m_OverVal = (src^dst)&0x8000; break;
case 0x10: ROLC_WORD; PutbackRMWord(ModRM,(WORD)dst); m_OverVal = (src^dst)&0x8000; break;
case 0x18: RORC_WORD; PutbackRMWord(ModRM,(WORD)dst); m_OverVal = (src^dst)&0x8000; break;
case 0x20: SHL_WORD(1); m_OverVal = (src^dst)&0x8000; break;
case 0x28: SHR_WORD(1); m_OverVal = (src^dst)&0x8000; break;
case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",PC()); break;
case 0x38: SHRA_WORD(1); m_OverVal = 0; break;
}
}
@ -508,7 +508,7 @@ OP( 0xd2, i_rotshft_bcl ) {
case 0x18: do { RORC_BYTE; c--; CLK(1); } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break;
case 0x20: SHL_BYTE(c); break;
case 0x28: SHR_BYTE(c); break;
case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",PC(nec_state)); break;
case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",PC()); break;
case 0x38: SHRA_BYTE(c); break;
}
}
@ -524,148 +524,148 @@ OP( 0xd3, i_rotshft_wcl ) {
case 0x18: do { RORC_WORD; c--; CLK(1); } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break;
case 0x20: SHL_WORD(c); break;
case 0x28: SHR_WORD(c); break;
case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",PC(nec_state)); break;
case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",PC()); break;
case 0x38: SHRA_WORD(c); break;
}
}
OP( 0xd4, i_aam ) { FETCH(); Breg(AH) = Breg(AL) / 10; Breg(AL) %= 10; SetSZPF_Word(Wreg(AW)); CLKS(15,15,12); }
OP( 0xd5, i_aad ) { FETCH(); Breg(AL) = Breg(AH) * 10 + Breg(AL); Breg(AH) = 0; SetSZPF_Byte(Breg(AL)); CLKS(7,7,8); }
OP( 0xd6, i_setalc ) { Breg(AL) = (CF)?0xff:0x00; nec_state->icount-=3; logerror("%06x: Undefined opcode (SETALC)\n",PC(nec_state)); }
OP( 0xd6, i_setalc ) { Breg(AL) = (CF)?0xff:0x00; m_icount-=3; logerror("%06x: Undefined opcode (SETALC)\n",PC()); }
OP( 0xd7, i_trans ) { UINT32 dest = (Wreg(BW)+Breg(AL))&0xffff; Breg(AL) = GetMemB(DS0, dest); CLKS(9,9,5); }
OP( 0xd8, i_fpo ) { GetModRM; nec_state->icount-=2; logerror("%06x: Unimplemented floating point control %04x\n",PC(nec_state),ModRM); }
OP( 0xd8, i_fpo ) { GetModRM; m_icount-=2; logerror("%06x: Unimplemented floating point control %04x\n",PC(),ModRM); }
OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH(); Wreg(CW)--; if (!ZF && Wreg(CW)) { nec_state->ip = (WORD)(nec_state->ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); }
OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH(); Wreg(CW)--; if ( ZF && Wreg(CW)) { nec_state->ip = (WORD)(nec_state->ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); }
OP( 0xe2, i_loop ) { INT8 disp = (INT8)FETCH(); Wreg(CW)--; if (Wreg(CW)) { nec_state->ip = (WORD)(nec_state->ip+disp); /*CHANGE_PC;*/ CLKS(13,13,6); } else CLKS(5,5,3); }
OP( 0xe3, i_jcxz ) { INT8 disp = (INT8)FETCH(); if (Wreg(CW) == 0) { nec_state->ip = (WORD)(nec_state->ip+disp); /*CHANGE_PC;*/ CLKS(13,13,6); } else CLKS(5,5,3); }
OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH(); Wreg(CW)--; if (!ZF && Wreg(CW)) { m_ip = (WORD)(m_ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); }
OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH(); Wreg(CW)--; if ( ZF && Wreg(CW)) { m_ip = (WORD)(m_ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); }
OP( 0xe2, i_loop ) { INT8 disp = (INT8)FETCH(); Wreg(CW)--; if (Wreg(CW)) { m_ip = (WORD)(m_ip+disp); /*CHANGE_PC;*/ CLKS(13,13,6); } else CLKS(5,5,3); }
OP( 0xe3, i_jcxz ) { INT8 disp = (INT8)FETCH(); if (Wreg(CW) == 0) { m_ip = (WORD)(m_ip+disp); /*CHANGE_PC;*/ CLKS(13,13,6); } else CLKS(5,5,3); }
OP( 0xe4, i_inal ) { UINT8 port = FETCH(); Breg(AL) = read_port_byte(port); CLKS(9,9,5); }
OP( 0xe5, i_inax ) { UINT8 port = FETCH(); Wreg(AW) = read_port_word(port); CLKW(13,13,7,13,9,5,port); }
OP( 0xe6, i_outal ) { UINT8 port = FETCH(); write_port_byte(port, Breg(AL)); CLKS(8,8,3); }
OP( 0xe7, i_outax ) { UINT8 port = FETCH(); write_port_word(port, Wreg(AW)); CLKW(12,12,5,12,8,3,port); }
OP( 0xe8, i_call_d16 ) { UINT32 tmp; tmp = FETCHWORD(); PUSH(nec_state->ip); nec_state->ip = (WORD)(nec_state->ip+(INT16)tmp); CHANGE_PC; nec_state->icount-=24; }
OP( 0xe9, i_jmp_d16 ) { UINT32 tmp; tmp = FETCHWORD(); nec_state->ip = (WORD)(nec_state->ip+(INT16)tmp); CHANGE_PC; nec_state->icount-=15; }
OP( 0xea, i_jmp_far ) { UINT32 tmp,tmp1; tmp = FETCHWORD(); tmp1 = FETCHWORD(); Sreg(PS) = (WORD)tmp1; nec_state->ip = (WORD)tmp; CHANGE_PC; nec_state->icount-=27; }
OP( 0xeb, i_jmp_d8 ) { int tmp = (int)((INT8)FETCH()); nec_state->icount-=12; nec_state->ip = (WORD)(nec_state->ip+tmp); }
OP( 0xe8, i_call_d16 ) { UINT32 tmp; tmp = FETCHWORD(); PUSH(m_ip); m_ip = (WORD)(m_ip+(INT16)tmp); CHANGE_PC; m_icount-=24; }
OP( 0xe9, i_jmp_d16 ) { UINT32 tmp; tmp = FETCHWORD(); m_ip = (WORD)(m_ip+(INT16)tmp); CHANGE_PC; m_icount-=15; }
OP( 0xea, i_jmp_far ) { UINT32 tmp,tmp1; tmp = FETCHWORD(); tmp1 = FETCHWORD(); Sreg(PS) = (WORD)tmp1; m_ip = (WORD)tmp; CHANGE_PC; m_icount-=27; }
OP( 0xeb, i_jmp_d8 ) { int tmp = (int)((INT8)FETCH()); m_icount-=12; m_ip = (WORD)(m_ip+tmp); }
OP( 0xec, i_inaldx ) { Breg(AL) = read_port_byte(Wreg(DW)); CLKS(8,8,5);}
OP( 0xed, i_inaxdx ) { Wreg(AW) = read_port_word(Wreg(DW)); CLKW(12,12,7,12,8,5,Wreg(DW)); }
OP( 0xee, i_outdxal ) { write_port_byte(Wreg(DW), Breg(AL)); CLKS(8,8,3); }
OP( 0xef, i_outdxax ) { write_port_word(Wreg(DW), Wreg(AW)); CLKW(12,12,5,12,8,3,Wreg(DW)); }
OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",PC(nec_state)); nec_state->no_interrupt=1; CLK(2); }
OP( 0xf2, i_repne ) { UINT32 next = fetchop(nec_state); UINT16 c = Wreg(CW);
OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",PC()); m_no_interrupt=1; CLK(2); }
OP( 0xf2, i_repne ) { UINT32 next = fetchop(); UINT16 c = Wreg(CW);
switch(next) { /* Segments */
case 0x26: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS1)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x2e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(PS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x36: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(SS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x3e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS0)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x26: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS1)<<4; next = fetchop(); CLK(2); break;
case 0x2e: m_seg_prefix=TRUE; m_prefix_base=Sreg(PS)<<4; next = fetchop(); CLK(2); break;
case 0x36: m_seg_prefix=TRUE; m_prefix_base=Sreg(SS)<<4; next = fetchop(); CLK(2); break;
case 0x3e: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS0)<<4; next = fetchop(); CLK(2); break;
}
switch(next) {
case 0x6c: CLK(2); if (c) do { i_insb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(nec_state); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(nec_state); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
default: logerror("%06x: REPNE invalid\n",PC(nec_state)); nec_instruction[next](nec_state);
case 0x6c: CLK(2); if (c) do { i_insb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && ZF==0); Wreg(CW)=c; break;
default: logerror("%06x: REPNE invalid\n",PC()); (this->*s_nec_instruction[next])();
}
nec_state->seg_prefix=FALSE;
m_seg_prefix=FALSE;
}
OP( 0xf3, i_repe ) { UINT32 next = fetchop(nec_state); UINT16 c = Wreg(CW);
OP( 0xf3, i_repe ) { UINT32 next = fetchop(); UINT16 c = Wreg(CW);
switch(next) { /* Segments */
case 0x26: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS1)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x2e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(PS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x36: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(SS)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x3e: nec_state->seg_prefix=TRUE; nec_state->prefix_base=Sreg(DS0)<<4; next = fetchop(nec_state); CLK(2); break;
case 0x26: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS1)<<4; next = fetchop(); CLK(2); break;
case 0x2e: m_seg_prefix=TRUE; m_prefix_base=Sreg(PS)<<4; next = fetchop(); CLK(2); break;
case 0x36: m_seg_prefix=TRUE; m_prefix_base=Sreg(SS)<<4; next = fetchop(); CLK(2); break;
case 0x3e: m_seg_prefix=TRUE; m_prefix_base=Sreg(DS0)<<4; next = fetchop(); CLK(2); break;
}
switch(next) {
case 0x6c: CLK(2); if (c) do { i_insb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(nec_state); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(nec_state); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(nec_state); c--; } while (c>0); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(nec_state); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(nec_state); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
default: logerror("%06x: REPE invalid\n",PC(nec_state)); nec_instruction[next](nec_state);
case 0x6c: CLK(2); if (c) do { i_insb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6d: CLK(2); if (c) do { i_insw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6e: CLK(2); if (c) do { i_outsb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0x6f: CLK(2); if (c) do { i_outsw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa4: CLK(2); if (c) do { i_movsb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa5: CLK(2); if (c) do { i_movsw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xa6: CLK(2); if (c) do { i_cmpsb(); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
case 0xa7: CLK(2); if (c) do { i_cmpsw(); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
case 0xaa: CLK(2); if (c) do { i_stosb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xab: CLK(2); if (c) do { i_stosw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xac: CLK(2); if (c) do { i_lodsb(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0); Wreg(CW)=c; break;
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && ZF==1); Wreg(CW)=c; break;
default: logerror("%06x: REPE invalid\n",PC()); (this->*s_nec_instruction[next])();
}
nec_state->seg_prefix=FALSE;
m_seg_prefix=FALSE;
}
OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",PC(nec_state)); nec_state->halted=1; nec_state->icount=0; }
OP( 0xf5, i_cmc ) { nec_state->CarryVal = !CF; CLK(2); }
OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",PC()); m_halted=1; m_icount=0; }
OP( 0xf5, i_cmc ) { m_CarryVal = !CF; CLK(2); }
OP( 0xf6, i_f6pre ) { UINT32 tmp; UINT32 uresult,uresult2; INT32 result,result2;
GetModRM; tmp = GetRMByte(ModRM);
switch (ModRM & 0x38) {
case 0x00: tmp &= FETCH(); nec_state->CarryVal = nec_state->OverVal = 0; SetSZPF_Byte(tmp); nec_state->icount-=(ModRM >=0xc0 )?4:11; break; /* TEST */
case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",PC(nec_state)); break;
case 0x10: PutbackRMByte(ModRM,~tmp); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NOT */
case 0x18: nec_state->CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Byte(tmp); PutbackRMByte(ModRM,tmp&0xff); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NEG */
case 0x20: uresult = Breg(AL)*tmp; Wreg(AW)=(WORD)uresult; nec_state->CarryVal=nec_state->OverVal=(Breg(AH)!=0); nec_state->icount-=(ModRM >=0xc0 )?30:36; break; /* MULU */
case 0x28: result = (INT16)((INT8)Breg(AL))*(INT16)((INT8)tmp); Wreg(AW)=(WORD)result; nec_state->CarryVal=nec_state->OverVal=(Breg(AH)!=0); nec_state->icount-=(ModRM >=0xc0 )?30:36; break; /* MUL */
case 0x30: if (tmp) { DIVUB; } else nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); nec_state->icount-=(ModRM >=0xc0 )?43:53; break;
case 0x38: if (tmp) { DIVB; } else nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); nec_state->icount-=(ModRM >=0xc0 )?43:53; break;
case 0x00: tmp &= FETCH(); m_CarryVal = m_OverVal = 0; SetSZPF_Byte(tmp); m_icount-=(ModRM >=0xc0 )?4:11; break; /* TEST */
case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",PC()); break;
case 0x10: PutbackRMByte(ModRM,~tmp); m_icount-=(ModRM >=0xc0 )?2:16; break; /* NOT */
case 0x18: m_CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Byte(tmp); PutbackRMByte(ModRM,tmp&0xff); m_icount-=(ModRM >=0xc0 )?2:16; break; /* NEG */
case 0x20: uresult = Breg(AL)*tmp; Wreg(AW)=(WORD)uresult; m_CarryVal=m_OverVal=(Breg(AH)!=0); m_icount-=(ModRM >=0xc0 )?30:36; break; /* MULU */
case 0x28: result = (INT16)((INT8)Breg(AL))*(INT16)((INT8)tmp); Wreg(AW)=(WORD)result; m_CarryVal=m_OverVal=(Breg(AH)!=0); m_icount-=(ModRM >=0xc0 )?30:36; break; /* MUL */
case 0x30: if (tmp) { DIVUB; } else nec_interrupt(NEC_DIVIDE_VECTOR, BRK); m_icount-=(ModRM >=0xc0 )?43:53; break;
case 0x38: if (tmp) { DIVB; } else nec_interrupt(NEC_DIVIDE_VECTOR, BRK); m_icount-=(ModRM >=0xc0 )?43:53; break;
}
}
OP( 0xf7, i_f7pre ) { UINT32 tmp,tmp2; UINT32 uresult,uresult2; INT32 result,result2;
GetModRM; tmp = GetRMWord(ModRM);
switch (ModRM & 0x38) {
case 0x00: tmp2 = FETCHWORD(); tmp &= tmp2; nec_state->CarryVal = nec_state->OverVal = 0; SetSZPF_Word(tmp); nec_state->icount-=(ModRM >=0xc0 )?4:11; break; /* TEST */
case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",PC(nec_state)); break;
case 0x10: PutbackRMWord(ModRM,~tmp); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NOT */
case 0x18: nec_state->CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Word(tmp); PutbackRMWord(ModRM,tmp&0xffff); nec_state->icount-=(ModRM >=0xc0 )?2:16; break; /* NEG */
case 0x20: uresult = Wreg(AW)*tmp; Wreg(AW)=uresult&0xffff; Wreg(DW)=((UINT32)uresult)>>16; nec_state->CarryVal=nec_state->OverVal=(Wreg(DW)!=0); nec_state->icount-=(ModRM >=0xc0 )?30:36; break; /* MULU */
case 0x28: result = (INT32)((INT16)Wreg(AW))*(INT32)((INT16)tmp); Wreg(AW)=result&0xffff; Wreg(DW)=result>>16; nec_state->CarryVal=nec_state->OverVal=(Wreg(DW)!=0); nec_state->icount-=(ModRM >=0xc0 )?30:36; break; /* MUL */
case 0x30: if (tmp) { DIVUW; } else nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); nec_state->icount-=(ModRM >=0xc0 )?43:53; break;
case 0x38: if (tmp) { DIVW; } else nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); nec_state->icount-=(ModRM >=0xc0 )?43:53; break;
case 0x00: tmp2 = FETCHWORD(); tmp &= tmp2; m_CarryVal = m_OverVal = 0; SetSZPF_Word(tmp); m_icount-=(ModRM >=0xc0 )?4:11; break; /* TEST */
case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",PC()); break;
case 0x10: PutbackRMWord(ModRM,~tmp); m_icount-=(ModRM >=0xc0 )?2:16; break; /* NOT */
case 0x18: m_CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Word(tmp); PutbackRMWord(ModRM,tmp&0xffff); m_icount-=(ModRM >=0xc0 )?2:16; break; /* NEG */
case 0x20: uresult = Wreg(AW)*tmp; Wreg(AW)=uresult&0xffff; Wreg(DW)=((UINT32)uresult)>>16; m_CarryVal=m_OverVal=(Wreg(DW)!=0); m_icount-=(ModRM >=0xc0 )?30:36; break; /* MULU */
case 0x28: result = (INT32)((INT16)Wreg(AW))*(INT32)((INT16)tmp); Wreg(AW)=result&0xffff; Wreg(DW)=result>>16; m_CarryVal=m_OverVal=(Wreg(DW)!=0); m_icount-=(ModRM >=0xc0 )?30:36; break; /* MUL */
case 0x30: if (tmp) { DIVUW; } else nec_interrupt(NEC_DIVIDE_VECTOR, BRK); m_icount-=(ModRM >=0xc0 )?43:53; break;
case 0x38: if (tmp) { DIVW; } else nec_interrupt(NEC_DIVIDE_VECTOR, BRK); m_icount-=(ModRM >=0xc0 )?43:53; break;
}
}
OP( 0xf8, i_clc ) { nec_state->CarryVal = 0; CLK(2); }
OP( 0xf9, i_stc ) { nec_state->CarryVal = 1; CLK(2); }
OP( 0xf8, i_clc ) { m_CarryVal = 0; CLK(2); }
OP( 0xf9, i_stc ) { m_CarryVal = 1; CLK(2); }
OP( 0xfa, i_di ) { SetIF(0); CLK(2); }
OP( 0xfb, i_ei ) { SetIF(1); CLK(2); }
OP( 0xfc, i_cld ) { SetDF(0); CLK(2); }
OP( 0xfd, i_std ) { SetDF(1); CLK(2); }
OP( 0xfe, i_fepre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMByte(ModRM);
switch(ModRM & 0x38) {
case 0x00: tmp1 = tmp+1; nec_state->OverVal = (tmp==0x7f); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* INC */
case 0x08: tmp1 = tmp-1; nec_state->OverVal = (tmp==0x80); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* DEC */
default: logerror("%06x: FE Pre with unimplemented mod\n",PC(nec_state));
case 0x00: tmp1 = tmp+1; m_OverVal = (tmp==0x7f); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* INC */
case 0x08: tmp1 = tmp-1; m_OverVal = (tmp==0x80); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* DEC */
default: logerror("%06x: FE Pre with unimplemented mod\n",PC());
}
}
OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM);
switch(ModRM & 0x38) {
case 0x00: tmp1 = tmp+1; nec_state->OverVal = (tmp==0x7fff); SetAF(tmp1,tmp,1); SetSZPF_Word(tmp1); PutbackRMWord(ModRM,(WORD)tmp1); CLKM(2,2,2,24,16,7); break; /* INC */
case 0x08: tmp1 = tmp-1; nec_state->OverVal = (tmp==0x8000); SetAF(tmp1,tmp,1); SetSZPF_Word(tmp1); PutbackRMWord(ModRM,(WORD)tmp1); CLKM(2,2,2,24,16,7); break; /* DEC */
case 0x10: PUSH(nec_state->ip); nec_state->ip = (WORD)tmp; CHANGE_PC; nec_state->icount-=(ModRM >=0xc0 )?16:20; break; /* CALL */
case 0x18: tmp1 = Sreg(PS); Sreg(PS) = GetnextRMWord; PUSH(tmp1); PUSH(nec_state->ip); nec_state->ip = tmp; CHANGE_PC; nec_state->icount-=(ModRM >=0xc0 )?16:26; break; /* CALL FAR */
case 0x20: nec_state->ip = tmp; CHANGE_PC; nec_state->icount-=13; break; /* JMP */
case 0x28: nec_state->ip = tmp; Sreg(PS) = GetnextRMWord; CHANGE_PC; nec_state->icount-=15; break; /* JMP FAR */
case 0x30: PUSH(tmp); nec_state->icount-=4; break;
default: logerror("%06x: FF Pre with unimplemented mod\n",PC(nec_state));
case 0x00: tmp1 = tmp+1; m_OverVal = (tmp==0x7fff); SetAF(tmp1,tmp,1); SetSZPF_Word(tmp1); PutbackRMWord(ModRM,(WORD)tmp1); CLKM(2,2,2,24,16,7); break; /* INC */
case 0x08: tmp1 = tmp-1; m_OverVal = (tmp==0x8000); SetAF(tmp1,tmp,1); SetSZPF_Word(tmp1); PutbackRMWord(ModRM,(WORD)tmp1); CLKM(2,2,2,24,16,7); break; /* DEC */
case 0x10: PUSH(m_ip); m_ip = (WORD)tmp; CHANGE_PC; m_icount-=(ModRM >=0xc0 )?16:20; break; /* CALL */
case 0x18: tmp1 = Sreg(PS); Sreg(PS) = GetnextRMWord; PUSH(tmp1); PUSH(m_ip); m_ip = tmp; CHANGE_PC; m_icount-=(ModRM >=0xc0 )?16:26; break; /* CALL FAR */
case 0x20: m_ip = tmp; CHANGE_PC; m_icount-=13; break; /* JMP */
case 0x28: m_ip = tmp; Sreg(PS) = GetnextRMWord; CHANGE_PC; m_icount-=15; break; /* JMP FAR */
case 0x30: PUSH(tmp); m_icount-=4; break;
default: logerror("%06x: FF Pre with unimplemented mod\n",PC());
}
}
static void i_invalid(nec_state_t *nec_state)
void nec_common_device::i_invalid()
{
nec_state->icount-=10;
logerror("%06x: Invalid Opcode\n",PC(nec_state));
m_icount-=10;
logerror("%06x: Invalid Opcode\n",PC());
}

761
src/emu/cpu/nec/necinstr.h
View File

@ -1,507 +1,260 @@
static void i_add_br8(nec_state_t *nec_state);
static void i_add_wr16(nec_state_t *nec_state);
static void i_add_r8b(nec_state_t *nec_state);
static void i_add_r16w(nec_state_t *nec_state);
static void i_add_ald8(nec_state_t *nec_state);
static void i_add_axd16(nec_state_t *nec_state);
static void i_push_es(nec_state_t *nec_state);
static void i_pop_es(nec_state_t *nec_state);
static void i_or_br8(nec_state_t *nec_state);
static void i_or_r8b(nec_state_t *nec_state);
static void i_or_wr16(nec_state_t *nec_state);
static void i_or_r16w(nec_state_t *nec_state);
static void i_or_ald8(nec_state_t *nec_state);
static void i_or_axd16(nec_state_t *nec_state);
static void i_push_cs(nec_state_t *nec_state);
static void i_pre_nec(nec_state_t *nec_state);
static void i_adc_br8(nec_state_t *nec_state);
static void i_adc_wr16(nec_state_t *nec_state);
static void i_adc_r8b(nec_state_t *nec_state);
static void i_adc_r16w(nec_state_t *nec_state);
static void i_adc_ald8(nec_state_t *nec_state);
static void i_adc_axd16(nec_state_t *nec_state);
static void i_push_ss(nec_state_t *nec_state);
static void i_pop_ss(nec_state_t *nec_state);
static void i_sbb_br8(nec_state_t *nec_state);
static void i_sbb_wr16(nec_state_t *nec_state);
static void i_sbb_r8b(nec_state_t *nec_state);
static void i_sbb_r16w(nec_state_t *nec_state);
static void i_sbb_ald8(nec_state_t *nec_state);
static void i_sbb_axd16(nec_state_t *nec_state);
static void i_push_ds(nec_state_t *nec_state);
static void i_pop_ds(nec_state_t *nec_state);
static void i_and_br8(nec_state_t *nec_state);
static void i_and_r8b(nec_state_t *nec_state);
static void i_and_wr16(nec_state_t *nec_state);
static void i_and_r16w(nec_state_t *nec_state);
static void i_and_ald8(nec_state_t *nec_state);
static void i_and_axd16(nec_state_t *nec_state);
static void i_es(nec_state_t *nec_state);
static void i_daa(nec_state_t *nec_state);
static void i_sub_br8(nec_state_t *nec_state);
static void i_sub_wr16(nec_state_t *nec_state);
static void i_sub_r8b(nec_state_t *nec_state);
static void i_sub_r16w(nec_state_t *nec_state);
static void i_sub_ald8(nec_state_t *nec_state);
static void i_sub_axd16(nec_state_t *nec_state);
static void i_cs(nec_state_t *nec_state);
static void i_das(nec_state_t *nec_state);
static void i_xor_br8(nec_state_t *nec_state);
static void i_xor_r8b(nec_state_t *nec_state);
static void i_xor_wr16(nec_state_t *nec_state);
static void i_xor_r16w(nec_state_t *nec_state);
static void i_xor_ald8(nec_state_t *nec_state);
static void i_xor_axd16(nec_state_t *nec_state);
static void i_ss(nec_state_t *nec_state);
static void i_aaa(nec_state_t *nec_state);
static void i_cmp_br8(nec_state_t *nec_state);
static void i_cmp_wr16(nec_state_t *nec_state);
static void i_cmp_r8b(nec_state_t *nec_state);
static void i_cmp_r16w(nec_state_t *nec_state);
static void i_cmp_ald8(nec_state_t *nec_state);
static void i_cmp_axd16(nec_state_t *nec_state);
static void i_ds(nec_state_t *nec_state);
static void i_aas(nec_state_t *nec_state);
static void i_inc_ax(nec_state_t *nec_state);
static void i_inc_cx(nec_state_t *nec_state);
static void i_inc_dx(nec_state_t *nec_state);
static void i_inc_bx(nec_state_t *nec_state);
static void i_inc_sp(nec_state_t *nec_state);
static void i_inc_bp(nec_state_t *nec_state);
static void i_inc_si(nec_state_t *nec_state);
static void i_inc_di(nec_state_t *nec_state);
static void i_dec_ax(nec_state_t *nec_state);
static void i_dec_cx(nec_state_t *nec_state);
static void i_dec_dx(nec_state_t *nec_state);
static void i_dec_bx(nec_state_t *nec_state);
static void i_dec_sp(nec_state_t *nec_state);
static void i_dec_bp(nec_state_t *nec_state);
static void i_dec_si(nec_state_t *nec_state);
static void i_dec_di(nec_state_t *nec_state);
static void i_push_ax(nec_state_t *nec_state);
static void i_push_cx(nec_state_t *nec_state);
static void i_push_dx(nec_state_t *nec_state);
static void i_push_bx(nec_state_t *nec_state);
static void i_push_sp(nec_state_t *nec_state);
static void i_push_bp(nec_state_t *nec_state);
static void i_push_si(nec_state_t *nec_state);
static void i_push_di(nec_state_t *nec_state);
static void i_pop_ax(nec_state_t *nec_state);
static void i_pop_cx(nec_state_t *nec_state);
static void i_pop_dx(nec_state_t *nec_state);
static void i_pop_bx(nec_state_t *nec_state);
static void i_pop_sp(nec_state_t *nec_state);
static void i_pop_bp(nec_state_t *nec_state);
static void i_pop_si(nec_state_t *nec_state);
static void i_pop_di(nec_state_t *nec_state);
static void i_pusha(nec_state_t *nec_state);
static void i_popa(nec_state_t *nec_state);
static void i_chkind(nec_state_t *nec_state);
static void i_repnc(nec_state_t *nec_state);
static void i_repc(nec_state_t *nec_state);
static void i_push_d16(nec_state_t *nec_state);
static void i_imul_d16(nec_state_t *nec_state);
static void i_push_d8(nec_state_t *nec_state);
static void i_imul_d8(nec_state_t *nec_state);
static void i_insb(nec_state_t *nec_state);
static void i_insw(nec_state_t *nec_state);
static void i_outsb(nec_state_t *nec_state);
static void i_outsw(nec_state_t *nec_state);
static void i_jo(nec_state_t *nec_state);
static void i_jno(nec_state_t *nec_state);
static void i_jc(nec_state_t *nec_state);
static void i_jnc(nec_state_t *nec_state);
static void i_jz(nec_state_t *nec_state);
static void i_jnz(nec_state_t *nec_state);
static void i_jce(nec_state_t *nec_state);
static void i_jnce(nec_state_t *nec_state);
static void i_js(nec_state_t *nec_state);
static void i_jns(nec_state_t *nec_state);
static void i_jp(nec_state_t *nec_state);
static void i_jnp(nec_state_t *nec_state);
static void i_jl(nec_state_t *nec_state);
static void i_jnl(nec_state_t *nec_state);
static void i_jle(nec_state_t *nec_state);
static void i_jnle(nec_state_t *nec_state);
static void i_80pre(nec_state_t *nec_state);
static void i_82pre(nec_state_t *nec_state);
static void i_81pre(nec_state_t *nec_state);
static void i_83pre(nec_state_t *nec_state);
static void i_test_br8(nec_state_t *nec_state);
static void i_test_wr16(nec_state_t *nec_state);
static void i_xchg_br8(nec_state_t *nec_state);
static void i_xchg_wr16(nec_state_t *nec_state);
static void i_mov_br8(nec_state_t *nec_state);
static void i_mov_r8b(nec_state_t *nec_state);
static void i_mov_wr16(nec_state_t *nec_state);
static void i_mov_r16w(nec_state_t *nec_state);
static void i_mov_wsreg(nec_state_t *nec_state);
static void i_lea(nec_state_t *nec_state);
static void i_mov_sregw(nec_state_t *nec_state);
static void i_invalid(nec_state_t *nec_state);
static void i_popw(nec_state_t *nec_state);
static void i_nop(nec_state_t *nec_state);
static void i_xchg_axcx(nec_state_t *nec_state);
static void i_xchg_axdx(nec_state_t *nec_state);
static void i_xchg_axbx(nec_state_t *nec_state);
static void i_xchg_axsp(nec_state_t *nec_state);
static void i_xchg_axbp(nec_state_t *nec_state);
static void i_xchg_axsi(nec_state_t *nec_state);
static void i_xchg_axdi(nec_state_t *nec_state);
static void i_cbw(nec_state_t *nec_state);
static void i_cwd(nec_state_t *nec_state);
static void i_call_far(nec_state_t *nec_state);
static void i_pushf(nec_state_t *nec_state);
static void i_popf(nec_state_t *nec_state);
static void i_sahf(nec_state_t *nec_state);
static void i_lahf(nec_state_t *nec_state);
static void i_mov_aldisp(nec_state_t *nec_state);
static void i_mov_axdisp(nec_state_t *nec_state);
static void i_mov_dispal(nec_state_t *nec_state);
static void i_mov_dispax(nec_state_t *nec_state);
static void i_movsb(nec_state_t *nec_state);
static void i_movsw(nec_state_t *nec_state);
static void i_cmpsb(nec_state_t *nec_state);
static void i_cmpsw(nec_state_t *nec_state);
static void i_test_ald8(nec_state_t *nec_state);
static void i_test_axd16(nec_state_t *nec_state);
static void i_stosb(nec_state_t *nec_state);
static void i_stosw(nec_state_t *nec_state);
static void i_lodsb(nec_state_t *nec_state);
static void i_lodsw(nec_state_t *nec_state);
static void i_scasb(nec_state_t *nec_state);
static void i_scasw(nec_state_t *nec_state);
static void i_mov_ald8(nec_state_t *nec_state);
static void i_mov_cld8(nec_state_t *nec_state);
static void i_mov_dld8(nec_state_t *nec_state);
static void i_mov_bld8(nec_state_t *nec_state);
static void i_mov_ahd8(nec_state_t *nec_state);
static void i_mov_chd8(nec_state_t *nec_state);
static void i_mov_dhd8(nec_state_t *nec_state);
static void i_mov_bhd8(nec_state_t *nec_state);
static void i_mov_axd16(nec_state_t *nec_state);
static void i_mov_cxd16(nec_state_t *nec_state);
static void i_mov_dxd16(nec_state_t *nec_state);
static void i_mov_bxd16(nec_state_t *nec_state);
static void i_mov_spd16(nec_state_t *nec_state);
static void i_mov_bpd16(nec_state_t *nec_state);
static void i_mov_sid16(nec_state_t *nec_state);
static void i_mov_did16(nec_state_t *nec_state);
static void i_rotshft_bd8(nec_state_t *nec_state);
static void i_rotshft_wd8(nec_state_t *nec_state);
static void i_ret_d16(nec_state_t *nec_state);
static void i_ret(nec_state_t *nec_state);
static void i_les_dw(nec_state_t *nec_state);
static void i_lds_dw(nec_state_t *nec_state);
static void i_mov_bd8(nec_state_t *nec_state);
static void i_mov_wd16(nec_state_t *nec_state);
static void i_enter(nec_state_t *nec_state);
static void i_leave(nec_state_t *nec_state);
static void i_retf_d16(nec_state_t *nec_state);
static void i_retf(nec_state_t *nec_state);
static void i_int3(nec_state_t *nec_state);
static void i_int(nec_state_t *nec_state);
static void i_into(nec_state_t *nec_state);
static void i_iret(nec_state_t *nec_state);
static void i_rotshft_b(nec_state_t *nec_state);
static void i_rotshft_w(nec_state_t *nec_state);
static void i_rotshft_bcl(nec_state_t *nec_state);
static void i_rotshft_wcl(nec_state_t *nec_state);
static void i_aam(nec_state_t *nec_state);
static void i_aad(nec_state_t *nec_state);
static void i_setalc(nec_state_t *nec_state);
static void i_trans(nec_state_t *nec_state);
static void i_fpo(nec_state_t *nec_state);
static void i_loopne(nec_state_t *nec_state);
static void i_loope(nec_state_t *nec_state);
static void i_loop(nec_state_t *nec_state);
static void i_jcxz(nec_state_t *nec_state);
static void i_inal(nec_state_t *nec_state);
static void i_inax(nec_state_t *nec_state);
static void i_outal(nec_state_t *nec_state);
static void i_outax(nec_state_t *nec_state);
static void i_call_d16(nec_state_t *nec_state);
static void i_jmp_d16(nec_state_t *nec_state);
static void i_jmp_far(nec_state_t *nec_state);
static void i_jmp_d8(nec_state_t *nec_state);
static void i_inaldx(nec_state_t *nec_state);
static void i_inaxdx(nec_state_t *nec_state);
static void i_outdxal(nec_state_t *nec_state);
static void i_outdxax(nec_state_t *nec_state);
static void i_lock(nec_state_t *nec_state);
static void i_repne(nec_state_t *nec_state);
static void i_repe(nec_state_t *nec_state);
static void i_hlt(nec_state_t *nec_state);
static void i_cmc(nec_state_t *nec_state);
static void i_f6pre(nec_state_t *nec_state);
static void i_f7pre(nec_state_t *nec_state);
static void i_clc(nec_state_t *nec_state);
static void i_stc(nec_state_t *nec_state);
static void i_di(nec_state_t *nec_state);
static void i_ei(nec_state_t *nec_state);
static void i_cld(nec_state_t *nec_state);
static void i_std(nec_state_t *nec_state);
static void i_fepre(nec_state_t *nec_state);
static void i_ffpre(nec_state_t *nec_state);
static void i_wait(nec_state_t *nec_state);
static void (*const nec_instruction[256])(nec_state_t *nec_state) =
const nec_common_device::nec_ophandler nec_common_device::s_nec_instruction[256] =
{
i_add_br8, /* 0x00 */
i_add_wr16, /* 0x01 */
i_add_r8b, /* 0x02 */
i_add_r16w, /* 0x03 */
i_add_ald8, /* 0x04 */
i_add_axd16, /* 0x05 */
i_push_es, /* 0x06 */
i_pop_es, /* 0x07 */
i_or_br8, /* 0x08 */
i_or_wr16, /* 0x09 */
i_or_r8b, /* 0x0a */
i_or_r16w, /* 0x0b */
i_or_ald8, /* 0x0c */
i_or_axd16, /* 0x0d */
i_push_cs, /* 0x0e */
i_pre_nec, /* 0x0f */
i_adc_br8, /* 0x10 */
i_adc_wr16, /* 0x11 */
i_adc_r8b, /* 0x12 */
i_adc_r16w, /* 0x13 */
i_adc_ald8, /* 0x14 */
i_adc_axd16, /* 0x15 */
i_push_ss, /* 0x16 */
i_pop_ss, /* 0x17 */
i_sbb_br8, /* 0x18 */
i_sbb_wr16, /* 0x19 */
i_sbb_r8b, /* 0x1a */
i_sbb_r16w, /* 0x1b */
i_sbb_ald8, /* 0x1c */
i_sbb_axd16, /* 0x1d */
i_push_ds, /* 0x1e */
i_pop_ds, /* 0x1f */
i_and_br8, /* 0x20 */
i_and_wr16, /* 0x21 */
i_and_r8b, /* 0x22 */
i_and_r16w, /* 0x23 */
i_and_ald8, /* 0x24 */
i_and_axd16, /* 0x25 */
i_es, /* 0x26 */
i_daa, /* 0x27 */
i_sub_br8, /* 0x28 */
i_sub_wr16, /* 0x29 */
i_sub_r8b, /* 0x2a */
i_sub_r16w, /* 0x2b */
i_sub_ald8, /* 0x2c */
i_sub_axd16, /* 0x2d */
i_cs, /* 0x2e */
i_das, /* 0x2f */
i_xor_br8, /* 0x30 */
i_xor_wr16, /* 0x31 */
i_xor_r8b, /* 0x32 */
i_xor_r16w, /* 0x33 */
i_xor_ald8, /* 0x34 */
i_xor_axd16, /* 0x35 */
i_ss, /* 0x36 */
i_aaa, /* 0x37 */
i_cmp_br8, /* 0x38 */
i_cmp_wr16, /* 0x39 */
i_cmp_r8b, /* 0x3a */
i_cmp_r16w, /* 0x3b */
i_cmp_ald8, /* 0x3c */
i_cmp_axd16, /* 0x3d */
i_ds, /* 0x3e */
i_aas, /* 0x3f */
i_inc_ax, /* 0x40 */
i_inc_cx, /* 0x41 */
i_inc_dx, /* 0x42 */
i_inc_bx, /* 0x43 */
i_inc_sp, /* 0x44 */
i_inc_bp, /* 0x45 */
i_inc_si, /* 0x46 */
i_inc_di, /* 0x47 */
i_dec_ax, /* 0x48 */
i_dec_cx, /* 0x49 */
i_dec_dx, /* 0x4a */
i_dec_bx, /* 0x4b */
i_dec_sp, /* 0x4c */
i_dec_bp, /* 0x4d */
i_dec_si, /* 0x4e */
i_dec_di, /* 0x4f */
i_push_ax, /* 0x50 */
i_push_cx, /* 0x51 */
i_push_dx, /* 0x52 */
i_push_bx, /* 0x53 */
i_push_sp, /* 0x54 */
i_push_bp, /* 0x55 */
i_push_si, /* 0x56 */
i_push_di, /* 0x57 */
i_pop_ax, /* 0x58 */
i_pop_cx, /* 0x59 */
i_pop_dx, /* 0x5a */
i_pop_bx, /* 0x5b */
i_pop_sp, /* 0x5c */
i_pop_bp, /* 0x5d */
i_pop_si, /* 0x5e */
i_pop_di, /* 0x5f */
i_pusha, /* 0x60 */
i_popa, /* 0x61 */
i_chkind, /* 0x62 */
i_invalid, /* 0x63 */
i_repnc, /* 0x64 */
i_repc, /* 0x65 */
i_invalid, /* 0x66 */
i_invalid, /* 0x67 */
i_push_d16, /* 0x68 */
i_imul_d16, /* 0x69 */
i_push_d8, /* 0x6a */
i_imul_d8, /* 0x6b */
i_insb, /* 0x6c */
i_insw, /* 0x6d */
i_outsb, /* 0x6e */
i_outsw, /* 0x6f */
i_jo, /* 0x70 */
i_jno, /* 0x71 */
i_jc, /* 0x72 */
i_jnc, /* 0x73 */
i_jz, /* 0x74 */
i_jnz, /* 0x75 */
i_jce, /* 0x76 */
i_jnce, /* 0x77 */
i_js, /* 0x78 */
i_jns, /* 0x79 */
i_jp, /* 0x7a */
i_jnp, /* 0x7b */
i_jl, /* 0x7c */
i_jnl, /* 0x7d */
i_jle, /* 0x7e */
i_jnle, /* 0x7f */
i_80pre, /* 0x80 */
i_81pre, /* 0x81 */
i_82pre, /* 0x82 */
i_83pre, /* 0x83 */
i_test_br8, /* 0x84 */
i_test_wr16, /* 0x85 */
i_xchg_br8, /* 0x86 */
i_xchg_wr16, /* 0x87 */
i_mov_br8, /* 0x88 */
i_mov_wr16, /* 0x89 */
i_mov_r8b, /* 0x8a */
i_mov_r16w, /* 0x8b */
i_mov_wsreg, /* 0x8c */
i_lea, /* 0x8d */
i_mov_sregw, /* 0x8e */
i_popw, /* 0x8f */
i_nop, /* 0x90 */
i_xchg_axcx, /* 0x91 */
i_xchg_axdx, /* 0x92 */
i_xchg_axbx, /* 0x93 */
i_xchg_axsp, /* 0x94 */
i_xchg_axbp, /* 0x95 */
i_xchg_axsi, /* 0x96 */
i_xchg_axdi, /* 0x97 */
i_cbw, /* 0x98 */
i_cwd, /* 0x99 */
i_call_far, /* 0x9a */
i_wait, /* 0x9b */
i_pushf, /* 0x9c */
i_popf, /* 0x9d */
i_sahf, /* 0x9e */
i_lahf, /* 0x9f */
i_mov_aldisp, /* 0xa0 */
i_mov_axdisp, /* 0xa1 */
i_mov_dispal, /* 0xa2 */
i_mov_dispax, /* 0xa3 */
i_movsb, /* 0xa4 */
i_movsw, /* 0xa5 */
i_cmpsb, /* 0xa6 */
i_cmpsw, /* 0xa7 */
i_test_ald8, /* 0xa8 */
i_test_axd16, /* 0xa9 */
i_stosb, /* 0xaa */
i_stosw, /* 0xab */
i_lodsb, /* 0xac */
i_lodsw, /* 0xad */
i_scasb, /* 0xae */
i_scasw, /* 0xaf */
i_mov_ald8, /* 0xb0 */
i_mov_cld8, /* 0xb1 */
i_mov_dld8, /* 0xb2 */
i_mov_bld8, /* 0xb3 */
i_mov_ahd8, /* 0xb4 */
i_mov_chd8, /* 0xb5 */
i_mov_dhd8, /* 0xb6 */
i_mov_bhd8, /* 0xb7 */
i_mov_axd16, /* 0xb8 */
i_mov_cxd16, /* 0xb9 */
i_mov_dxd16, /* 0xba */
i_mov_bxd16, /* 0xbb */
i_mov_spd16, /* 0xbc */
i_mov_bpd16, /* 0xbd */
i_mov_sid16, /* 0xbe */
i_mov_did16, /* 0xbf */
i_rotshft_bd8, /* 0xc0 */
i_rotshft_wd8, /* 0xc1 */
i_ret_d16, /* 0xc2 */
i_ret, /* 0xc3 */
i_les_dw, /* 0xc4 */
i_lds_dw, /* 0xc5 */
i_mov_bd8, /* 0xc6 */
i_mov_wd16, /* 0xc7 */
i_enter, /* 0xc8 */
i_leave, /* 0xc9 */
i_retf_d16, /* 0xca */
i_retf, /* 0xcb */
i_int3, /* 0xcc */
i_int, /* 0xcd */
i_into, /* 0xce */
i_iret, /* 0xcf */
i_rotshft_b, /* 0xd0 */
i_rotshft_w, /* 0xd1 */
i_rotshft_bcl, /* 0xd2 */
i_rotshft_wcl, /* 0xd3 */
i_aam, /* 0xd4 */
i_aad, /* 0xd5 */
i_setalc, /* 0xd6 */
i_trans, /* 0xd7 */
i_fpo, /* 0xd8 */
i_fpo, /* 0xd9 */
i_fpo, /* 0xda */
i_fpo, /* 0xdb */
i_fpo, /* 0xdc */
i_fpo, /* 0xdd */
i_fpo, /* 0xde */
i_fpo, /* 0xdf */
i_loopne, /* 0xe0 */
i_loope, /* 0xe1 */
i_loop, /* 0xe2 */
i_jcxz, /* 0xe3 */
i_inal, /* 0xe4 */
i_inax, /* 0xe5 */
i_outal, /* 0xe6 */
i_outax, /* 0xe7 */
i_call_d16, /* 0xe8 */
i_jmp_d16, /* 0xe9 */
i_jmp_far, /* 0xea */
i_jmp_d8, /* 0xeb */
i_inaldx, /* 0xec */
i_inaxdx, /* 0xed */
i_outdxal, /* 0xee */
i_outdxax, /* 0xef */
i_lock, /* 0xf0 */
i_invalid, /* 0xf1 */
i_repne, /* 0xf2 */
i_repe, /* 0xf3 */
i_hlt, /* 0xf4 */
i_cmc, /* 0xf5 */
i_f6pre, /* 0xf6 */
i_f7pre, /* 0xf7 */
i_clc, /* 0xf8 */
i_stc, /* 0xf9 */
i_di, /* 0xfa */
i_ei, /* 0xfb */
i_cld, /* 0xfc */
i_std, /* 0xfd */
i_fepre, /* 0xfe */
i_ffpre /* 0xff */
&nec_common_device::i_add_br8, /* 0x00 */
&nec_common_device::i_add_wr16, /* 0x01 */
&nec_common_device::i_add_r8b, /* 0x02 */
&nec_common_device::i_add_r16w, /* 0x03 */
&nec_common_device::i_add_ald8, /* 0x04 */
&nec_common_device::i_add_axd16, /* 0x05 */
&nec_common_device::i_push_es, /* 0x06 */
&nec_common_device::i_pop_es, /* 0x07 */
&nec_common_device::i_or_br8, /* 0x08 */
&nec_common_device::i_or_wr16, /* 0x09 */
&nec_common_device::i_or_r8b, /* 0x0a */
&nec_common_device::i_or_r16w, /* 0x0b */
&nec_common_device::i_or_ald8, /* 0x0c */
&nec_common_device::i_or_axd16, /* 0x0d */
&nec_common_device::i_push_cs, /* 0x0e */
&nec_common_device::i_pre_nec, /* 0x0f */
&nec_common_device::i_adc_br8, /* 0x10 */
&nec_common_device::i_adc_wr16, /* 0x11 */
&nec_common_device::i_adc_r8b, /* 0x12 */
&nec_common_device::i_adc_r16w, /* 0x13 */
&nec_common_device::i_adc_ald8, /* 0x14 */
&nec_common_device::i_adc_axd16, /* 0x15 */
&nec_common_device::i_push_ss, /* 0x16 */
&nec_common_device::i_pop_ss, /* 0x17 */
&nec_common_device::i_sbb_br8, /* 0x18 */
&nec_common_device::i_sbb_wr16, /* 0x19 */
&nec_common_device::i_sbb_r8b, /* 0x1a */
&nec_common_device::i_sbb_r16w, /* 0x1b */
&nec_common_device::i_sbb_ald8, /* 0x1c */
&nec_common_device::i_sbb_axd16, /* 0x1d */
&nec_common_device::i_push_ds, /* 0x1e */
&nec_common_device::i_pop_ds, /* 0x1f */
&nec_common_device::i_and_br8, /* 0x20 */
&nec_common_device::i_and_wr16, /* 0x21 */
&nec_common_device::i_and_r8b, /* 0x22 */
&nec_common_device::i_and_r16w, /* 0x23 */
&nec_common_device::i_and_ald8, /* 0x24 */
&nec_common_device::i_and_axd16, /* 0x25 */
&nec_common_device::i_es, /* 0x26 */
&nec_common_device::i_daa, /* 0x27 */
&nec_common_device::i_sub_br8, /* 0x28 */
&nec_common_device::i_sub_wr16, /* 0x29 */
&nec_common_device::i_sub_r8b, /* 0x2a */
&nec_common_device::i_sub_r16w, /* 0x2b */
&nec_common_device::i_sub_ald8, /* 0x2c */
&nec_common_device::i_sub_axd16, /* 0x2d */
&nec_common_device::i_cs, /* 0x2e */
&nec_common_device::i_das, /* 0x2f */
&nec_common_device::i_xor_br8, /* 0x30 */
&nec_common_device::i_xor_wr16, /* 0x31 */
&nec_common_device::i_xor_r8b, /* 0x32 */
&nec_common_device::i_xor_r16w, /* 0x33 */
&nec_common_device::i_xor_ald8, /* 0x34 */
&nec_common_device::i_xor_axd16, /* 0x35 */
&nec_common_device::i_ss, /* 0x36 */
&nec_common_device::i_aaa, /* 0x37 */
&nec_common_device::i_cmp_br8, /* 0x38 */
&nec_common_device::i_cmp_wr16, /* 0x39 */
&nec_common_device::i_cmp_r8b, /* 0x3a */
&nec_common_device::i_cmp_r16w, /* 0x3b */
&nec_common_device::i_cmp_ald8, /* 0x3c */
&nec_common_device::i_cmp_axd16, /* 0x3d */
&nec_common_device::i_ds, /* 0x3e */
&nec_common_device::i_aas, /* 0x3f */
&nec_common_device::i_inc_ax, /* 0x40 */
&nec_common_device::i_inc_cx, /* 0x41 */
&nec_common_device::i_inc_dx, /* 0x42 */
&nec_common_device::i_inc_bx, /* 0x43 */
&nec_common_device::i_inc_sp, /* 0x44 */
&nec_common_device::i_inc_bp, /* 0x45 */
&nec_common_device::i_inc_si, /* 0x46 */
&nec_common_device::i_inc_di, /* 0x47 */
&nec_common_device::i_dec_ax, /* 0x48 */
&nec_common_device::i_dec_cx, /* 0x49 */
&nec_common_device::i_dec_dx, /* 0x4a */
&nec_common_device::i_dec_bx, /* 0x4b */
&nec_common_device::i_dec_sp, /* 0x4c */
&nec_common_device::i_dec_bp, /* 0x4d */
&nec_common_device::i_dec_si, /* 0x4e */
&nec_common_device::i_dec_di, /* 0x4f */
&nec_common_device::i_push_ax, /* 0x50 */
&nec_common_device::i_push_cx, /* 0x51 */
&nec_common_device::i_push_dx, /* 0x52 */
&nec_common_device::i_push_bx, /* 0x53 */
&nec_common_device::i_push_sp, /* 0x54 */
&nec_common_device::i_push_bp, /* 0x55 */
&nec_common_device::i_push_si, /* 0x56 */
&nec_common_device::i_push_di, /* 0x57 */
&nec_common_device::i_pop_ax, /* 0x58 */
&nec_common_device::i_pop_cx, /* 0x59 */
&nec_common_device::i_pop_dx, /* 0x5a */
&nec_common_device::i_pop_bx, /* 0x5b */
&nec_common_device::i_pop_sp, /* 0x5c */
&nec_common_device::i_pop_bp, /* 0x5d */
&nec_common_device::i_pop_si, /* 0x5e */
&nec_common_device::i_pop_di, /* 0x5f */
&nec_common_device::i_pusha, /* 0x60 */
&nec_common_device::i_popa, /* 0x61 */
&nec_common_device::i_chkind, /* 0x62 */
&nec_common_device::i_invalid, /* 0x63 */
&nec_common_device::i_repnc, /* 0x64 */
&nec_common_device::i_repc, /* 0x65 */
&nec_common_device::i_invalid, /* 0x66 */
&nec_common_device::i_invalid, /* 0x67 */
&nec_common_device::i_push_d16, /* 0x68 */
&nec_common_device::i_imul_d16, /* 0x69 */
&nec_common_device::i_push_d8, /* 0x6a */
&nec_common_device::i_imul_d8, /* 0x6b */
&nec_common_device::i_insb, /* 0x6c */
&nec_common_device::i_insw, /* 0x6d */
&nec_common_device::i_outsb, /* 0x6e */
&nec_common_device::i_outsw, /* 0x6f */
&nec_common_device::i_jo, /* 0x70 */
&nec_common_device::i_jno, /* 0x71 */
&nec_common_device::i_jc, /* 0x72 */
&nec_common_device::i_jnc, /* 0x73 */
&nec_common_device::i_jz, /* 0x74 */
&nec_common_device::i_jnz, /* 0x75 */
&nec_common_device::i_jce, /* 0x76 */
&nec_common_device::i_jnce, /* 0x77 */
&nec_common_device::i_js, /* 0x78 */
&nec_common_device::i_jns, /* 0x79 */
&nec_common_device::i_jp, /* 0x7a */
&nec_common_device::i_jnp, /* 0x7b */
&nec_common_device::i_jl, /* 0x7c */
&nec_common_device::i_jnl, /* 0x7d */
&nec_common_device::i_jle, /* 0x7e */
&nec_common_device::i_jnle, /* 0x7f */
&nec_common_device::i_80pre, /* 0x80 */
&nec_common_device::i_81pre, /* 0x81 */
&nec_common_device::i_82pre, /* 0x82 */
&nec_common_device::i_83pre, /* 0x83 */
&nec_common_device::i_test_br8, /* 0x84 */
&nec_common_device::i_test_wr16, /* 0x85 */
&nec_common_device::i_xchg_br8, /* 0x86 */
&nec_common_device::i_xchg_wr16, /* 0x87 */
&nec_common_device::i_mov_br8, /* 0x88 */
&nec_common_device::i_mov_wr16, /* 0x89 */
&nec_common_device::i_mov_r8b, /* 0x8a */
&nec_common_device::i_mov_r16w, /* 0x8b */
&nec_common_device::i_mov_wsreg, /* 0x8c */
&nec_common_device::i_lea, /* 0x8d */
&nec_common_device::i_mov_sregw, /* 0x8e */
&nec_common_device::i_popw, /* 0x8f */
&nec_common_device::i_nop, /* 0x90 */
&nec_common_device::i_xchg_axcx, /* 0x91 */
&nec_common_device::i_xchg_axdx, /* 0x92 */
&nec_common_device::i_xchg_axbx, /* 0x93 */
&nec_common_device::i_xchg_axsp, /* 0x94 */
&nec_common_device::i_xchg_axbp, /* 0x95 */
&nec_common_device::i_xchg_axsi, /* 0x96 */
&nec_common_device::i_xchg_axdi, /* 0x97 */
&nec_common_device::i_cbw, /* 0x98 */
&nec_common_device::i_cwd, /* 0x99 */
&nec_common_device::i_call_far, /* 0x9a */
&nec_common_device::i_wait, /* 0x9b */
&nec_common_device::i_pushf, /* 0x9c */
&nec_common_device::i_popf, /* 0x9d */
&nec_common_device::i_sahf, /* 0x9e */
&nec_common_device::i_lahf, /* 0x9f */
&nec_common_device::i_mov_aldisp, /* 0xa0 */
&nec_common_device::i_mov_axdisp, /* 0xa1 */
&nec_common_device::i_mov_dispal, /* 0xa2 */
&nec_common_device::i_mov_dispax, /* 0xa3 */
&nec_common_device::i_movsb, /* 0xa4 */
&nec_common_device::i_movsw, /* 0xa5 */
&nec_common_device::i_cmpsb, /* 0xa6 */
&nec_common_device::i_cmpsw, /* 0xa7 */
&nec_common_device::i_test_ald8, /* 0xa8 */
&nec_common_device::i_test_axd16, /* 0xa9 */
&nec_common_device::i_stosb, /* 0xaa */
&nec_common_device::i_stosw, /* 0xab */
&nec_common_device::i_lodsb, /* 0xac */
&nec_common_device::i_lodsw, /* 0xad */
&nec_common_device::i_scasb, /* 0xae */
&nec_common_device::i_scasw, /* 0xaf */
&nec_common_device::i_mov_ald8, /* 0xb0 */
&nec_common_device::i_mov_cld8, /* 0xb1 */
&nec_common_device::i_mov_dld8, /* 0xb2 */
&nec_common_device::i_mov_bld8, /* 0xb3 */
&nec_common_device::i_mov_ahd8, /* 0xb4 */
&nec_common_device::i_mov_chd8, /* 0xb5 */
&nec_common_device::i_mov_dhd8, /* 0xb6 */
&nec_common_device::i_mov_bhd8, /* 0xb7 */
&nec_common_device::i_mov_axd16, /* 0xb8 */
&nec_common_device::i_mov_cxd16, /* 0xb9 */
&nec_common_device::i_mov_dxd16, /* 0xba */
&nec_common_device::i_mov_bxd16, /* 0xbb */
&nec_common_device::i_mov_spd16, /* 0xbc */
&nec_common_device::i_mov_bpd16, /* 0xbd */
&nec_common_device::i_mov_sid16, /* 0xbe */
&nec_common_device::i_mov_did16, /* 0xbf */
&nec_common_device::i_rotshft_bd8, /* 0xc0 */
&nec_common_device::i_rotshft_wd8, /* 0xc1 */
&nec_common_device::i_ret_d16, /* 0xc2 */
&nec_common_device::i_ret, /* 0xc3 */
&nec_common_device::i_les_dw, /* 0xc4 */
&nec_common_device::i_lds_dw, /* 0xc5 */
&nec_common_device::i_mov_bd8, /* 0xc6 */
&nec_common_device::i_mov_wd16, /* 0xc7 */
&nec_common_device::i_enter, /* 0xc8 */
&nec_common_device::i_leave, /* 0xc9 */
&nec_common_device::i_retf_d16, /* 0xca */
&nec_common_device::i_retf, /* 0xcb */
&nec_common_device::i_int3, /* 0xcc */
&nec_common_device::i_int, /* 0xcd */
&nec_common_device::i_into, /* 0xce */
&nec_common_device::i_iret, /* 0xcf */
&nec_common_device::i_rotshft_b, /* 0xd0 */
&nec_common_device::i_rotshft_w, /* 0xd1 */
&nec_common_device::i_rotshft_bcl, /* 0xd2 */
&nec_common_device::i_rotshft_wcl, /* 0xd3 */
&nec_common_device::i_aam, /* 0xd4 */
&nec_common_device::i_aad, /* 0xd5 */
&nec_common_device::i_setalc, /* 0xd6 */
&nec_common_device::i_trans, /* 0xd7 */
&nec_common_device::i_fpo, /* 0xd8 */
&nec_common_device::i_fpo, /* 0xd9 */
&nec_common_device::i_fpo, /* 0xda */
&nec_common_device::i_fpo, /* 0xdb */
&nec_common_device::i_fpo, /* 0xdc */
&nec_common_device::i_fpo, /* 0xdd */
&nec_common_device::i_fpo, /* 0xde */
&nec_common_device::i_fpo, /* 0xdf */
&nec_common_device::i_loopne, /* 0xe0 */
&nec_common_device::i_loope, /* 0xe1 */
&nec_common_device::i_loop, /* 0xe2 */
&nec_common_device::i_jcxz, /* 0xe3 */
&nec_common_device::i_inal, /* 0xe4 */
&nec_common_device::i_inax, /* 0xe5 */
&nec_common_device::i_outal, /* 0xe6 */
&nec_common_device::i_outax, /* 0xe7 */
&nec_common_device::i_call_d16, /* 0xe8 */
&nec_common_device::i_jmp_d16, /* 0xe9 */
&nec_common_device::i_jmp_far, /* 0xea */
&nec_common_device::i_jmp_d8, /* 0xeb */
&nec_common_device::i_inaldx, /* 0xec */
&nec_common_device::i_inaxdx, /* 0xed */
&nec_common_device::i_outdxal, /* 0xee */
&nec_common_device::i_outdxax, /* 0xef */
&nec_common_device::i_lock, /* 0xf0 */
&nec_common_device::i_invalid, /* 0xf1 */
&nec_common_device::i_repne, /* 0xf2 */
&nec_common_device::i_repe, /* 0xf3 */
&nec_common_device::i_hlt, /* 0xf4 */
&nec_common_device::i_cmc, /* 0xf5 */
&nec_common_device::i_f6pre, /* 0xf6 */
&nec_common_device::i_f7pre, /* 0xf7 */
&nec_common_device::i_clc, /* 0xf8 */
&nec_common_device::i_stc, /* 0xf9 */
&nec_common_device::i_di, /* 0xfa */
&nec_common_device::i_ei, /* 0xfb */
&nec_common_device::i_cld, /* 0xfc */
&nec_common_device::i_std, /* 0xfd */
&nec_common_device::i_fepre, /* 0xfe */
&nec_common_device::i_ffpre /* 0xff */
};

154
src/emu/cpu/nec/necmacro.h
View File

@ -1,24 +1,24 @@
/* parameter x = result, y = source 1, z = source 2 */
#define SetTF(x) (nec_state->TF = (x))
#define SetIF(x) (nec_state->IF = (x))
#define SetDF(x) (nec_state->DF = (x))
#define SetMD(x) (nec_state->MF = (x)) /* OB [19.07.99] Mode Flag V30 */
#define SetTF(x) (m_TF = (x))
#define SetIF(x) (m_IF = (x))
#define SetDF(x) (m_DF = (x))
#define SetMD(x) (m_MF = (x)) /* OB [19.07.99] Mode Flag V30 */
#define SetCFB(x) (nec_state->CarryVal = (x) & 0x100)
#define SetCFW(x) (nec_state->CarryVal = (x) & 0x10000)
#define SetAF(x,y,z) (nec_state->AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
#define SetSF(x) (nec_state->SignVal = (x))
#define SetZF(x) (nec_state->ZeroVal = (x))
#define SetPF(x) (nec_state->ParityVal = (x))
#define SetCFB(x) (m_CarryVal = (x) & 0x100)
#define SetCFW(x) (m_CarryVal = (x) & 0x10000)
#define SetAF(x,y,z) (m_AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
#define SetSF(x) (m_SignVal = (x))
#define SetZF(x) (m_ZeroVal = (x))
#define SetPF(x) (m_ParityVal = (x))
#define SetSZPF_Byte(x) (nec_state->SignVal=nec_state->ZeroVal=nec_state->ParityVal=(INT8)(x))
#define SetSZPF_Word(x) (nec_state->SignVal=nec_state->ZeroVal=nec_state->ParityVal=(INT16)(x))
#define SetSZPF_Byte(x) (m_SignVal=m_ZeroVal=m_ParityVal=(INT8)(x))
#define SetSZPF_Word(x) (m_SignVal=m_ZeroVal=m_ParityVal=(INT16)(x))
#define SetOFW_Add(x,y,z) (nec_state->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
#define SetOFB_Add(x,y,z) (nec_state->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
#define SetOFW_Sub(x,y,z) (nec_state->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
#define SetOFB_Sub(x,y,z) (nec_state->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
#define SetOFW_Add(x,y,z) (m_OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
#define SetOFB_Add(x,y,z) (m_OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
#define SetOFW_Sub(x,y,z) (m_OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
#define SetOFB_Sub(x,y,z) (m_OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
#define ADDB { UINT32 res=dst+src; SetCFB(res); SetOFB_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define ADDW { UINT32 res=dst+src; SetCFW(res); SetOFW_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
@ -26,19 +26,19 @@
#define SUBB { UINT32 res=dst-src; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define SUBW { UINT32 res=dst-src; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
#define ORB dst|=src; nec_state->CarryVal=nec_state->OverVal=nec_state->AuxVal=0; SetSZPF_Byte(dst)
#define ORW dst|=src; nec_state->CarryVal=nec_state->OverVal=nec_state->AuxVal=0; SetSZPF_Word(dst)
#define ORB dst|=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Byte(dst)
#define ORW dst|=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Word(dst)
#define ANDB dst&=src; nec_state->CarryVal=nec_state->OverVal=nec_state->AuxVal=0; SetSZPF_Byte(dst)
#define ANDW dst&=src; nec_state->CarryVal=nec_state->OverVal=nec_state->AuxVal=0; SetSZPF_Word(dst)
#define ANDB dst&=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Byte(dst)
#define ANDW dst&=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Word(dst)
#define XORB dst^=src; nec_state->CarryVal=nec_state->OverVal=nec_state->AuxVal=0; SetSZPF_Byte(dst)
#define XORW dst^=src; nec_state->CarryVal=nec_state->OverVal=nec_state->AuxVal=0; SetSZPF_Word(dst)
#define XORB dst^=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Byte(dst)
#define XORW dst^=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Word(dst)
#define IncWordReg(Reg) \
unsigned tmp = (unsigned)Wreg(Reg); \
unsigned tmp1 = tmp+1; \
nec_state->OverVal = (tmp == 0x7fff); \
m_OverVal = (tmp == 0x7fff); \
SetAF(tmp1,tmp,1); \
SetSZPF_Word(tmp1); \
Wreg(Reg)=tmp1
@ -46,7 +46,7 @@
#define DecWordReg(Reg) \
unsigned tmp = (unsigned)Wreg(Reg); \
unsigned tmp1 = tmp-1; \
nec_state->OverVal = (tmp == 0x8000); \
m_OverVal = (tmp == 0x8000); \
SetAF(tmp1,tmp,1); \
SetSZPF_Word(tmp1); \
Wreg(Reg)=tmp1
@ -58,8 +58,8 @@
if (flag) \
{ \
static const UINT8 table[3]={3,10,10}; \
nec_state->ip = (WORD)(nec_state->ip+tmp); \
nec_state->icount-=table[nec_state->chip_type/8]; \
m_ip = (WORD)(m_ip+tmp); \
m_icount-=table[m_chip_type/8]; \
CHANGE_PC; \
return; \
}
@ -70,13 +70,13 @@
UINT16 tmp; \
tmp = Breg(AL) + param1; \
Breg(AL) = tmp; \
nec_state->AuxVal = 1; \
nec_state->CarryVal |= tmp & 0x100; \
m_AuxVal = 1; \
m_CarryVal |= tmp & 0x100; \
} \
if (CF || (Breg(AL)>0x9f)) \
{ \
Breg(AL) += param2; \
nec_state->CarryVal = 1; \
m_CarryVal = 1; \
} \
SetSZPF_Byte(Breg(AL))
@ -85,13 +85,13 @@
{ \
Breg(AL) += param1; \
Breg(AH) += param2; \
nec_state->AuxVal = 1; \
nec_state->CarryVal = 1; \
m_AuxVal = 1; \
m_CarryVal = 1; \
} \
else \
{ \
nec_state->AuxVal = 0; \
nec_state->CarryVal = 0; \
m_AuxVal = 0; \
m_CarryVal = 0; \
} \
Breg(AL) &= 0x0F
@ -101,8 +101,8 @@
tmp=Breg(Mod_RM.RM.b[ModRM]); \
} \
else { \
(*GetEA[ModRM])(nec_state); \
tmp=read_mem_byte(EA); \
(this->*s_GetEA[ModRM])(); \
tmp=read_mem_byte(m_EA); \
}
#define BITOP_WORD \
@ -111,8 +111,8 @@
tmp=Wreg(Mod_RM.RM.w[ModRM]); \
} \
else { \
(*GetEA[ModRM])(nec_state); \
tmp=read_mem_word(EA); \
(this->*s_GetEA[ModRM])(); \
tmp=read_mem_word(m_EA); \
}
#define BIT_NOT \
@ -127,26 +127,26 @@
Wreg(Reg) = Wreg(AW); \
Wreg(AW) = tmp
#define ROL_BYTE nec_state->CarryVal = dst & 0x80; dst = (dst << 1)+CF
#define ROL_WORD nec_state->CarryVal = dst & 0x8000; dst = (dst << 1)+CF
#define ROR_BYTE nec_state->CarryVal = dst & 0x1; dst = (dst >> 1)+(CF<<7)
#define ROR_WORD nec_state->CarryVal = dst & 0x1; dst = (dst >> 1)+(CF<<15)
#define ROL_BYTE m_CarryVal = dst & 0x80; dst = (dst << 1)+CF
#define ROL_WORD m_CarryVal = dst & 0x8000; dst = (dst << 1)+CF
#define ROR_BYTE m_CarryVal = dst & 0x1; dst = (dst >> 1)+(CF<<7)
#define ROR_WORD m_CarryVal = dst & 0x1; dst = (dst >> 1)+(CF<<15)
#define ROLC_BYTE dst = (dst << 1) + CF; SetCFB(dst)
#define ROLC_WORD dst = (dst << 1) + CF; SetCFW(dst)
#define RORC_BYTE dst = (CF<<8)+dst; nec_state->CarryVal = dst & 0x01; dst >>= 1
#define RORC_WORD dst = (CF<<16)+dst; nec_state->CarryVal = dst & 0x01; dst >>= 1
#define SHL_BYTE(c) nec_state->icount-=c; dst <<= c; SetCFB(dst); SetSZPF_Byte(dst); PutbackRMByte(ModRM,(BYTE)dst)
#define SHL_WORD(c) nec_state->icount-=c; dst <<= c; SetCFW(dst); SetSZPF_Word(dst); PutbackRMWord(ModRM,(WORD)dst)
#define SHR_BYTE(c) nec_state->icount-=c; dst >>= c-1; nec_state->CarryVal = dst & 0x1; dst >>= 1; SetSZPF_Byte(dst); PutbackRMByte(ModRM,(BYTE)dst)
#define SHR_WORD(c) nec_state->icount-=c; dst >>= c-1; nec_state->CarryVal = dst & 0x1; dst >>= 1; SetSZPF_Word(dst); PutbackRMWord(ModRM,(WORD)dst)
#define SHRA_BYTE(c) nec_state->icount-=c; dst = ((INT8)dst) >> (c-1); nec_state->CarryVal = dst & 0x1; dst = ((INT8)((BYTE)dst)) >> 1; SetSZPF_Byte(dst); PutbackRMByte(ModRM,(BYTE)dst)
#define SHRA_WORD(c) nec_state->icount-=c; dst = ((INT16)dst) >> (c-1); nec_state->CarryVal = dst & 0x1; dst = ((INT16)((WORD)dst)) >> 1; SetSZPF_Word(dst); PutbackRMWord(ModRM,(WORD)dst)
#define RORC_BYTE dst = (CF<<8)+dst; m_CarryVal = dst & 0x01; dst >>= 1
#define RORC_WORD dst = (CF<<16)+dst; m_CarryVal = dst & 0x01; dst >>= 1
#define SHL_BYTE(c) m_icount-=c; dst <<= c; SetCFB(dst); SetSZPF_Byte(dst); PutbackRMByte(ModRM,(BYTE)dst)
#define SHL_WORD(c) m_icount-=c; dst <<= c; SetCFW(dst); SetSZPF_Word(dst); PutbackRMWord(ModRM,(WORD)dst)
#define SHR_BYTE(c) m_icount-=c; dst >>= c-1; m_CarryVal = dst & 0x1; dst >>= 1; SetSZPF_Byte(dst); PutbackRMByte(ModRM,(BYTE)dst)
#define SHR_WORD(c) m_icount-=c; dst >>= c-1; m_CarryVal = dst & 0x1; dst >>= 1; SetSZPF_Word(dst); PutbackRMWord(ModRM,(WORD)dst)
#define SHRA_BYTE(c) m_icount-=c; dst = ((INT8)dst) >> (c-1); m_CarryVal = dst & 0x1; dst = ((INT8)((BYTE)dst)) >> 1; SetSZPF_Byte(dst); PutbackRMByte(ModRM,(BYTE)dst)
#define SHRA_WORD(c) m_icount-=c; dst = ((INT16)dst) >> (c-1); m_CarryVal = dst & 0x1; dst = ((INT16)((WORD)dst)) >> 1; SetSZPF_Word(dst); PutbackRMWord(ModRM,(WORD)dst)
#define DIVUB \
uresult = Wreg(AW); \
uresult2 = uresult % tmp; \
if ((uresult /= tmp) > 0xff) { \
nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); break; \
nec_interrupt(NEC_DIVIDE_VECTOR, BRK); break; \
} else { \
Breg(AL) = uresult; \
Breg(AH) = uresult2; \
@ -156,7 +156,7 @@
result = (INT16)Wreg(AW); \
result2 = result % (INT16)((INT8)tmp); \
if ((result /= (INT16)((INT8)tmp)) > 0xff) { \
nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); break; \
nec_interrupt(NEC_DIVIDE_VECTOR, BRK); break; \
} else { \
Breg(AL) = result; \
Breg(AH) = result2; \
@ -166,7 +166,7 @@
uresult = (((UINT32)Wreg(DW)) << 16) | Wreg(AW);\
uresult2 = uresult % tmp; \
if ((uresult /= tmp) > 0xffff) { \
nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); break; \
nec_interrupt(NEC_DIVIDE_VECTOR, BRK); break; \
} else { \
Wreg(AW)=uresult; \
Wreg(DW)=uresult2; \
@ -176,7 +176,7 @@
result = ((UINT32)Wreg(DW) << 16) + Wreg(AW); \
result2 = result % (INT32)((INT16)tmp); \
if ((result /= (INT32)((INT16)tmp)) > 0xffff) { \
nec_interrupt(nec_state, NEC_DIVIDE_VECTOR, BRK); break; \
nec_interrupt(NEC_DIVIDE_VECTOR, BRK); break; \
} else { \
Wreg(AW)=result; \
Wreg(DW)=result2; \
@ -188,20 +188,20 @@
unsigned di = Wreg(IY); \
unsigned si = Wreg(IX); \
static const UINT8 table[3]={18,19,19}; \
if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",PC(nec_state)); \
nec_state->ZeroVal = nec_state->CarryVal = 0; \
if (m_seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",PC()); \
m_ZeroVal = m_CarryVal = 0; \
for (i=0;i<count;i++) { \
nec_state->icount-=table[nec_state->chip_type/8]; \
m_icount-=table[m_chip_type/8]; \
tmp = GetMemB(DS0, si); \
tmp2 = GetMemB(DS1, di); \
v1 = (tmp>>4)*10 + (tmp&0xf); \
v2 = (tmp2>>4)*10 + (tmp2&0xf); \
result = v1+v2+nec_state->CarryVal; \
nec_state->CarryVal = result > 99 ? 1 : 0; \
result = v1+v2+m_CarryVal; \
m_CarryVal = result > 99 ? 1 : 0; \
result = result % 100; \
v1 = ((result/10)<<4) | (result % 10); \
PutMemB(DS1, di,v1); \
if (v1) nec_state->ZeroVal = 1; \
if (v1) m_ZeroVal = 1; \
si++; \
di++; \
} \
@ -213,25 +213,25 @@
unsigned di = Wreg(IY); \
unsigned si = Wreg(IX); \
static const UINT8 table[3]={18,19,19}; \
if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",PC(nec_state)); \
nec_state->ZeroVal = nec_state->CarryVal = 0; \
if (m_seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",PC()); \
m_ZeroVal = m_CarryVal = 0; \
for (i=0;i<count;i++) { \
nec_state->icount-=table[nec_state->chip_type/8]; \
m_icount-=table[m_chip_type/8]; \
tmp = GetMemB(DS1, di); \
tmp2 = GetMemB(DS0, si); \
v1 = (tmp>>4)*10 + (tmp&0xf); \
v2 = (tmp2>>4)*10 + (tmp2&0xf); \
if (v1 < (v2+nec_state->CarryVal)) { \
if (v1 < (v2+m_CarryVal)) { \
v1+=100; \
result = v1-(v2+nec_state->CarryVal); \
nec_state->CarryVal = 1; \
result = v1-(v2+m_CarryVal); \
m_CarryVal = 1; \
} else { \
result = v1-(v2+nec_state->CarryVal); \
nec_state->CarryVal = 0; \
result = v1-(v2+m_CarryVal); \
m_CarryVal = 0; \
} \
v1 = ((result/10)<<4) | (result % 10); \
PutMemB(DS1, di,v1); \
if (v1) nec_state->ZeroVal = 1; \
if (v1) m_ZeroVal = 1; \
si++; \
di++; \
} \
@ -243,24 +243,24 @@
unsigned di = Wreg(IY); \
unsigned si = Wreg(IX); \
static const UINT8 table[3]={14,19,19}; \
if (nec_state->seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",PC(nec_state)); \
nec_state->ZeroVal = nec_state->CarryVal = 0; \
if (m_seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",PC()); \
m_ZeroVal = m_CarryVal = 0; \
for (i=0;i<count;i++) { \
nec_state->icount-=table[nec_state->chip_type/8]; \
m_icount-=table[m_chip_type/8]; \
tmp = GetMemB(DS1, di); \
tmp2 = GetMemB(DS0, si); \
v1 = (tmp>>4)*10 + (tmp&0xf); \
v2 = (tmp2>>4)*10 + (tmp2&0xf); \
if (v1 < (v2+nec_state->CarryVal)) { \
if (v1 < (v2+m_CarryVal)) { \
v1+=100; \
result = v1-(v2+nec_state->CarryVal); \
nec_state->CarryVal = 1; \
result = v1-(v2+m_CarryVal); \
m_CarryVal = 1; \
} else { \
result = v1-(v2+nec_state->CarryVal); \
nec_state->CarryVal = 0; \
result = v1-(v2+m_CarryVal); \
m_CarryVal = 0; \
} \
v1 = ((result/10)<<4) | (result % 10); \
if (v1) nec_state->ZeroVal = 1; \
if (v1) m_ZeroVal = 1; \
si++; \
di++; \
} \

24
src/emu/cpu/nec/necmodrm.h
View File

@ -13,23 +13,23 @@ static struct {
#define RegByte(ModRM) Breg(Mod_RM.reg.b[ModRM])
#define GetRMWord(ModRM) \
((ModRM) >= 0xc0 ? Wreg(Mod_RM.RM.w[ModRM]) : ( (*GetEA[ModRM])(nec_state), read_mem_word( EA ) ))
((ModRM) >= 0xc0 ? Wreg(Mod_RM.RM.w[ModRM]) : ( (this->*s_GetEA[ModRM])(), read_mem_word( m_EA ) ))
#define PutbackRMWord(ModRM,val) \
{ \
if (ModRM >= 0xc0) Wreg(Mod_RM.RM.w[ModRM])=val; \
else write_mem_word(EA,val); \
else write_mem_word(m_EA,val); \
}
#define GetnextRMWord read_mem_word((EA&0xf0000)|((EA+2)&0xffff))
#define GetnextRMWord read_mem_word((m_EA&0xf0000)|((m_EA+2)&0xffff))
#define PutRMWord(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
Wreg(Mod_RM.RM.w[ModRM])=val; \
else { \
(*GetEA[ModRM])(nec_state); \
write_mem_word( EA ,val); \
(this->*s_GetEA[ModRM])(); \
write_mem_word( m_EA ,val); \
} \
}
@ -39,21 +39,21 @@ static struct {
if (ModRM >= 0xc0) \
Wreg(Mod_RM.RM.w[ModRM]) = FETCHWORD(); \
else { \
(*GetEA[ModRM])(nec_state); \
(this->*s_GetEA[ModRM])(); \
val = FETCHWORD(); \
write_mem_word( EA , val); \
write_mem_word( m_EA , val); \
} \
}
#define GetRMByte(ModRM) \
((ModRM) >= 0xc0 ? Breg(Mod_RM.RM.b[ModRM]) : read_mem_byte( (*GetEA[ModRM])(nec_state) ))
((ModRM) >= 0xc0 ? Breg(Mod_RM.RM.b[ModRM]) : read_mem_byte( (this->*s_GetEA[ModRM])() ))
#define PutRMByte(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
Breg(Mod_RM.RM.b[ModRM])=val; \
else \
write_mem_byte( (*GetEA[ModRM])(nec_state) ,val); \
write_mem_byte( (this->*s_GetEA[ModRM])() ,val); \
}
#define PutImmRMByte(ModRM) \
@ -61,8 +61,8 @@ static struct {
if (ModRM >= 0xc0) \
Breg(Mod_RM.RM.b[ModRM])=FETCH(); \
else { \
(*GetEA[ModRM])(nec_state); \
write_mem_byte( EA , FETCH() ); \
(this->*s_GetEA[ModRM])(); \
write_mem_byte( m_EA , FETCH() ); \
} \
}
@ -71,7 +71,7 @@ static struct {
if (ModRM >= 0xc0) \
Breg(Mod_RM.RM.b[ModRM])=val; \
else \
write_mem_byte(EA,val); \
write_mem_byte(m_EA,val); \
}
#define DEF_br8 \

126
src/emu/cpu/nec/necpriv.h
View File

@ -26,53 +26,9 @@ enum INTSOURCES
NMI_IRQ = 2,
};
/* NEC registers */
union necbasicregs
{ /* eight general registers */
UINT16 w[8]; /* viewed as 16 bits registers */
UINT8 b[16]; /* or as 8 bit registers */
};
struct nec_state_t
{
necbasicregs regs;
offs_t fetch_xor;
UINT16 sregs[4];
UINT16 ip;
/* PSW flags */
INT32 SignVal;
UINT32 AuxVal, OverVal, ZeroVal, CarryVal, ParityVal; /* 0 or non-0 valued flags */
UINT8 TF, IF, DF, MF; /* 0 or 1 valued flags */
/* interrupt related */
UINT32 pending_irq;
UINT32 nmi_state;
UINT32 irq_state;
UINT32 poll_state;
UINT8 no_interrupt;
UINT8 halted;
device_irq_acknowledge_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
direct_read_data *direct;
address_space *io;
int icount;
UINT8 prefetch_size;
UINT8 prefetch_cycles;
INT8 prefetch_count;
UINT8 prefetch_reset;
UINT32 chip_type;
UINT32 prefix_base; /* base address of the latest prefix segment */
UINT8 seg_prefix; /* prefix segment indicator */
};
enum SREGS { DS1, PS, SS, DS0 };
enum WREGS { AW, CW, DW, BW, SP, BP, IX, IY };
enum SREGS { DS1=0, PS, SS, DS0 };
enum WREGS { AW=0, CW, DW, BW, SP, BP, IX, IY };
enum BREGS {
AL = NATIVE_ENDIAN_VALUE_LE_BE(0x0, 0x1),
AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1, 0x0),
@ -84,30 +40,30 @@ enum BREGS {
BH = NATIVE_ENDIAN_VALUE_LE_BE(0x7, 0x6),
};
#define Sreg(x) nec_state->sregs[x]
#define Wreg(x) nec_state->regs.w[x]
#define Breg(x) nec_state->regs.b[x]
#define Sreg(x) m_sregs[x]
#define Wreg(x) m_regs.w[x]
#define Breg(x) m_regs.b[x]
#define PC(n) ((Sreg(PS)<<4)+(n)->ip)
#define PC() ((Sreg(PS)<<4)+m_ip)
#define CF (nec_state->CarryVal!=0)
#define SF (nec_state->SignVal<0)
#define ZF (nec_state->ZeroVal==0)
#define PF parity_table[(BYTE)nec_state->ParityVal]
#define AF (nec_state->AuxVal!=0)
#define OF (nec_state->OverVal!=0)
#define CF (m_CarryVal!=0)
#define SF (m_SignVal<0)
#define ZF (m_ZeroVal==0)
#define PF parity_table[(BYTE)m_ParityVal]
#define AF (m_AuxVal!=0)
#define OF (m_OverVal!=0)
/************************************************************************/
#define read_mem_byte(a) nec_state->program->read_byte(a)
#define read_mem_word(a) nec_state->program->read_word_unaligned(a)
#define write_mem_byte(a,d) nec_state->program->write_byte((a),(d))
#define write_mem_word(a,d) nec_state->program->write_word_unaligned((a),(d))
#define read_mem_byte(a) m_program->read_byte(a)
#define read_mem_word(a) m_program->read_word_unaligned(a)
#define write_mem_byte(a,d) m_program->write_byte((a),(d))
#define write_mem_word(a,d) m_program->write_word_unaligned((a),(d))
#define read_port_byte(a) nec_state->io->read_byte(a)
#define read_port_word(a) nec_state->io->read_word_unaligned(a)
#define write_port_byte(a,d) nec_state->io->write_byte((a),(d))
#define write_port_word(a,d) nec_state->io->write_word_unaligned((a),(d))
#define read_port_byte(a) m_io->read_byte(a)
#define read_port_word(a) m_io->read_word_unaligned(a)
#define write_port_byte(a,d) m_io->write_byte((a),(d))
#define write_port_word(a,d) m_io->write_word_unaligned((a),(d))
/************************************************************************/
@ -115,7 +71,7 @@ enum BREGS {
#define SegBase(Seg) (Sreg(Seg) << 4)
#define DefaultBase(Seg) ((nec_state->seg_prefix && (Seg==DS0 || Seg==SS)) ? nec_state->prefix_base : Sreg(Seg) << 4)
#define DefaultBase(Seg) ((m_seg_prefix && (Seg==DS0 || Seg==SS)) ? m_prefix_base : Sreg(Seg) << 4)
#define GetMemB(Seg,Off) (read_mem_byte(DefaultBase(Seg) + (Off)))
#define GetMemW(Seg,Off) (read_mem_word(DefaultBase(Seg) + (Off)))
@ -125,9 +81,9 @@ enum BREGS {
/* prefetch timing */
#define FETCH() fetch(nec_state)
#define FETCHWORD() fetchword(nec_state)
#define EMPTY_PREFETCH() nec_state->prefetch_reset = 1
#define FETCH() fetch()
#define FETCHWORD() fetchword()
#define EMPTY_PREFETCH() m_prefetch_reset = 1
#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); }
@ -147,27 +103,27 @@ enum BREGS {
Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated.
*/
#define CLK(all) nec_state->icount-=all
#define CLKS(v20,v30,v33) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33; nec_state->icount-=(ccount>>nec_state->chip_type)&0x7f; }
#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; nec_state->icount-=(addr&1)?((ocount>>nec_state->chip_type)&0x7f):((ecount>>nec_state->chip_type)&0x7f); }
#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; nec_state->icount-=( ModRM >=0xc0 )?((ccount>>nec_state->chip_type)&0x7f):((mcount>>nec_state->chip_type)&0x7f); }
#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) nec_state->icount-=vall; else nec_state->icount-=(addr&1)?((ocount>>nec_state->chip_type)&0x7f):((ecount>>nec_state->chip_type)&0x7f); }
#define CLK(all) m_icount-=all
#define CLKS(v20,v30,v33) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33; m_icount-=(ccount>>m_chip_type)&0x7f; }
#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); }
#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; m_icount-=( ModRM >=0xc0 )?((ccount>>m_chip_type)&0x7f):((mcount>>m_chip_type)&0x7f); }
#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) m_icount-=vall; else m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); }
/************************************************************************/
#define CompressFlags() (WORD)(int(CF) | 0x02 | (int(PF) << 2) | (int(AF) << 4) | (int(ZF) << 6) \
| (int(SF) << 7) | (nec_state->TF << 8) | (nec_state->IF << 9) \
| (nec_state->DF << 10) | (int(OF) << 11) | 0x7000 | (nec_state->MF << 15))
| (int(SF) << 7) | (m_TF << 8) | (m_IF << 9) \
| (m_DF << 10) | (int(OF) << 11) | 0x7000 | (m_MF << 15))
#define ExpandFlags(f) \
{ \
nec_state->CarryVal = (f) & 0x0001; \
nec_state->ParityVal = !((f) & 0x0004); \
nec_state->AuxVal = (f) & 0x0010; \
nec_state->ZeroVal = !((f) & 0x0040); \
nec_state->SignVal = (f) & 0x0080 ? -1 : 0; \
nec_state->TF = ((f) & 0x0100) == 0x0100; \
nec_state->IF = ((f) & 0x0200) == 0x0200; \
nec_state->DF = ((f) & 0x0400) == 0x0400; \
nec_state->OverVal = (f) & 0x0800; \
nec_state->MF = ((f) & 0x8000) == 0x8000; \
m_CarryVal = (f) & 0x0001; \
m_ParityVal = !((f) & 0x0004); \
m_AuxVal = (f) & 0x0010; \
m_ZeroVal = !((f) & 0x0040); \
m_SignVal = (f) & 0x0080 ? -1 : 0; \
m_TF = ((f) & 0x0100) == 0x0100; \
m_IF = ((f) & 0x0200) == 0x0200; \
m_DF = ((f) & 0x0400) == 0x0400; \
m_OverVal = (f) & 0x0800; \
m_MF = ((f) & 0x8000) == 0x8000; \
}

887
src/emu/cpu/nec/v25.c
View File

File diff suppressed because it is too large Load Diff

453
src/emu/cpu/nec/v25.h Normal file
View File

@ -0,0 +1,453 @@
/* ASG 971222 -- rewrote this interface */
#ifndef __NEC_V25_H_
#define __NEC_V25_H_
#define NEC_INPUT_LINE_INTP0 10
#define NEC_INPUT_LINE_INTP1 11
#define NEC_INPUT_LINE_INTP2 12
#define NEC_INPUT_LINE_POLL 20
#define V25_PORT_P0 0x10000
#define V25_PORT_P1 0x10002
#define V25_PORT_P2 0x10004
#define V25_PORT_PT 0x10006
enum
{
V25_PC=0,
V25_IP, V25_AW, V25_CW, V25_DW, V25_BW, V25_SP, V25_BP, V25_IX, V25_IY,
V25_FLAGS, V25_ES, V25_CS, V25_SS, V25_DS,
V25_PENDING
};
#define MCFG_V25_CONFIG(_table) \
v25_common_device::set_decryption_table(*device, _table);
class v25_common_device : public cpu_device
{
public:
// construction/destruction
v25_common_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, bool is_16bit, offs_t fetch_xor, UINT8 prefetch_size, UINT8 prefetch_cycles, UINT32 chip_type);
// static configuration helpers
static void set_decryption_table(device_t &device, const UINT8 *decryption_table) { downcast<v25_common_device &>(device).m_v25v35_decryptiontable = decryption_table; }
TIMER_CALLBACK_MEMBER(v25_timer_callback);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 80; }
virtual UINT32 execute_input_lines() const { return 1; }
virtual UINT32 execute_default_irq_vector() const { return 0xff; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL); }
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
virtual void state_import(const device_state_entry &entry);
virtual void state_export(const device_state_entry &entry);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
virtual UINT32 disasm_max_opcode_bytes() const { return 8; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
address_space_config m_io_config;
/* internal RAM and register banks */
union internalram
{
UINT16 w[128];
UINT8 b[256];
};
internalram m_ram;
offs_t m_fetch_xor;
UINT16 m_ip;
/* PSW flags */
INT32 m_SignVal;
UINT32 m_AuxVal, m_OverVal, m_ZeroVal, m_CarryVal, m_ParityVal; /* 0 or non-0 valued flags */
UINT8 m_IBRK, m_F0, m_F1, m_TF, m_IF, m_DF, m_MF; /* 0 or 1 valued flags */
UINT8 m_RBW, m_RBB; /* current register bank base, preshifted for word and byte registers */
/* interrupt related */
UINT32 m_pending_irq;
UINT32 m_unmasked_irq;
UINT32 m_bankswitch_irq;
UINT8 m_priority_inttu, m_priority_intd, m_priority_intp, m_priority_ints0, m_priority_ints1;
UINT8 m_IRQS, m_ISPR;
UINT32 m_nmi_state;
UINT32 m_irq_state;
UINT32 m_poll_state;
UINT32 m_mode_state;
UINT32 m_intp_state[3];
UINT8 m_no_interrupt;
UINT8 m_halted;
/* timer related */
UINT16 m_TM0, m_MD0, m_TM1, m_MD1;
UINT8 m_TMC0, m_TMC1;
emu_timer *m_timers[4];
/* system control */
UINT8 m_RAMEN, m_TB, m_PCK; /* PRC register */
UINT32 m_IDB;
address_space *m_program;
direct_read_data *m_direct;
address_space *m_io;
int m_icount;
UINT8 m_prefetch_size;
UINT8 m_prefetch_cycles;
INT8 m_prefetch_count;
UINT8 m_prefetch_reset;
UINT32 m_chip_type;
UINT32 m_prefix_base; /* base address of the latest prefix segment */
UINT8 m_seg_prefix; /* prefix segment indicator */
UINT32 m_EA;
UINT16 m_EO;
UINT16 m_E16;
UINT32 m_debugger_temp;
const UINT8 *m_v25v35_decryptiontable; // internal decryption table
typedef void (v25_common_device::*nec_ophandler)();
typedef UINT32 (v25_common_device::*nec_eahandler)();
static const nec_ophandler s_nec_instruction[256];
static const nec_eahandler s_GetEA[192];
inline void prefetch();
void do_prefetch(int previous_ICount);
inline UINT8 fetch();
inline UINT16 fetchword();
inline UINT8 fetchop();
void nec_interrupt(unsigned int_num, int /*INTSOURCES*/ source);
void nec_bankswitch(unsigned bank_num);
void nec_trap();
void external_int();
UINT8 read_irqcontrol(int /*INTSOURCES*/ source, UINT8 priority);
UINT8 read_sfr(unsigned o);
UINT16 read_sfr_word(unsigned o);
void write_irqcontrol(int /*INTSOURCES*/ source, UINT8 d);
void write_sfr(unsigned o, UINT8 d);
void write_sfr_word(unsigned o, UINT16 d);
UINT8 v25_read_byte(unsigned a);
UINT16 v25_read_word(unsigned a);
void v25_write_byte(unsigned a, UINT8 d);
void v25_write_word(unsigned a, UINT16 d);
void i_add_br8();
void i_add_wr16();
void i_add_r8b();
void i_add_r16w();
void i_add_ald8();
void i_add_axd16();
void i_push_es();
void i_pop_es();
void i_or_br8();
void i_or_r8b();
void i_or_wr16();
void i_or_r16w();
void i_or_ald8();
void i_or_axd16();
void i_push_cs();
void i_pre_nec();
void i_pre_v25();
void i_adc_br8();
void i_adc_wr16();
void i_adc_r8b();
void i_adc_r16w();
void i_adc_ald8();
void i_adc_axd16();
void i_push_ss();
void i_pop_ss();
void i_sbb_br8();
void i_sbb_wr16();
void i_sbb_r8b();
void i_sbb_r16w();
void i_sbb_ald8();
void i_sbb_axd16();
void i_push_ds();
void i_pop_ds();
void i_and_br8();
void i_and_r8b();
void i_and_wr16();
void i_and_r16w();
void i_and_ald8();
void i_and_axd16();
void i_es();
void i_daa();
void i_sub_br8();
void i_sub_wr16();
void i_sub_r8b();
void i_sub_r16w();
void i_sub_ald8();
void i_sub_axd16();
void i_cs();
void i_das();
void i_xor_br8();
void i_xor_r8b();
void i_xor_wr16();
void i_xor_r16w();
void i_xor_ald8();
void i_xor_axd16();
void i_ss();
void i_aaa();
void i_cmp_br8();
void i_cmp_wr16();
void i_cmp_r8b();
void i_cmp_r16w();
void i_cmp_ald8();
void i_cmp_axd16();
void i_ds();
void i_aas();
void i_inc_ax();
void i_inc_cx();
void i_inc_dx();
void i_inc_bx();
void i_inc_sp();
void i_inc_bp();
void i_inc_si();
void i_inc_di();
void i_dec_ax();
void i_dec_cx();
void i_dec_dx();
void i_dec_bx();
void i_dec_sp();
void i_dec_bp();
void i_dec_si();
void i_dec_di();
void i_push_ax();
void i_push_cx();
void i_push_dx();
void i_push_bx();
void i_push_sp();
void i_push_bp();
void i_push_si();
void i_push_di();
void i_pop_ax();
void i_pop_cx();
void i_pop_dx();
void i_pop_bx();
void i_pop_sp();
void i_pop_bp();
void i_pop_si();
void i_pop_di();
void i_pusha();
void i_popa();
void i_chkind();
void i_repnc();
void i_repc();
void i_push_d16();
void i_imul_d16();
void i_push_d8();
void i_imul_d8();
void i_insb();
void i_insw();
void i_outsb();
void i_outsw();
void i_jo();
void i_jno();
void i_jc();
void i_jnc();
void i_jz();
void i_jnz();
void i_jce();
void i_jnce();
void i_js();
void i_jns();
void i_jp();
void i_jnp();
void i_jl();
void i_jnl();
void i_jle();
void i_jnle();
void i_80pre();
void i_82pre();
void i_81pre();
void i_83pre();
void i_test_br8();
void i_test_wr16();
void i_xchg_br8();
void i_xchg_wr16();
void i_mov_br8();
void i_mov_r8b();
void i_mov_wr16();
void i_mov_r16w();
void i_mov_wsreg();
void i_lea();
void i_mov_sregw();
void i_invalid();
void i_popw();
void i_nop();
void i_xchg_axcx();
void i_xchg_axdx();
void i_xchg_axbx();
void i_xchg_axsp();
void i_xchg_axbp();
void i_xchg_axsi();
void i_xchg_axdi();
void i_cbw();
void i_cwd();
void i_call_far();
void i_pushf();
void i_popf();
void i_sahf();
void i_lahf();
void i_mov_aldisp();
void i_mov_axdisp();
void i_mov_dispal();
void i_mov_dispax();
void i_movsb();
void i_movsw();
void i_cmpsb();
void i_cmpsw();
void i_test_ald8();
void i_test_axd16();
void i_stosb();
void i_stosw();
void i_lodsb();
void i_lodsw();
void i_scasb();
void i_scasw();
void i_mov_ald8();
void i_mov_cld8();
void i_mov_dld8();
void i_mov_bld8();
void i_mov_ahd8();
void i_mov_chd8();
void i_mov_dhd8();
void i_mov_bhd8();
void i_mov_axd16();
void i_mov_cxd16();
void i_mov_dxd16();
void i_mov_bxd16();
void i_mov_spd16();
void i_mov_bpd16();
void i_mov_sid16();
void i_mov_did16();
void i_rotshft_bd8();
void i_rotshft_wd8();
void i_ret_d16();
void i_ret();
void i_les_dw();
void i_lds_dw();
void i_mov_bd8();
void i_mov_wd16();
void i_enter();
void i_leave();
void i_retf_d16();
void i_retf();
void i_int3();
void i_int();
void i_into();
void i_iret();
void i_rotshft_b();
void i_rotshft_w();
void i_rotshft_bcl();
void i_rotshft_wcl();
void i_aam();
void i_aad();
void i_setalc();
void i_trans();
void i_fpo();
void i_loopne();
void i_loope();
void i_loop();
void i_jcxz();
void i_inal();
void i_inax();
void i_outal();
void i_outax();
void i_call_d16();
void i_jmp_d16();
void i_jmp_far();
void i_jmp_d8();
void i_inaldx();
void i_inaxdx();
void i_outdxal();
void i_outdxax();
void i_lock();
void i_repne();
void i_repe();
void i_hlt();
void i_cmc();
void i_f6pre();
void i_f7pre();
void i_clc();
void i_stc();
void i_di();
void i_ei();
void i_cld();
void i_std();
void i_fepre();
void i_ffpre();
void i_wait();
void i_brkn();
void i_brks();
UINT32 EA_000();
UINT32 EA_001();
UINT32 EA_002();
UINT32 EA_003();
UINT32 EA_004();
UINT32 EA_005();
UINT32 EA_006();
UINT32 EA_007();
UINT32 EA_100();
UINT32 EA_101();
UINT32 EA_102();
UINT32 EA_103();
UINT32 EA_104();
UINT32 EA_105();
UINT32 EA_106();
UINT32 EA_107();
UINT32 EA_200();
UINT32 EA_201();
UINT32 EA_202();
UINT32 EA_203();
UINT32 EA_204();
UINT32 EA_205();
UINT32 EA_206();
UINT32 EA_207();
};
class v25_device : public v25_common_device
{
public:
v25_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class v35_device : public v25_common_device
{
public:
v35_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
extern const device_type V25;
extern const device_type V35;
#endif

44
src/emu/cpu/nec/v25instr.c
View File

@ -3,47 +3,47 @@
if (ModRM >= 0xc0) \
tmp = Wreg(Mod_RM.RM.w[ModRM]) & 0x7; \
else { \
logerror("%06x: Invalid MODRM for register banking instruction\n",PC(nec_state)); \
logerror("%06x: Invalid MODRM for register banking instruction\n",PC()); \
tmp = 0; \
}
#define RETRBI \
tmp = (Wreg(PSW_SAVE) & 0x7000) >> 12; \
nec_state->ip = Wreg(PC_SAVE); \
m_ip = Wreg(PC_SAVE); \
ExpandFlags(Wreg(PSW_SAVE)); \
SetRB(tmp); \
CHANGE_PC
#define TSKSW \
Wreg(PSW_SAVE) = CompressFlags(); \
Wreg(PC_SAVE) = nec_state->ip; \
Wreg(PC_SAVE) = m_ip; \
SetRB(tmp); \
nec_state->ip = Wreg(PC_SAVE); \
m_ip = Wreg(PC_SAVE); \
ExpandFlags(Wreg(PSW_SAVE)); \
CHANGE_PC
#define MOVSPA \
tmp = (Wreg(PSW_SAVE) & 0x7000) >> 8; \
Sreg(SS) = nec_state->ram.w[tmp+SS]; \
Wreg(SP) = nec_state->ram.w[tmp+SP]
Sreg(SS) = m_ram.w[tmp+SS]; \
Wreg(SP) = m_ram.w[tmp+SP]
#define MOVSPB \
tmp <<= 4; \
nec_state->ram.w[tmp+SS] = Sreg(SS); \
nec_state->ram.w[tmp+SP] = Wreg(SP)
m_ram.w[tmp+SS] = Sreg(SS); \
m_ram.w[tmp+SP] = Wreg(SP)
#define FINT \
for(tmp = 1; tmp < 0x100; tmp <<= 1) { \
if(nec_state->ISPR & tmp) { \
nec_state->ISPR &= ~tmp; \
if(m_ISPR & tmp) { \
m_ISPR &= ~tmp; \
break; \
} \
}
OP( 0x0f, i_pre_v25 ) { UINT32 ModRM, tmp, tmp2;
switch (FETCH()) {
case 0x10 : BITOP_BYTE; CLKS(3,3,4); tmp2 = Breg(CL) & 0x7; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x11 : BITOP_WORD; CLKS(3,3,4); tmp2 = Breg(CL) & 0xf; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x10 : BITOP_BYTE; CLKS(3,3,4); tmp2 = Breg(CL) & 0x7; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x11 : BITOP_WORD; CLKS(3,3,4); tmp2 = Breg(CL) & 0xf; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x12 : BITOP_BYTE; CLKS(5,5,4); tmp2 = Breg(CL) & 0x7; tmp &= ~(1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Clr */
case 0x13 : BITOP_WORD; CLKS(5,5,4); tmp2 = Breg(CL) & 0xf; tmp &= ~(1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Clr */
case 0x14 : BITOP_BYTE; CLKS(4,4,4); tmp2 = Breg(CL) & 0x7; tmp |= (1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Set */
@ -51,8 +51,8 @@ OP( 0x0f, i_pre_v25 ) { UINT32 ModRM, tmp, tmp2;
case 0x16 : BITOP_BYTE; CLKS(4,4,4); tmp2 = Breg(CL) & 0x7; BIT_NOT; PutbackRMByte(ModRM,tmp); break; /* Not */
case 0x17 : BITOP_WORD; CLKS(4,4,4); tmp2 = Breg(CL) & 0xf; BIT_NOT; PutbackRMWord(ModRM,tmp); break; /* Not */
case 0x18 : BITOP_BYTE; CLKS(4,4,4); tmp2 = (FETCH()) & 0x7; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x19 : BITOP_WORD; CLKS(4,4,4); tmp2 = (FETCH()) & 0xf; nec_state->ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; nec_state->CarryVal=nec_state->OverVal=0; break; /* Test */
case 0x18 : BITOP_BYTE; CLKS(4,4,4); tmp2 = (FETCH()) & 0x7; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x19 : BITOP_WORD; CLKS(4,4,4); tmp2 = (FETCH()) & 0xf; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */
case 0x1a : BITOP_BYTE; CLKS(6,6,4); tmp2 = (FETCH()) & 0x7; tmp &= ~(1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Clr */
case 0x1b : BITOP_WORD; CLKS(6,6,4); tmp2 = (FETCH()) & 0xf; tmp &= ~(1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Clr */
case 0x1c : BITOP_BYTE; CLKS(5,5,4); tmp2 = (FETCH()) & 0x7; tmp |= (1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Set */
@ -66,17 +66,17 @@ OP( 0x0f, i_pre_v25 ) { UINT32 ModRM, tmp, tmp2;
case 0x26 : CMP4S; CLKS(7,7,2); break;
case 0x28 : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= Breg(AL) & 0xf; Breg(AL) = (Breg(AL) & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(13,13,9,28,28,15); break;
case 0x2a : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp2 = (Breg(AL) & 0xf)<<4; Breg(AL) = (Breg(AL) & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(17,17,13,32,32,19); break;
case 0x2d : GetRB; nec_bankswitch(nec_state, tmp); CLK(15); break;
case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC(nec_state)); break;
case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC(nec_state)); break;
case 0x2d : GetRB; nec_bankswitch(tmp); CLK(15); break;
case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC()); break;
case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC()); break;
case 0x91 : RETRBI; CLK(12); break;
case 0x92 : FINT; CLK(2); nec_state->no_interrupt = 1; break;
case 0x92 : FINT; CLK(2); m_no_interrupt = 1; break;
case 0x94 : GetRB; TSKSW; CLK(20); break;
case 0x95 : GetRB; MOVSPB; CLK(11); break;
case 0x9e : logerror("%06x: STOP\n",PC(nec_state)); nec_state->icount=0; break;
default: logerror("%06x: Unknown V25 instruction\n",PC(nec_state)); break;
case 0x9e : logerror("%06x: STOP\n",PC()); m_icount=0; break;
default: logerror("%06x: Unknown V25 instruction\n",PC()); break;
}
}
OP( 0x63, i_brkn ) { nec_interrupt(nec_state, FETCH(), BRKN); CLKS(50,50,24); }
OP( 0xF1, i_brks ) { nec_interrupt(nec_state, FETCH(), BRKS); CLKS(50,50,24); }
OP( 0x63, i_brkn ) { nec_interrupt(FETCH(), BRKN); CLKS(50,50,24); }
OP( 0xF1, i_brks ) { nec_interrupt(FETCH(), BRKS); CLKS(50,50,24); }

765
src/emu/cpu/nec/v25instr.h
View File

@ -1,510 +1,259 @@
static void i_add_br8(nec_state_t *nec_state);
static void i_add_wr16(nec_state_t *nec_state);
static void i_add_r8b(nec_state_t *nec_state);
static void i_add_r16w(nec_state_t *nec_state);
static void i_add_ald8(nec_state_t *nec_state);
static void i_add_axd16(nec_state_t *nec_state);
static void i_push_es(nec_state_t *nec_state);
static void i_pop_es(nec_state_t *nec_state);
static void i_or_br8(nec_state_t *nec_state);
static void i_or_r8b(nec_state_t *nec_state);
static void i_or_wr16(nec_state_t *nec_state);
static void i_or_r16w(nec_state_t *nec_state);
static void i_or_ald8(nec_state_t *nec_state);
static void i_or_axd16(nec_state_t *nec_state);
static void i_push_cs(nec_state_t *nec_state);
ATTR_UNUSED static void i_pre_nec(nec_state_t *nec_state);
static void i_pre_v25(nec_state_t *nec_state);
static void i_adc_br8(nec_state_t *nec_state);
static void i_adc_wr16(nec_state_t *nec_state);
static void i_adc_r8b(nec_state_t *nec_state);
static void i_adc_r16w(nec_state_t *nec_state);
static void i_adc_ald8(nec_state_t *nec_state);
static void i_adc_axd16(nec_state_t *nec_state);
static void i_push_ss(nec_state_t *nec_state);
static void i_pop_ss(nec_state_t *nec_state);
static void i_sbb_br8(nec_state_t *nec_state);
static void i_sbb_wr16(nec_state_t *nec_state);
static void i_sbb_r8b(nec_state_t *nec_state);
static void i_sbb_r16w(nec_state_t *nec_state);
static void i_sbb_ald8(nec_state_t *nec_state);
static void i_sbb_axd16(nec_state_t *nec_state);
static void i_push_ds(nec_state_t *nec_state);
static void i_pop_ds(nec_state_t *nec_state);
static void i_and_br8(nec_state_t *nec_state);
static void i_and_r8b(nec_state_t *nec_state);
static void i_and_wr16(nec_state_t *nec_state);
static void i_and_r16w(nec_state_t *nec_state);
static void i_and_ald8(nec_state_t *nec_state);
static void i_and_axd16(nec_state_t *nec_state);
static void i_es(nec_state_t *nec_state);
static void i_daa(nec_state_t *nec_state);
static void i_sub_br8(nec_state_t *nec_state);
static void i_sub_wr16(nec_state_t *nec_state);
static void i_sub_r8b(nec_state_t *nec_state);
static void i_sub_r16w(nec_state_t *nec_state);
static void i_sub_ald8(nec_state_t *nec_state);
static void i_sub_axd16(nec_state_t *nec_state);
static void i_cs(nec_state_t *nec_state);
static void i_das(nec_state_t *nec_state);
static void i_xor_br8(nec_state_t *nec_state);
static void i_xor_r8b(nec_state_t *nec_state);
static void i_xor_wr16(nec_state_t *nec_state);
static void i_xor_r16w(nec_state_t *nec_state);
static void i_xor_ald8(nec_state_t *nec_state);
static void i_xor_axd16(nec_state_t *nec_state);
static void i_ss(nec_state_t *nec_state);
static void i_aaa(nec_state_t *nec_state);
static void i_cmp_br8(nec_state_t *nec_state);
static void i_cmp_wr16(nec_state_t *nec_state);
static void i_cmp_r8b(nec_state_t *nec_state);
static void i_cmp_r16w(nec_state_t *nec_state);
static void i_cmp_ald8(nec_state_t *nec_state);
static void i_cmp_axd16(nec_state_t *nec_state);
static void i_ds(nec_state_t *nec_state);
static void i_aas(nec_state_t *nec_state);
static void i_inc_ax(nec_state_t *nec_state);
static void i_inc_cx(nec_state_t *nec_state);
static void i_inc_dx(nec_state_t *nec_state);
static void i_inc_bx(nec_state_t *nec_state);
static void i_inc_sp(nec_state_t *nec_state);
static void i_inc_bp(nec_state_t *nec_state);
static void i_inc_si(nec_state_t *nec_state);
static void i_inc_di(nec_state_t *nec_state);
static void i_dec_ax(nec_state_t *nec_state);
static void i_dec_cx(nec_state_t *nec_state);
static void i_dec_dx(nec_state_t *nec_state);
static void i_dec_bx(nec_state_t *nec_state);
static void i_dec_sp(nec_state_t *nec_state);
static void i_dec_bp(nec_state_t *nec_state);
static void i_dec_si(nec_state_t *nec_state);
static void i_dec_di(nec_state_t *nec_state);
static void i_push_ax(nec_state_t *nec_state);
static void i_push_cx(nec_state_t *nec_state);
static void i_push_dx(nec_state_t *nec_state);
static void i_push_bx(nec_state_t *nec_state);
static void i_push_sp(nec_state_t *nec_state);
static void i_push_bp(nec_state_t *nec_state);
static void i_push_si(nec_state_t *nec_state);
static void i_push_di(nec_state_t *nec_state);
static void i_pop_ax(nec_state_t *nec_state);
static void i_pop_cx(nec_state_t *nec_state);
static void i_pop_dx(nec_state_t *nec_state);
static void i_pop_bx(nec_state_t *nec_state);
static void i_pop_sp(nec_state_t *nec_state);
static void i_pop_bp(nec_state_t *nec_state);
static void i_pop_si(nec_state_t *nec_state);
static void i_pop_di(nec_state_t *nec_state);
static void i_pusha(nec_state_t *nec_state);
static void i_popa(nec_state_t *nec_state);
static void i_chkind(nec_state_t *nec_state);
static void i_brkn(nec_state_t *nec_state);
static void i_repnc(nec_state_t *nec_state);
static void i_repc(nec_state_t *nec_state);
static void i_push_d16(nec_state_t *nec_state);
static void i_imul_d16(nec_state_t *nec_state);
static void i_push_d8(nec_state_t *nec_state);
static void i_imul_d8(nec_state_t *nec_state);
static void i_insb(nec_state_t *nec_state);
static void i_insw(nec_state_t *nec_state);
static void i_outsb(nec_state_t *nec_state);
static void i_outsw(nec_state_t *nec_state);
static void i_jo(nec_state_t *nec_state);
static void i_jno(nec_state_t *nec_state);
static void i_jc(nec_state_t *nec_state);
static void i_jnc(nec_state_t *nec_state);
static void i_jz(nec_state_t *nec_state);
static void i_jnz(nec_state_t *nec_state);
static void i_jce(nec_state_t *nec_state);
static void i_jnce(nec_state_t *nec_state);
static void i_js(nec_state_t *nec_state);
static void i_jns(nec_state_t *nec_state);
static void i_jp(nec_state_t *nec_state);
static void i_jnp(nec_state_t *nec_state);
static void i_jl(nec_state_t *nec_state);
static void i_jnl(nec_state_t *nec_state);
static void i_jle(nec_state_t *nec_state);
static void i_jnle(nec_state_t *nec_state);
static void i_80pre(nec_state_t *nec_state);
static void i_82pre(nec_state_t *nec_state);
static void i_81pre(nec_state_t *nec_state);
static void i_83pre(nec_state_t *nec_state);
static void i_test_br8(nec_state_t *nec_state);
static void i_test_wr16(nec_state_t *nec_state);
static void i_xchg_br8(nec_state_t *nec_state);
static void i_xchg_wr16(nec_state_t *nec_state);
static void i_mov_br8(nec_state_t *nec_state);
static void i_mov_r8b(nec_state_t *nec_state);
static void i_mov_wr16(nec_state_t *nec_state);
static void i_mov_r16w(nec_state_t *nec_state);
static void i_mov_wsreg(nec_state_t *nec_state);
static void i_lea(nec_state_t *nec_state);
static void i_mov_sregw(nec_state_t *nec_state);
static void i_invalid(nec_state_t *nec_state);
static void i_popw(nec_state_t *nec_state);
static void i_nop(nec_state_t *nec_state);
static void i_xchg_axcx(nec_state_t *nec_state);
static void i_xchg_axdx(nec_state_t *nec_state);
static void i_xchg_axbx(nec_state_t *nec_state);
static void i_xchg_axsp(nec_state_t *nec_state);
static void i_xchg_axbp(nec_state_t *nec_state);
static void i_xchg_axsi(nec_state_t *nec_state);
static void i_xchg_axdi(nec_state_t *nec_state);
static void i_cbw(nec_state_t *nec_state);
static void i_cwd(nec_state_t *nec_state);
static void i_call_far(nec_state_t *nec_state);
static void i_pushf(nec_state_t *nec_state);
static void i_popf(nec_state_t *nec_state);
static void i_sahf(nec_state_t *nec_state);
static void i_lahf(nec_state_t *nec_state);
static void i_mov_aldisp(nec_state_t *nec_state);
static void i_mov_axdisp(nec_state_t *nec_state);
static void i_mov_dispal(nec_state_t *nec_state);
static void i_mov_dispax(nec_state_t *nec_state);
static void i_movsb(nec_state_t *nec_state);
static void i_movsw(nec_state_t *nec_state);
static void i_cmpsb(nec_state_t *nec_state);
static void i_cmpsw(nec_state_t *nec_state);
static void i_test_ald8(nec_state_t *nec_state);
static void i_test_axd16(nec_state_t *nec_state);
static void i_stosb(nec_state_t *nec_state);
static void i_stosw(nec_state_t *nec_state);
static void i_lodsb(nec_state_t *nec_state);
static void i_lodsw(nec_state_t *nec_state);
static void i_scasb(nec_state_t *nec_state);
static void i_scasw(nec_state_t *nec_state);
static void i_mov_ald8(nec_state_t *nec_state);
static void i_mov_cld8(nec_state_t *nec_state);
static void i_mov_dld8(nec_state_t *nec_state);
static void i_mov_bld8(nec_state_t *nec_state);
static void i_mov_ahd8(nec_state_t *nec_state);
static void i_mov_chd8(nec_state_t *nec_state);
static void i_mov_dhd8(nec_state_t *nec_state);
static void i_mov_bhd8(nec_state_t *nec_state);
static void i_mov_axd16(nec_state_t *nec_state);
static void i_mov_cxd16(nec_state_t *nec_state);
static void i_mov_dxd16(nec_state_t *nec_state);
static void i_mov_bxd16(nec_state_t *nec_state);
static void i_mov_spd16(nec_state_t *nec_state);
static void i_mov_bpd16(nec_state_t *nec_state);
static void i_mov_sid16(nec_state_t *nec_state);
static void i_mov_did16(nec_state_t *nec_state);
static void i_rotshft_bd8(nec_state_t *nec_state);
static void i_rotshft_wd8(nec_state_t *nec_state);
static void i_ret_d16(nec_state_t *nec_state);
static void i_ret(nec_state_t *nec_state);
static void i_les_dw(nec_state_t *nec_state);
static void i_lds_dw(nec_state_t *nec_state);
static void i_mov_bd8(nec_state_t *nec_state);
static void i_mov_wd16(nec_state_t *nec_state);
static void i_enter(nec_state_t *nec_state);
static void i_leave(nec_state_t *nec_state);
static void i_retf_d16(nec_state_t *nec_state);
static void i_retf(nec_state_t *nec_state);
static void i_int3(nec_state_t *nec_state);
static void i_int(nec_state_t *nec_state);
static void i_into(nec_state_t *nec_state);
static void i_iret(nec_state_t *nec_state);
static void i_rotshft_b(nec_state_t *nec_state);
static void i_rotshft_w(nec_state_t *nec_state);
static void i_rotshft_bcl(nec_state_t *nec_state);
static void i_rotshft_wcl(nec_state_t *nec_state);
static void i_aam(nec_state_t *nec_state);
static void i_aad(nec_state_t *nec_state);
static void i_setalc(nec_state_t *nec_state);
static void i_trans(nec_state_t *nec_state);
static void i_fpo(nec_state_t *nec_state);
static void i_loopne(nec_state_t *nec_state);
static void i_loope(nec_state_t *nec_state);
static void i_loop(nec_state_t *nec_state);
static void i_jcxz(nec_state_t *nec_state);
static void i_inal(nec_state_t *nec_state);
static void i_inax(nec_state_t *nec_state);
static void i_outal(nec_state_t *nec_state);
static void i_outax(nec_state_t *nec_state);
static void i_call_d16(nec_state_t *nec_state);
static void i_jmp_d16(nec_state_t *nec_state);
static void i_jmp_far(nec_state_t *nec_state);
static void i_jmp_d8(nec_state_t *nec_state);
static void i_inaldx(nec_state_t *nec_state);
static void i_inaxdx(nec_state_t *nec_state);
static void i_outdxal(nec_state_t *nec_state);
static void i_outdxax(nec_state_t *nec_state);
static void i_lock(nec_state_t *nec_state);
static void i_brks(nec_state_t *nec_state);
static void i_repne(nec_state_t *nec_state);
static void i_repe(nec_state_t *nec_state);
static void i_hlt(nec_state_t *nec_state);
static void i_cmc(nec_state_t *nec_state);
static void i_f6pre(nec_state_t *nec_state);
static void i_f7pre(nec_state_t *nec_state);
static void i_clc(nec_state_t *nec_state);
static void i_stc(nec_state_t *nec_state);
static void i_di(nec_state_t *nec_state);
static void i_ei(nec_state_t *nec_state);
static void i_cld(nec_state_t *nec_state);
static void i_std(nec_state_t *nec_state);
static void i_fepre(nec_state_t *nec_state);
static void i_ffpre(nec_state_t *nec_state);
static void i_wait(nec_state_t *nec_state);
static void (*const nec_instruction[256])(nec_state_t *nec_state) =
const v25_common_device::nec_ophandler v25_common_device::s_nec_instruction[256] =
{
i_add_br8, /* 0x00 */
i_add_wr16, /* 0x01 */
i_add_r8b, /* 0x02 */
i_add_r16w, /* 0x03 */
i_add_ald8, /* 0x04 */
i_add_axd16, /* 0x05 */
i_push_es, /* 0x06 */
i_pop_es, /* 0x07 */
i_or_br8, /* 0x08 */
i_or_wr16, /* 0x09 */
i_or_r8b, /* 0x0a */
i_or_r16w, /* 0x0b */
i_or_ald8, /* 0x0c */
i_or_axd16, /* 0x0d */
i_push_cs, /* 0x0e */
i_pre_v25, /* 0x0f */
i_adc_br8, /* 0x10 */
i_adc_wr16, /* 0x11 */
i_adc_r8b, /* 0x12 */
i_adc_r16w, /* 0x13 */
i_adc_ald8, /* 0x14 */
i_adc_axd16, /* 0x15 */
i_push_ss, /* 0x16 */
i_pop_ss, /* 0x17 */
i_sbb_br8, /* 0x18 */
i_sbb_wr16, /* 0x19 */
i_sbb_r8b, /* 0x1a */
i_sbb_r16w, /* 0x1b */
i_sbb_ald8, /* 0x1c */
i_sbb_axd16, /* 0x1d */
i_push_ds, /* 0x1e */
i_pop_ds, /* 0x1f */
i_and_br8, /* 0x20 */
i_and_wr16, /* 0x21 */
i_and_r8b, /* 0x22 */
i_and_r16w, /* 0x23 */
i_and_ald8, /* 0x24 */
i_and_axd16, /* 0x25 */
i_es, /* 0x26 */
i_daa, /* 0x27 */
i_sub_br8, /* 0x28 */
i_sub_wr16, /* 0x29 */
i_sub_r8b, /* 0x2a */
i_sub_r16w, /* 0x2b */
i_sub_ald8, /* 0x2c */
i_sub_axd16, /* 0x2d */
i_cs, /* 0x2e */
i_das, /* 0x2f */
i_xor_br8, /* 0x30 */
i_xor_wr16, /* 0x31 */
i_xor_r8b, /* 0x32 */
i_xor_r16w, /* 0x33 */
i_xor_ald8, /* 0x34 */
i_xor_axd16, /* 0x35 */
i_ss, /* 0x36 */
i_aaa, /* 0x37 */
i_cmp_br8, /* 0x38 */
i_cmp_wr16, /* 0x39 */
i_cmp_r8b, /* 0x3a */
i_cmp_r16w, /* 0x3b */
i_cmp_ald8, /* 0x3c */
i_cmp_axd16, /* 0x3d */
i_ds, /* 0x3e */
i_aas, /* 0x3f */
i_inc_ax, /* 0x40 */
i_inc_cx, /* 0x41 */
i_inc_dx, /* 0x42 */
i_inc_bx, /* 0x43 */
i_inc_sp, /* 0x44 */
i_inc_bp, /* 0x45 */
i_inc_si, /* 0x46 */
i_inc_di, /* 0x47 */
i_dec_ax, /* 0x48 */
i_dec_cx, /* 0x49 */
i_dec_dx, /* 0x4a */
i_dec_bx, /* 0x4b */
i_dec_sp, /* 0x4c */
i_dec_bp, /* 0x4d */
i_dec_si, /* 0x4e */
i_dec_di, /* 0x4f */
i_push_ax, /* 0x50 */
i_push_cx, /* 0x51 */
i_push_dx, /* 0x52 */
i_push_bx, /* 0x53 */
i_push_sp, /* 0x54 */
i_push_bp, /* 0x55 */
i_push_si, /* 0x56 */
i_push_di, /* 0x57 */
i_pop_ax, /* 0x58 */
i_pop_cx, /* 0x59 */
i_pop_dx, /* 0x5a */
i_pop_bx, /* 0x5b */
i_pop_sp, /* 0x5c */
i_pop_bp, /* 0x5d */
i_pop_si, /* 0x5e */
i_pop_di, /* 0x5f */
i_pusha, /* 0x60 */
i_popa, /* 0x61 */
i_chkind, /* 0x62 */
i_brkn, /* 0x63 - V25S/V35S only */
i_repnc, /* 0x64 */
i_repc, /* 0x65 */
i_invalid, /* 0x66 */
i_invalid, /* 0x67 */
i_push_d16, /* 0x68 */
i_imul_d16, /* 0x69 */
i_push_d8, /* 0x6a */
i_imul_d8, /* 0x6b */
i_insb, /* 0x6c */
i_insw, /* 0x6d */
i_outsb, /* 0x6e */
i_outsw, /* 0x6f */
i_jo, /* 0x70 */
i_jno, /* 0x71 */
i_jc, /* 0x72 */
i_jnc, /* 0x73 */
i_jz, /* 0x74 */
i_jnz, /* 0x75 */
i_jce, /* 0x76 */
i_jnce, /* 0x77 */
i_js, /* 0x78 */
i_jns, /* 0x79 */
i_jp, /* 0x7a */
i_jnp, /* 0x7b */
i_jl, /* 0x7c */
i_jnl, /* 0x7d */
i_jle, /* 0x7e */
i_jnle, /* 0x7f */
i_80pre, /* 0x80 */
i_81pre, /* 0x81 */
i_82pre, /* 0x82 */
i_83pre, /* 0x83 */
i_test_br8, /* 0x84 */
i_test_wr16, /* 0x85 */
i_xchg_br8, /* 0x86 */
i_xchg_wr16, /* 0x87 */
i_mov_br8, /* 0x88 */
i_mov_wr16, /* 0x89 */
i_mov_r8b, /* 0x8a */
i_mov_r16w, /* 0x8b */
i_mov_wsreg, /* 0x8c */
i_lea, /* 0x8d */
i_mov_sregw, /* 0x8e */
i_popw, /* 0x8f */
i_nop, /* 0x90 */
i_xchg_axcx, /* 0x91 */
i_xchg_axdx, /* 0x92 */
i_xchg_axbx, /* 0x93 */
i_xchg_axsp, /* 0x94 */
i_xchg_axbp, /* 0x95 */
i_xchg_axsi, /* 0x96 */
i_xchg_axdi, /* 0x97 */
i_cbw, /* 0x98 */
i_cwd, /* 0x99 */
i_call_far, /* 0x9a */
i_wait, /* 0x9b */
i_pushf, /* 0x9c */
i_popf, /* 0x9d */
i_sahf, /* 0x9e */
i_lahf, /* 0x9f */
i_mov_aldisp, /* 0xa0 */
i_mov_axdisp, /* 0xa1 */
i_mov_dispal, /* 0xa2 */
i_mov_dispax, /* 0xa3 */
i_movsb, /* 0xa4 */
i_movsw, /* 0xa5 */
i_cmpsb, /* 0xa6 */
i_cmpsw, /* 0xa7 */
i_test_ald8, /* 0xa8 */
i_test_axd16, /* 0xa9 */
i_stosb, /* 0xaa */
i_stosw, /* 0xab */
i_lodsb, /* 0xac */
i_lodsw, /* 0xad */
i_scasb, /* 0xae */
i_scasw, /* 0xaf */
i_mov_ald8, /* 0xb0 */
i_mov_cld8, /* 0xb1 */
i_mov_dld8, /* 0xb2 */
i_mov_bld8, /* 0xb3 */
i_mov_ahd8, /* 0xb4 */
i_mov_chd8, /* 0xb5 */
i_mov_dhd8, /* 0xb6 */
i_mov_bhd8, /* 0xb7 */
i_mov_axd16, /* 0xb8 */
i_mov_cxd16, /* 0xb9 */
i_mov_dxd16, /* 0xba */
i_mov_bxd16, /* 0xbb */
i_mov_spd16, /* 0xbc */
i_mov_bpd16, /* 0xbd */
i_mov_sid16, /* 0xbe */
i_mov_did16, /* 0xbf */
i_rotshft_bd8, /* 0xc0 */
i_rotshft_wd8, /* 0xc1 */
i_ret_d16, /* 0xc2 */
i_ret, /* 0xc3 */
i_les_dw, /* 0xc4 */
i_lds_dw, /* 0xc5 */
i_mov_bd8, /* 0xc6 */
i_mov_wd16, /* 0xc7 */
i_enter, /* 0xc8 */
i_leave, /* 0xc9 */
i_retf_d16, /* 0xca */
i_retf, /* 0xcb */
i_int3, /* 0xcc */
i_int, /* 0xcd */
i_into, /* 0xce */
i_iret, /* 0xcf */
i_rotshft_b, /* 0xd0 */
i_rotshft_w, /* 0xd1 */
i_rotshft_bcl, /* 0xd2 */
i_rotshft_wcl, /* 0xd3 */
i_aam, /* 0xd4 */
i_aad, /* 0xd5 */
i_setalc, /* 0xd6 */
i_trans, /* 0xd7 */
i_fpo, /* 0xd8 */
i_fpo, /* 0xd9 */
i_fpo, /* 0xda */
i_fpo, /* 0xdb */
i_fpo, /* 0xdc */
i_fpo, /* 0xdd */
i_fpo, /* 0xde */
i_fpo, /* 0xdf */
i_loopne, /* 0xe0 */
i_loope, /* 0xe1 */
i_loop, /* 0xe2 */
i_jcxz, /* 0xe3 */
i_inal, /* 0xe4 */
i_inax, /* 0xe5 */
i_outal, /* 0xe6 */
i_outax, /* 0xe7 */
i_call_d16, /* 0xe8 */
i_jmp_d16, /* 0xe9 */
i_jmp_far, /* 0xea */
i_jmp_d8, /* 0xeb */
i_inaldx, /* 0xec */
i_inaxdx, /* 0xed */
i_outdxal, /* 0xee */
i_outdxax, /* 0xef */
i_lock, /* 0xf0 */
i_brks, /* 0xf1 */
i_repne, /* 0xf2 */
i_repe, /* 0xf3 */
i_hlt, /* 0xf4 */
i_cmc, /* 0xf5 */
i_f6pre, /* 0xf6 */
i_f7pre, /* 0xf7 */
i_clc, /* 0xf8 */
i_stc, /* 0xf9 */
i_di, /* 0xfa */
i_ei, /* 0xfb */
i_cld, /* 0xfc */
i_std, /* 0xfd */
i_fepre, /* 0xfe */
i_ffpre /* 0xff */
&v25_common_device::i_add_br8, /* 0x00 */
&v25_common_device::i_add_wr16, /* 0x01 */
&v25_common_device::i_add_r8b, /* 0x02 */
&v25_common_device::i_add_r16w, /* 0x03 */
&v25_common_device::i_add_ald8, /* 0x04 */
&v25_common_device::i_add_axd16, /* 0x05 */
&v25_common_device::i_push_es, /* 0x06 */
&v25_common_device::i_pop_es, /* 0x07 */
&v25_common_device::i_or_br8, /* 0x08 */
&v25_common_device::i_or_wr16, /* 0x09 */
&v25_common_device::i_or_r8b, /* 0x0a */
&v25_common_device::i_or_r16w, /* 0x0b */
&v25_common_device::i_or_ald8, /* 0x0c */
&v25_common_device::i_or_axd16, /* 0x0d */
&v25_common_device::i_push_cs, /* 0x0e */
&v25_common_device::i_pre_v25, /* 0x0f */
&v25_common_device::i_adc_br8, /* 0x10 */
&v25_common_device::i_adc_wr16, /* 0x11 */
&v25_common_device::i_adc_r8b, /* 0x12 */
&v25_common_device::i_adc_r16w, /* 0x13 */
&v25_common_device::i_adc_ald8, /* 0x14 */
&v25_common_device::i_adc_axd16, /* 0x15 */
&v25_common_device::i_push_ss, /* 0x16 */
&v25_common_device::i_pop_ss, /* 0x17 */
&v25_common_device::i_sbb_br8, /* 0x18 */
&v25_common_device::i_sbb_wr16, /* 0x19 */
&v25_common_device::i_sbb_r8b, /* 0x1a */
&v25_common_device::i_sbb_r16w, /* 0x1b */
&v25_common_device::i_sbb_ald8, /* 0x1c */
&v25_common_device::i_sbb_axd16, /* 0x1d */
&v25_common_device::i_push_ds, /* 0x1e */
&v25_common_device::i_pop_ds, /* 0x1f */
&v25_common_device::i_and_br8, /* 0x20 */
&v25_common_device::i_and_wr16, /* 0x21 */
&v25_common_device::i_and_r8b, /* 0x22 */
&v25_common_device::i_and_r16w, /* 0x23 */
&v25_common_device::i_and_ald8, /* 0x24 */
&v25_common_device::i_and_axd16, /* 0x25 */
&v25_common_device::i_es, /* 0x26 */
&v25_common_device::i_daa, /* 0x27 */
&v25_common_device::i_sub_br8, /* 0x28 */
&v25_common_device::i_sub_wr16, /* 0x29 */
&v25_common_device::i_sub_r8b, /* 0x2a */
&v25_common_device::i_sub_r16w, /* 0x2b */
&v25_common_device::i_sub_ald8, /* 0x2c */
&v25_common_device::i_sub_axd16, /* 0x2d */
&v25_common_device::i_cs, /* 0x2e */
&v25_common_device::i_das, /* 0x2f */
&v25_common_device::i_xor_br8, /* 0x30 */
&v25_common_device::i_xor_wr16, /* 0x31 */
&v25_common_device::i_xor_r8b, /* 0x32 */
&v25_common_device::i_xor_r16w, /* 0x33 */
&v25_common_device::i_xor_ald8, /* 0x34 */
&v25_common_device::i_xor_axd16, /* 0x35 */
&v25_common_device::i_ss, /* 0x36 */
&v25_common_device::i_aaa, /* 0x37 */
&v25_common_device::i_cmp_br8, /* 0x38 */
&v25_common_device::i_cmp_wr16, /* 0x39 */
&v25_common_device::i_cmp_r8b, /* 0x3a */
&v25_common_device::i_cmp_r16w, /* 0x3b */
&v25_common_device::i_cmp_ald8, /* 0x3c */
&v25_common_device::i_cmp_axd16, /* 0x3d */
&v25_common_device::i_ds, /* 0x3e */
&v25_common_device::i_aas, /* 0x3f */
&v25_common_device::i_inc_ax, /* 0x40 */
&v25_common_device::i_inc_cx, /* 0x41 */
&v25_common_device::i_inc_dx, /* 0x42 */
&v25_common_device::i_inc_bx, /* 0x43 */
&v25_common_device::i_inc_sp, /* 0x44 */
&v25_common_device::i_inc_bp, /* 0x45 */
&v25_common_device::i_inc_si, /* 0x46 */
&v25_common_device::i_inc_di, /* 0x47 */
&v25_common_device::i_dec_ax, /* 0x48 */
&v25_common_device::i_dec_cx, /* 0x49 */
&v25_common_device::i_dec_dx, /* 0x4a */
&v25_common_device::i_dec_bx, /* 0x4b */
&v25_common_device::i_dec_sp, /* 0x4c */
&v25_common_device::i_dec_bp, /* 0x4d */
&v25_common_device::i_dec_si, /* 0x4e */
&v25_common_device::i_dec_di, /* 0x4f */
&v25_common_device::i_push_ax, /* 0x50 */
&v25_common_device::i_push_cx, /* 0x51 */
&v25_common_device::i_push_dx, /* 0x52 */
&v25_common_device::i_push_bx, /* 0x53 */
&v25_common_device::i_push_sp, /* 0x54 */
&v25_common_device::i_push_bp, /* 0x55 */
&v25_common_device::i_push_si, /* 0x56 */
&v25_common_device::i_push_di, /* 0x57 */
&v25_common_device::i_pop_ax, /* 0x58 */
&v25_common_device::i_pop_cx, /* 0x59 */
&v25_common_device::i_pop_dx, /* 0x5a */
&v25_common_device::i_pop_bx, /* 0x5b */
&v25_common_device::i_pop_sp, /* 0x5c */
&v25_common_device::i_pop_bp, /* 0x5d */
&v25_common_device::i_pop_si, /* 0x5e */
&v25_common_device::i_pop_di, /* 0x5f */
&v25_common_device::i_pusha, /* 0x60 */
&v25_common_device::i_popa, /* 0x61 */
&v25_common_device::i_chkind, /* 0x62 */
&v25_common_device::i_brkn, /* 0x63 - V25S/V35S only */
&v25_common_device::i_repnc, /* 0x64 */
&v25_common_device::i_repc, /* 0x65 */
&v25_common_device::i_invalid, /* 0x66 */
&v25_common_device::i_invalid, /* 0x67 */
&v25_common_device::i_push_d16, /* 0x68 */
&v25_common_device::i_imul_d16, /* 0x69 */
&v25_common_device::i_push_d8, /* 0x6a */
&v25_common_device::i_imul_d8, /* 0x6b */
&v25_common_device::i_insb, /* 0x6c */
&v25_common_device::i_insw, /* 0x6d */
&v25_common_device::i_outsb, /* 0x6e */
&v25_common_device::i_outsw, /* 0x6f */
&v25_common_device::i_jo, /* 0x70 */
&v25_common_device::i_jno, /* 0x71 */
&v25_common_device::i_jc, /* 0x72 */
&v25_common_device::i_jnc, /* 0x73 */
&v25_common_device::i_jz, /* 0x74 */
&v25_common_device::i_jnz, /* 0x75 */
&v25_common_device::i_jce, /* 0x76 */
&v25_common_device::i_jnce, /* 0x77 */
&v25_common_device::i_js, /* 0x78 */
&v25_common_device::i_jns, /* 0x79 */
&v25_common_device::i_jp, /* 0x7a */
&v25_common_device::i_jnp, /* 0x7b */
&v25_common_device::i_jl, /* 0x7c */
&v25_common_device::i_jnl, /* 0x7d */
&v25_common_device::i_jle, /* 0x7e */
&v25_common_device::i_jnle, /* 0x7f */
&v25_common_device::i_80pre, /* 0x80 */
&v25_common_device::i_81pre, /* 0x81 */
&v25_common_device::i_82pre, /* 0x82 */
&v25_common_device::i_83pre, /* 0x83 */
&v25_common_device::i_test_br8, /* 0x84 */
&v25_common_device::i_test_wr16, /* 0x85 */
&v25_common_device::i_xchg_br8, /* 0x86 */
&v25_common_device::i_xchg_wr16, /* 0x87 */
&v25_common_device::i_mov_br8, /* 0x88 */
&v25_common_device::i_mov_wr16, /* 0x89 */
&v25_common_device::i_mov_r8b, /* 0x8a */
&v25_common_device::i_mov_r16w, /* 0x8b */
&v25_common_device::i_mov_wsreg, /* 0x8c */
&v25_common_device::i_lea, /* 0x8d */
&v25_common_device::i_mov_sregw, /* 0x8e */
&v25_common_device::i_popw, /* 0x8f */
&v25_common_device::i_nop, /* 0x90 */
&v25_common_device::i_xchg_axcx, /* 0x91 */
&v25_common_device::i_xchg_axdx, /* 0x92 */
&v25_common_device::i_xchg_axbx, /* 0x93 */
&v25_common_device::i_xchg_axsp, /* 0x94 */
&v25_common_device::i_xchg_axbp, /* 0x95 */
&v25_common_device::i_xchg_axsi, /* 0x96 */
&v25_common_device::i_xchg_axdi, /* 0x97 */
&v25_common_device::i_cbw, /* 0x98 */
&v25_common_device::i_cwd, /* 0x99 */
&v25_common_device::i_call_far, /* 0x9a */
&v25_common_device::i_wait, /* 0x9b */
&v25_common_device::i_pushf, /* 0x9c */
&v25_common_device::i_popf, /* 0x9d */
&v25_common_device::i_sahf, /* 0x9e */
&v25_common_device::i_lahf, /* 0x9f */
&v25_common_device::i_mov_aldisp, /* 0xa0 */
&v25_common_device::i_mov_axdisp, /* 0xa1 */
&v25_common_device::i_mov_dispal, /* 0xa2 */
&v25_common_device::i_mov_dispax, /* 0xa3 */
&v25_common_device::i_movsb, /* 0xa4 */
&v25_common_device::i_movsw, /* 0xa5 */
&v25_common_device::i_cmpsb, /* 0xa6 */
&v25_common_device::i_cmpsw, /* 0xa7 */
&v25_common_device::i_test_ald8, /* 0xa8 */
&v25_common_device::i_test_axd16, /* 0xa9 */
&v25_common_device::i_stosb, /* 0xaa */
&v25_common_device::i_stosw, /* 0xab */
&v25_common_device::i_lodsb, /* 0xac */
&v25_common_device::i_lodsw, /* 0xad */
&v25_common_device::i_scasb, /* 0xae */
&v25_common_device::i_scasw, /* 0xaf */
&v25_common_device::i_mov_ald8, /* 0xb0 */
&v25_common_device::i_mov_cld8, /* 0xb1 */
&v25_common_device::i_mov_dld8, /* 0xb2 */
&v25_common_device::i_mov_bld8, /* 0xb3 */
&v25_common_device::i_mov_ahd8, /* 0xb4 */
&v25_common_device::i_mov_chd8, /* 0xb5 */
&v25_common_device::i_mov_dhd8, /* 0xb6 */
&v25_common_device::i_mov_bhd8, /* 0xb7 */
&v25_common_device::i_mov_axd16, /* 0xb8 */
&v25_common_device::i_mov_cxd16, /* 0xb9 */
&v25_common_device::i_mov_dxd16, /* 0xba */
&v25_common_device::i_mov_bxd16, /* 0xbb */
&v25_common_device::i_mov_spd16, /* 0xbc */
&v25_common_device::i_mov_bpd16, /* 0xbd */
&v25_common_device::i_mov_sid16, /* 0xbe */
&v25_common_device::i_mov_did16, /* 0xbf */
&v25_common_device::i_rotshft_bd8, /* 0xc0 */
&v25_common_device::i_rotshft_wd8, /* 0xc1 */
&v25_common_device::i_ret_d16, /* 0xc2 */
&v25_common_device::i_ret, /* 0xc3 */
&v25_common_device::i_les_dw, /* 0xc4 */
&v25_common_device::i_lds_dw, /* 0xc5 */
&v25_common_device::i_mov_bd8, /* 0xc6 */
&v25_common_device::i_mov_wd16, /* 0xc7 */
&v25_common_device::i_enter, /* 0xc8 */
&v25_common_device::i_leave, /* 0xc9 */
&v25_common_device::i_retf_d16, /* 0xca */
&v25_common_device::i_retf, /* 0xcb */
&v25_common_device::i_int3, /* 0xcc */
&v25_common_device::i_int, /* 0xcd */
&v25_common_device::i_into, /* 0xce */
&v25_common_device::i_iret, /* 0xcf */
&v25_common_device::i_rotshft_b, /* 0xd0 */
&v25_common_device::i_rotshft_w, /* 0xd1 */
&v25_common_device::i_rotshft_bcl, /* 0xd2 */
&v25_common_device::i_rotshft_wcl, /* 0xd3 */
&v25_common_device::i_aam, /* 0xd4 */
&v25_common_device::i_aad, /* 0xd5 */
&v25_common_device::i_setalc, /* 0xd6 */
&v25_common_device::i_trans, /* 0xd7 */
&v25_common_device::i_fpo, /* 0xd8 */
&v25_common_device::i_fpo, /* 0xd9 */
&v25_common_device::i_fpo, /* 0xda */
&v25_common_device::i_fpo, /* 0xdb */
&v25_common_device::i_fpo, /* 0xdc */
&v25_common_device::i_fpo, /* 0xdd */
&v25_common_device::i_fpo, /* 0xde */
&v25_common_device::i_fpo, /* 0xdf */
&v25_common_device::i_loopne, /* 0xe0 */
&v25_common_device::i_loope, /* 0xe1 */
&v25_common_device::i_loop, /* 0xe2 */
&v25_common_device::i_jcxz, /* 0xe3 */
&v25_common_device::i_inal, /* 0xe4 */
&v25_common_device::i_inax, /* 0xe5 */
&v25_common_device::i_outal, /* 0xe6 */
&v25_common_device::i_outax, /* 0xe7 */
&v25_common_device::i_call_d16, /* 0xe8 */
&v25_common_device::i_jmp_d16, /* 0xe9 */
&v25_common_device::i_jmp_far, /* 0xea */
&v25_common_device::i_jmp_d8, /* 0xeb */
&v25_common_device::i_inaldx, /* 0xec */
&v25_common_device::i_inaxdx, /* 0xed */
&v25_common_device::i_outdxal, /* 0xee */
&v25_common_device::i_outdxax, /* 0xef */
&v25_common_device::i_lock, /* 0xf0 */
&v25_common_device::i_brks, /* 0xf1 */
&v25_common_device::i_repne, /* 0xf2 */
&v25_common_device::i_repe, /* 0xf3 */
&v25_common_device::i_hlt, /* 0xf4 */
&v25_common_device::i_cmc, /* 0xf5 */
&v25_common_device::i_f6pre, /* 0xf6 */
&v25_common_device::i_f7pre, /* 0xf7 */
&v25_common_device::i_clc, /* 0xf8 */
&v25_common_device::i_stc, /* 0xf9 */
&v25_common_device::i_di, /* 0xfa */
&v25_common_device::i_ei, /* 0xfb */
&v25_common_device::i_cld, /* 0xfc */
&v25_common_device::i_std, /* 0xfd */
&v25_common_device::i_fepre, /* 0xfe */
&v25_common_device::i_ffpre /* 0xff */
};

157
src/emu/cpu/nec/v25priv.h
View File

@ -59,68 +59,6 @@ enum INTSOURCES
BRKS = 1 << 18
};
/* internal RAM and register banks */
union internalram
{
UINT16 w[128];
UINT8 b[256];
};
struct v25_state_t
{
internalram ram;
offs_t fetch_xor;
UINT16 ip;
/* PSW flags */
INT32 SignVal;
UINT32 AuxVal, OverVal, ZeroVal, CarryVal, ParityVal; /* 0 or non-0 valued flags */
UINT8 IBRK, F0, F1, TF, IF, DF, MF; /* 0 or 1 valued flags */
UINT8 RBW, RBB; /* current register bank base, preshifted for word and byte registers */
/* interrupt related */
UINT32 pending_irq;
UINT32 unmasked_irq;
UINT32 bankswitch_irq;
UINT8 priority_inttu, priority_intd, priority_intp, priority_ints0, priority_ints1;
UINT8 IRQS, ISPR;
UINT32 nmi_state;
UINT32 irq_state;
UINT32 poll_state;
UINT32 mode_state;
UINT32 intp_state[3];
UINT8 no_interrupt;
UINT8 halted;
/* timer related */
UINT16 TM0, MD0, TM1, MD1;
UINT8 TMC0, TMC1;
emu_timer *timers[4];
/* system control */
UINT8 RAMEN, TB, PCK; /* PRC register */
UINT32 IDB;
device_irq_acknowledge_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
direct_read_data *direct;
address_space *io;
int icount;
const nec_config *config;
UINT8 prefetch_size;
UINT8 prefetch_cycles;
INT8 prefetch_count;
UINT8 prefetch_reset;
UINT32 chip_type;
UINT32 prefix_base; /* base address of the latest prefix segment */
UINT8 seg_prefix; /* prefix segment indicator */
};
enum {
VECTOR_PC = 0x02/2,
PSW_SAVE = 0x04/2,
@ -156,38 +94,33 @@ enum BREGS {
BH = NATIVE_ENDIAN_VALUE_LE_BE(0x19, 0x18)
};
#define SetRB(x) do { nec_state->RBW = (x) << 4; nec_state->RBB = (x) << 5; } while (0)
#define SetRB(x) do { m_RBW = (x) << 4; m_RBB = (x) << 5; } while (0)
#define Sreg(x) nec_state->ram.w[nec_state->RBW + (x)]
#define Wreg(x) nec_state->ram.w[nec_state->RBW + (x)]
#define Breg(x) nec_state->ram.b[nec_state->RBB + (x)]
#define Sreg(x) m_ram.w[m_RBW + (x)]
#define Wreg(x) m_ram.w[m_RBW + (x)]
#define Breg(x) m_ram.b[m_RBB + (x)]
#define PC(n) ((Sreg(PS)<<4)+(n)->ip)
#define PC() ((Sreg(PS)<<4)+m_ip)
#define CF (nec_state->CarryVal!=0)
#define SF (nec_state->SignVal<0)
#define ZF (nec_state->ZeroVal==0)
#define PF parity_table[(BYTE)nec_state->ParityVal]
#define AF (nec_state->AuxVal!=0)
#define OF (nec_state->OverVal!=0)
#define RB (nec_state->RBW >> 4)
#define CF (m_CarryVal!=0)
#define SF (m_SignVal<0)
#define ZF (m_ZeroVal==0)
#define PF parity_table[(BYTE)m_ParityVal]
#define AF (m_AuxVal!=0)
#define OF (m_OverVal!=0)
#define RB (m_RBW >> 4)
/************************************************************************/
UINT8 v25_read_byte(v25_state_t *nec_state, unsigned a);
UINT16 v25_read_word(v25_state_t *nec_state, unsigned a);
void v25_write_byte(v25_state_t *nec_state, unsigned a, UINT8 d);
void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d);
#define read_mem_byte(a) v25_read_byte((a))
#define read_mem_word(a) v25_read_word((a))
#define write_mem_byte(a,d) v25_write_byte((a),(d))
#define write_mem_word(a,d) v25_write_word((a),(d))
#define read_mem_byte(a) v25_read_byte(nec_state,(a))
#define read_mem_word(a) v25_read_word(nec_state,(a))
#define write_mem_byte(a,d) v25_write_byte(nec_state,(a),(d))
#define write_mem_word(a,d) v25_write_word(nec_state,(a),(d))
#define read_port_byte(a) nec_state->io->read_byte(a)
#define read_port_word(a) nec_state->io->read_word_unaligned(a)
#define write_port_byte(a,d) nec_state->io->write_byte((a),(d))
#define write_port_word(a,d) nec_state->io->write_word_unaligned((a),(d))
#define read_port_byte(a) m_io->read_byte(a)
#define read_port_word(a) m_io->read_word_unaligned(a)
#define write_port_byte(a,d) m_io->write_byte((a),(d))
#define write_port_word(a,d) m_io->write_word_unaligned((a),(d))
/************************************************************************/
@ -195,7 +128,7 @@ void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d);
#define SegBase(Seg) (Sreg(Seg) << 4)
#define DefaultBase(Seg) ((nec_state->seg_prefix && (Seg==DS0 || Seg==SS)) ? nec_state->prefix_base : Sreg(Seg) << 4)
#define DefaultBase(Seg) ((m_seg_prefix && (Seg==DS0 || Seg==SS)) ? m_prefix_base : Sreg(Seg) << 4)
#define GetMemB(Seg,Off) (read_mem_byte(DefaultBase(Seg) + (Off)))
#define GetMemW(Seg,Off) (read_mem_word(DefaultBase(Seg) + (Off)))
@ -205,9 +138,9 @@ void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d);
/* prefetch timing */
#define FETCH() fetch(nec_state)
#define FETCHWORD() fetchword(nec_state)
#define EMPTY_PREFETCH() nec_state->prefetch_reset = 1
#define FETCH() fetch()
#define FETCHWORD() fetchword()
#define EMPTY_PREFETCH() m_prefetch_reset = 1
#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); }
@ -227,31 +160,31 @@ void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d);
Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated.
*/
#define CLK(all) nec_state->icount-=all
#define CLKS(v20,v30,v33) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33; nec_state->icount-=(ccount>>nec_state->chip_type)&0x7f; }
#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; nec_state->icount-=(addr&1)?((ocount>>nec_state->chip_type)&0x7f):((ecount>>nec_state->chip_type)&0x7f); }
#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; nec_state->icount-=( ModRM >=0xc0 )?((ccount>>nec_state->chip_type)&0x7f):((mcount>>nec_state->chip_type)&0x7f); }
#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) nec_state->icount-=vall; else nec_state->icount-=(addr&1)?((ocount>>nec_state->chip_type)&0x7f):((ecount>>nec_state->chip_type)&0x7f); }
#define CLK(all) m_icount-=all
#define CLKS(v20,v30,v33) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33; m_icount-=(ccount>>m_chip_type)&0x7f; }
#define CLKW(v20o,v30o,v33o,v20e,v30e,v33e,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); }
#define CLKM(v20,v30,v33,v20m,v30m,v33m) { const UINT32 ccount=(v20<<16)|(v30<<8)|v33, mcount=(v20m<<16)|(v30m<<8)|v33m; m_icount-=( ModRM >=0xc0 )?((ccount>>m_chip_type)&0x7f):((mcount>>m_chip_type)&0x7f); }
#define CLKR(v20o,v30o,v33o,v20e,v30e,v33e,vall,addr) { const UINT32 ocount=(v20o<<16)|(v30o<<8)|v33o, ecount=(v20e<<16)|(v30e<<8)|v33e; if (ModRM >=0xc0) m_icount-=vall; else m_icount-=(addr&1)?((ocount>>m_chip_type)&0x7f):((ecount>>m_chip_type)&0x7f); }
/************************************************************************/
#define CompressFlags() (WORD)(CF | (nec_state->IBRK << 1) | (PF << 2) | (nec_state->F0 << 3) | (AF << 4) \
| (nec_state->F1 << 5) | (ZF << 6) | (SF << 7) | (nec_state->TF << 8) | (nec_state->IF << 9) \
| (nec_state->DF << 10) | (OF << 11) | (RB << 12) | (nec_state->MF << 15))
#define CompressFlags() (WORD)(CF | (m_IBRK << 1) | (PF << 2) | (m_F0 << 3) | (AF << 4) \
| (m_F1 << 5) | (ZF << 6) | (SF << 7) | (m_TF << 8) | (m_IF << 9) \
| (m_DF << 10) | (OF << 11) | (RB << 12) | (m_MF << 15))
#define ExpandFlags(f) \
{ \
nec_state->CarryVal = (f) & 0x0001; \
nec_state->IBRK = ((f) & 0x0002) == 0x0002; \
nec_state->ParityVal = !((f) & 0x0004); \
nec_state->F0 = ((f) & 0x0008) == 0x0008; \
nec_state->AuxVal = (f) & 0x0010; \
nec_state->F1 = ((f) & 0x0020) == 0x0020; \
nec_state->ZeroVal = !((f) & 0x0040); \
nec_state->SignVal = (f) & 0x0080 ? -1 : 0; \
nec_state->TF = ((f) & 0x0100) == 0x0100; \
nec_state->IF = ((f) & 0x0200) == 0x0200; \
nec_state->DF = ((f) & 0x0400) == 0x0400; \
nec_state->OverVal = (f) & 0x0800; \
m_CarryVal = (f) & 0x0001; \
m_IBRK = ((f) & 0x0002) == 0x0002; \
m_ParityVal = !((f) & 0x0004); \
m_F0 = ((f) & 0x0008) == 0x0008; \
m_AuxVal = (f) & 0x0010; \
m_F1 = ((f) & 0x0020) == 0x0020; \
m_ZeroVal = !((f) & 0x0040); \
m_SignVal = (f) & 0x0080 ? -1 : 0; \
m_TF = ((f) & 0x0100) == 0x0100; \
m_IF = ((f) & 0x0200) == 0x0200; \
m_DF = ((f) & 0x0400) == 0x0400; \
m_OverVal = (f) & 0x0800; \
/* RB only changes on BRKCS/RETRBI/TSKSW, so skip it */ \
nec_state->MF = ((f) & 0x8000) == 0x8000; \
m_MF = ((f) & 0x8000) == 0x8000; \
}

272
src/emu/cpu/nec/v25sfr.c
View File

@ -5,64 +5,64 @@
****************************************************************************/
#include "emu.h"
#include "nec.h"
#include "v25.h"
#include "v25priv.h"
static UINT8 read_irqcontrol(v25_state_t *nec_state, INTSOURCES source, UINT8 priority)
UINT8 v25_common_device::read_irqcontrol(int /*INTSOURCES*/ source, UINT8 priority)
{
return (((nec_state->pending_irq & source) ? 0x80 : 0x00)
| ((nec_state->unmasked_irq & source) ? 0x00 : 0x40)
| ((nec_state->bankswitch_irq & source) ? 0x10 : 0x00)
return (((m_pending_irq & source) ? 0x80 : 0x00)
| ((m_unmasked_irq & source) ? 0x00 : 0x40)
| ((m_bankswitch_irq & source) ? 0x10 : 0x00)
| priority);
}
static UINT8 read_sfr(v25_state_t *nec_state, unsigned o)
UINT8 v25_common_device::read_sfr(unsigned o)
{
UINT8 ret;
switch(o)
{
case 0x00: /* P0 */
ret = nec_state->io->read_byte(V25_PORT_P0);
ret = m_io->read_byte(V25_PORT_P0);
break;
case 0x08: /* P1 */
/* P1 is combined with the interrupt lines */
ret = ((nec_state->io->read_byte(V25_PORT_P1) & 0xF0)
| (nec_state->nmi_state ? 0x00 : 0x01)
| (nec_state->intp_state[0] ? 0x00 : 0x02)
| (nec_state->intp_state[1] ? 0x00 : 0x04)
| (nec_state->intp_state[2] ? 0x00 : 0x08));
ret = ((m_io->read_byte(V25_PORT_P1) & 0xF0)
| (m_nmi_state ? 0x00 : 0x01)
| (m_intp_state[0] ? 0x00 : 0x02)
| (m_intp_state[1] ? 0x00 : 0x04)
| (m_intp_state[2] ? 0x00 : 0x08));
break;
case 0x10: /* P2 */
ret = nec_state->io->read_byte(V25_PORT_P2);
ret = m_io->read_byte(V25_PORT_P2);
break;
case 0x38: /* PT */
ret = nec_state->io->read_byte(V25_PORT_PT);
ret = m_io->read_byte(V25_PORT_PT);
break;
case 0x4C: /* EXIC0 */
ret = read_irqcontrol(nec_state, INTP0, nec_state->priority_intp);
ret = read_irqcontrol(INTP0, m_priority_intp);
break;
case 0x4D: /* EXIC1 */
ret = read_irqcontrol(nec_state, INTP1, 7);
ret = read_irqcontrol(INTP1, 7);
break;
case 0x4E: /* EXIC2 */
ret = read_irqcontrol(nec_state, INTP2, 7);
ret = read_irqcontrol(INTP2, 7);
break;
case 0x9C: /* TMIC0 */
ret = read_irqcontrol(nec_state, INTTU0, nec_state->priority_inttu);
ret = read_irqcontrol(INTTU0, m_priority_inttu);
break;
case 0x9D: /* TMIC1 */
ret = read_irqcontrol(nec_state, INTTU1, 7);
ret = read_irqcontrol(INTTU1, 7);
break;
case 0x9E: /* TMIC2 */
ret = read_irqcontrol(nec_state, INTTU2, 7);
ret = read_irqcontrol(INTTU2, 7);
break;
case 0xEA: /* FLAG */
ret = ((nec_state->F0 << 3) | (nec_state->F1 << 5));
ret = ((m_F0 << 3) | (m_F1 << 5));
break;
case 0xEB: /* PRC */
ret = (nec_state->RAMEN ? 0x40 : 0);
switch (nec_state->TB)
ret = (m_RAMEN ? 0x40 : 0);
switch (m_TB)
{
case 10:
break;
@ -76,7 +76,7 @@ static UINT8 read_sfr(v25_state_t *nec_state, unsigned o)
ret |= 0x0C;
break;
}
switch (nec_state->PCK)
switch (m_PCK)
{
case 2:
break;
@ -89,74 +89,74 @@ static UINT8 read_sfr(v25_state_t *nec_state, unsigned o)
}
break;
case 0xEC: /* TBIC */
ret = read_irqcontrol(nec_state, INTTB, 7);
ret = read_irqcontrol(INTTB, 7);
break;
case 0xEF: /* IRQS */
ret = nec_state->IRQS;
ret = m_IRQS;
break;
case 0xFC: /* ISPR */
ret = nec_state->ISPR;
ret = m_ISPR;
break;
case 0xFF: /* IDB */
ret = (nec_state->IDB >> 12);
ret = (m_IDB >> 12);
break;
default:
logerror("%06x: Read from special function register %02x\n",PC(nec_state),o);
logerror("%06x: Read from special function register %02x\n",PC(),o);
ret = 0;
}
return ret;
}
static UINT16 read_sfr_word(v25_state_t *nec_state, unsigned o)
UINT16 v25_common_device::read_sfr_word(unsigned o)
{
UINT16 ret;
switch(o)
{
case 0x80: /* TM0 */
logerror("%06x: Warning: read back TM0\n",PC(nec_state));
ret = nec_state->TM0;
logerror("%06x: Warning: read back TM0\n",PC());
ret = m_TM0;
break;
case 0x82: /* MD0 */
logerror("%06x: Warning: read back MD0\n",PC(nec_state));
ret = nec_state->MD0;
logerror("%06x: Warning: read back MD0\n",PC());
ret = m_MD0;
break;
case 0x88: /* TM1 */
logerror("%06x: Warning: read back TM1\n",PC(nec_state));
ret = nec_state->TM1;
logerror("%06x: Warning: read back TM1\n",PC());
ret = m_TM1;
break;
case 0x8A: /* MD1 */
logerror("%06x: Warning: read back MD1\n",PC(nec_state));
ret = nec_state->MD1;
logerror("%06x: Warning: read back MD1\n",PC());
ret = m_MD1;
break;
default:
ret = (read_sfr(nec_state, o) | (read_sfr(nec_state, o+1) << 8));
ret = (read_sfr(o) | (read_sfr(o+1) << 8));
}
return ret;
}
static void write_irqcontrol(v25_state_t *nec_state, INTSOURCES source, UINT8 d)
void v25_common_device::write_irqcontrol(int /*INTSOURCES*/ source, UINT8 d)
{
if(d & 0x80)
nec_state->pending_irq |= source;
m_pending_irq |= source;
else
nec_state->pending_irq &= ~source;
m_pending_irq &= ~source;
if(d & 0x40)
nec_state->unmasked_irq &= ~source;
m_unmasked_irq &= ~source;
else
nec_state->unmasked_irq |= source;
m_unmasked_irq |= source;
if(d & 0x20)
logerror("%06x: Warning: macro service function not implemented\n",PC(nec_state));
logerror("%06x: Warning: macro service function not implemented\n",PC());
if(d & 0x10)
nec_state->bankswitch_irq |= source;
m_bankswitch_irq |= source;
else
nec_state->bankswitch_irq &= ~source;
m_bankswitch_irq &= ~source;
}
static void write_sfr(v25_state_t *nec_state, unsigned o, UINT8 d)
void v25_common_device::write_sfr(unsigned o, UINT8 d)
{
int tmp;
attotime time;
@ -167,234 +167,234 @@ static void write_sfr(v25_state_t *nec_state, unsigned o, UINT8 d)
switch(o)
{
case 0x00: /* P0 */
nec_state->io->write_byte(V25_PORT_P0, d);
m_io->write_byte(V25_PORT_P0, d);
break;
case 0x08: /* P1 */
/* only the upper four bits of P1 can be used as output */
nec_state->io->write_byte(V25_PORT_P1, d & 0xF0);
m_io->write_byte(V25_PORT_P1, d & 0xF0);
break;
case 0x10: /* P2 */
nec_state->io->write_byte(V25_PORT_P2, d);
m_io->write_byte(V25_PORT_P2, d);
break;
case 0x4C: /* EXIC0 */
write_irqcontrol(nec_state, INTP0, d);
nec_state->priority_intp = d & 0x7;
write_irqcontrol(INTP0, d);
m_priority_intp = d & 0x7;
break;
case 0x4D: /* EXIC1 */
write_irqcontrol(nec_state, INTP1, d);
write_irqcontrol(INTP1, d);
break;
case 0x4E: /* EXIC2 */
write_irqcontrol(nec_state, INTP2, d);
write_irqcontrol(INTP2, d);
break;
case 0x90: /* TMC0 */
nec_state->TMC0 = d;
m_TMC0 = d;
if(d & 1) /* oneshot mode */
{
if(d & 0x80)
{
tmp = nec_state->TM0 * nec_state->PCK * ((d & 0x40) ? 128 : 12 );
time = attotime::from_hz(nec_state->device->unscaled_clock()) * tmp;
nec_state->timers[0]->adjust(time, INTTU0);
tmp = m_TM0 * m_PCK * ((d & 0x40) ? 128 : 12 );
time = attotime::from_hz(unscaled_clock()) * tmp;
m_timers[0]->adjust(time, INTTU0);
}
else
nec_state->timers[0]->adjust(attotime::never);
m_timers[0]->adjust(attotime::never);
if(d & 0x20)
{
tmp = nec_state->MD0 * nec_state->PCK * ((d & 0x10) ? 128 : 12 );
time = attotime::from_hz(nec_state->device->unscaled_clock()) * tmp;
nec_state->timers[1]->adjust(time, INTTU1);
tmp = m_MD0 * m_PCK * ((d & 0x10) ? 128 : 12 );
time = attotime::from_hz(unscaled_clock()) * tmp;
m_timers[1]->adjust(time, INTTU1);
}
else
nec_state->timers[1]->adjust(attotime::never);
m_timers[1]->adjust(attotime::never);
}
else /* interval mode */
{
if(d & 0x80)
{
tmp = nec_state->MD0 * nec_state->PCK * ((d & 0x40) ? 128 : 6 );
time = attotime::from_hz(nec_state->device->unscaled_clock()) * tmp;
nec_state->timers[0]->adjust(time, INTTU0, time);
nec_state->timers[1]->adjust(attotime::never);
nec_state->TM0 = nec_state->MD0;
tmp = m_MD0 * m_PCK * ((d & 0x40) ? 128 : 6 );
time = attotime::from_hz(unscaled_clock()) * tmp;
m_timers[0]->adjust(time, INTTU0, time);
m_timers[1]->adjust(attotime::never);
m_TM0 = m_MD0;
}
else
{
nec_state->timers[0]->adjust(attotime::never);
nec_state->timers[1]->adjust(attotime::never);
m_timers[0]->adjust(attotime::never);
m_timers[1]->adjust(attotime::never);
}
}
break;
case 0x91: /* TMC1 */
nec_state->TMC1 = d & 0xC0;
m_TMC1 = d & 0xC0;
if(d & 0x80)
{
tmp = nec_state->MD1 * nec_state->PCK * ((d & 0x40) ? 128 : 6 );
time = attotime::from_hz(nec_state->device->unscaled_clock()) * tmp;
nec_state->timers[2]->adjust(time, INTTU2, time);
nec_state->TM1 = nec_state->MD1;
tmp = m_MD1 * m_PCK * ((d & 0x40) ? 128 : 6 );
time = attotime::from_hz(unscaled_clock()) * tmp;
m_timers[2]->adjust(time, INTTU2, time);
m_TM1 = m_MD1;
}
else
nec_state->timers[2]->adjust(attotime::never);
m_timers[2]->adjust(attotime::never);
break;
case 0x9C: /* TMIC0 */
write_irqcontrol(nec_state, INTTU0, d);
nec_state->priority_inttu = d & 0x7;
write_irqcontrol(INTTU0, d);
m_priority_inttu = d & 0x7;
break;
case 0x9D: /* TMIC1 */
write_irqcontrol(nec_state, INTTU1, d);
write_irqcontrol(INTTU1, d);
break;
case 0x9E: /* TMIC2 */
write_irqcontrol(nec_state, INTTU2, d);
write_irqcontrol(INTTU2, d);
break;
case 0xEA: /* FLAG */
nec_state->F0 = ((d & 0x08) == 0x08);
nec_state->F1 = ((d & 0x20) == 0x20);
m_F0 = ((d & 0x08) == 0x08);
m_F1 = ((d & 0x20) == 0x20);
break;
case 0xEB: /* PRC */
logerror("%06x: PRC set to %02x\n", PC(nec_state), d);
nec_state->RAMEN = ((d & 0x40) == 0x40);
nec_state->TB = timebases[(d & 0x0C) >> 2];
nec_state->PCK = clocks[d & 0x03];
if (nec_state->PCK == 0)
logerror("%06x: PRC set to %02x\n", PC(), d);
m_RAMEN = ((d & 0x40) == 0x40);
m_TB = timebases[(d & 0x0C) >> 2];
m_PCK = clocks[d & 0x03];
if (m_PCK == 0)
{
logerror(" Warning: invalid clock divider\n");
nec_state->PCK = 8;
m_PCK = 8;
}
tmp = nec_state->PCK << nec_state->TB;
time = attotime::from_hz(nec_state->device->unscaled_clock()) * tmp;
nec_state->timers[3]->adjust(time, INTTB, time);
logerror(" Internal RAM %sabled\n", (nec_state->RAMEN ? "en" : "dis"));
logerror(" Time base set to 2^%d\n", nec_state->TB);
logerror(" Clock divider set to %d\n", nec_state->PCK);
tmp = m_PCK << m_TB;
time = attotime::from_hz(unscaled_clock()) * tmp;
m_timers[3]->adjust(time, INTTB, time);
logerror(" Internal RAM %sabled\n", (m_RAMEN ? "en" : "dis"));
logerror(" Time base set to 2^%d\n", m_TB);
logerror(" Clock divider set to %d\n", m_PCK);
break;
case 0xEC: /* TBIC */
/* time base interrupt doesn't support macro service, bank switching or priority control */
write_irqcontrol(nec_state, INTTB, d & 0xC0);
write_irqcontrol(INTTB, d & 0xC0);
break;
case 0xFF: /* IDB */
nec_state->IDB = (d << 12) | 0xE00;
logerror("%06x: IDB set to %02x\n",PC(nec_state),d);
m_IDB = (d << 12) | 0xE00;
logerror("%06x: IDB set to %02x\n",PC(),d);
break;
default:
logerror("%06x: Wrote %02x to special function register %02x\n",PC(nec_state),d,o);
logerror("%06x: Wrote %02x to special function register %02x\n",PC(),d,o);
}
}
static void write_sfr_word(v25_state_t *nec_state, unsigned o, UINT16 d)
void v25_common_device::write_sfr_word(unsigned o, UINT16 d)
{
switch(o)
{
case 0x80: /* TM0 */
nec_state->TM0 = d;
m_TM0 = d;
break;
case 0x82: /* MD0 */
nec_state->MD0 = d;
m_MD0 = d;
break;
case 0x88: /* TM1 */
nec_state->TM1 = d;
m_TM1 = d;
break;
case 0x8A: /* MD1 */
nec_state->MD1 = d;
m_MD1 = d;
break;
default:
write_sfr(nec_state, o, d);
write_sfr(nec_state, o+1, d >> 8);
write_sfr(o, d);
write_sfr(o+1, d >> 8);
}
}
UINT8 v25_read_byte(v25_state_t *nec_state, unsigned a)
UINT8 v25_common_device::v25_read_byte(unsigned a)
{
if((a & 0xFFE00) == nec_state->IDB || a == 0xFFFFF)
if((a & 0xFFE00) == m_IDB || a == 0xFFFFF)
{
unsigned o = a & 0x1FF;
if(nec_state->RAMEN && o < 0x100)
return nec_state->ram.b[BYTE_XOR_LE(o)];
if(m_RAMEN && o < 0x100)
return m_ram.b[BYTE_XOR_LE(o)];
if(o >= 0x100)
return read_sfr(nec_state, o-0x100);
return read_sfr(o-0x100);
}
return nec_state->program->read_byte(a);
return m_program->read_byte(a);
}
UINT16 v25_read_word(v25_state_t *nec_state, unsigned a)
UINT16 v25_common_device::v25_read_word(unsigned a)
{
if( a & 1 )
return (v25_read_byte(nec_state, a) | (v25_read_byte(nec_state, a + 1) << 8));
return (v25_read_byte(a) | (v25_read_byte(a + 1) << 8));
if((a & 0xFFE00) == nec_state->IDB)
if((a & 0xFFE00) == m_IDB)
{
unsigned o = a & 0x1FF;
if(nec_state->RAMEN && o < 0x100)
return nec_state->ram.w[o/2];
if(m_RAMEN && o < 0x100)
return m_ram.w[o/2];
if(o >= 0x100)
return read_sfr_word(nec_state, o-0x100);
return read_sfr_word(o-0x100);
}
if(a == 0xFFFFE) /* not sure about this - manual says FFFFC-FFFFE are "reserved" */
return (nec_state->program->read_byte(a) | (read_sfr(nec_state, 0xFF) << 8));
return (m_program->read_byte(a) | (read_sfr(0xFF) << 8));
return nec_state->program->read_word(a);
return m_program->read_word(a);
}
void v25_write_byte(v25_state_t *nec_state, unsigned a, UINT8 d)
void v25_common_device::v25_write_byte(unsigned a, UINT8 d)
{
if((a & 0xFFE00) == nec_state->IDB || a == 0xFFFFF)
if((a & 0xFFE00) == m_IDB || a == 0xFFFFF)
{
unsigned o = a & 0x1FF;
if(nec_state->RAMEN && o < 0x100)
if(m_RAMEN && o < 0x100)
{
nec_state->ram.b[BYTE_XOR_LE(o)] = d;
m_ram.b[BYTE_XOR_LE(o)] = d;
return;
}
if(o >= 0x100)
{
write_sfr(nec_state, o-0x100, d);
write_sfr(o-0x100, d);
return;
}
}
nec_state->program->write_byte(a, d);
m_program->write_byte(a, d);
}
void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d)
void v25_common_device::v25_write_word(unsigned a, UINT16 d)
{
if( a & 1 )
{
v25_write_byte(nec_state, a, d);
v25_write_byte(nec_state, a + 1, d >> 8);
v25_write_byte(a, d);
v25_write_byte(a + 1, d >> 8);
return;
}
if((a & 0xFFE00) == nec_state->IDB)
if((a & 0xFFE00) == m_IDB)
{
unsigned o = a & 0x1FF;
if(nec_state->RAMEN && o < 0x100)
if(m_RAMEN && o < 0x100)
{
nec_state->ram.w[o/2] = d;
m_ram.w[o/2] = d;
return;
}
if(o >= 0x100)
{
write_sfr_word(nec_state, o-0x100, d);
write_sfr_word(o-0x100, d);
return;
}
}
if(a == 0xFFFFE) /* not sure about this - manual says FFFFC-FFFFE are "reserved" */
{
nec_state->program->write_byte(a, d);
write_sfr(nec_state, 0xFF, d >> 8);
m_program->write_byte(a, d);
write_sfr(0xFF, d >> 8);
return;
}
nec_state->program->write_word(a, d);
m_program->write_word(a, d);
}

6
src/mame/drivers/cb2001.c
View File

@ -41,7 +41,7 @@ this seems more like 8-bit hardware, maybe it should be v25, not v35...
*************************************************************************************************/
#include "emu.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "sound/ay8910.h"
#include "machine/i8255.h"
@ -832,11 +832,9 @@ static const ay8910_interface cb2001_ay8910_config =
DEVCB_NULL
};
static const nec_config cb2001_config = { cb2001_decryption_table, };
static MACHINE_CONFIG_START( cb2001, cb2001_state )
MCFG_CPU_ADD("maincpu", V35, 20000000) // CPU91A-011-0016JK004; encrypted cpu like nec v25/35 used in some irem game
MCFG_CPU_CONFIG(cb2001_config)
MCFG_V25_CONFIG(cb2001_decryption_table)
MCFG_CPU_PROGRAM_MAP(cb2001_map)
MCFG_CPU_IO_MAP(cb2001_io)
MCFG_CPU_VBLANK_INT_DRIVER("screen", cb2001_state, vblank_irq)

11
src/mame/drivers/m107.c
View File

@ -25,6 +25,7 @@ confirmed for m107 games as well.
#include "emu.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "includes/m107.h"
#include "includes/iremipt.h"
#include "machine/irem_cpu.h"
@ -753,8 +754,6 @@ GFXDECODE_END
/***************************************************************************/
static const nec_config firebarr_config ={ rtypeleo_decryption_table, };
static MACHINE_CONFIG_START( firebarr, m107_state )
/* basic machine hardware */
@ -764,7 +763,7 @@ static MACHINE_CONFIG_START( firebarr, m107_state )
MCFG_CPU_ADD("soundcpu", V35, 14318000)
MCFG_CPU_PROGRAM_MAP(sound_map)
MCFG_CPU_CONFIG(firebarr_config)
MCFG_V25_CONFIG(rtypeleo_decryption_table)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", m107_state, m107_scanline_interrupt, "screen", 0, 1)
@ -794,7 +793,6 @@ static MACHINE_CONFIG_START( firebarr, m107_state )
MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
MACHINE_CONFIG_END
static const nec_config dsoccr94_config ={ dsoccr94_decryption_table, };
static MACHINE_CONFIG_DERIVED( dsoccr94, firebarr )
/* basic machine hardware */
@ -802,21 +800,20 @@ static MACHINE_CONFIG_DERIVED( dsoccr94, firebarr )
MCFG_CPU_CLOCK(20000000/2) /* NEC V33, Could be 28MHz clock? */
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(dsoccr94_config)
MCFG_V25_CONFIG(dsoccr94_decryption_table)
/* video hardware */
MCFG_GFXDECODE(m107)
MACHINE_CONFIG_END
static const nec_config wpksoc_config ={ leagueman_decryption_table, };
static MACHINE_CONFIG_DERIVED( wpksoc, firebarr )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(wpksoc_map)
MCFG_CPU_IO_MAP(wpksoc_io_map)
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(wpksoc_config)
MCFG_V25_CONFIG(leagueman_decryption_table)
MACHINE_CONFIG_END
/***************************************************************************/

5
src/mame/drivers/m72.c
View File

@ -84,6 +84,7 @@ other supported games as well.
#include "emu.h"
#include "cpu/z80/z80.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "machine/irem_cpu.h"
#include "sound/2151intf.h"
#include "includes/iremipt.h"
@ -2326,11 +2327,9 @@ static MACHINE_CONFIG_START( cosmccop, m72_state )
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.40)
MACHINE_CONFIG_END
static const nec_config kengo_config ={ gunforce_decryption_table, };
static MACHINE_CONFIG_DERIVED( kengo, cosmccop )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(kengo_config)
MCFG_V25_CONFIG(gunforce_decryption_table)
MACHINE_CONFIG_END

19
src/mame/drivers/m90.c
View File

@ -19,6 +19,7 @@
#include "emu.h"
#include "cpu/z80/z80.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "includes/iremipt.h"
#include "machine/irem_cpu.h"
#include "sound/dac.h"
@ -738,48 +739,42 @@ static MACHINE_CONFIG_START( m90, m90_state )
MACHINE_CONFIG_END
static const nec_config hasamu_config ={ gunforce_decryption_table, };
static MACHINE_CONFIG_DERIVED( hasamu, m90 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(hasamu_config)
MCFG_V25_CONFIG(gunforce_decryption_table)
MACHINE_CONFIG_END
static const nec_config quizf1_config ={ lethalth_decryption_table, };
static MACHINE_CONFIG_DERIVED( quizf1, m90 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(quizf1_config)
MCFG_V25_CONFIG(lethalth_decryption_table)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_VISIBLE_AREA(6*8, 54*8-1, 17*8-8, 47*8-1+8)
MACHINE_CONFIG_END
static const nec_config matchit2_config ={ matchit2_decryption_table, };
static MACHINE_CONFIG_DERIVED( matchit2, m90 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(matchit2_config)
MCFG_V25_CONFIG(matchit2_decryption_table)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_VISIBLE_AREA(6*8, 54*8-1, 17*8-8, 47*8-1+8)
MACHINE_CONFIG_END
static const nec_config riskchal_config ={ gussun_decryption_table, };
static MACHINE_CONFIG_DERIVED( riskchal, m90 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(riskchal_config)
MCFG_V25_CONFIG(gussun_decryption_table)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_VISIBLE_AREA(10*8, 50*8-1, 17*8, 47*8-1)
MACHINE_CONFIG_END
static const nec_config bomberman_config ={ bomberman_decryption_table, };
static MACHINE_CONFIG_DERIVED( bombrman, m90 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(bomberman_config)
MCFG_V25_CONFIG(bomberman_decryption_table)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_VISIBLE_AREA(10*8, 50*8-1, 17*8, 47*8-1)
MACHINE_CONFIG_END
static const nec_config dynablaster_config ={ dynablaster_decryption_table, };
static MACHINE_CONFIG_DERIVED( bbmanwj, m90 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(dynablaster_config)
MCFG_V25_CONFIG(dynablaster_decryption_table)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_VISIBLE_AREA(10*8, 50*8-1, 17*8, 47*8-1)
MACHINE_CONFIG_END

40
src/mame/drivers/m92.c
View File

@ -196,6 +196,7 @@ psoldier dip locations still need verification.
#include "emu.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "includes/m92.h"
#include "includes/iremipt.h"
#include "machine/irem_cpu.h"
@ -954,48 +955,41 @@ static MACHINE_CONFIG_START( m92, m92_state )
MACHINE_CONFIG_END
static const nec_config gunforce_config ={ gunforce_decryption_table, };
static MACHINE_CONFIG_DERIVED( gunforce, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(gunforce_config)
MCFG_V25_CONFIG(gunforce_decryption_table)
MACHINE_CONFIG_END
static const nec_config bmaster_config ={ bomberman_decryption_table, };
static MACHINE_CONFIG_DERIVED( bmaster, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(bmaster_config)
MCFG_V25_CONFIG(bomberman_decryption_table)
MACHINE_CONFIG_END
static const nec_config lethalth_config ={ lethalth_decryption_table, };
static MACHINE_CONFIG_DERIVED( lethalth, m92 )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(lethalth_map)
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(lethalth_config)
MCFG_V25_CONFIG(lethalth_decryption_table)
MACHINE_CONFIG_END
static const nec_config uccops_config ={ dynablaster_decryption_table, };
static MACHINE_CONFIG_DERIVED( uccops, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(uccops_config)
MCFG_V25_CONFIG(dynablaster_decryption_table)
MACHINE_CONFIG_END
static const nec_config mysticri_config ={ mysticri_decryption_table, };
static MACHINE_CONFIG_DERIVED( mysticri, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(mysticri_config)
MCFG_V25_CONFIG(mysticri_decryption_table)
MACHINE_CONFIG_END
static const nec_config majtitl2_config ={ majtitl2_decryption_table, };
static MACHINE_CONFIG_DERIVED( majtitl2, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(majtitl2_config)
MCFG_V25_CONFIG(majtitl2_decryption_table)
MACHINE_CONFIG_END
static const nec_config hook_config ={ hook_decryption_table, };
static MACHINE_CONFIG_DERIVED( hook, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(hook_config)
MCFG_V25_CONFIG(hook_decryption_table)
MACHINE_CONFIG_END
static MACHINE_CONFIG_START( ppan, m92_state )
@ -1034,24 +1028,21 @@ static MACHINE_CONFIG_START( ppan, m92_state )
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
MACHINE_CONFIG_END
static const nec_config rtypeleo_config ={ rtypeleo_decryption_table, };
static MACHINE_CONFIG_DERIVED( rtypeleo, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(rtypeleo_config)
MCFG_V25_CONFIG(rtypeleo_decryption_table)
MACHINE_CONFIG_END
static const nec_config inthunt_config ={ inthunt_decryption_table, };
static MACHINE_CONFIG_DERIVED( inthunt, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(inthunt_config)
MCFG_V25_CONFIG(inthunt_decryption_table)
MACHINE_CONFIG_END
static const nec_config nbbatman_config ={ leagueman_decryption_table, };
static MACHINE_CONFIG_DERIVED( nbbatman, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(nbbatman_config)
MCFG_V25_CONFIG(leagueman_decryption_table)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( nbbatman2bl, m92 )
@ -1066,26 +1057,23 @@ static MACHINE_CONFIG_DERIVED( nbbatman2bl, m92 )
MACHINE_CONFIG_END
static const nec_config psoldier_config ={ psoldier_decryption_table, };
static MACHINE_CONFIG_DERIVED( psoldier, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(psoldier_config)
MCFG_V25_CONFIG(psoldier_decryption_table)
/* video hardware */
MCFG_GFXDECODE(psoldier)
MACHINE_CONFIG_END
static const nec_config dsoccr94_config ={ dsoccr94_decryption_table, };
static MACHINE_CONFIG_DERIVED( dsoccr94j, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(dsoccr94_config)
MCFG_V25_CONFIG(dsoccr94_decryption_table)
/* video hardware */
MCFG_GFXDECODE(psoldier)
MACHINE_CONFIG_END
static const nec_config gunforc2_config ={ lethalth_decryption_table, };
static MACHINE_CONFIG_DERIVED( gunforc2, m92 )
MCFG_CPU_MODIFY("soundcpu")
MCFG_CPU_CONFIG(gunforc2_config)
MCFG_V25_CONFIG(lethalth_decryption_table)
MACHINE_CONFIG_END
/***************************************************************************/

6
src/mame/drivers/segas32.c
View File

@ -332,7 +332,7 @@ orunners: Interleaved with the dj and << >> buttons is the data the drives the
#include "emu.h"
#include "cpu/z80/z80.h"
#include "cpu/v60/v60.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "rendlay.h"
#include "includes/segas32.h"
#include "machine/eepromser.h"
@ -2210,14 +2210,12 @@ static MACHINE_CONFIG_START( system32, segas32_state )
MACHINE_CONFIG_END
static const nec_config ga2_v25_config ={ ga2_v25_opcode_table, };
static MACHINE_CONFIG_DERIVED( system32_v25, system32 )
/* add a V25 for protection */
MCFG_CPU_ADD("mcu", V25, 10000000)
MCFG_CPU_PROGRAM_MAP(ga2_v25_map)
MCFG_CPU_CONFIG(ga2_v25_config)
MCFG_V25_CONFIG(ga2_v25_opcode_table)
MACHINE_CONFIG_END

14
src/mame/drivers/toaplan2.c
View File

@ -349,7 +349,7 @@ To Do / Unknowns:
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/nec/nec.h"
#include "cpu/nec/v25.h"
#include "cpu/z80/z80.h"
#include "cpu/z180/z180.h"
#include "machine/eepromser.h"
@ -3006,8 +3006,6 @@ a4849 cd
*/
static const nec_config nitro_config ={ nitro_decryption_table, };
static MACHINE_CONFIG_START( dogyuun, toaplan2_state )
/* basic machine hardware */
@ -3018,7 +3016,7 @@ static MACHINE_CONFIG_START( dogyuun, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_25MHz/2) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(v25_mem)
MCFG_CPU_IO_MAP(dogyuun_v25_port)
MCFG_CPU_CONFIG(nitro_config)
MCFG_V25_CONFIG(nitro_decryption_table)
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@ -3062,7 +3060,7 @@ static MACHINE_CONFIG_START( kbash, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_16MHz) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(kbash_v25_mem)
MCFG_CPU_IO_MAP(v25_port)
MCFG_CPU_CONFIG(nitro_config)
MCFG_V25_CONFIG(nitro_decryption_table)
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@ -3298,8 +3296,6 @@ static const UINT8 ts001turbo_decryption_table[256] = {
/*r*//*r*//*r*//*r*//*r*//*r*//*r*//*r*/ /*r*//*x*//*r*//*r*//*r*/ /*r*/
};
static const nec_config ts001turbo_config ={ ts001turbo_decryption_table, };
static MACHINE_CONFIG_START( fixeight, toaplan2_state )
@ -3311,7 +3307,7 @@ static MACHINE_CONFIG_START( fixeight, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_16MHz) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(fixeight_v25_mem)
MCFG_CPU_IO_MAP(fixeight_v25_port)
MCFG_CPU_CONFIG(ts001turbo_config)
MCFG_V25_CONFIG(ts001turbo_decryption_table)
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@ -3390,7 +3386,7 @@ static MACHINE_CONFIG_START( vfive, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_20MHz/2) /* Verified on pcb, NEC V25 type Toaplan mark scratched out */
MCFG_CPU_PROGRAM_MAP(vfive_v25_mem)
MCFG_CPU_IO_MAP(v25_port)
MCFG_CPU_CONFIG(nitro_config)
MCFG_V25_CONFIG(nitro_decryption_table)
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)