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-indy_indigo2.cpp: Various changes: [Ryan Holtz]

Browse Source 
* Split Indigo 2 into a derived class.
 * Eliminated MACHINE_CONFIG_START/END.
 * Hooked up pullups on EISA I/O space.

-ioc2.cpp: Various changes: [Ryan Holtz]
 * Converted to use logmacro.
 * Made logging more verbose.
 * Added savestate support.
 * Hooked up Timer1/Timer0 interrupts.

-hpc3.cpp: Various changes: [Ryan Holtz]
 * Updated to MAME code standards.
 * Converted to use logmacro.
 * Made logging more verbose.
 * Added savestate support.
 * Partially hooked up second SCSI controller for Indigo 2.
 * Hooked up second DAC.
 * Fixed a bug that prevented the DAC DMA timer from stopping.
 * Hooked up PIO/DMA config register logging.

-sgi.cpp: Various changes: [Ryan Holtz]
 * Updated to MAME code standards.
 * Converted to use logmacro.
 * Made logging more verbose.
 * Made RPSS counter more accurate.
 * Added semaphore registers.

-newport.cpp: Various changes: [Ryan Holtz]
 * Updated to MAME code standards.
 * Converted to use logmacro.
 * Made logging more verbose.
This commit is contained in:
mooglyguy 2018-11-08 20:59:02 +01:00
parent 7301399d2e
commit ffeabc4560
9 changed files with 2287 additions and 1871 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

207
src/mame/drivers/indy_indigo2.cpp
View File

@ -4,21 +4,39 @@
*
* SGI IP22 Indigo2/Indy workstation
*
* Todo: Fix tod clock set problem
* Fix NVRAM saving
* Fix SCSI DMA to handle chains properly
* Probably many more things
* Known Issues:
* - The proper hookup for the MAC address is unknown, requiring
* a fake MAC to be set up before any IRIX installers will proceed.
* - The IRIX 6.5.x installer kernel-panics on startup.
* - The IRIX 5.3 installer hangs after loading.
* - The Gentoo Linux live CD hangs on starting the kernel.
* - The disk formatting/partitioning utility for IRIX, fx, has
* various issues, from the disk formatting too quickly to hanging
* when exercising the disk.
* - Disk accesses frequently result in a "SYNC negotiation error"
* message.
*
* Memory map:
*
* 00000000 - 0007ffff Alias for first 512kbyte of RAM
* 00080000 - 0008ffff EISA I/O space (pullups on Indy)
* 00090000 - 0009ffff EISA I/O space Alias (pullups on Indy)
* 000a0000 - 07ffffff EISA Memory
* 08000000 - 17ffffff Low System Memory
* 18000000 - 1effffff RESERVED - Unused
* 1f000000 - 1f3fffff GIO - GFX
* 1f400000 - 1f5fffff GIO - EXP0
* 1f600000 - 1f9fffff GIO - EXP1 - Unused
* 1fa00000 - 1fa02047 Memory Controller
* 1fa00000 - 1fa1ffff Memory Controller
* 1fb00000 - 1fb1a7ff HPC3 CHIP1
* 1fb80000 - 1fb9a7ff HPC3 CHIP0
* 1fc00000 - 1fc7ffff BIOS
* 1fc00000 - 1fffffff BIOS
* 20000000 - 2fffffff High System Memory
* 30000000 - 7fffffff Reserved
* 80000000 - ffffffff EISA Memory
*
* IP22/24 has 2 pieces of PC-compatible hardware: the 8042 PS/2 keyboard/mouse
* interface and the 8254 PIT. Both are licensed cores embedded in the IOC custom chip.
*
* References used:
* MipsLinux: http://www.mips-linux.org/
@ -29,14 +47,15 @@
* NetBSD: http://www.netbsd.org/
* gxemul: http://gavare.se/gxemul/
*
* Gentoo LiveCD r5 boot instructions:
* mess -cdrom gentoor5.chd ip225015
* enter the command interpreter and type "sashARCS". press enter and
* it'll autoboot.
* Gentoo LiveCD r5 boot instructions:
* - Specify an appropriate LiveCD image at the command line.
* - Enter the command interpreter and type "sashARCS". Press enter and
* it will autoboot.
*
* IRIX boot instructions:
* mess -cdrom irix656inst1.chd ip225015
* at the menu, choose either "run diagnostics" or "install system software"
* IRIX boot instructions:
* - Specify an appropriate IRIX CD image at the command line.
* - At the menu, choose either "run diagnostics" or "install
* system software".
*
\*********************************************************************/
@ -72,7 +91,8 @@ public:
, m_mainram(*this, "mainram")
, m_mem_ctrl(*this, "memctrl")
, m_scsi_ctrl(*this, "wd33c93")
, m_dac(*this, "dac")
, m_ldac(*this, "ldac")
, m_rdac(*this, "rdac")
, m_newport(*this, "newport")
, m_hal2(*this, HAL2_TAG)
, m_hpc3(*this, HPC3_TAG)
@ -81,22 +101,21 @@ public:
{
}
void ip22_base(machine_config &config);
void ip225015(machine_config &config);
void ip224613(machine_config &config);
void ip244415(machine_config &config);
void init_ip225015();
private:
virtual void machine_start() override;
protected:
virtual void machine_reset() override;
DECLARE_READ32_MEMBER(unknown_r);
DECLARE_READ32_MEMBER(enet_r);
DECLARE_WRITE32_MEMBER(enet_w);
DECLARE_READ32_MEMBER(eisa_io_r);
DECLARE_WRITE32_MEMBER(ip22_write_ram);
void ip225015_map(address_map &map);
void ip22_map(address_map &map);
static void cdrom_config(device_t *device);
@ -109,7 +128,8 @@ private:
required_shared_ptr<uint32_t> m_mainram;
required_device<sgi_mc_device> m_mem_ctrl;
required_device<wd33c93_device> m_scsi_ctrl;
required_device<dac_16bit_r2r_twos_complement_device> m_dac;
required_device<dac_16bit_r2r_twos_complement_device> m_ldac;
required_device<dac_16bit_r2r_twos_complement_device> m_rdac;
required_device<newport_video_device> m_newport;
required_device<hal2_device> m_hal2;
required_device<hpc3_device> m_hpc3;
@ -124,6 +144,23 @@ private:
/*static*/ char const *const ip22_state::IOC2_TAG = "ioc2";
/*static*/ char const *const ip22_state::RTC_TAG = "rtc";
class ip24_state : public ip22_state
{
public:
ip24_state(const machine_config &mconfig, device_type type, const char *tag)
: ip22_state(mconfig, type, tag)
, m_scsi_ctrl2(*this, "wd33c93_2")
{
}
void ip244415(machine_config &config);
private:
void ip24_map(address_map &map);
required_device<wd33c93_device> m_scsi_ctrl2;
};
#define VERBOSE_LEVEL ( 0 )
inline void ATTR_PRINTF(3,4) ip22_state::verboselog(int n_level, const char *s_fmt, ... )
@ -162,6 +199,11 @@ WRITE32_MEMBER(ip22_state::enet_w)
}
}
READ32_MEMBER(ip22_state::eisa_io_r)
{
return 0xffffffff;
}
// a bit hackish, but makes the memory detection work properly and allows a big cleanup of the mapping
WRITE32_MEMBER(ip22_state::ip22_write_ram)
{
@ -181,29 +223,43 @@ WRITE32_MEMBER(ip22_state::ip22_write_ram)
COMBINE_DATA(&m_mainram[offset]);
}
void ip22_state::ip225015_map(address_map &map)
READ32_MEMBER(ip22_state::unknown_r)
{
return 0x043b2800;
}
void ip22_state::ip22_map(address_map &map)
{
map(0x00000000, 0x0007ffff).bankrw("bank1"); /* mirror of first 512k of main RAM */
map(0x00080000, 0x0009ffff).r(FUNC(ip22_state::eisa_io_r));
map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip22_state::ip22_write_ram)); /* 128 MB of main RAM */
map(0x1f0f0000, 0x1f0f1fff).rw(m_newport, FUNC(newport_video_device::rex3_r), FUNC(newport_video_device::rex3_w));
//map(0x1f4f0100, 0x1f4f0103).r(FUNC(ip22_state::unknown_r));
map(0x1fa00000, 0x1fa1ffff).rw(m_mem_ctrl, FUNC(sgi_mc_device::read), FUNC(sgi_mc_device::write));
map(0x1fb80000, 0x1fb8ffff).rw(m_hpc3, FUNC(hpc3_device::pbusdma_r), FUNC(hpc3_device::pbusdma_w));
map(0x1fb90000, 0x1fb9ffff).rw(m_hpc3, FUNC(hpc3_device::hd_enet_r), FUNC(hpc3_device::hd_enet_w));
map(0x1fbb0000, 0x1fbb0003).ram(); /* unknown, but read a lot and discarded */
map(0x1fbc0000, 0x1fbc7fff).rw(m_hpc3, FUNC(hpc3_device::hd0_r), FUNC(hpc3_device::hd0_w));
map(0x1fbc8000, 0x1fbcffff).rw(m_hpc3, FUNC(hpc3_device::unkpbus0_r), FUNC(hpc3_device::unkpbus0_w)).share("unkpbus0");
map(0x1fb80000, 0x1fb8ffff).rw(m_hpc3, FUNC(hpc3_device::pbusdma_r), FUNC(hpc3_device::pbusdma_w));
map(0x1fbc0000, 0x1fbc7fff).rw(m_hpc3, FUNC(hpc3_device::hd_r<0>), FUNC(hpc3_device::hd_w<0>));
map(0x1fbd4000, 0x1fbd44ff).rw(FUNC(ip22_state::enet_r), FUNC(ip22_state::enet_w));
map(0x1fbd8000, 0x1fbd83ff).rw(m_hal2, FUNC(hal2_device::read), FUNC(hal2_device::write));
map(0x1fbd8400, 0x1fbd87ff).ram(); /* hack */
map(0x1fbd9000, 0x1fbd93ff).rw(m_hpc3, FUNC(hpc3_device::pbus4_r), FUNC(hpc3_device::pbus4_w));
map(0x1fbd9800, 0x1fbd9bff).rw(m_ioc2, FUNC(ioc2_device::read), FUNC(ioc2_device::write));
map(0x1fbdc000, 0x1fbdc7ff).ram();
map(0x1fbdd000, 0x1fbdd3ff).ram();
map(0x1fbdc000, 0x1fbdcfff).rw(m_hpc3, FUNC(hpc3_device::dma_config_r), FUNC(hpc3_device::dma_config_w));
map(0x1fbdd000, 0x1fbddfff).rw(m_hpc3, FUNC(hpc3_device::pio_config_r), FUNC(hpc3_device::pio_config_w));
map(0x1fbe0000, 0x1fbe04ff).rw(m_rtc, FUNC(ds1386_device::data_r), FUNC(ds1386_device::data_w)).umask32(0x000000ff);
map(0x1fc00000, 0x1fc7ffff).rom().region("user1", 0);
map(0x20000000, 0x27ffffff).share("mainram").ram().w(FUNC(ip22_state::ip22_write_ram));
}
void ip24_state::ip24_map(address_map &map)
{
ip22_map(map);
map(0x1fbc8000, 0x1fbcffff).rw(m_hpc3, FUNC(hpc3_device::hd_r<1>), FUNC(hpc3_device::hd_w<1>));
}
void ip22_state::machine_reset()
{
// set up low RAM mirror
@ -212,16 +268,6 @@ void ip22_state::machine_reset()
m_maincpu->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS);
}
void ip22_state::machine_start()
{
}
void ip22_state::init_ip225015()
{
// IP22 uses 2 pieces of PC-compatible hardware: the 8042 PS/2 keyboard/mouse
// interface and the 8254 PIT. Both are licensed cores embedded in the IOC custom chip.
}
static INPUT_PORTS_START( ip225015 )
PORT_START("IN0") // unused IN0
PORT_START("DSW0") // unused IN1
@ -237,11 +283,8 @@ void ip22_state::cdrom_config(device_t *device)
MCFG_SOUND_ROUTE(1, ":rspeaker", 1.0)
}
void ip22_state::ip225015(machine_config &config)
void ip22_state::ip22_base(machine_config &config)
{
R5000BE(config, m_maincpu, 50000000*3);
m_maincpu->set_addrmap(AS_PROGRAM, &ip22_state::ip225015_map);
/* video hardware */
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_refresh_hz(60);
@ -249,24 +292,29 @@ void ip22_state::ip225015(machine_config &config)
screen.set_size(1280+64, 1024+64);
screen.set_visarea(0, 1279, 0, 1023);
screen.set_screen_update("newport", FUNC(newport_video_device::screen_update));
screen.screen_vblank().set(m_newport, FUNC(newport_video_device::vblank_w));
PALETTE(config, "palette", 65536);
NEWPORT_VIDEO(config, m_newport);
NEWPORT_VIDEO(config, m_newport, m_maincpu, m_ioc2);
SGI_MC(config, m_mem_ctrl);
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_dac, 0);
m_dac->add_route(ALL_OUTPUTS, "lspeaker", 0.25);
m_dac->add_route(ALL_OUTPUTS, "rspeaker", 0.25);
DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_ldac, 0);
m_ldac->add_route(ALL_OUTPUTS, "lspeaker", 0.25);
DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_rdac, 0);
m_rdac->add_route(ALL_OUTPUTS, "rspeaker", 0.25);
voltage_regulator_device &vreg = VOLTAGE_REGULATOR(config, "vref");
vreg.set_output(5.0);
vreg.add_route(0, "dac", 1.0, DAC_VREF_POS_INPUT);
vreg.add_route(0, "dac", -1.0, DAC_VREF_NEG_INPUT);
vreg.add_route(0, "ldac", 1.0, DAC_VREF_POS_INPUT);
vreg.add_route(0, "rdac", 1.0, DAC_VREF_POS_INPUT);
vreg.add_route(0, "ldac", -1.0, DAC_VREF_NEG_INPUT);
vreg.add_route(0, "rdac", -1.0, DAC_VREF_NEG_INPUT);
scsi_port_device &scsi(SCSI_PORT(config, "scsi"));
scsi.set_slot_device(1, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_1));
@ -279,26 +327,51 @@ void ip22_state::ip225015(machine_config &config)
SGI_HAL2(config, m_hal2);
SGI_IOC2_GUINNESS(config, m_ioc2, m_maincpu);
SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_ioc2, m_dac);
DS1386_8K(config, m_rtc, 32768);
MACHINE_CONFIG_END
}
MACHINE_CONFIG_START(ip22_state::ip224613)
ip225015(config);
MCFG_DEVICE_REPLACE("maincpu", R4600BE, 133333333)
//MCFG_MIPS3_ICACHE_SIZE(32768)
//MCFG_MIPS3_DCACHE_SIZE(32768)
MCFG_DEVICE_PROGRAM_MAP( ip225015_map)
MACHINE_CONFIG_END
void ip22_state::ip225015(machine_config &config)
{
ip22_base(config);
MACHINE_CONFIG_START(ip22_state::ip244415)
ip225015(config);
MCFG_DEVICE_REPLACE("maincpu", R4600BE, 150000000)
//MCFG_MIPS3_ICACHE_SIZE(32768)
//MCFG_MIPS3_DCACHE_SIZE(32768)
MCFG_DEVICE_PROGRAM_MAP(ip225015_map)
MACHINE_CONFIG_END
R5000BE(config, m_maincpu, 50000000*3);
m_maincpu->set_icache_size(32768);
m_maincpu->set_dcache_size(32768);
m_maincpu->set_addrmap(AS_PROGRAM, &ip22_state::ip22_map);
SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_ioc2, m_ldac, m_rdac);
}
void ip22_state::ip224613(machine_config &config)
{
ip22_base(config);
R4600BE(config, m_maincpu, 33333333*4);
m_maincpu->set_icache_size(32768);
m_maincpu->set_dcache_size(32768);
m_maincpu->set_addrmap(AS_PROGRAM, &ip22_state::ip22_map);
SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_ioc2, m_ldac, m_rdac);
}
void ip24_state::ip244415(machine_config &config)
{
ip22_base(config);
R4400BE(config, m_maincpu, 50000000*3);
m_maincpu->set_icache_size(32768);
m_maincpu->set_dcache_size(32768);
m_maincpu->set_addrmap(AS_PROGRAM, &ip24_state::ip24_map);
SCSI_PORT(config, "scsi2");
WD33C93(config, m_scsi_ctrl2);
m_scsi_ctrl2->set_scsi_port("scsi2");
m_scsi_ctrl2->irq_cb().set(m_hpc3, FUNC(hpc3_device::scsi_irq));
SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_scsi_ctrl2, m_ioc2, m_ldac, m_rdac);
}
/* SCC init ip225015
* Channel A
@ -344,7 +417,7 @@ ROM_START( ip244415 )
ROM_LOAD( "ip244415.bin", 0x000000, 0x080000, CRC(2f37825a) SHA1(0d48c573b53a307478820b85aacb57b868297ca3) )
ROM_END
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
COMP( 1993, ip225015, 0, 0, ip225015, ip225015, ip22_state, init_ip225015, "Silicon Graphics Inc", "Indy (R5000, 150MHz)", MACHINE_NOT_WORKING )
COMP( 1993, ip224613, 0, 0, ip224613, ip225015, ip22_state, init_ip225015, "Silicon Graphics Inc", "Indy (R4600, 133MHz)", MACHINE_NOT_WORKING )
COMP( 1994, ip244415, 0, 0, ip244415, ip225015, ip22_state, init_ip225015, "Silicon Graphics Inc", "Indigo2 (R4400, 150MHz)", MACHINE_NOT_WORKING )
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
COMP( 1993, ip225015, 0, 0, ip225015, ip225015, ip22_state, empty_init, "Silicon Graphics Inc", "Indy (R5000, 150MHz)", MACHINE_NOT_WORKING )
COMP( 1993, ip224613, 0, 0, ip224613, ip225015, ip22_state, empty_init, "Silicon Graphics Inc", "Indy (R4600, 133MHz)", MACHINE_NOT_WORKING )
COMP( 1994, ip244415, 0, 0, ip244415, ip225015, ip24_state, empty_init, "Silicon Graphics Inc", "Indigo2 (R4400, 150MHz)", MACHINE_NOT_WORKING )

417
src/mame/machine/hpc3.cpp
View File

@ -9,95 +9,157 @@
#include "emu.h"
#include "machine/hpc3.h"
#define LOG_UNKNOWN (1 << 0)
#define LOG_PBUS_DMA (1 << 1)
#define LOG_SCSI (1 << 2)
#define LOG_ETHERNET (1 << 3)
#define LOG_PBUS4 (1 << 4)
#define LOG_CHAIN (1 << 5)
#define VERBOSE (0)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(SGI_HPC3, hpc3_device, "hpc3", "SGI HPC3")
hpc3_device::hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SGI_HPC3, tag, owner, clock)
, m_maincpu(*this, finder_base::DUMMY_TAG)
, m_wd33c93(*this, finder_base::DUMMY_TAG)
, m_wd33c93_2(*this, finder_base::DUMMY_TAG)
, m_ioc2(*this, finder_base::DUMMY_TAG)
, m_dac(*this, finder_base::DUMMY_TAG)
, m_ldac(*this, finder_base::DUMMY_TAG)
, m_rdac(*this, finder_base::DUMMY_TAG)
, m_mainram(*this, ":mainram")
, m_unkpbus0(*this, ":unkpbus0")
{
}
#define VERBOSE_LEVEL (0)
inline void ATTR_PRINTF(3,4) hpc3_device::verboselog(int n_level, const char *s_fmt, ...)
{
if (VERBOSE_LEVEL >= n_level)
{
va_list v;
char buf[32768];
va_start(v, s_fmt);
vsprintf(buf, s_fmt, v);
va_end(v);
logerror("%s: %s", machine().describe_context(), buf);
}
}
void hpc3_device::device_start()
{
m_pbus_dma_timer = timer_alloc(TIMER_PBUS_DMA);
m_pbus_dma_timer->adjust(attotime::never);
save_item(NAME(m_enetr_nbdp));
save_item(NAME(m_enetr_cbp));
save_item(NAME(m_unk0));
save_item(NAME(m_unk1));
save_item(NAME(m_ic_unk0));
save_item(NAME(m_scsi0_desc));
save_item(NAME(m_scsi0_addr));
save_item(NAME(m_scsi0_flags));
save_item(NAME(m_scsi0_byte_count));
save_item(NAME(m_scsi0_next_addr));
save_item(NAME(m_scsi0_dma_ctrl));
save_item(NAME(m_pio_config));
for (uint32_t i = 0; i < 8; i++)
{
save_item(NAME(m_pbus_dma[i].m_active), i);
save_item(NAME(m_pbus_dma[i].m_cur_ptr), i);
save_item(NAME(m_pbus_dma[i].m_desc_ptr), i);
save_item(NAME(m_pbus_dma[i].m_desc_flags), i);
save_item(NAME(m_pbus_dma[i].m_next_ptr), i);
save_item(NAME(m_pbus_dma[i].m_bytes_left), i);
save_item(NAME(m_pbus_dma[i].m_config), i);
m_pbus_dma[i].m_timer = timer_alloc(TIMER_PBUS_DMA + i);
m_pbus_dma[i].m_timer->adjust(attotime::never);
}
}
void hpc3_device::device_reset()
{
m_enetr_nbdp = 0x80000000;
m_enetr_cbp = 0x80000000;
m_pbus_dma.m_active = 0;
m_pbus_dma_timer->adjust(attotime::never);
m_unk0 = 0;
m_unk1 = 0;
m_ic_unk0 = 0;
m_scsi0_desc = 0;
m_scsi0_addr = 0;
m_scsi0_flags = 0;
m_scsi0_byte_count = 0;
m_scsi0_next_addr = 0;
m_scsi0_dma_ctrl = 0;
for (uint32_t i = 0; i < 8; i++)
{
m_pbus_dma[i].m_active = 0;
m_pbus_dma[i].m_cur_ptr = 0;
m_pbus_dma[i].m_desc_ptr = 0;
m_pbus_dma[i].m_desc_flags = 0;
m_pbus_dma[i].m_next_ptr = 0;
m_pbus_dma[i].m_bytes_left = 0;
m_pbus_dma[i].m_config = 0;
m_pbus_dma[i].m_active = false;
m_pbus_dma[i].m_timer->adjust(attotime::never);
}
}
void hpc3_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_PBUS_DMA:
do_dma(ptr, param);
case TIMER_PBUS_DMA+1:
case TIMER_PBUS_DMA+2:
do_pbus_dma(id - TIMER_PBUS_DMA);
break;
case TIMER_PBUS_DMA+0:
case TIMER_PBUS_DMA+3:
case TIMER_PBUS_DMA+4:
case TIMER_PBUS_DMA+5:
case TIMER_PBUS_DMA+6:
case TIMER_PBUS_DMA+7:
LOGMASKED(LOG_UNKNOWN, "HPC3: Ignoring active PBUS DMA on channel %d\n", id - TIMER_PBUS_DMA);
break;
default:
assert_always(false, "Unknown id in hpc3_device::device_timer");
}
}
TIMER_CALLBACK_MEMBER(hpc3_device::do_dma)
void hpc3_device::do_pbus_dma(uint32_t channel)
{
m_pbus_dma_timer->adjust(attotime::never);
pbus_dma_t &dma = m_pbus_dma[channel];
if (m_pbus_dma.m_active)
if (dma.m_active && (channel == 1 || channel == 2))
{
address_space &space = m_maincpu->space(AS_PROGRAM);
uint16_t temp16 = space.read_dword(m_pbus_dma.m_cur_ptr) >> 16;
uint16_t temp16 = space.read_dword(dma.m_cur_ptr) >> 16;
int16_t stemp16 = (int16_t)((temp16 >> 8) | (temp16 << 8));
m_dac->write(stemp16);
if (channel == 1)
m_ldac->write(stemp16);
else
m_rdac->write(stemp16);
m_pbus_dma.m_cur_ptr += 4;
m_pbus_dma.m_words_left -= 4;
dma.m_cur_ptr += 4;
dma.m_bytes_left -= 4;
if (m_pbus_dma.m_words_left == 0)
if (dma.m_bytes_left == 0)
{
if (m_pbus_dma.m_next_ptr != 0)
if (!BIT(dma.m_desc_flags, 31))
{
m_pbus_dma.m_desc_ptr = m_pbus_dma.m_next_ptr;
logerror("Next PBUS_DMA_DescPtr = %08x\n", m_pbus_dma.m_desc_ptr); fflush(stdout);
m_pbus_dma.m_cur_ptr = space.read_dword(m_pbus_dma.m_desc_ptr);
m_pbus_dma.m_words_left = space.read_dword(m_pbus_dma.m_desc_ptr + 4);
m_pbus_dma.m_next_ptr = space.read_dword(m_pbus_dma.m_desc_ptr + 8);
logerror("Next PBUS_DMA_CurPtr = %08x\n", m_pbus_dma.m_cur_ptr); fflush(stdout);
logerror("Next PBUS_DMA_WordsLeft = %08x\n", m_pbus_dma.m_words_left); fflush(stdout);
logerror("Next PBUS_DMA_NextPtr = %08x\n", m_pbus_dma.m_next_ptr); fflush(stdout);
dma.m_desc_ptr = dma.m_next_ptr;
LOGMASKED(LOG_PBUS_DMA, "Channel %d Next PBUS_DMA_DescPtr = %08x\n", channel, dma.m_desc_ptr); fflush(stdout);
dma.m_cur_ptr = space.read_dword(dma.m_desc_ptr);
dma.m_desc_flags = space.read_dword(dma.m_desc_ptr + 4);
dma.m_bytes_left = dma.m_desc_flags & 0x7fffffff;
dma.m_next_ptr = space.read_dword(dma.m_desc_ptr + 8);
LOGMASKED(LOG_PBUS_DMA, "Channel %d Next PBUS_DMA_CurPtr = %08x\n", channel, dma.m_cur_ptr); fflush(stdout);
LOGMASKED(LOG_PBUS_DMA, "Channel %d Next PBUS_DMA_BytesLeft = %08x\n", channel, dma.m_bytes_left); fflush(stdout);
LOGMASKED(LOG_PBUS_DMA, "Channel %d Next PBUS_DMA_NextPtr = %08x\n", channel, dma.m_next_ptr); fflush(stdout);
}
else
{
m_pbus_dma.m_active = 0;
dma.m_active = false;
dma.m_timer->adjust(attotime::never);
return;
}
}
m_pbus_dma_timer->adjust(attotime::from_hz(44100));
dma.m_timer->adjust(attotime::from_hz(44100));
}
else
{
dma.m_timer->adjust(attotime::never);
}
}
@ -106,19 +168,19 @@ READ32_MEMBER(hpc3_device::hd_enet_r)
switch (offset)
{
case 0x0004/4:
//verboselog(machine, 0, "HPC3 SCSI0DESC Read: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, m_scsi0_desc);
LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DESC Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_scsi0_desc);
return m_scsi0_desc;
case 0x1004/4:
//verboselog(machine, 0, "HPC3 SCSI0DMACTRL Read: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, m_scsi0_dma_ctrl);
LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DMACTRL Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_scsi0_dma_ctrl);
return m_scsi0_dma_ctrl;
case 0x4000/4:
//verboselog(machine, 2, "HPC3 ENETR CBP Read: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, m_enetr_nbdp);
LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR CBP Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_enetr_nbdp);
return m_enetr_cbp;
case 0x4004/4:
//verboselog(machine, 2, "HPC3 ENETR NBDP Read: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, m_enetr_nbdp);
LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR NBDP Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_enetr_nbdp);
return m_enetr_nbdp;
default:
//verboselog(machine, 0, "Unknown HPC3 ENET/HDx Read: %08x (%08x)\n", 0x1fb90000 + (offset << 2), mem_mask);
LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx Read: %08x (%08x)\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask);
return 0;
}
}
@ -128,101 +190,104 @@ WRITE32_MEMBER(hpc3_device::hd_enet_w)
switch (offset)
{
case 0x0004/4:
//verboselog(machine, 2, "HPC3 SCSI0DESC Write: %08x\n", data);
LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DESC Write: %08x\n", machine().describe_context(), data);
m_scsi0_desc = data;
break;
case 0x1004/4:
//verboselog(machine, 2, "HPC3 SCSI0DMACTRL Write: %08x\n", data);
LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DMACTRL Write: %08x\n", machine().describe_context(), data);
m_scsi0_dma_ctrl = data;
break;
case 0x4000/4:
//verboselog(machine, 2, "HPC3 ENETR CBP Write: %08x\n", data);
LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR CBP Write: %08x\n", machine().describe_context(), data);
m_enetr_cbp = data;
break;
case 0x4004/4:
//verboselog(machine, 2, "HPC3 ENETR NBDP Write: %08x\n", data);
LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR NBDP Write: %08x\n", machine().describe_context(), data);
m_enetr_nbdp = data;
break;
default:
//verboselog(machine, 0, "Unknown HPC3 ENET/HDx write: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, data);
LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx write: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, data);
break;
}
}
READ32_MEMBER(hpc3_device::hd0_r)
template<uint32_t index>
READ32_MEMBER(hpc3_device::hd_r)
{
switch (offset)
{
case 0x0000/4:
case 0x4000/4:
// //verboselog(machine, 2, "HPC3 HD0 Status Read: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, nHPC3_hd0_regs[0x17]);
if (ACCESSING_BITS_0_7)
{
return m_wd33c93->read(space, 0);
}
else
{
return 0;
const uint8_t ret = index ? m_wd33c93_2->read(space, 0) : m_wd33c93->read(space, 0);
LOGMASKED(LOG_SCSI, "%s: SCSI%d Read 0: %02x\n", machine().describe_context(), index, ret);
return ret;
}
break;
case 0x0004/4:
case 0x4004/4:
// //verboselog(machine, 2, "HPC3 HD0 Register Read: %08x (%08x): %08x\n", 0x1fb90000 + (offset << 2), mem_mask, nHPC3_hd0_regs[nHPC3_hd0_register]);
if (ACCESSING_BITS_0_7)
{
return m_wd33c93->read(space, 1);
}
else
{
return 0;
const uint8_t ret = index ? m_wd33c93_2->read(space, 1) : m_wd33c93->read(space, 1);
LOGMASKED(LOG_SCSI, "%s: SCSI%d Read 1: %02x\n", machine().describe_context(), index, ret);
return ret;
}
break;
default:
//verboselog(machine, 0, "Unknown HPC3 HD0 Read: %08x (%08x) [%x] PC=%x\n", 0x1fbc0000 + (offset << 2), mem_mask, offset, m_maincpu->pc());
return 0;
LOGMASKED(LOG_SCSI | LOG_UNKNOWN, "%s: %s: Unknown HPC3 HD%d Read: %08x & %08x\n", machine().describe_context(), machine().describe_context(),
index, 0x1fbc4000 + (offset << 2) + index * 0x8000, mem_mask);
break;
}
return 0;
}
WRITE32_MEMBER(hpc3_device::hd0_w)
template<uint32_t index>
WRITE32_MEMBER(hpc3_device::hd_w)
{
switch (offset)
{
case 0x0000/4:
case 0x4000/4:
// //verboselog(machine, 2, "HPC3 HD0 Register Select Write: %08x\n", data);
case 0x0000:
if (ACCESSING_BITS_0_7)
{
m_wd33c93->write(space, 0, data & 0x000000ff);
LOGMASKED(LOG_SCSI, "%s: SCSI%d Write 0 = %02x\n", machine().describe_context(), index, (uint8_t)data);
index ? m_wd33c93_2->write(space, 0, data & 0xff) : m_wd33c93->write(space, 0, data & 0xff);
}
break;
case 0x0004/4:
case 0x4004/4:
// //verboselog(machine, 2, "HPC3 HD0 Register %d Write: %08x\n", nHPC3_hd0_register, data);
case 0x0001:
if (ACCESSING_BITS_0_7)
{
m_wd33c93->write(space, 1, data & 0x000000ff);
LOGMASKED(LOG_SCSI, "%s: SCSI%d Write 1 = %02x\n", machine().describe_context(), index, (uint8_t)data);
index ? m_wd33c93_2->write(space, 1, data & 0xff) : m_wd33c93->write(space, 1, data & 0xff);
}
break;
default:
//verboselog(machine, 0, "Unknown HPC3 HD0 Write: %08x (%08x): %08x\n", 0x1fbc0000 + (offset << 2), mem_mask, data);
LOGMASKED(LOG_SCSI | LOG_UNKNOWN, "%s: %s: Unknown HPC3 HD%d Write: %08x = %08x & %08x\n", machine().describe_context(), machine().describe_context(),
index, 0x1fbc4000 + (offset << 2) + index * 0x8000, data, mem_mask);
break;
}
}
template DECLARE_READ32_MEMBER(hpc3_device::hd_r<0>);
template DECLARE_READ32_MEMBER(hpc3_device::hd_r<1>);
template DECLARE_WRITE32_MEMBER(hpc3_device::hd_w<0>);
template DECLARE_WRITE32_MEMBER(hpc3_device::hd_w<1>);
READ32_MEMBER(hpc3_device::pbus4_r)
{
switch (offset)
{
case 0x0004/4:
//verboselog(machine, 2, "HPC3 PBUS4 Unknown 0 Read: (%08x): %08x\n", mem_mask, m_unk0);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 0 Read: (%08x): %08x\n", machine().describe_context(), mem_mask, m_unk0);
return m_unk0;
case 0x000c/4:
//verboselog(machine, 2, "Interrupt Controller(?) Read: (%08x): %08x\n", mem_mask, m_ic_unk0);
LOGMASKED(LOG_PBUS4, "%s: Interrupt Controller(?) Read: (%08x): %08x\n", machine().describe_context(), mem_mask, m_ic_unk0);
return m_ic_unk0;
case 0x0014/4:
//verboselog(machine, 2, "HPC3 PBUS4 Unknown 1 Read: (%08x): %08x\n", mem_mask, m_unk1);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 1 Read: (%08x): %08x\n", machine().describe_context(), mem_mask, m_unk1);
return m_unk1;
default:
//verboselog(machine, 0, "Unknown HPC3 PBUS4 Read: %08x (%08x)\n", 0x1fbd9000 + (offset << 2), mem_mask);
LOGMASKED(LOG_PBUS4 | LOG_UNKNOWN, "%s: Unknown HPC3 PBUS4 Read: %08x (%08x)\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), mem_mask);
return 0;
}
}
@ -232,112 +297,163 @@ WRITE32_MEMBER(hpc3_device::pbus4_w)
switch (offset)
{
case 0x0004/4:
//verboselog(machine, 2, "HPC3 PBUS4 Unknown 0 Write: %08x (%08x)\n", data, mem_mask);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_unk0 = data;
break;
case 0x000c/4:
//verboselog(machine, 2, "Interrupt Controller(?) Write: (%08x): %08x\n", mem_mask, data);
LOGMASKED(LOG_PBUS4, "%s: Interrupt Controller(?) Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_ic_unk0 = data;
break;
case 0x0014/4:
//verboselog(machine, 2, "HPC3 PBUS4 Unknown 1 Write: %08x (%08x)\n", data, mem_mask);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_unk1 = data;
break;
default:
//verboselog(machine, 0, "Unknown HPC3 PBUS4 Write: %08x (%08x): %08x\n", 0x1fbd9000 + (offset << 2), mem_mask, data);
LOGMASKED(LOG_PBUS4 | LOG_UNKNOWN, "%s: Unknown HPC3 PBUS4 Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), data, mem_mask);
break;
}
}
READ32_MEMBER(hpc3_device::pbusdma_r)
{
//uint32_t channel = offset / (0x2000/4);
//verboselog(machine(), 0, "PBUS DMA Channel %d Read: 0x%08x (%08x)\n", channel, 0x1fb80000 + offset*4, mem_mask);
uint32_t channel = offset / (0x2000/4);
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Read: %08x & %08x\n", machine().describe_context(), channel, 0x1fb80000 + offset*4, mem_mask);
return 0;
}
WRITE32_MEMBER(hpc3_device::pbusdma_w)
{
uint32_t channel = offset / (0x2000/4);
pbus_dma_t &dma = m_pbus_dma[channel];
switch (offset & 0x07ff)
{
case 0x0000/4:
//verboselog(machine, 0, "PBUS DMA Channel %d Buffer Pointer Write: 0x%08x\n", channel, data);
return;
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Buffer Pointer Write: %08x\n", machine().describe_context(), channel, data);
break;
case 0x0004/4:
//verboselog(machine, 0, "PBUS DMA Channel %d Descriptor Pointer Write: 0x%08x\n", channel, data);
if (channel == 1)
{
m_pbus_dma.m_desc_ptr = data;
logerror("PBUS_DMA_DescPtr = %08x\n", m_pbus_dma.m_desc_ptr); fflush(stdout);
m_pbus_dma.m_cur_ptr = space.read_dword(m_pbus_dma.m_desc_ptr);
m_pbus_dma.m_words_left = space.read_dword(m_pbus_dma.m_desc_ptr + 4);
m_pbus_dma.m_next_ptr = space.read_dword(m_pbus_dma.m_desc_ptr + 8);
logerror("PBUS_DMA_CurPtr = %08x\n", m_pbus_dma.m_cur_ptr); fflush(stdout);
logerror("PBUS_DMA_WordsLeft = %08x\n", m_pbus_dma.m_words_left); fflush(stdout);
logerror("PBUS_DMA_NextPtr = %08x\n", m_pbus_dma.m_next_ptr); fflush(stdout);
}
return;
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Descriptor Pointer Write: %08x\n", machine().describe_context(), channel, data);
dma.m_desc_ptr = data;
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS_DMA_DescPtr = %08x\n", machine().describe_context(), dma.m_desc_ptr); fflush(stdout);
dma.m_cur_ptr = space.read_dword(dma.m_desc_ptr);
dma.m_desc_flags = space.read_dword(dma.m_desc_ptr + 4);
dma.m_next_ptr = space.read_dword(dma.m_desc_ptr + 8);
dma.m_bytes_left = dma.m_desc_flags & 0x7fffffff;
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS_DMA_CurPtr = %08x\n", machine().describe_context(), dma.m_cur_ptr); fflush(stdout);
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS_DMA_BytesLeft = %08x\n", machine().describe_context(), dma.m_bytes_left); fflush(stdout);
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS_DMA_NextPtr = %08x\n", machine().describe_context(), dma.m_next_ptr); fflush(stdout);
break;
case 0x1000/4:
logerror("PBUS DMA Channel %d Control Register Write: 0x%08x\n", channel, data);
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Control Register Write: %08x\n", machine().describe_context(), channel, data);
if (data & PBUS_CTRL_ENDIAN)
{
logerror(" Little Endian\n");
}
LOGMASKED(LOG_PBUS_DMA, " Little Endian\n");
else
{
logerror(" Big Endian\n");
}
LOGMASKED(LOG_PBUS_DMA, " Big Endian\n");
if (data & PBUS_CTRL_RECV)
{
logerror(" RX DMA\n");
}
LOGMASKED(LOG_PBUS_DMA, " RX DMA\n");
else
{
logerror(" TX DMA\n");
}
LOGMASKED(LOG_PBUS_DMA, " TX DMA\n");
if (data & PBUS_CTRL_FLUSH)
{
logerror(" Flush for RX\n");
}
LOGMASKED(LOG_PBUS_DMA, " Flush for RX\n");
if (data & PBUS_CTRL_DMASTART)
{
logerror(" Start DMA\n");
}
LOGMASKED(LOG_PBUS_DMA, " Start DMA\n");
if (data & PBUS_CTRL_LOAD_EN)
LOGMASKED(LOG_PBUS_DMA, " Load Enable\n");
LOGMASKED(LOG_PBUS_DMA, " High Water Mark: %04x bytes\n", (data & PBUS_CTRL_HIGHWATER) >> 8);
LOGMASKED(LOG_PBUS_DMA, " FIFO Begin: Row %04x\n", (data & PBUS_CTRL_FIFO_BEG) >> 16);
LOGMASKED(LOG_PBUS_DMA, " FIFO End: Row %04x\n", (data & PBUS_CTRL_FIFO_END) >> 24);
if (((data & PBUS_CTRL_DMASTART) && (data & PBUS_CTRL_LOAD_EN)) && (channel == 1 || channel == 2))
{
logerror(" Load Enable\n");
LOGMASKED(LOG_PBUS_DMA, " Starting DMA\n");
dma.m_timer->adjust(attotime::from_hz(44100));
dma.m_active = true;
}
logerror(" High Water Mark: %04x bytes\n", (data & PBUS_CTRL_HIGHWATER) >> 8);
logerror(" FIFO Begin: Row %04x\n", (data & PBUS_CTRL_FIFO_BEG) >> 16);
logerror(" FIFO End: Rowe %04x\n", (data & PBUS_CTRL_FIFO_END) >> 24);
if ((data & PBUS_CTRL_DMASTART) || (data & PBUS_CTRL_LOAD_EN))
{
m_pbus_dma_timer->adjust(attotime::from_hz(44100));
m_pbus_dma.m_active = 1;
}
return;
break;
default:
LOGMASKED(LOG_PBUS_DMA | LOG_UNKNOWN, "%s: Unknown PBUS DMA Channel %d Write: %08x = %08x & %08x\n", machine().describe_context(), channel, 0x1fb80000 + offset*4, data, mem_mask);
break;
}
logerror("Unknown PBUS DMA Channel %d Write: 0x%08x: 0x%08x (%08x)\n", channel, 0x1fb80000 + offset*4, data, mem_mask);
}
READ32_MEMBER(hpc3_device::dma_config_r)
{
const uint32_t channel = (offset >> 7) & 7;
const uint32_t data = m_pbus_dma[channel].m_config;
LOGMASKED(LOG_PBUS_DMA, "%s: Read Channel %d DMA Configuration: %08x & %08x\n", machine().describe_context(), channel, data, mem_mask);
return data;
}
WRITE32_MEMBER(hpc3_device::dma_config_w)
{
const uint32_t channel = (offset >> 7) & 7;
COMBINE_DATA(&m_pbus_dma[channel].m_config);
LOGMASKED(LOG_PBUS_DMA, "%s: Write Channel %d DMA Configuration: %08x & %08x\n", machine().describe_context(), channel, data, mem_mask);
LOGMASKED(LOG_PBUS_DMA, " DMA Read State D3 gio_clk cycles: %d\n", BIT(data, 0) ? 2 : 3);
LOGMASKED(LOG_PBUS_DMA, " DMA Read State D4 gio_clk cycles: %d\n", (data >> 1) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " DMA Read State D5 gio_clk cycles: %d\n", (data >> 5) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " DMA Write State D3 gio_clk cycles: %d\n", BIT(data, 9) ? 2 : 3);
LOGMASKED(LOG_PBUS_DMA, " DMA Write State D4 gio_clk cycles: %d\n", (data >> 10) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " DMA Write State D5 gio_clk cycles: %d\n", (data >> 14) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " Device Bit Width: %d\n", BIT(data, 18) ? 16 : 32);
LOGMASKED(LOG_PBUS_DMA, " Even Address Bytes on %s\n", BIT(data, 19) ? "15..8" : "7..0");
LOGMASKED(LOG_PBUS_DMA, " Device %s Real-Time\n", BIT(data, 21) ? "is" : "is not");
LOGMASKED(LOG_PBUS_DMA, " Burst Count: %d\n", (data >> 22) & 0x1f);
LOGMASKED(LOG_PBUS_DMA, " %sUse Unsynchronized DREQ\n", BIT(data, 27) ? "" : "Do Not ");
}
READ32_MEMBER(hpc3_device::pio_config_r)
{
uint32_t channel = (offset >> 6) & 15;
if (channel >= 10)
{
channel = (channel & 1) ? 9 : 8;
}
const uint32_t data = m_pio_config[channel];
LOGMASKED(LOG_PBUS_DMA, "%s: Read Channel %d PIO Configuration: %08x & %08x\n", machine().describe_context(), channel, data, mem_mask);
return data;
}
WRITE32_MEMBER(hpc3_device::pio_config_w)
{
uint32_t channel = (offset >> 6) & 15;
if (channel >= 10)
{
channel = (channel & 1) ? 9 : 8;
}
COMBINE_DATA(&m_pio_config[channel]);
LOGMASKED(LOG_PBUS_DMA, "%s: Write Channel %d PIO Configuration: %08x & %08x\n", machine().describe_context(), channel, data, mem_mask);
LOGMASKED(LOG_PBUS_DMA, " PIO Read State P2 gio_clk cycles: %d\n", BIT(data, 0) ? 1 : 2);
LOGMASKED(LOG_PBUS_DMA, " PIO Read State P3 gio_clk cycles: %d\n", (data >> 1) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " PIO Read State P4 gio_clk cycles: %d\n", (data >> 5) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " PIO Write State P2 gio_clk cycles: %d\n", BIT(data, 9) ? 1 : 2);
LOGMASKED(LOG_PBUS_DMA, " PIO Write State P3 gio_clk cycles: %d\n", (data >> 10) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " PIO Write State P4 gio_clk cycles: %d\n", (data >> 14) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " Device Bit Width: %d\n", BIT(data, 18) ? 16 : 32);
LOGMASKED(LOG_PBUS_DMA, " Even Address Bytes on %s\n", BIT(data, 19) ? "15..8" : "7..0");
}
READ32_MEMBER(hpc3_device::unkpbus0_r)
{
LOGMASKED(LOG_UNKNOWN, "%s: Unknown PBUS Read: %08x & %08x\n", machine().describe_context(), 0x1fbc8000 + offset*4, mem_mask);
return 0;
//logerror("Unknown PBUS Read: 0x%08x (%08x)\n", 0x1fbc8000 + offset*4, mem_mask);
//return m_unkpbus0[offset];
}
WRITE32_MEMBER(hpc3_device::unkpbus0_w)
{
//logerror("Unknown PBUS Write: 0x%08x = 0x%08x (%08x)\n", 0x1fbc8000 + offset*4, data, mem_mask);
//COMBINE_DATA(&m_unkpbus0[offset]);
LOGMASKED(LOG_UNKNOWN, "%s: Unknown PBUS Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbc8000 + offset*4, data, mem_mask);
}
void hpc3_device::dump_chain(address_space &space, uint32_t ch_base)
{
logerror("node: %08x %08x %08x (len = %x)\n", space.read_dword(ch_base), space.read_dword(ch_base+4), space.read_dword(ch_base+8), space.read_dword(ch_base+4) & 0x3fff);
LOGMASKED(LOG_CHAIN, "node: %08x %08x %08x (len = %x)\n", space.read_dword(ch_base), space.read_dword(ch_base+4), space.read_dword(ch_base+8), space.read_dword(ch_base+4) & 0x3fff);
if ((space.read_dword(ch_base+8) != 0) && !(space.read_dword(ch_base+4) & 0x80000000))
{
@ -351,7 +467,7 @@ void hpc3_device::fetch_chain(address_space &space)
m_scsi0_flags = space.read_dword(m_scsi0_desc+4);
m_scsi0_byte_count = m_scsi0_flags & 0x3fff;
m_scsi0_next_addr = space.read_dword(m_scsi0_desc+8);
//logerror("Fetching chain from %08x: %08x %08x %08x (length %04x)\n", m_scsi0_desc, m_scsi0_addr, m_scsi0_flags, m_scsi0_next_addr, m_scsi0_byte_count);
LOGMASKED(LOG_CHAIN, "Fetching chain from %08x: %08x %08x %08x (length %04x)\n", m_scsi0_desc, m_scsi0_addr, m_scsi0_flags, m_scsi0_next_addr, m_scsi0_byte_count);
}
bool hpc3_device::decrement_chain(address_space &space)
@ -375,13 +491,14 @@ WRITE_LINE_MEMBER(hpc3_device::scsi_irq)
if (state)
{
uint8_t dma_buffer[4096];
if (m_wd33c93->get_dma_count())
{
//logerror("m_wd33c93->get_dma_count() is %d\n", m_wd33c93->get_dma_count());
LOGMASKED(LOG_SCSI, "m_wd33c93->get_dma_count() is %d\n", m_wd33c93->get_dma_count());
if (m_scsi0_dma_ctrl & HPC3_DMACTRL_ENABLE)
{
if (m_scsi0_dma_ctrl & HPC3_DMACTRL_IRQ)
logerror("IP22: Unhandled SCSI DMA IRQ\n");
LOGMASKED(LOG_SCSI, "IP22: Unhandled SCSI DMA IRQ\n");
}
bool big_endian = (m_scsi0_dma_ctrl & HPC3_DMACTRL_ENDIAN);
@ -394,18 +511,18 @@ WRITE_LINE_MEMBER(hpc3_device::scsi_irq)
//dump_chain(space, m_scsi0_desc);
fetch_chain(space);
//logerror("DMA to device: %d bytes @ %x\n", byte_count, m_scsi0_addr);
LOGMASKED(LOG_SCSI, "DMA to SCSI device: %d bytes from %08x\n", byte_count, m_scsi0_addr);
if (byte_count <= 512)
{
for (int i = 0; i < byte_count; i++)
{
m_dma_buffer[big_endian ? BYTE4_XOR_BE(i) : BYTE4_XOR_LE(i)] = space.read_byte(m_scsi0_addr+i);
dma_buffer[big_endian ? BYTE4_XOR_BE(i) : BYTE4_XOR_LE(i)] = space.read_byte(m_scsi0_addr+i);
if (!decrement_chain(space))
break;
}
m_wd33c93->dma_write_data(byte_count, m_dma_buffer);
m_wd33c93->dma_write_data(byte_count, dma_buffer);
}
else
{
@ -416,13 +533,13 @@ WRITE_LINE_MEMBER(hpc3_device::scsi_irq)
for (int i = 0; i < sub_count; i++)
{
m_dma_buffer[big_endian ? BYTE4_XOR_BE(dstoffs+i) : BYTE4_XOR_LE(dstoffs+i)] = space.read_byte(m_scsi0_addr);
dma_buffer[big_endian ? BYTE4_XOR_BE(dstoffs+i) : BYTE4_XOR_LE(dstoffs+i)] = space.read_byte(m_scsi0_addr);
m_scsi0_addr++;
if (!decrement_chain(space))
break;
}
m_wd33c93->dma_write_data(sub_count, m_dma_buffer);
m_wd33c93->dma_write_data(sub_count, dma_buffer);
byte_count -= sub_count;
}
@ -438,15 +555,15 @@ WRITE_LINE_MEMBER(hpc3_device::scsi_irq)
//dump_chain(space, m_scsi0_desc);
fetch_chain(space);
// logerror("DMA from device: %d words @ %x\n", words, dstoffs);
LOGMASKED(LOG_SCSI, "DMA from SCSI device: %d bytes to %08x\n", byte_count, m_scsi0_addr);
if (byte_count < 512)
{
m_wd33c93->dma_read_data(byte_count, m_dma_buffer);
m_wd33c93->dma_read_data(byte_count, dma_buffer);
for (int i = 0; i < byte_count; i++)
{
space.write_byte(big_endian ? BYTE4_XOR_BE(m_scsi0_addr+i) : BYTE4_XOR_LE(m_scsi0_addr+i), m_dma_buffer[i]);
space.write_byte(big_endian ? BYTE4_XOR_BE(m_scsi0_addr+i) : BYTE4_XOR_LE(m_scsi0_addr+i), dma_buffer[i]);
if (!decrement_chain(space))
break;
}
@ -455,11 +572,11 @@ WRITE_LINE_MEMBER(hpc3_device::scsi_irq)
{
while (byte_count)
{
int sub_count = m_wd33c93->dma_read_data(512, m_dma_buffer);
int sub_count = m_wd33c93->dma_read_data(512, dma_buffer);
for (int i = 0; i < sub_count; i++)
{
space.write_byte(big_endian ? BYTE4_XOR_BE(m_scsi0_addr) : BYTE4_XOR_LE(m_scsi0_addr), m_dma_buffer[i]);
space.write_byte(big_endian ? BYTE4_XOR_BE(m_scsi0_addr) : BYTE4_XOR_LE(m_scsi0_addr), dma_buffer[i]);
m_scsi0_addr++;
if (!decrement_chain(space))
break;

48
src/mame/machine/hpc3.h
View File

@ -19,22 +19,33 @@
class hpc3_device : public device_t
{
public:
template <typename T, typename U, typename V, typename W>
hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&scsi_tag, V &&ioc2_tag, W &&dac_tag)
template <typename T, typename U, typename V, typename W, typename X>
hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner
, T &&cpu_tag, U &&scsi_tag, V &&ioc2_tag, W &&ldac_tag, X &&rdac_tag)
: hpc3_device(mconfig, tag, owner, (uint32_t)0)
{
m_maincpu.set_tag(std::forward<T>(cpu_tag));
m_wd33c93.set_tag(std::forward<U>(scsi_tag));
m_ioc2.set_tag(std::forward<V>(ioc2_tag));
m_dac.set_tag(std::forward<W>(dac_tag));
m_ldac.set_tag(std::forward<W>(ldac_tag));
m_rdac.set_tag(std::forward<X>(rdac_tag));
}
template <typename T, typename U, typename V, typename W, typename X, typename Y>
hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner
, T &&cpu_tag, U &&scsi_tag, V &&scsi2_tag, W &&ioc2_tag, X &&ldac_tag, Y &&rdac_tag)
: hpc3_device(mconfig, tag, owner
, std::forward<T>(cpu_tag), std::forward<U>(scsi_tag), std::forward<W>(ioc2_tag), std::forward<X>(ldac_tag), std::forward<Y>(rdac_tag))
{
m_wd33c93_2.set_tag(std::forward<V>(scsi2_tag));
}
hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
DECLARE_READ32_MEMBER(hd_enet_r);
DECLARE_WRITE32_MEMBER(hd_enet_w);
DECLARE_READ32_MEMBER(hd0_r);
DECLARE_WRITE32_MEMBER(hd0_w);
template <uint32_t index> DECLARE_READ32_MEMBER(hd_r);
template <uint32_t index> DECLARE_WRITE32_MEMBER(hd_w);
DECLARE_READ32_MEMBER(pbus4_r);
DECLARE_WRITE32_MEMBER(pbus4_w);
DECLARE_READ32_MEMBER(pbusdma_r);
@ -42,15 +53,20 @@ public:
DECLARE_READ32_MEMBER(unkpbus0_r);
DECLARE_WRITE32_MEMBER(unkpbus0_w);
DECLARE_WRITE_LINE_MEMBER(scsi_irq);
DECLARE_READ32_MEMBER(dma_config_r);
DECLARE_WRITE32_MEMBER(dma_config_w);
DECLARE_READ32_MEMBER(pio_config_r);
DECLARE_WRITE32_MEMBER(pio_config_w);
TIMER_CALLBACK_MEMBER(do_dma);
DECLARE_WRITE_LINE_MEMBER(scsi_irq);
protected:
void device_start() override;
void device_reset() override;
void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
void do_pbus_dma(uint32_t channel);
void dump_chain(address_space &space, uint32_t ch_base);
void fetch_chain(address_space &space);
bool decrement_chain(address_space &space);
@ -59,11 +75,14 @@ protected:
struct pbus_dma_t
{
uint8_t m_active;
bool m_active;
uint32_t m_cur_ptr;
uint32_t m_desc_ptr;
uint32_t m_desc_flags;
uint32_t m_next_ptr;
uint32_t m_words_left;
uint32_t m_bytes_left;
uint32_t m_config;
emu_timer *m_timer;
};
enum
@ -99,10 +118,11 @@ protected:
required_device<mips3_device> m_maincpu;
required_device<wd33c93_device> m_wd33c93;
optional_device<wd33c93_device> m_wd33c93_2;
required_device<ioc2_device> m_ioc2;
required_device<dac_16bit_r2r_twos_complement_device> m_dac;
required_device<dac_16bit_r2r_twos_complement_device> m_ldac;
required_device<dac_16bit_r2r_twos_complement_device> m_rdac;
required_shared_ptr<uint32_t> m_mainram;
required_shared_ptr<uint32_t> m_unkpbus0;
uint32_t m_enetr_nbdp;
uint32_t m_enetr_cbp;
@ -115,10 +135,8 @@ protected:
uint32_t m_scsi0_byte_count;
uint32_t m_scsi0_next_addr;
uint32_t m_scsi0_dma_ctrl;
pbus_dma_t m_pbus_dma;
emu_timer *m_pbus_dma_timer;
uint8_t m_dma_buffer[4096];
pbus_dma_t m_pbus_dma[8];
uint32_t m_pio_config[10];
inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... );
};

251
src/mame/machine/ioc2.cpp
View File

@ -10,6 +10,23 @@
#include "bus/rs232/rs232.h"
#include "machine/ioc2.h"
#define LOG_PI1 (1 << 0)
#define LOG_SERIAL (1 << 1)
#define LOG_MOUSEKBD (1 << 2)
#define LOG_PANEL (1 << 3)
#define LOG_SYSID (1 << 4)
#define LOG_READ (1 << 5)
#define LOG_DMA_SEL (1 << 6)
#define LOG_RESET (1 << 7)
#define LOG_WRITE (1 << 8)
#define LOG_INT3 (1 << 9)
#define LOG_PIT (1 << 10)
#define LOG_ALL (LOG_PI1 | LOG_SERIAL | LOG_MOUSEKBD | LOG_PANEL | LOG_SYSID | LOG_READ | LOG_DMA_SEL | LOG_RESET | LOG_WRITE | LOG_INT3 | LOG_PIT)
#define LOG_DEFAULT (LOG_ALL & ~(LOG_SYSID | LOG_MOUSEKBD))
#define VERBOSE (0)
#include "logmacro.h"
/*static*/ char const *const ioc2_device::SCC_TAG = "scc";
/*static*/ char const *const ioc2_device::PI1_TAG = "pi1";
/*static*/ char const *const ioc2_device::KBDC_TAG = "kbdc";
@ -79,6 +96,8 @@ void ioc2_device::device_add_mconfig(machine_config &config)
m_pit->set_clk<0>(1000000);
m_pit->set_clk<1>(1000000);
m_pit->set_clk<2>(1000000);
m_pit->out_handler<0>().set(FUNC(ioc2_device::timer0_int));
m_pit->out_handler<1>().set(FUNC(ioc2_device::timer1_int));
m_pit->out_handler<2>().set(m_kbdc, FUNC(kbdc8042_device::write_out2));
}
@ -105,7 +124,6 @@ ioc2_device::ioc2_device(const machine_config &mconfig, device_type type, const
, m_int3_map_mask0_reg(0)
, m_int3_map_mask1_reg(0)
, m_int3_map_pol_reg(0)
, m_int3_timer_clear_reg(0)
, m_int3_err_status_reg(0)
, m_par_read_cnt(0)
, m_par_cntl(0)
@ -114,7 +132,27 @@ ioc2_device::ioc2_device(const machine_config &mconfig, device_type type, const
void ioc2_device::device_start()
{
m_front_panel_reg = FRONT_PANEL_POWER_STATE;
save_item(NAME(m_par_read_cnt));
save_item(NAME(m_par_cntl));
save_item(NAME(m_gen_ctrl_select_reg));
save_item(NAME(m_gen_ctrl_reg));
save_item(NAME(m_front_panel_reg));
save_item(NAME(m_read_reg));
save_item(NAME(m_dma_sel));
save_item(NAME(m_reset_reg));
save_item(NAME(m_write_reg));
save_item(NAME(m_int3_local0_status_reg));
save_item(NAME(m_int3_local0_mask_reg));
save_item(NAME(m_int3_local1_status_reg));
save_item(NAME(m_int3_local1_mask_reg));
save_item(NAME(m_int3_map_status_reg));
save_item(NAME(m_int3_map_mask0_reg));
save_item(NAME(m_int3_map_mask1_reg));
save_item(NAME(m_int3_map_pol_reg));
save_item(NAME(m_int3_err_status_reg));
}
void ioc2_device::device_reset()
@ -139,7 +177,6 @@ void ioc2_device::device_reset()
m_int3_map_mask0_reg = 0;
m_int3_map_mask1_reg = 0;
m_int3_map_pol_reg = 0;
m_int3_timer_clear_reg = 0;
m_int3_err_status_reg = 0;
}
@ -165,41 +202,112 @@ void ioc2_device::lower_local1_irq(uint8_t source_mask)
m_int3_local1_status_reg &= ~source_mask;
}
READ32_MEMBER( ioc2_device::read )
WRITE_LINE_MEMBER(ioc2_device::timer0_int)
{
m_maincpu->set_input_line(MIPS3_IRQ2, ASSERT_LINE);
}
WRITE_LINE_MEMBER(ioc2_device::timer1_int)
{
m_maincpu->set_input_line(MIPS3_IRQ3, ASSERT_LINE);
}
READ32_MEMBER(ioc2_device::read)
{
switch (offset)
{
case PI1_DATA_REG:
{
const uint8_t data = m_pi1->read(space, offset, 0xff);;
LOGMASKED(LOG_PI1, "%s: Read PI1 Data Register: %02x\n", machine().describe_context(), data);
return data;
}
case PI1_CTRL_REG:
{
const uint8_t data = m_pi1->read(space, offset, 0xff);
LOGMASKED(LOG_PI1, "%s: Read PI1 Control Register: %02x\n", machine().describe_context(), data);
return data;
}
case PI1_STATUS_REG:
return m_pi1->read(space, offset, 0xff);
{
const uint8_t data = m_pi1->read(space, offset, 0xff);
LOGMASKED(LOG_PI1, "%s: Read PI1 Status Register: %02x\n", machine().describe_context(), data);
return data;
}
case PI1_DMA_CTRL_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 DMA Control Register: 00\n", machine().describe_context());
return 0;
case PI1_INT_STATUS_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 Interrupt Status Register: 00\n", machine().describe_context());
return 0;
case PI1_INT_MASK_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 Interrupt Mask Register: 00\n", machine().describe_context());
return 0;
case PI1_TIMER1_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 Timer1 Register: 00\n", machine().describe_context());
return 0;
case PI1_TIMER2_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 Timer2 Register: 00\n", machine().describe_context());
return 0;
case PI1_TIMER3_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 Timer3 Register: 00\n", machine().describe_context());
return 0;
case PI1_TIMER4_REG:
LOGMASKED(LOG_PI1, "%s: Read PI1 Timer4 Register: 00\n", machine().describe_context());
return 0;
case SERIAL1_CMD_REG:
{
const uint8_t data = m_scc->ba_cd_r(space, (offset - SERIAL1_CMD_REG) ^ 3);
LOGMASKED(LOG_SERIAL, "%s: Read Serial 1 Command Register: %02x\n", machine().describe_context(), data);
return data;
}
case SERIAL1_DATA_REG:
{
const uint8_t data = m_scc->ba_cd_r(space, (offset - SERIAL1_CMD_REG) ^ 3);
LOGMASKED(LOG_SERIAL, "%s: Read Serial 1 Data Register: %02x\n", machine().describe_context(), data);
return data;
}
case SERIAL2_CMD_REG:
{
const uint8_t data = m_scc->ba_cd_r(space, (offset - SERIAL1_CMD_REG) ^ 3);
LOGMASKED(LOG_SERIAL, "%s: Read Serial 2 Command Register: %02x\n", machine().describe_context(), data);
return data;
}
case SERIAL2_DATA_REG:
return m_scc->ba_cd_r(space, (offset - SERIAL1_CMD_REG) ^ 3);
{
const uint8_t data = m_scc->ba_cd_r(space, (offset - SERIAL1_CMD_REG) ^ 3);
LOGMASKED(LOG_SERIAL, "%s: Read Serial 2 Data Register: %02x\n", machine().describe_context(), data);
return data;
}
case KBD_MOUSE_REGS1:
{
const uint8_t data = m_kbdc->data_r(space, (offset - KBD_MOUSE_REGS1) * 4);
LOGMASKED(LOG_MOUSEKBD, "%s: Read Keyboard/Mouse Register 1: %02x\n", machine().describe_context(), data);
return data;
}
case KBD_MOUSE_REGS2:
return m_kbdc->data_r(space, (offset - KBD_MOUSE_REGS1) * 4);
{
const uint8_t data = m_kbdc->data_r(space, (offset - KBD_MOUSE_REGS1) * 4);
LOGMASKED(LOG_MOUSEKBD, "%s: Read Keyboard/Mouse Register 2: %02x\n", machine().describe_context(), data);
return data;
}
case PANEL_REG:
LOGMASKED(LOG_PANEL, "%s: Read Front Panel Register: %02x\n", machine().describe_context(), m_front_panel_reg);
return m_front_panel_reg;
case SYSID_REG:
return get_system_id();
{
const uint8_t data = get_system_id();
LOGMASKED(LOG_SYSID, "%s: Read System ID Register: %02x\n", machine().describe_context(), data);
return data;
}
case READ_REG:
LOGMASKED(LOG_READ, "%s: Read Read Register: %02x\n", machine().describe_context(), m_read_reg);
return m_read_reg;
case DMA_SEL_REG:
@ -208,9 +316,11 @@ READ32_MEMBER( ioc2_device::read )
// 2 RW Parallel Port DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [this makes sense. -ed.]
// 1 RW ISDN Channel B DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [is this a copy/paste error? perhaps "Parallel Port" should be "ISDN Channel B"?]
// 0 RW [same text as above. Another copy/paste error, maybe? Should be channel A, with the bit selecting DMA channel 0/1 for ISDN channel A, the and the same for ISDN channel B in bit 1?]
LOGMASKED(LOG_DMA_SEL, "%s: Read DMA Select Register: %02x\n", machine().describe_context(), m_dma_sel);
return m_dma_sel;
case RESET_REG:
LOGMASKED(LOG_RESET, "%s: Read Reset Register: %02x\n", machine().describe_context(), m_reset_reg);
return m_reset_reg;
case WRITE_REG:
@ -225,43 +335,93 @@ READ32_MEMBER( ioc2_device::read )
// 2 RW Ethernet Port Select. Set low for TP, high for AUI. This setting is only used when Auto Select is in manual mode. Cleared at reset.
// 1 RW Ethernet UTP/STP select. Set low to select 150 ohm termination fro shielded TP (default), set high to select 100 ohm termination for unshielded TP. Cleared at reset.
// 0 RW Ethernet Normal Threshold (NTH) select. Set low to select the normal TP squelch threshold (default), high to reduce threshold by 4.5 dB (set low when reset).
LOGMASKED(LOG_WRITE, "%s: Read Write Register: %02x\n", machine().describe_context(), m_write_reg);
return m_write_reg;
case INT3_LOCAL0_STATUS_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Local0 Status Register: %02x\n", machine().describe_context(), m_int3_local0_status_reg);
return m_int3_local0_status_reg;
}
case INT3_LOCAL0_MASK_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), m_int3_local0_mask_reg);
return m_int3_local0_mask_reg;
}
case INT3_LOCAL1_STATUS_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Local1 Status Register: %02x\n", machine().describe_context(), m_int3_local1_status_reg);
return m_int3_local1_status_reg;
}
case INT3_LOCAL1_MASK_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), m_int3_local1_mask_reg);
return m_int3_local1_mask_reg;
}
case INT3_MAP_STATUS_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Status Register: %02x\n", machine().describe_context(), m_int3_map_status_reg);
return m_int3_map_status_reg;
}
case INT3_MAP_MASK0_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), m_int3_map_mask0_reg);
return m_int3_map_mask0_reg;
}
case INT3_MAP_MASK1_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), m_int3_map_mask1_reg);
return m_int3_map_mask1_reg;
}
case INT3_MAP_POLARITY_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Polarity Register: %02x\n", machine().describe_context(), m_int3_map_pol_reg);
return m_int3_map_pol_reg;
}
case INT3_TIMER_CLEAR_REG:
return m_int3_timer_clear_reg;
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Timer Clear (ignored)\n", machine().describe_context());
return 0;
}
case INT3_ERROR_STATUS_REG:
{
LOGMASKED(LOG_INT3, "%s: Read Interrupt Error Status Register: %02x\n", machine().describe_context(), m_int3_err_status_reg);
return m_int3_err_status_reg;
}
case TIMER_COUNT0_REG:
{
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
LOGMASKED(LOG_PIT, "%s: Read Timer Count0 Register: %02x\n", machine().describe_context(), data);
return data;
}
case TIMER_COUNT1_REG:
{
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
LOGMASKED(LOG_PIT, "%s: Read Timer Count1 Register: %02x\n", machine().describe_context(), data);
return data;
}
case TIMER_COUNT2_REG:
{
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
LOGMASKED(LOG_PIT, "%s: Read Timer Count2 Register: %02x\n", machine().describe_context(), data);
return data;
}
case TIMER_CONTROL_REG:
return m_pit->read(offset - TIMER_COUNT0_REG);
{
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
LOGMASKED(LOG_PIT, "%s: Read Timer Control Register: %02x\n", machine().describe_context(), data);
return data;
}
}
return 0;
@ -272,33 +432,68 @@ WRITE32_MEMBER( ioc2_device::write )
switch (offset)
{
case PI1_DATA_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Data Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pi1->write(space, offset, data & 0xff, 0xff);
return;
case PI1_CTRL_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Control Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pi1->write(space, offset, data & 0xff, 0xff);
return;
case PI1_STATUS_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Status Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pi1->write(space, offset, data & 0xff, 0xff);
return;
case PI1_DMA_CTRL_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 DMA Control Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case PI1_INT_STATUS_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Interrupt Status Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case PI1_INT_MASK_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Interrupt Mask Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case PI1_TIMER1_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer1 Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case PI1_TIMER2_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer2 Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case PI1_TIMER3_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer3 Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case PI1_TIMER4_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer4 Register: %02x\n", machine().describe_context(), (uint8_t)data);
return;
case SERIAL1_CMD_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 1 Command Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_scc->ba_cd_w(space, (offset - SERIAL1_CMD_REG) ^ 3, data & 0xff);
return;
case SERIAL1_DATA_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 1 Data Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_scc->ba_cd_w(space, (offset - SERIAL1_CMD_REG) ^ 3, data & 0xff);
return;
case SERIAL2_CMD_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 2 Command Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_scc->ba_cd_w(space, (offset - SERIAL1_CMD_REG) ^ 3, data & 0xff);
return;
case SERIAL2_DATA_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 2 Data Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_scc->ba_cd_w(space, (offset - SERIAL1_CMD_REG) ^ 3, data & 0xff);
return;
case KBD_MOUSE_REGS1:
LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 1: %02x\n", machine().describe_context(), (uint8_t)data);
m_kbdc->data_w(space, (offset - KBD_MOUSE_REGS1) * 4, data & 0xff);
return;
case KBD_MOUSE_REGS2:
LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 2: %02x\n", machine().describe_context(), (uint8_t)data);
m_kbdc->data_w(space, (offset - KBD_MOUSE_REGS1) * 4, data & 0xff);
return;
case PANEL_REG:
LOGMASKED(LOG_PANEL, "%s: Write Front Panel Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_front_panel_reg &= ~(data & (FRONT_PANEL_VOL_UP_INT | FRONT_PANEL_VOL_DOWN_INT | FRONT_PANEL_POWER_BUTTON_INT));
return;
@ -310,14 +505,15 @@ WRITE32_MEMBER( ioc2_device::write )
// 2 RW Parallel Port DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [this makes sense. -ed.]
// 1 RW ISDN Channel B DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [is this a copy/paste error? perhaps "Parallel Port" should be "ISDN Channel B"?]
// 0 RW [same text as above. Another copy/paste error, maybe? Should be channel A, with the bit selecting DMA channel 0/1 for ISDN channel A, the and the same for ISDN channel B in bit 1?]
LOGMASKED(LOG_DMA_SEL, "%s: Write DMA Select Register: %02x\n", machine().describe_context(), (uint8_t)data);
uint8_t old = m_dma_sel;
m_dma_sel = data;
uint8_t diff = old ^ m_dma_sel;
if (diff & DMA_SEL_CLOCK_SEL_MASK)
uint8_t changed = old ^ m_dma_sel;
if (changed & DMA_SEL_CLOCK_SEL_MASK)
{
if (diff & DMA_SEL_CLOCK_SEL_EXT)
if (changed & DMA_SEL_CLOCK_SEL_EXT)
{
logerror("%s: External clock select %sselected\n", machine().describe_context(), (old & DMA_SEL_CLOCK_SEL_EXT) != 0 ? "de" : "");
LOGMASKED(LOG_DMA_SEL, "%s: External clock select %sselected\n", machine().describe_context(), (old & DMA_SEL_CLOCK_SEL_EXT) != 0 ? "de" : "");
// TODO: verify the external Rx/Tx clock, is it fixed or programmable?
}
}
@ -326,10 +522,12 @@ WRITE32_MEMBER( ioc2_device::write )
}
case RESET_REG:
LOGMASKED(LOG_RESET, "%s: Write Reset Register: %02x\n", machine().describe_context(), (uint8_t)data);
handle_reset_reg_write(data);
return;
case WRITE_REG:
LOGMASKED(LOG_RESET, "%s: Write Write Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_write_reg = data;
return;
@ -342,6 +540,7 @@ WRITE32_MEMBER( ioc2_device::write )
case INT3_LOCAL0_MASK_REG:
{
LOGMASKED(LOG_INT3, "%s: Write Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data);
uint8_t old = m_int3_local0_mask_reg;
m_int3_local0_mask_reg = data;
bool old_line = (old & m_int3_local0_status_reg) != 0;
@ -356,6 +555,7 @@ WRITE32_MEMBER( ioc2_device::write )
case INT3_LOCAL1_MASK_REG:
{
LOGMASKED(LOG_INT3, "%s: Write Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data);
uint8_t old = m_int3_local1_mask_reg;
m_int3_local1_mask_reg = data;
bool old_line = (old & m_int3_local1_status_reg) != 0;
@ -370,23 +570,46 @@ WRITE32_MEMBER( ioc2_device::write )
case INT3_MAP_MASK0_REG:
// TODO: Implement mappable interrupts
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_int3_map_mask0_reg = data;
return;
case INT3_MAP_MASK1_REG:
// TODO: Implement mappable interrupts
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_int3_map_mask1_reg = data;
return;
case INT3_MAP_POLARITY_REG:
// TODO: Mappable interrupt polarity select
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Polarity Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_int3_map_pol_reg = data;
return;
case INT3_TIMER_CLEAR_REG:
{
LOGMASKED(LOG_INT3, "%s: Write Interrupt Timer Clear Register: %02x\n", machine().describe_context(), (uint8_t)data);
if (BIT(data, 0))
m_maincpu->set_input_line(MIPS3_IRQ2, CLEAR_LINE);
if (BIT(data, 1))
m_maincpu->set_input_line(MIPS3_IRQ3, CLEAR_LINE);
return;
}
case TIMER_COUNT0_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Count0 Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
return;
case TIMER_COUNT1_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Count1 Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
return;
case TIMER_COUNT2_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Count2 Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
return;
case TIMER_CONTROL_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Control Register: %02x\n", machine().describe_context(), (uint8_t)data);
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
return;
}

4
src/mame/machine/ioc2.h
View File

@ -67,6 +67,9 @@ protected:
virtual void device_add_mconfig(machine_config &config) override;
virtual ioport_constructor device_input_ports() const override;
DECLARE_WRITE_LINE_MEMBER(timer0_int);
DECLARE_WRITE_LINE_MEMBER(timer1_int);
enum
{
PI1_DATA_REG = 0x00/4,
@ -160,7 +163,6 @@ protected:
uint8_t m_int3_map_mask0_reg;
uint8_t m_int3_map_mask1_reg;
uint8_t m_int3_map_pol_reg;
uint8_t m_int3_timer_clear_reg;
uint8_t m_int3_err_status_reg;
uint32_t m_par_read_cnt;

714
src/mame/machine/sgi.cpp
View File

@ -11,69 +11,65 @@
#include "emu.h"
#include "sgi.h"
#define VERBOSE_LEVEL ( 2 )
#define LOG_READS (1 << 0)
#define LOG_WRITES (1 << 1)
#define LOG_WATCHDOG (1 << 2)
#define LOG_MEMCFG (1 << 3)
#define LOG_UNKNOWN (1 << 4)
#define LOG_DEFAULT (LOG_READS | LOG_WRITES | LOG_WATCHDOG)
#if 0
static inline void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ... )
{
if( VERBOSE_LEVEL >= n_level )
{
va_list v;
char buf[ 32768 ];
va_start( v, s_fmt );
vsprintf( buf, s_fmt, v );
va_end( v );
logerror( "%s: %s", machine.describe_context(), buf );
}
}
#endif
#define VERBOSE (0)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(SGI_MC, sgi_mc_device, "sgi_mc", "SGI Memory Controller")
sgi_mc_device::sgi_mc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SGI_MC, tag, owner, clock),
m_tUpdateTimer(nullptr),
m_nCPUControl0(0),
m_nCPUControl1(0),
m_nWatchdog(0),
m_nSysID(0),
m_nRPSSDiv(0),
m_nRefCntPreload(0),
m_nRefCnt(0),
m_nGIO64ArbParam(0),
m_nArbCPUTime(0),
m_nArbBurstTime(0),
m_nMemCfg0(0),
m_nMemCfg1(0),
m_nCPUMemAccCfg(0),
m_nGIOMemAccCfg(0),
m_nCPUErrorAddr(0),
m_nCPUErrorStatus(0),
m_nGIOErrorAddr(0),
m_nGIOErrorStatus(0),
m_nSysSemaphore(0),
m_nGIOLock(0),
m_nEISALock(0),
m_nGIO64TransMask(0),
m_nGIO64Subst(0),
m_nDMAIntrCause(0),
m_nDMAControl(0),
m_nDMATLBEntry0Hi(0),
m_nDMATLBEntry0Lo(0),
m_nDMATLBEntry1Hi(0),
m_nDMATLBEntry1Lo(0),
m_nDMATLBEntry2Hi(0),
m_nDMATLBEntry2Lo(0),
m_nDMATLBEntry3Hi(0),
m_nDMATLBEntry3Lo(0),
m_nRPSSCounter(0),
m_nDMAMemAddr(0),
m_nDMALineCntWidth(0),
m_nDMALineZoomStride(0),
m_nDMAGIO64Addr(0),
m_nDMAMode(0),
m_nDMAZoomByteCnt(0),
m_nDMARunning(0)
m_rpss_timer(nullptr),
m_cpu_control0(0),
m_cpu_control1(0),
m_watchdog(0),
m_sys_id(0),
m_rpss_divider(0),
m_refcnt_preload(0),
m_refcnt(0),
m_gio64_arb_param(0),
m_arb_cpu_time(0),
m_arb_burst_time(0),
m_mem_config0(0),
m_mem_config1(0),
m_cpu_mem_access_config(0),
m_gio_mem_access_config(0),
m_cpu_error_addr(0),
m_cpu_error_status(0),
m_gio_error_addr(0),
m_gio_error_status(0),
m_sys_semaphore(0),
m_gio_lock(0),
m_eisa_lock(0),
m_gio64_translate_mask(0),
m_gio64_substitute_bits(0),
m_dma_int_cause(0),
m_dma_control(0),
m_dma_tlb_entry0_hi(0),
m_dma_tlb_entry0_lo(0),
m_dma_tlb_entry1_hi(0),
m_dma_tlb_entry1_lo(0),
m_dma_tlb_entry2_hi(0),
m_dma_tlb_entry2_lo(0),
m_dma_tlb_entry3_hi(0),
m_dma_tlb_entry3_lo(0),
m_rpss_counter(0),
m_dma_mem_addr(0),
m_dma_size(0),
m_dma_stride(0),
m_dma_gio64_addr(0),
m_dma_mode(0),
m_dma_count(0),
m_dma_running(0),
m_rpss_divide_counter(0),
m_rpss_divide_count(0),
m_rpss_increment(0)
{
}
@ -86,477 +82,449 @@ void sgi_mc_device::device_start()
// if Indigo2, ID appropriately
if (!strcmp(machine().system().name, "ip244415"))
{
m_nSysID = 0x11; // rev. B MC, EISA bus present
m_sys_id = 0x11; // rev. B MC, EISA bus present
}
timer_init();
m_rpss_timer = timer_alloc(TIMER_RPSS);
m_rpss_timer->adjust(attotime::never);
save_item(NAME(m_nCPUControl0));
save_item(NAME(m_nCPUControl1));
save_item(NAME(m_nWatchdog));
save_item(NAME(m_nSysID));
save_item(NAME(m_nRPSSDiv));
save_item(NAME(m_nRefCntPreload));
save_item(NAME(m_nRefCnt));
save_item(NAME(m_nGIO64ArbParam));
save_item(NAME(m_nArbCPUTime));
save_item(NAME(m_nArbBurstTime));
save_item(NAME(m_nMemCfg0));
save_item(NAME(m_nMemCfg1));
save_item(NAME(m_nCPUMemAccCfg));
save_item(NAME(m_nGIOMemAccCfg));
save_item(NAME(m_nCPUErrorAddr));
save_item(NAME(m_nCPUErrorStatus));
save_item(NAME(m_nGIOErrorAddr));
save_item(NAME(m_nGIOErrorStatus));
save_item(NAME(m_nSysSemaphore));
save_item(NAME(m_nGIOLock));
save_item(NAME(m_nEISALock));
save_item(NAME(m_nGIO64TransMask));
save_item(NAME(m_nGIO64Subst));
save_item(NAME(m_nDMAIntrCause));
save_item(NAME(m_nDMAControl));
save_item(NAME(m_nDMATLBEntry0Hi));
save_item(NAME(m_nDMATLBEntry0Lo));
save_item(NAME(m_nDMATLBEntry1Hi));
save_item(NAME(m_nDMATLBEntry1Lo));
save_item(NAME(m_nDMATLBEntry2Hi));
save_item(NAME(m_nDMATLBEntry2Lo));
save_item(NAME(m_nDMATLBEntry3Hi));
save_item(NAME(m_nDMATLBEntry3Lo));
save_item(NAME(m_nRPSSCounter));
save_item(NAME(m_nDMAMemAddr));
save_item(NAME(m_nDMALineCntWidth));
save_item(NAME(m_nDMALineZoomStride));
save_item(NAME(m_nDMAGIO64Addr));
save_item(NAME(m_nDMAMode));
save_item(NAME(m_nDMAZoomByteCnt));
save_item(NAME(m_nDMARunning));
save_item(NAME(m_cpu_control0));
save_item(NAME(m_cpu_control1));
save_item(NAME(m_watchdog));
save_item(NAME(m_sys_id));
save_item(NAME(m_rpss_divider));
save_item(NAME(m_refcnt_preload));
save_item(NAME(m_refcnt));
save_item(NAME(m_gio64_arb_param));
save_item(NAME(m_arb_cpu_time));
save_item(NAME(m_arb_burst_time));
save_item(NAME(m_mem_config0));
save_item(NAME(m_mem_config1));
save_item(NAME(m_cpu_mem_access_config));
save_item(NAME(m_gio_mem_access_config));
save_item(NAME(m_cpu_error_addr));
save_item(NAME(m_cpu_error_status));
save_item(NAME(m_gio_error_addr));
save_item(NAME(m_gio_error_status));
save_item(NAME(m_sys_semaphore));
save_item(NAME(m_gio_lock));
save_item(NAME(m_eisa_lock));
save_item(NAME(m_gio64_translate_mask));
save_item(NAME(m_gio64_substitute_bits));
save_item(NAME(m_dma_int_cause));
save_item(NAME(m_dma_control));
save_item(NAME(m_dma_tlb_entry0_hi));
save_item(NAME(m_dma_tlb_entry0_lo));
save_item(NAME(m_dma_tlb_entry1_hi));
save_item(NAME(m_dma_tlb_entry1_lo));
save_item(NAME(m_dma_tlb_entry2_hi));
save_item(NAME(m_dma_tlb_entry2_lo));
save_item(NAME(m_dma_tlb_entry3_hi));
save_item(NAME(m_dma_tlb_entry3_lo));
save_item(NAME(m_rpss_counter));
save_item(NAME(m_dma_mem_addr));
save_item(NAME(m_dma_size));
save_item(NAME(m_dma_stride));
save_item(NAME(m_dma_gio64_addr));
save_item(NAME(m_dma_mode));
save_item(NAME(m_dma_count));
save_item(NAME(m_dma_running));
save_item(NAME(m_semaphore));
save_item(NAME(m_rpss_divide_counter));
save_item(NAME(m_rpss_divide_count));
save_item(NAME(m_rpss_increment));
}
READ32_MEMBER( sgi_mc_device::read )
void sgi_mc_device::device_reset()
{
memset(m_semaphore, 0, sizeof(uint32_t) * 16);
m_rpss_timer->adjust(attotime::from_hz(10000000), 0, attotime::from_hz(10000000));
m_rpss_divider = 0x0104;
m_rpss_divide_counter = 4;
m_rpss_divide_count = 4;
m_rpss_increment = 1;
}
READ32_MEMBER(sgi_mc_device::read)
{
offset <<= 2;
switch( offset )
switch (offset & ~4)
{
case 0x0000:
case 0x0004:
//verboselog( machine(), 3, "CPU Control 0 Read: %08x (%08x)\n", m_nCPUControl0, mem_mask );
return m_nCPUControl0;
LOGMASKED(LOG_READS, "%s: CPU Control 0 Read: %08x & %08x\n", machine().describe_context(), m_cpu_control0, mem_mask);
return m_cpu_control0;
case 0x0008:
case 0x000c:
//verboselog( machine(), 2, "CPU Control 1 Read: %08x (%08x)\n", m_nCPUControl1, mem_mask );
return m_nCPUControl1;
LOGMASKED(LOG_READS, "%s: CPU Control 1 Read: %08x & %08x\n", machine().describe_context(), m_cpu_control1, mem_mask);
return m_cpu_control1;
case 0x0010:
case 0x0014:
//verboselog( machine(), 2, "Watchdog Timer Read: %08x (%08x)\n", m_nWatchdog, mem_mask );
return m_nWatchdog;
LOGMASKED(LOG_WATCHDOG, "%s: Watchdog Timer Read: %08x & %08x\n", machine().describe_context(), m_watchdog, mem_mask);
return m_watchdog;
case 0x0018:
case 0x001c:
//verboselog( machine(), 2, "System ID Read: %08x (%08x)\n", m_nSysID, mem_mask );
return m_nSysID;
LOGMASKED(LOG_READS, "%s: System ID Read: %08x & %08x\n", machine().describe_context(), m_sys_id, mem_mask);
return m_sys_id;
case 0x0028:
case 0x002c:
//verboselog( machine(), 2, "RPSS Divider Read: %08x (%08x)\n", m_nRPSSDiv, mem_mask );
return m_nRPSSDiv;
LOGMASKED(LOG_READS, "%s: RPSS Divider Read: %08x & %08x\n", machine().describe_context(), m_rpss_divider, mem_mask);
return m_rpss_divider;
case 0x0030:
case 0x0034:
//verboselog( machine(), 2, "R4000 EEPROM Read\n" );
LOGMASKED(LOG_READS, "%s: R4000 EEPROM Read\n", machine().describe_context());
return 0;
case 0x0040:
case 0x0044:
//verboselog( machine(), 2, "Refresh Count Preload Read: %08x (%08x)\n", m_nRefCntPreload, mem_mask );
return m_nRefCntPreload;
LOGMASKED(LOG_READS, "%s: Refresh Count Preload Read: %08x & %08x\n", machine().describe_context(), m_refcnt_preload, mem_mask);
return m_refcnt_preload;
case 0x0048:
case 0x004c:
//verboselog( machine(), 2, "Refresh Count Read: %08x (%08x)\n", m_nRefCnt, mem_mask );
return m_nRefCnt;
LOGMASKED(LOG_READS, "%s: Refresh Count Read: %08x & %08x\n", machine().describe_context(), m_refcnt, mem_mask);
return m_refcnt;
case 0x0080:
case 0x0084:
//verboselog( machine(), 2, "GIO64 Arbitration Param Read: %08x (%08x)\n", m_nGIO64ArbParam, mem_mask );
return m_nGIO64ArbParam;
LOGMASKED(LOG_READS, "%s: GIO64 Arbitration Param Read: %08x & %08x\n", machine().describe_context(), m_gio64_arb_param, mem_mask);
return m_gio64_arb_param;
case 0x0088:
case 0x008c:
//verboselog( machine(), 2, "Arbiter CPU Time Read: %08x (%08x)\n", m_nArbCPUTime, mem_mask );
return m_nArbCPUTime;
LOGMASKED(LOG_READS, "%s: Arbiter CPU Time Read: %08x & %08x\n", machine().describe_context(), m_arb_cpu_time, mem_mask);
return m_arb_cpu_time;
case 0x0098:
case 0x009c:
//verboselog( machine(), 2, "Arbiter Long Burst Time Read: %08x (%08x)\n", m_nArbBurstTime, mem_mask );
return m_nArbBurstTime;
LOGMASKED(LOG_READS, "%s: Arbiter Long Burst Time Read: %08x & %08x\n", machine().describe_context(), m_arb_burst_time, mem_mask);
return m_arb_burst_time;
case 0x00c0:
case 0x00c4:
//verboselog( machine(), 3, "Memory Configuration Register 0 Read: %08x (%08x)\n", m_nMemCfg0, mem_mask );
return m_nMemCfg0;
LOGMASKED(LOG_MEMCFG, "%s: Memory Configuration Register 0 Read: %08x & %08x\n", machine().describe_context(), m_mem_config0, mem_mask);
return m_mem_config0;
case 0x00c8:
case 0x00cc:
//verboselog( machine(), 3, "Memory Configuration Register 1 Read: %08x (%08x)\n", m_nMemCfg1, mem_mask );
return m_nMemCfg1;
LOGMASKED(LOG_MEMCFG, "%s: Memory Configuration Register 1 Read: %08x & %08x\n", machine().describe_context(), m_mem_config1, mem_mask);
return m_mem_config1;
case 0x00d0:
case 0x00d4:
//verboselog( machine(), 2, "CPU Memory Access Config Params Read: %08x (%08x)\n", m_nCPUMemAccCfg, mem_mask );
return m_nCPUMemAccCfg;
LOGMASKED(LOG_READS, "%s: CPU Memory Access Config Params Read: %08x & %08x\n", machine().describe_context(), m_cpu_mem_access_config, mem_mask);
return m_cpu_mem_access_config;
case 0x00d8:
case 0x00dc:
//verboselog( machine(), 2, "GIO Memory Access Config Params Read: %08x (%08x)\n", m_nGIOMemAccCfg, mem_mask );
return m_nGIOMemAccCfg;
LOGMASKED(LOG_READS, "%s: GIO Memory Access Config Params Read: %08x & %08x\n", machine().describe_context(), m_gio_mem_access_config, mem_mask);
return m_gio_mem_access_config;
case 0x00e0:
case 0x00e4:
//verboselog( machine(), 2, "CPU Error Address Read: %08x (%08x)\n", m_nCPUErrorAddr, mem_mask );
return m_nCPUErrorAddr;
LOGMASKED(LOG_READS, "%s: CPU Error Address Read: %08x & %08x\n", machine().describe_context(), m_cpu_error_addr, mem_mask);
return m_cpu_error_addr;
case 0x00e8:
case 0x00ec:
//verboselog( machine(), 2, "CPU Error Status Read: %08x (%08x)\n", m_nCPUErrorStatus, mem_mask );
return m_nCPUErrorStatus;
LOGMASKED(LOG_READS, "%s: CPU Error Status Read: %08x & %08x\n", machine().describe_context(), m_cpu_error_status, mem_mask);
return m_cpu_error_status;
case 0x00f0:
case 0x00f4:
//verboselog( machine(), 2, "GIO Error Address Read: %08x (%08x)\n", m_nGIOErrorAddr, mem_mask );
return m_nGIOErrorAddr;
LOGMASKED(LOG_READS, "%s: GIO Error Address Read: %08x & %08x\n", machine().describe_context(), m_gio_error_addr, mem_mask);
return m_gio_error_addr;
case 0x00f8:
case 0x00fc:
//verboselog( machine(), 2, "GIO Error Status Read: %08x (%08x)\n", m_nGIOErrorStatus, mem_mask );
return m_nGIOErrorStatus;
LOGMASKED(LOG_READS, "%s: GIO Error Status Read: %08x & %08x\n", machine().describe_context(), m_gio_error_status, mem_mask);
return m_gio_error_status;
case 0x0100:
case 0x0104:
//verboselog( machine(), 2, "System Semaphore Read: %08x (%08x)\n", m_nSysSemaphore, mem_mask );
return m_nSysSemaphore;
LOGMASKED(LOG_READS, "%s: System Semaphore Read: %08x & %08x\n", machine().describe_context(), m_sys_semaphore, mem_mask);
return m_sys_semaphore;
case 0x0108:
case 0x010c:
//verboselog( machine(), 2, "GIO Lock Read: %08x (%08x)\n", m_nGIOLock, mem_mask );
return m_nGIOLock;
LOGMASKED(LOG_READS, "%s: GIO Lock Read: %08x & %08x\n", machine().describe_context(), m_gio_lock, mem_mask);
return m_gio_lock;
case 0x0110:
case 0x0114:
//verboselog( machine(), 2, "EISA Lock Read: %08x (%08x)\n", m_nEISALock, mem_mask );
return m_nEISALock;
LOGMASKED(LOG_READS, "%s: EISA Lock Read: %08x & %08x\n", machine().describe_context(), m_eisa_lock, mem_mask);
return m_eisa_lock;
case 0x0150:
case 0x0154:
//verboselog( machine(), 2, "GIO64 Translation Address Mask Read: %08x (%08x)\n", m_nGIO64TransMask, mem_mask );
return m_nGIO64TransMask;
LOGMASKED(LOG_READS, "%s: GIO64 Translation Address Mask Read: %08x & %08x\n", machine().describe_context(), m_gio64_translate_mask, mem_mask);
return m_gio64_translate_mask;
case 0x0158:
case 0x015c:
//verboselog( machine(), 2, "GIO64 Translation Address Substitution Bits Read: %08x (%08x)\n", m_nGIO64Subst, mem_mask );
return m_nGIO64Subst;
LOGMASKED(LOG_READS, "%s: GIO64 Translation Address Substitution Bits Read: %08x & %08x\n", machine().describe_context(), m_gio64_substitute_bits, mem_mask);
return m_gio64_substitute_bits;
case 0x0160:
case 0x0164:
//verboselog( machine(), 2, "DMA Interrupt Cause: %08x (%08x)\n", m_nDMAIntrCause, mem_mask );
return m_nDMAIntrCause;
LOGMASKED(LOG_READS, "%s: DMA Interrupt Cause: %08x & %08x\n", machine().describe_context(), m_dma_int_cause, mem_mask);
return m_dma_int_cause;
case 0x0168:
case 0x016c:
//verboselog( machine(), 2, "DMA Control Read: %08x (%08x)\n", m_nDMAControl, mem_mask );
return m_nDMAControl;
LOGMASKED(LOG_READS, "%s: DMA Control Read: %08x & %08x\n", machine().describe_context(), m_dma_control, mem_mask);
return m_dma_control;
case 0x0180:
case 0x0184:
//verboselog( machine(), 2, "DMA TLB Entry 0 High Read: %08x (%08x)\n", m_nDMATLBEntry0Hi, mem_mask );
return m_nDMATLBEntry0Hi;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 0 High Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry0_hi, mem_mask);
return m_dma_tlb_entry0_hi;
case 0x0188:
case 0x018c:
//verboselog( machine(), 2, "DMA TLB Entry 0 Low Read: %08x (%08x)\n", m_nDMATLBEntry0Lo, mem_mask );
return m_nDMATLBEntry0Lo;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 0 Low Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry0_lo, mem_mask);
return m_dma_tlb_entry0_lo;
case 0x0190:
case 0x0194:
//verboselog( machine(), 2, "DMA TLB Entry 1 High Read: %08x (%08x)\n", m_nDMATLBEntry1Hi, mem_mask );
return m_nDMATLBEntry1Hi;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 1 High Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry1_hi, mem_mask);
return m_dma_tlb_entry1_hi;
case 0x0198:
case 0x019c:
//verboselog( machine(), 2, "DMA TLB Entry 1 Low Read: %08x (%08x)\n", m_nDMATLBEntry1Lo, mem_mask );
return m_nDMATLBEntry1Lo;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 1 Low Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry1_lo, mem_mask);
return m_dma_tlb_entry1_lo;
case 0x01a0:
case 0x01a4:
//verboselog( machine(), 2, "DMA TLB Entry 2 High Read: %08x (%08x)\n", m_nDMATLBEntry2Hi, mem_mask );
return m_nDMATLBEntry2Hi;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 2 High Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry2_hi, mem_mask);
return m_dma_tlb_entry2_hi;
case 0x01a8:
case 0x01ac:
//verboselog( machine(), 2, "DMA TLB Entry 2 Low Read: %08x (%08x)\n", m_nDMATLBEntry2Lo, mem_mask );
return m_nDMATLBEntry2Lo;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 2 Low Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry2_lo, mem_mask);
return m_dma_tlb_entry2_lo;
case 0x01b0:
case 0x01b4:
//verboselog( machine(), 2, "DMA TLB Entry 3 High Read: %08x (%08x)\n", m_nDMATLBEntry3Hi, mem_mask );
return m_nDMATLBEntry3Hi;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 3 High Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry3_hi, mem_mask);
return m_dma_tlb_entry3_hi;
case 0x01b8:
case 0x01bc:
//verboselog( machine(), 2, "DMA TLB Entry 3 Low Read: %08x (%08x)\n", m_nDMATLBEntry3Lo, mem_mask );
return m_nDMATLBEntry3Lo;
LOGMASKED(LOG_READS, "%s: DMA TLB Entry 3 Low Read: %08x & %08x\n", machine().describe_context(), m_dma_tlb_entry3_lo, mem_mask);
return m_dma_tlb_entry3_lo;
case 0x1000:
case 0x1004:
//verboselog( machine(), 2, "RPSS 100ns Counter Read: %08x (%08x)\n", m_nRPSSCounter, mem_mask );
return m_nRPSSCounter;
LOGMASKED(LOG_READS, "%s: RPSS 100ns Counter Read: %08x & %08x\n", machine().describe_context(), m_rpss_counter, mem_mask);
return m_rpss_counter;
case 0x2000:
case 0x2004:
case 0x2008:
case 0x200c:
//verboselog( machine(), 0, "DMA Memory Address Read: %08x (%08x)\n", m_nDMAMemAddr, mem_mask );
return m_nDMAMemAddr;
LOGMASKED(LOG_READS, "%s: DMA Memory Address Read: %08x & %08x\n", machine().describe_context(), m_dma_mem_addr, mem_mask);
return m_dma_mem_addr;
case 0x2010:
case 0x2014:
//verboselog( machine(), 0, "DMA Line Count and Width Read: %08x (%08x)\n", m_nDMALineCntWidth, mem_mask );
return m_nDMALineCntWidth;
LOGMASKED(LOG_READS, "%s: DMA Line Count and Width Read: %08x & %08x\n", machine().describe_context(), m_dma_size, mem_mask);
return m_dma_size;
case 0x2018:
case 0x201c:
//verboselog( machine(), 0, "DMA Line Zoom and Stride Read: %08x (%08x)\n", m_nDMALineZoomStride, mem_mask );
return m_nDMALineZoomStride;
LOGMASKED(LOG_READS, "%s: DMA Line Zoom and Stride Read: %08x & %08x\n", machine().describe_context(), m_dma_stride, mem_mask);
return m_dma_stride;
case 0x2020:
case 0x2024:
case 0x2028:
case 0x202c:
//verboselog( machine(), 0, "DMA GIO64 Address Read: %08x (%08x)\n", m_nDMAGIO64Addr, mem_mask );
return m_nDMAGIO64Addr;
LOGMASKED(LOG_READS, "%s: DMA GIO64 Address Read: %08x & %08x\n", machine().describe_context(), m_dma_gio64_addr, mem_mask);
return m_dma_gio64_addr;
case 0x2030:
case 0x2034:
//verboselog( machine(), 0, "DMA Mode Write: %08x (%08x)\n", m_nDMAMode, mem_mask );
return m_nDMAMode;
LOGMASKED(LOG_READS, "%s: DMA Mode Write: %08x & %08x\n", machine().describe_context(), m_dma_mode, mem_mask);
return m_dma_mode;
case 0x2038:
case 0x203c:
//verboselog( machine(), 0, "DMA Zoom Count Read: %08x (%08x)\n", m_nDMAZoomByteCnt, mem_mask );
return m_nDMAZoomByteCnt;
// case 0x2040:
// case 0x2044:
// //verboselog( machine(), 2, "DMA Start Write: %08x (%08x)\n", data, mem_mask );
// Start DMA
// m_nDMARunning = 1;
// break;
LOGMASKED(LOG_READS, "%s: DMA Zoom Count Read: %08x & %08x\n", machine().describe_context(), m_dma_count, mem_mask);
return m_dma_count;
case 0x2040:
LOGMASKED(LOG_READS, "%s: DMA Start Read\n", machine().describe_context());
return 0;
case 0x2048:
case 0x204c:
//verboselog( machine(), 0, "VDMA Running Read: %08x (%08x)\n", m_nDMARunning, mem_mask );
if( m_nDMARunning == 1 )
LOGMASKED(LOG_READS, "%s: VDMA Running Read: %08x & %08x\n", machine().describe_context(), m_dma_running, mem_mask);
if (m_dma_running == 1)
{
m_nDMARunning = 0;
m_dma_running = 0;
return 0x00000040;
}
else
{
return 0;
}
case 0x10000:
case 0x11000:
case 0x12000:
case 0x13000:
case 0x14000:
case 0x15000:
case 0x16000:
case 0x17000:
case 0x18000:
case 0x19000:
case 0x1a000:
case 0x1b000:
case 0x1c000:
case 0x1d000:
case 0x1e000:
case 0x1f000:
{
const uint32_t data = m_semaphore[(offset - 0x10000) >> 12];
LOGMASKED(LOG_READS, "%s: Semaphore %d Read: %08x & %08x\n", machine().describe_context(), (offset - 0x10000) >> 12, data, mem_mask);
m_semaphore[(offset - 0x10000) >> 12] = 1;
return data;
}
default:
LOGMASKED(LOG_READS | LOG_UNKNOWN, "%s: Unmapped MC read: %08x & %08x\n", machine().describe_context(), 0x1fa00000 + offset, mem_mask);
return 0;
}
//verboselog( machine(), 0, "Unmapped MC read: 0x%08x (%08x)\n", 0x1fa00000 + offset, mem_mask );
return 0;
}
WRITE32_MEMBER( sgi_mc_device::write )
{
offset <<= 2;
switch( offset )
switch (offset & ~4)
{
case 0x0000:
case 0x0004:
//verboselog( machine(), 2, "CPU Control 0 Write: %08x (%08x)\n", data, mem_mask );
m_nCPUControl0 = data;
LOGMASKED(LOG_WRITES, "%s: CPU Control 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_cpu_control0 = data;
break;
case 0x0008:
case 0x000c:
//verboselog( machine(), 2, "CPU Control 1 Write: %08x (%08x)\n", data, mem_mask );
m_nCPUControl1 = data;
LOGMASKED(LOG_WRITES, "%s: CPU Control 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_cpu_control1 = data;
break;
case 0x0010:
case 0x0014:
//verboselog( machine(), 2, "Watchdog Timer Clear" );
m_nWatchdog = 0;
LOGMASKED(LOG_WATCHDOG, "%s: Watchdog Timer Clear\n", machine().describe_context());
m_watchdog = 0;
break;
case 0x0028:
case 0x002c:
//verboselog( machine(), 2, "RPSS Divider Write: %08x (%08x)\n", data, mem_mask );
m_nRPSSDiv = data;
LOGMASKED(LOG_WRITES, "%s: RPSS Divider Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_rpss_divider = data;
m_rpss_divide_count = (int)(m_rpss_divider & 0xff);
m_rpss_divide_counter = m_rpss_divide_count;
m_rpss_increment = (m_rpss_divider >> 8) & 0xff;
break;
case 0x0030:
case 0x0034:
//verboselog( machine(), 2, "R4000 EEPROM Write\n" );
LOGMASKED(LOG_WRITES, "%s: R4000 EEPROM Write: CS:%d, SCK:%d, SO:%d\n", machine().describe_context(),
BIT(data, 1), BIT(data, 2), BIT(data, 3));
break;
case 0x0040:
case 0x0044:
//verboselog( machine(), 2, "Refresh Count Preload Write: %08x (%08x)\n", data, mem_mask );
m_nRefCntPreload = data;
LOGMASKED(LOG_WRITES, "%s: Refresh Count Preload Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_refcnt_preload = data;
break;
case 0x0080:
case 0x0084:
//verboselog( machine(), 2, "GIO64 Arbitration Param Write: %08x (%08x)\n", data, mem_mask );
m_nGIO64ArbParam = data;
LOGMASKED(LOG_WRITES, "%s: GIO64 Arbitration Param Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_gio64_arb_param = data;
break;
case 0x0088:
case 0x008c:
//verboselog( machine(), 3, "Arbiter CPU Time Write: %08x (%08x)\n", data, mem_mask );
m_nArbCPUTime = data;
LOGMASKED(LOG_WRITES, "%s: Arbiter CPU Time Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_arb_cpu_time = data;
break;
case 0x0098:
case 0x009c:
//verboselog( machine(), 3, "Arbiter Long Burst Time Write: %08x (%08x)\n", data, mem_mask );
m_nArbBurstTime = data;
LOGMASKED(LOG_WRITES, "%s: Arbiter Long Burst Time Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_arb_burst_time = data;
break;
case 0x00c0:
case 0x00c4:
//verboselog( machine(), 3, "Memory Configuration Register 0 Write: %08x (%08x)\n", data, mem_mask );
m_nMemCfg0 = data;
LOGMASKED(LOG_MEMCFG, "%s: Memory Configuration Register 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_mem_config0 = data;
break;
case 0x00c8:
case 0x00cc:
//verboselog( machine(), 3, "Memory Configuration Register 1 Write: %08x (%08x)\n", data, mem_mask );
m_nMemCfg1 = data;
LOGMASKED(LOG_MEMCFG, "%s: Memory Configuration Register 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_mem_config1 = data;
break;
case 0x00d0:
case 0x00d4:
//verboselog( machine(), 2, "CPU Memory Access Config Params Write: %08x (%08x)\n", data, mem_mask );
m_nCPUMemAccCfg = data;
LOGMASKED(LOG_WRITES, "%s: CPU Memory Access Config Params Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_cpu_mem_access_config = data;
break;
case 0x00d8:
case 0x00dc:
//verboselog( machine(), 2, "GIO Memory Access Config Params Write: %08x (%08x)\n", data, mem_mask );
m_nGIOMemAccCfg = data;
LOGMASKED(LOG_WRITES, "%s: GIO Memory Access Config Params Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_gio_mem_access_config = data;
break;
case 0x00e8:
case 0x00ec:
//verboselog( machine(), 2, "CPU Error Status Clear\n" );
m_nCPUErrorStatus = 0;
LOGMASKED(LOG_WRITES, "%s: CPU Error Status Clear\n", machine().describe_context());
m_cpu_error_status = 0;
break;
case 0x00f8:
case 0x00fc:
//verboselog( machine(), 2, "GIO Error Status Clear\n" );
m_nGIOErrorStatus = 0;
LOGMASKED(LOG_WRITES, "%s: GIO Error Status Clear\n", machine().describe_context());
m_gio_error_status = 0;
break;
case 0x0100:
case 0x0104:
//verboselog( machine(), 2, "System Semaphore Write: %08x (%08x)\n", data, mem_mask );
m_nSysSemaphore = data;
LOGMASKED(LOG_WRITES, "%s: System Semaphore Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_sys_semaphore = data;
break;
case 0x0108:
case 0x010c:
//verboselog( machine(), 2, "GIO Lock Write: %08x (%08x)\n", data, mem_mask );
m_nGIOLock = data;
LOGMASKED(LOG_WRITES, "%s: GIO Lock Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_gio_lock = data;
break;
case 0x0110:
case 0x0114:
//verboselog( machine(), 2, "EISA Lock Write: %08x (%08x)\n", data, mem_mask );
m_nEISALock = data;
LOGMASKED(LOG_WRITES, "%s: EISA Lock Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_eisa_lock = data;
break;
case 0x0150:
case 0x0154:
//verboselog( machine(), 2, "GIO64 Translation Address Mask Write: %08x (%08x)\n", data, mem_mask );
m_nGIO64TransMask = data;
LOGMASKED(LOG_WRITES, "%s: GIO64 Translation Address Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_gio64_translate_mask = data;
break;
case 0x0158:
case 0x015c:
//verboselog( machine(), 2, "GIO64 Translation Address Substitution Bits Write: %08x (%08x)\n", data, mem_mask );
m_nGIO64Subst = data;
LOGMASKED(LOG_WRITES, "%s: GIO64 Translation Address Substitution Bits Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_gio64_substitute_bits = data;
break;
case 0x0160:
case 0x0164:
//verboselog( machine(), 0, "DMA Interrupt Cause Write: %08x (%08x)\n", data, mem_mask );
m_nDMAIntrCause = data;
LOGMASKED(LOG_WRITES, "%s: DMA Interrupt Cause Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_int_cause = data;
break;
case 0x0168:
case 0x016c:
//verboselog( machine(), 0, "DMA Control Write: %08x (%08x)\n", data, mem_mask );
m_nDMAControl = data;
LOGMASKED(LOG_WRITES, "%s: DMA Control Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_control = data;
break;
case 0x0180:
case 0x0184:
//verboselog( machine(), 0, "DMA TLB Entry 0 High Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry0Hi = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 0 High Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry0_hi = data;
break;
case 0x0188:
case 0x018c:
//verboselog( machine(), 0, "DMA TLB Entry 0 Low Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry0Lo = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 0 Low Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry0_lo = data;
break;
case 0x0190:
case 0x0194:
//verboselog( machine(), 0, "DMA TLB Entry 1 High Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry1Hi = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 1 High Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry1_hi = data;
break;
case 0x0198:
case 0x019c:
//verboselog( machine(), 0, "DMA TLB Entry 1 Low Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry1Lo = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 1 Low Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry1_lo = data;
break;
case 0x01a0:
case 0x01a4:
//verboselog( machine(), 0, "DMA TLB Entry 2 High Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry2Hi = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 2 High Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry2_hi = data;
break;
case 0x01a8:
case 0x01ac:
//verboselog( machine(), 0, "DMA TLB Entry 2 Low Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry2Lo = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 2 Low Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry2_lo = data;
break;
case 0x01b0:
case 0x01b4:
//verboselog( machine(), 0, "DMA TLB Entry 3 High Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry3Hi = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 3 High Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry3_hi = data;
break;
case 0x01b8:
case 0x01bc:
//verboselog( machine(), 0, "DMA TLB Entry 3 Low Write: %08x (%08x)\n", data, mem_mask );
m_nDMATLBEntry3Lo = data;
LOGMASKED(LOG_WRITES, "%s: DMA TLB Entry 3 Low Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_tlb_entry3_lo = data;
break;
case 0x2000:
case 0x2004:
//verboselog( machine(), 0, "DMA Memory Address Write: %08x (%08x)\n", data, mem_mask );
m_nDMAMemAddr = data;
LOGMASKED(LOG_WRITES, "%s: DMA Memory Address Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_mem_addr = data;
break;
case 0x2008:
case 0x200c:
//verboselog( machine(), 0, "DMA Memory Address + Default Params Write: %08x (%08x)\n", data, mem_mask );
m_nDMAMemAddr = data;
LOGMASKED(LOG_WRITES, "%s: DMA Memory Address + Default Params Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_mem_addr = data;
break;
case 0x2010:
case 0x2014:
//verboselog( machine(), 0, "DMA Line Count and Width Write: %08x (%08x)\n", data, mem_mask );
m_nDMALineCntWidth = data;
LOGMASKED(LOG_WRITES, "%s: DMA Line Count and Width Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_size = data;
break;
case 0x2018:
case 0x201c:
//verboselog( machine(), 0, "DMA Line Zoom and Stride Write: %08x (%08x)\n", data, mem_mask );
m_nDMALineZoomStride = data;
LOGMASKED(LOG_WRITES, "%s: DMA Line Zoom and Stride Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_stride = data;
break;
case 0x2020:
case 0x2024:
//verboselog( machine(), 0, "DMA GIO64 Address Write: %08x (%08x)\n", data, mem_mask );
m_nDMAGIO64Addr = data;
LOGMASKED(LOG_WRITES, "%s: DMA GIO64 Address Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_gio64_addr = data;
break;
case 0x2028:
case 0x202c:
//verboselog( machine(), 0, "DMA GIO64 Address Write + Start DMA: %08x (%08x)\n", data, mem_mask );
m_nDMAGIO64Addr = data;
LOGMASKED(LOG_WRITES, "%s: DMA GIO64 Address Write + Start DMA: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_gio64_addr = data;
// Start DMA
m_nDMARunning = 1;
m_dma_running = 1;
break;
case 0x2030:
case 0x2034:
//verboselog( machine(), 0, "DMA Mode Write: %08x (%08x)\n", data, mem_mask );
m_nDMAMode = data;
LOGMASKED(LOG_WRITES, "%s: DMA Mode Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_mode = data;
break;
case 0x2038:
case 0x203c:
//verboselog( machine(), 0, "DMA Zoom Count + Byte Count Write: %08x (%08x)\n", data, mem_mask );
m_nDMAZoomByteCnt = data;
LOGMASKED(LOG_WRITES, "%s: DMA Zoom Count + Byte Count Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_count = data;
break;
case 0x2040:
case 0x2044:
//verboselog( machine(), 0, "DMA Start Write: %08x (%08x)\n", data, mem_mask );
LOGMASKED(LOG_WRITES, "%s: DMA Start Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
// Start DMA
m_nDMARunning = 1;
m_dma_running = 1;
break;
case 0x2070:
case 0x2074:
//verboselog( machine(), 0, "DMA GIO64 Address Write + Default Params Write + Start DMA: %08x (%08x)\n", data, mem_mask );
m_nDMAGIO64Addr = data;
LOGMASKED(LOG_WRITES, "%s: DMA GIO64 Address Write + Default Params Write + Start DMA: %08x & %08x\n", machine().describe_context(), data, mem_mask);
m_dma_gio64_addr = data;
// Start DMA
m_nDMARunning = 1;
m_dma_running = 1;
break;
case 0x10000:
case 0x11000:
case 0x12000:
case 0x13000:
case 0x14000:
case 0x15000:
case 0x16000:
case 0x17000:
case 0x18000:
case 0x19000:
case 0x1a000:
case 0x1b000:
case 0x1c000:
case 0x1d000:
case 0x1e000:
case 0x1f000:
LOGMASKED(LOG_WRITES, "%s: Semaphore %d Write: %08x & %08x\n", machine().describe_context(), (offset - 0x10000) >> 12, data, mem_mask);
m_semaphore[(offset - 0x10000) >> 12] = data & 1;
break;
default:
//verboselog( machine(), 0, "Unmapped MC write: 0x%08x: %08x (%08x)\n", 0x1fa00000 + offset, data, mem_mask );
LOGMASKED(LOG_WRITES | LOG_UNKNOWN, "%s: Unmapped MC write: %08x: %08x & %08x\n", machine().describe_context(), 0x1fa00000 + offset, data, mem_mask);
break;
}
}
void sgi_mc_device::update()
void sgi_mc_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
m_nRPSSCounter += 1000;
}
TIMER_CALLBACK_MEMBER(sgi_mc_device::update_callback)
{
update();
}
void sgi_mc_device::timer_init()
{
m_tUpdateTimer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sgi_mc_device::update_callback), this));
m_tUpdateTimer->adjust(attotime::from_hz(10000), 0, attotime::from_hz(10000));
if (id == TIMER_RPSS)
{
m_rpss_divide_counter--;
if (m_rpss_divide_counter < 0)
{
m_rpss_divide_counter = m_rpss_divide_count;
m_rpss_counter += m_rpss_increment;
}
}
}

92
src/mame/machine/sgi.h
View File

@ -29,51 +29,59 @@ public:
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
static const device_timer_id TIMER_RPSS = 0;
private:
// internal state
emu_timer *m_tUpdateTimer;
uint32_t m_nCPUControl0;
uint32_t m_nCPUControl1;
uint32_t m_nWatchdog;
uint32_t m_nSysID;
uint32_t m_nRPSSDiv;
uint32_t m_nRefCntPreload;
uint32_t m_nRefCnt;
uint32_t m_nGIO64ArbParam;
uint32_t m_nArbCPUTime;
uint32_t m_nArbBurstTime;
uint32_t m_nMemCfg0;
uint32_t m_nMemCfg1;
uint32_t m_nCPUMemAccCfg;
uint32_t m_nGIOMemAccCfg;
uint32_t m_nCPUErrorAddr;
uint32_t m_nCPUErrorStatus;
uint32_t m_nGIOErrorAddr;
uint32_t m_nGIOErrorStatus;
uint32_t m_nSysSemaphore;
uint32_t m_nGIOLock;
uint32_t m_nEISALock;
uint32_t m_nGIO64TransMask;
uint32_t m_nGIO64Subst;
uint32_t m_nDMAIntrCause;
uint32_t m_nDMAControl;
uint32_t m_nDMATLBEntry0Hi;
uint32_t m_nDMATLBEntry0Lo;
uint32_t m_nDMATLBEntry1Hi;
uint32_t m_nDMATLBEntry1Lo;
uint32_t m_nDMATLBEntry2Hi;
uint32_t m_nDMATLBEntry2Lo;
uint32_t m_nDMATLBEntry3Hi;
uint32_t m_nDMATLBEntry3Lo;
uint32_t m_nRPSSCounter;
uint32_t m_nDMAMemAddr;
uint32_t m_nDMALineCntWidth;
uint32_t m_nDMALineZoomStride;
uint32_t m_nDMAGIO64Addr;
uint32_t m_nDMAMode;
uint32_t m_nDMAZoomByteCnt;
uint32_t m_nDMARunning;
emu_timer *m_rpss_timer;
uint32_t m_cpu_control0;
uint32_t m_cpu_control1;
uint32_t m_watchdog;
uint32_t m_sys_id;
uint32_t m_rpss_divider;
uint32_t m_refcnt_preload;
uint32_t m_refcnt;
uint32_t m_gio64_arb_param;
uint32_t m_arb_cpu_time;
uint32_t m_arb_burst_time;
uint32_t m_mem_config0;
uint32_t m_mem_config1;
uint32_t m_cpu_mem_access_config;
uint32_t m_gio_mem_access_config;
uint32_t m_cpu_error_addr;
uint32_t m_cpu_error_status;
uint32_t m_gio_error_addr;
uint32_t m_gio_error_status;
uint32_t m_sys_semaphore;
uint32_t m_gio_lock;
uint32_t m_eisa_lock;
uint32_t m_gio64_translate_mask;
uint32_t m_gio64_substitute_bits;
uint32_t m_dma_int_cause;
uint32_t m_dma_control;
uint32_t m_dma_tlb_entry0_hi;
uint32_t m_dma_tlb_entry0_lo;
uint32_t m_dma_tlb_entry1_hi;
uint32_t m_dma_tlb_entry1_lo;
uint32_t m_dma_tlb_entry2_hi;
uint32_t m_dma_tlb_entry2_lo;
uint32_t m_dma_tlb_entry3_hi;
uint32_t m_dma_tlb_entry3_lo;
uint32_t m_rpss_counter;
uint32_t m_dma_mem_addr;
uint32_t m_dma_size;
uint32_t m_dma_stride;
uint32_t m_dma_gio64_addr;
uint32_t m_dma_mode;
uint32_t m_dma_count;
uint32_t m_dma_running;
uint32_t m_semaphore[16];
int m_rpss_divide_counter;
int m_rpss_divide_count;
uint8_t m_rpss_increment;
void update();
TIMER_CALLBACK_MEMBER(update_callback);

2189
src/mame/video/newport.cpp
View File

File diff suppressed because it is too large Load Diff

236
src/mame/video/newport.h
View File

@ -9,21 +9,29 @@
#pragma once
#include "cpu/mips/mips3.h"
#include "machine/ioc2.h"
class newport_video_device : public device_t
{
public:
newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner)
template <typename T, typename U>
newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&ioc2_tag)
: newport_video_device(mconfig, tag, owner, (uint32_t)0) // TODO: Use actual pixel clock
{
m_maincpu.set_tag(std::forward<T>(cpu_tag));
m_ioc2.set_tag(std::forward<U>(ioc2_tag));
}
newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
DECLARE_READ32_MEMBER( rex3_r );
DECLARE_WRITE32_MEMBER( rex3_w );
DECLARE_READ32_MEMBER(rex3_r);
DECLARE_WRITE32_MEMBER(rex3_w);
uint32_t screen_update(screen_device &device, bitmap_rgb32 &bitmap, const rectangle &cliprect);
DECLARE_WRITE_LINE_MEMBER(vblank_w);
protected:
// device-level overrides
virtual void device_start() override;
@ -44,129 +52,145 @@ private:
DCR_CURSOR_SIZE_64 = 1
};
struct VC2_t
struct vc2_t
{
uint16_t nRegister[0x21];
uint16_t nRAM[0x8000];
uint8_t nRegIdx;
uint16_t nRegData;
uint16_t m_vid_entry;
uint16_t m_cursor_entry;
uint16_t m_cursor_x;
uint16_t m_cursor_y;
uint16_t m_cur_cursor_x;
uint16_t m_did_entry;
uint16_t m_scanline_len;
uint16_t m_ram_addr;
uint16_t m_vt_frame_ptr;
uint16_t m_vt_line_ptr;
uint16_t m_vt_line_run;
uint16_t m_vt_line_count;
uint16_t m_cursor_table_ptr;
uint16_t m_work_cursor_y;
uint16_t m_did_frame_ptr;
uint16_t m_did_line_ptr;
uint16_t m_display_ctrl;
uint16_t m_config;
uint16_t m_ram[0x8000];
uint8_t m_reg_idx;
uint16_t m_reg_data;
};
struct XMAP_t
struct xmap_t
{
uint32_t nRegister[0x08];
uint32_t nModeTable[0x20];
uint32_t m_config;
uint32_t m_revision;
uint32_t m_entries;
uint32_t m_cursor_cmap;
uint32_t m_popup_cmap;
uint32_t m_mode_table_idx;
uint32_t m_mode_table[0x20];
};
struct REX3_t
struct rex3_t
{
uint32_t nDrawMode1;
uint32_t nDrawMode0;
uint32_t nLSMode;
uint32_t nLSPattern;
uint32_t nLSPatSave;
uint32_t nZPattern;
uint32_t nColorBack;
uint32_t nColorVRAM;
uint32_t nAlphaRef;
//uint32_t nStall0;
uint32_t nSMask0X;
uint32_t nSMask0Y;
uint32_t nSetup;
uint32_t nStepZ;
uint32_t nXStart;
uint32_t nYStart;
uint32_t nXEnd;
uint32_t nYEnd;
uint32_t nXSave;
uint32_t nXYMove;
uint32_t nBresD;
uint32_t nBresS1;
uint32_t nBresOctInc1;
uint32_t nBresRndInc2;
uint32_t nBresE1;
uint32_t nBresS2;
uint32_t nAWeight0;
uint32_t nAWeight1;
uint32_t nXStartF;
uint32_t nYStartF;
uint32_t nXEndF;
uint32_t nYEndF;
uint32_t nXStartI;
//uint32_t nYEndF1;
uint32_t nXYStartI;
uint32_t nXYEndI;
uint32_t nXStartEndI;
uint32_t nColorRed;
uint32_t nColorAlpha;
uint32_t nColorGreen;
uint32_t nColorBlue;
uint32_t nSlopeRed;
uint32_t nSlopeAlpha;
uint32_t nSlopeGreen;
uint32_t nSlopeBlue;
uint32_t nWriteMask;
uint32_t nZeroFract;
uint32_t nZeroOverflow;
//uint32_t nColorIndex;
uint32_t nHostDataPortMSW;
uint32_t nHostDataPortLSW;
uint32_t nDCBMode;
uint32_t nDCBRegSelect;
uint32_t nDCBSlvSelect;
uint32_t nDCBDataMSW;
uint32_t nDCBDataLSW;
uint32_t nSMask1X;
uint32_t nSMask1Y;
uint32_t nSMask2X;
uint32_t nSMask2Y;
uint32_t nSMask3X;
uint32_t nSMask3Y;
uint32_t nSMask4X;
uint32_t nSMask4Y;
uint32_t nTopScanline;
uint32_t nXYWin;
uint32_t nClipMode;
uint32_t nConfig;
uint32_t nStatus;
uint8_t nXFerWidth;
#if 0
uint32_t nCurrentX;
uint32_t nCurrentY;
#endif
uint32_t nKludge_SkipLine;
uint32_t m_draw_mode0;
uint32_t m_draw_mode1;
uint32_t m_ls_mode;
uint32_t m_ls_pattern;
uint32_t m_ls_pattern_saved;
uint32_t m_z_pattern;
uint32_t m_color_back;
uint32_t m_color_vram;
uint32_t m_alpha_ref;
uint32_t m_smask0_x;
uint32_t m_smask0_y;
uint32_t m_setup;
uint32_t m_step_z;
uint32_t m_x_start;
uint32_t m_y_start;
uint32_t m_x_end;
uint32_t m_y_end;
uint32_t m_x_save;
uint32_t m_xy_move;
uint32_t m_bres_d;
uint32_t m_bres_s1;
uint32_t m_bres_octant_inc1;
uint32_t m_bres_round_inc2;
uint32_t m_bres_e1;
uint32_t m_bres_s2;
uint32_t m_a_weight0;
uint32_t m_a_weight1;
uint32_t m_x_start_f;
uint32_t m_y_start_f;
uint32_t m_x_end_f;
uint32_t m_y_end_f;
uint32_t m_x_start_i;
uint32_t m_xy_start_i;
uint32_t m_xy_end_i;
uint32_t m_x_start_end_i;
uint32_t m_color_red;
uint32_t m_color_alpha;
uint32_t m_color_green;
uint32_t m_color_blue;
uint32_t m_slope_red;
uint32_t m_slope_alpha;
uint32_t m_slope_green;
uint32_t m_slope_blue;
uint32_t m_write_mask;
uint32_t m_zero_fract;
uint32_t m_zero_overflow;
uint32_t m_host_dataport_msw;
uint32_t m_host_dataport_lsw;
uint32_t m_dcb_mode;
uint32_t m_dcb_reg_select;
uint32_t m_dcb_slave_select;
uint32_t m_dcb_data_msw;
uint32_t m_dcb_data_lsw;
uint32_t m_s_mask1_x;
uint32_t m_s_mask1_y;
uint32_t m_s_mask2_x;
uint32_t m_s_mask2_y;
uint32_t m_s_mask3_x;
uint32_t m_s_mask3_y;
uint32_t m_s_mask4_x;
uint32_t m_s_mask4_y;
uint32_t m_top_scanline;
uint32_t m_xy_window;
uint32_t m_clip_mode;
uint32_t m_config;
uint32_t m_status;
uint8_t m_xfer_width;
uint32_t m_skipline_kludge;
};
struct CMAP_t
struct cmap_t
{
uint16_t nPaletteIndex;
uint32_t nPalette[0x10000];
uint16_t m_palette_idx;
uint32_t m_palette[0x10000];
};
uint32_t get_cursor_pixel(int x, int y);
// internal state
DECLARE_READ32_MEMBER( cmap0_r );
DECLARE_WRITE32_MEMBER( cmap0_w );
DECLARE_READ32_MEMBER( cmap1_r );
DECLARE_READ32_MEMBER( xmap0_r );
DECLARE_WRITE32_MEMBER( xmap0_w );
DECLARE_READ32_MEMBER( xmap1_r );
DECLARE_WRITE32_MEMBER( xmap1_w );
DECLARE_READ32_MEMBER( vc2_r );
DECLARE_WRITE32_MEMBER( vc2_w );
void DoREX3Command();
DECLARE_READ32_MEMBER(cmap0_r);
DECLARE_WRITE32_MEMBER(cmap0_w);
DECLARE_READ32_MEMBER(cmap1_r);
DECLARE_READ32_MEMBER(xmap0_r);
DECLARE_WRITE32_MEMBER(xmap0_w);
DECLARE_READ32_MEMBER(xmap1_r);
DECLARE_WRITE32_MEMBER(xmap1_w);
DECLARE_READ32_MEMBER(vc2_r);
DECLARE_WRITE32_MEMBER(vc2_w);
void do_rex3_command();
VC2_t m_VC2;
XMAP_t m_XMAP0;
XMAP_t m_XMAP1;
REX3_t m_REX3;
required_device<mips3_device> m_maincpu;
required_device<ioc2_device> m_ioc2;
vc2_t m_vc2;
xmap_t m_xmap0;
xmap_t m_xmap1;
rex3_t m_rex3;
std::unique_ptr<uint32_t[]> m_base;
uint8_t m_nDrawGreen;
CMAP_t m_CMAP0;
cmap_t m_cmap0;
};
DECLARE_DEVICE_TYPE(NEWPORT_VIDEO, newport_video_device)