mame/regtests/jedutil/eqns/ispLEVER_Classic/gal18v10/test1/gal18v10-test1.syn
2015-11-05 13:41:25 +01:00

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JDF B
// Created by Version 1.6
PROJECT Untitled
DESIGN gal18v10 Normal
DEVKIT GAL18V10-15LJ
ENTRY ABEL/Schematic
MODULE gal18v10-test1.abl
MODSTYLE gal18v10_test1 Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ActiveHDL
TOPMODULE gal18v10_test1