mirror of
https://github.com/holub/mame
synced 2025-06-02 02:49:44 +03:00
0e627f1a54
timers into the scheduler. Retain TIMER devices as a separate wrapper in timer.c/.h. Inline wrappers are currently provided for all timer operations; a future update will bulk clean these up. Rather than using macros which hide generation of a string-ified name for callback functions, the new methods require passing both a function pointer plus a name string. A new macro FUNC() can be used to output both, and another macro MFUNC() can be used to output a stub-wrapped class member as a callback. Also added a time() method on the machine, so that machine->time() gives the current emulated time. A wrapper for timer_get_time is currently provided but will be bulk replaced in the future. For this update, convert all classic timer_alloc, timer_set, timer_pulse, and timer_call_after_resynch calls into method calls on the scheduler. For new device timers, added methods to the device_t class that make creating and managing these much simpler. Modern devices were updated to use these. Here are the regexes used; some manual cleanup (compiler-caught) will be needed since regex doesn't handle nested parentheses cleanly 1. Convert timer_call_after_resynch calls timer_call_after_resynch( *)\(( *)([^,;]+), *([^,;]+), *([^,;]+), *([^);]+)\) \3->scheduler().synchronize\1\(\2FUNC(\6), \5, \4\) 2. Clean up trailing 0, NULL parameters (synchronize[^;]+), 0, NULL\) \1) 3. Clean up trailing NULL parameters (synchronize[^;]+), NULL\) \1) 4. Clean up completely empty parameter lists synchronize\(FUNC\(NULL\)\) synchronize() 5. Convert timer_set calls timer_set( *)\(( *)([^,;]+), *([^,;]+), *([^,;]+), *([^,;]+), *([^);]+)\) \3->scheduler().timer_set\1\(\2\4, FUNC(\7), \6, \5\) 6. Clean up trailing 0, NULL parameters (timer_set[^;]+), 0, NULL\) \1) 7. Clean up trailing NULL parameters (timer_set[^;]+), NULL\) \1) 8. Convert timer_set calls timer_pulse( *)\(( *)([^,;]+), *([^,;]+), *([^,;]+), *([^,;]+), *([^);]+)\) \3->scheduler().timer_pulse\1\(\2\4, FUNC(\7), \6, \5\) 9. Clean up trailing 0, NULL parameters (timer_pulse[^;]+), 0, NULL\) \1) 10. Clean up trailing NULL parameters (timer_pulse[^;]+), NULL\) \1) 11. Convert timer_alloc calls timer_alloc( *)\(( *)([^,;]+), *([^,;]+), *([^);]+)\) \3->scheduler().timer_alloc\1\(\2FUNC(\4), \5\) 12. Clean up trailing NULL parameters (timer_alloc[^;]+), NULL\) \1) 13. Clean up trailing 0 parameters (timer_alloc[^;]+), 0\) \1) 14. Fix oddities introduced \&m_machine->scheduler() m_machine.scheduler()
655 lines
15 KiB
C
655 lines
15 KiB
C
/***************************************************************************
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asc.c
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Apple Sound Chip (ASC) 344S0063
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Enhanced Apple Sound Chip (EASC) 343S1063
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Emulation by R. Belmont
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Registers:
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0x800: VERSION
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0x801: MODE (1=FIFO mode, 2=wavetable mode)
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0x802: CONTROL (bit 0=analog or PWM output, 1=stereo/mono, 7=processing time exceeded)
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0x803: FIFO MODE (bit 7=clear FIFO, bit 1="non-ROM companding", bit 0="ROM companding")
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0x804: FIFO IRQ STATUS (bit 0=ch A 1/2 full, 1=ch A full, 2=ch B 1/2 full, 3=ch B full)
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0x805: WAVETABLE CONTROL (bits 0-3 wavetables 0-3 start)
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0x806: VOLUME (bits 2-4 = 3 bit internal ASC volume, bits 5-7 = volume control sent to Sony sound chip)
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0x807: CLOCK RATE (0 = Mac 22257 Hz, 1 = undefined, 2 = 22050 Hz, 3 = 44100 Hz)
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0x80a: PLAY REC A
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0x80f: TEST (bits 6-7 = digital test, bits 4-5 = analog test)
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0x810: WAVETABLE 0 PHASE (big-endian 9.15 fixed-point, only 24 bits valid)
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0x814: WAVETABLE 0 INCREMENT (big-endian 9.15 fixed-point, only 24 bits valid)
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0x818: WAVETABLE 1 PHASE
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0x81C: WAVETABLE 1 INCREMENT
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0x820: WAVETABLE 2 PHASE
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0x824: WAVETABLE 2 INCREMENT
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0x828: WAVETABLE 3 PHASE
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0x82C: WAVETABLE 3 INCREMENT
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***************************************************************************/
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#include "emu.h"
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#include "asc.h"
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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const device_type ASC = asc_device_config::static_alloc_device_config;
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//**************************************************************************
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// DEVICE CONFIGURATION
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//**************************************************************************
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//-------------------------------------------------
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// static_set_type - configuration helper to set
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// the chip type
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//-------------------------------------------------
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void asc_device_config::static_set_type(device_config *device, int type)
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{
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asc_device_config *asc = downcast<asc_device_config *>(device);
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asc->m_type = type;
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}
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//-------------------------------------------------
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// static_set_type - configuration helper to set
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// the IRQ callback
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//-------------------------------------------------
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void asc_device_config::static_set_irqf(device_config *device, void (*irqf)(device_t *device, int state))
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{
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asc_device_config *asc = downcast<asc_device_config *>(device);
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asc->m_irq_func = irqf;
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}
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//-------------------------------------------------
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// asc_device_config - constructor
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//-------------------------------------------------
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asc_device_config::asc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock)
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: device_config(mconfig, static_alloc_device_config, "ASC", tag, owner, clock),
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device_config_sound_interface(mconfig, *this)
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{
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}
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//-------------------------------------------------
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// static_alloc_device_config - allocate a new
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// configuration object
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//-------------------------------------------------
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device_config *asc_device_config::static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock)
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{
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return global_alloc(asc_device_config(mconfig, tag, owner, clock));
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}
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//-------------------------------------------------
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// alloc_device - allocate a new device object
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//-------------------------------------------------
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device_t *asc_device_config::alloc_device(running_machine &machine) const
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{
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return auto_alloc(&machine, asc_device(machine, *this));
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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// does nothing, this timer exists only to make MAME sync itself at our audio rate
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static TIMER_CALLBACK( sync_timer_cb )
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{
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asc_device *pDevice = (asc_device *)ptr;
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pDevice->m_stream->update();
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}
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//-------------------------------------------------
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// asc_device - constructor
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//-------------------------------------------------
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asc_device::asc_device(running_machine &_machine, const asc_device_config &config)
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: device_t(_machine, config),
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device_sound_interface(_machine, config, *this),
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m_config(config),
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m_chip_type(m_config.m_type),
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m_irq_cb(m_config.m_irq_func)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void asc_device::device_start()
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{
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// create the stream
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m_stream = m_machine.sound().stream_alloc(*this, 0, 2, 22257, this);
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memset(m_regs, 0, sizeof(m_regs));
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m_sync_timer = this->machine->scheduler().timer_alloc(FUNC(sync_timer_cb), this);
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state_save_register_device_item(this, 0, m_fifo_a_rdptr);
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state_save_register_device_item(this, 0, m_fifo_b_rdptr);
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state_save_register_device_item(this, 0, m_fifo_a_wrptr);
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state_save_register_device_item(this, 0, m_fifo_b_wrptr);
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state_save_register_device_item(this, 0, m_fifo_cap_a);
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state_save_register_device_item(this, 0, m_fifo_cap_b);
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state_save_register_device_item_array(this, 0, m_fifo_a);
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state_save_register_device_item_array(this, 0, m_fifo_b);
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state_save_register_device_item_array(this, 0, m_regs);
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state_save_register_device_item_array(this, 0, m_phase);
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state_save_register_device_item_array(this, 0, m_incr);
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void asc_device::device_reset()
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{
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m_stream->update();
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memset(m_regs, 0, sizeof(m_regs));
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memset(m_fifo_a, 0, sizeof(m_fifo_a));
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memset(m_fifo_b, 0, sizeof(m_fifo_b));
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memset(m_phase, 0, sizeof(m_phase));
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memset(m_incr, 0, sizeof(m_incr));
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m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
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m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
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m_fifo_cap_a = m_fifo_cap_b = 0;
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}
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//-------------------------------------------------
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// sound_stream_update - handle update requests for
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// our sound stream
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//-------------------------------------------------
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void asc_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
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{
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stream_sample_t *outL, *outR;
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int i, ch;
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static UINT32 wtoffs[2] = { 0, 0x200 };
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outL = outputs[0];
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outR = outputs[1];
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switch (m_regs[R_MODE-0x800] & 3)
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{
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case 0: // chip off
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for (i = 0; i < samples; i++)
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{
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outL[i] = outR[i] = 0;
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}
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break;
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case 1: // FIFO mode
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for (i = 0; i < samples; i++)
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{
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INT8 smpll, smplr;
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smpll = (INT8)m_fifo_a[m_fifo_a_rdptr]^0x80;
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smplr = (INT8)m_fifo_b[m_fifo_b_rdptr]^0x80;
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// don't advance the sample pointer if there are no more samples
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if (m_fifo_cap_a)
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{
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m_fifo_a_rdptr++;
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m_fifo_a_rdptr &= 0x3ff;
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m_fifo_cap_a--;
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}
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if (m_fifo_cap_b)
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{
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m_fifo_b_rdptr++;
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m_fifo_b_rdptr &= 0x3ff;
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m_fifo_cap_b--;
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}
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switch (m_chip_type)
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{
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case ASC_TYPE_SONORA:
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if (m_fifo_cap_a < 0x200)
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{
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m_regs[R_FIFOSTAT-0x800] |= 0x4; // fifo less than half full
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m_regs[R_FIFOSTAT-0x800] |= 0x8; // just pass the damn test
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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break;
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default:
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if (m_fifo_cap_a == 0x1ff)
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{
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m_regs[R_FIFOSTAT-0x800] |= 1; // fifo A half-empty
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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else if (m_fifo_cap_a == 0x1) // fifo A fully empty
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{
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m_regs[R_FIFOSTAT-0x800] |= 2; // fifo A empty
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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if (m_fifo_cap_b == 0x1ff)
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{
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m_regs[R_FIFOSTAT-0x800] |= 4; // fifo B half-empty
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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else if (m_fifo_cap_b == 0x1) // fifo B fully empty
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{
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m_regs[R_FIFOSTAT-0x800] |= 8; // fifo B empty
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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break;
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}
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outL[i] = smpll * 64;
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outR[i] = smplr * 64;
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}
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break;
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case 2: // wavetable mode
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for (i = 0; i < samples; i++)
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{
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INT32 mixL, mixR;
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INT8 smpl;
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mixL = mixR = 0;
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// update channel pointers
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for (ch = 0; ch < 4; ch++)
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{
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m_phase[ch] += m_incr[ch];
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if (ch < 2)
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{
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smpl = (INT8)m_fifo_a[((m_phase[ch]>>15)&0x1ff) + wtoffs[ch&1]];
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}
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else
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{
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smpl = (INT8)m_fifo_b[((m_phase[ch]>>15)&0x1ff) + wtoffs[ch&1]];
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}
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smpl ^= 0x80;
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mixL += smpl*256;
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mixR += smpl*256;
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}
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outL[i] = mixL>>2;
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outR[i] = mixR>>2;
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}
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break;
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}
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// printf("rdA %04x rdB %04x wrA %04x wrB %04x (capA %04x B %04x)\n", m_fifo_a_rdptr, m_fifo_b_rdptr, m_fifo_a_wrptr, m_fifo_b_wrptr, m_fifo_cap_a, m_fifo_cap_b);
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}
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//-------------------------------------------------
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// read - read from the chip's registers and internal RAM
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//-------------------------------------------------
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READ8_MEMBER( asc_device::read )
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{
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UINT8 rv;
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// printf("ASC: read at %x\n", offset);
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// not sure what actually happens when the CPU reads the FIFO...
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if (offset < 0x400)
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{
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return m_fifo_a[offset];
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}
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else if (offset < 0x800)
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{
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return m_fifo_b[offset-0x400];
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}
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else
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{
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m_stream->update();
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switch (offset)
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{
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case R_VERSION:
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switch (m_chip_type)
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{
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case ASC_TYPE_ASC:
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return 0;
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case ASC_TYPE_V8:
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case ASC_TYPE_EAGLE:
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case ASC_TYPE_SPICE:
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case ASC_TYPE_VASP:
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return 0xe8;
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case ASC_TYPE_SONORA:
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return 0xbc;
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default: // return the actual register value
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break;
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}
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break;
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case R_MODE:
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switch (m_chip_type)
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{
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case ASC_TYPE_V8:
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case ASC_TYPE_EAGLE:
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case ASC_TYPE_SPICE:
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case ASC_TYPE_VASP:
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return 1;
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default:
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break;
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}
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break;
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case R_CONTROL:
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switch (m_chip_type)
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{
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case ASC_TYPE_V8:
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case ASC_TYPE_EAGLE:
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case ASC_TYPE_SPICE:
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case ASC_TYPE_VASP:
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return 1;
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default:
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break;
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}
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break;
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case R_FIFOSTAT:
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if (m_chip_type == ASC_TYPE_V8)
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{
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rv = 3;
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}
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else
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{
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rv = m_regs[R_FIFOSTAT-0x800];
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}
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// printf("Read FIFO stat = %02x\n", rv);
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// reading this register clears all bits
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m_regs[R_FIFOSTAT-0x800] = 0;
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// reading this clears interrupts
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if (m_irq_cb)
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{
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m_irq_cb(this, 0);
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}
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return rv;
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break;
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default:
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break;
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}
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}
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// WT inc/phase registers - rebuild from "live" copies"
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if ((offset >= 0x810) && (offset <= 0x82f))
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{
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m_regs[0x11] = m_phase[0]>>16;
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m_regs[0x12] = m_phase[0]>>8;
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m_regs[0x13] = m_phase[0];
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m_regs[0x15] = m_incr[0]>>16;
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m_regs[0x16] = m_incr[0]>>8;
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m_regs[0x17] = m_incr[0];
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m_regs[0x19] = m_phase[1]>>16;
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m_regs[0x1a] = m_phase[1]>>8;
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m_regs[0x1b] = m_phase[1];
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m_regs[0x1d] = m_incr[1]>>16;
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m_regs[0x1e] = m_incr[1]>>8;
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m_regs[0x1f] = m_incr[1];
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m_regs[0x21] = m_phase[2]>>16;
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m_regs[0x22] = m_phase[2]>>8;
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m_regs[0x23] = m_phase[2];
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m_regs[0x25] = m_incr[2]>>16;
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m_regs[0x26] = m_incr[2]>>8;
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m_regs[0x27] = m_incr[2];
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m_regs[0x29] = m_phase[3]>>16;
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m_regs[0x2a] = m_phase[3]>>8;
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m_regs[0x2b] = m_phase[3];
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m_regs[0x2d] = m_incr[3]>>16;
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m_regs[0x2e] = m_incr[3]>>8;
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m_regs[0x2f] = m_incr[3];
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}
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return m_regs[offset-0x800];
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}
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//-------------------------------------------------
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// write - write to the chip's registers and internal RAM
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//-------------------------------------------------
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WRITE8_MEMBER( asc_device::write )
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{
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// printf("ASC: write %02x to %x\n", data, offset);
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if (offset < 0x400)
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{
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if (m_regs[R_MODE-0x800] == 1)
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{
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m_fifo_a[m_fifo_a_wrptr++] = data;
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m_fifo_cap_a++;
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if (m_fifo_cap_a == 0x3ff)
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{
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m_regs[R_FIFOSTAT-0x800] |= 2; // fifo A full
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}
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m_fifo_a_wrptr &= 0x3ff;
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}
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else
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{
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m_fifo_a[offset] = data;
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}
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}
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else if (offset < 0x800)
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{
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if (m_regs[R_MODE-0x800] == 1)
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{
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m_fifo_b[m_fifo_b_wrptr++] = data;
|
|
m_fifo_cap_b++;
|
|
|
|
if (m_fifo_cap_b == 0x3ff)
|
|
{
|
|
m_regs[R_FIFOSTAT-0x800] |= 8; // fifo B full
|
|
}
|
|
|
|
m_fifo_b_wrptr &= 0x3ff;
|
|
}
|
|
else
|
|
{
|
|
m_fifo_b[offset-0x400] = data;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// printf("ASC: %02x to %x (was %x)\n", data, offset, m_regs[offset-0x800]);
|
|
|
|
m_stream->update();
|
|
switch (offset)
|
|
{
|
|
case R_MODE:
|
|
data &= 3; // only bits 0 and 1 can be written
|
|
|
|
if (data != m_regs[R_MODE-0x800])
|
|
{
|
|
m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
|
|
m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
|
|
m_fifo_cap_a = m_fifo_cap_b = 0;
|
|
|
|
if (data != 0)
|
|
{
|
|
timer_adjust_periodic(m_sync_timer, attotime::zero, 0, attotime::from_hz(22257/4));
|
|
}
|
|
else
|
|
{
|
|
timer_adjust_oneshot(m_sync_timer, attotime::never, 0);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case R_FIFOMODE:
|
|
if (data & 0x80)
|
|
{
|
|
m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
|
|
m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
|
|
m_fifo_cap_a = m_fifo_cap_b = 0;
|
|
}
|
|
break;
|
|
|
|
case R_WTCONTROL:
|
|
// printf("One-shot wavetable %02x\n", data);
|
|
break;
|
|
|
|
case 0x811:
|
|
m_phase[0] &= 0x00ffff;
|
|
m_phase[0] |= data<<16;
|
|
break;
|
|
|
|
case 0x812:
|
|
m_phase[0] &= 0xff00ff;
|
|
m_phase[0] |= data<<8;
|
|
break;
|
|
|
|
case 0x813:
|
|
m_phase[0] &= 0xffff00;
|
|
m_phase[0] |= data;
|
|
break;
|
|
|
|
case 0x815:
|
|
m_incr[0] &= 0x00ffff;
|
|
m_incr[0] |= data<<16;
|
|
break;
|
|
|
|
case 0x816:
|
|
m_incr[0] &= 0xff00ff;
|
|
m_incr[0] |= data<<8;
|
|
break;
|
|
|
|
case 0x817:
|
|
m_incr[0] &= 0xffff00;
|
|
m_incr[0] |= data;
|
|
break;
|
|
|
|
case 0x819:
|
|
m_phase[1] &= 0x00ffff;
|
|
m_phase[1] |= data<<16;
|
|
break;
|
|
|
|
case 0x81a:
|
|
m_phase[1] &= 0xff00ff;
|
|
m_phase[1] |= data<<8;
|
|
break;
|
|
|
|
case 0x81b:
|
|
m_phase[1] &= 0xffff00;
|
|
m_phase[1] |= data;
|
|
break;
|
|
|
|
case 0x81d:
|
|
m_incr[1] &= 0x00ffff;
|
|
m_incr[1] |= data<<16;
|
|
break;
|
|
|
|
case 0x81e:
|
|
m_incr[1] &= 0xff00ff;
|
|
m_incr[1] |= data<<8;
|
|
break;
|
|
|
|
case 0x81f:
|
|
m_incr[1] &= 0xffff00;
|
|
m_incr[1] |= data;
|
|
break;
|
|
|
|
case 0x821:
|
|
m_phase[2] &= 0x00ffff;
|
|
m_phase[2] |= data<<16;
|
|
break;
|
|
|
|
case 0x822:
|
|
m_phase[2] &= 0xff00ff;
|
|
m_phase[2] |= data<<8;
|
|
break;
|
|
|
|
case 0x823:
|
|
m_phase[2] &= 0xffff00;
|
|
m_phase[2] |= data;
|
|
break;
|
|
|
|
case 0x825:
|
|
m_incr[2] &= 0x00ffff;
|
|
m_incr[2] |= data<<16;
|
|
break;
|
|
|
|
case 0x826:
|
|
m_incr[2] &= 0xff00ff;
|
|
m_incr[2] |= data<<8;
|
|
break;
|
|
|
|
case 0x827:
|
|
m_incr[2] &= 0xffff00;
|
|
m_incr[2] |= data;
|
|
break;
|
|
|
|
case 0x829:
|
|
m_phase[3] &= 0x00ffff;
|
|
m_phase[3] |= data<<16;
|
|
break;
|
|
|
|
case 0x82a:
|
|
m_phase[3] &= 0xff00ff;
|
|
m_phase[3] |= data<<8;
|
|
break;
|
|
|
|
case 0x82b:
|
|
m_phase[3] &= 0xffff00;
|
|
m_phase[3] |= data;
|
|
break;
|
|
|
|
case 0x82d:
|
|
m_incr[3] &= 0x00ffff;
|
|
m_incr[3] |= data<<16;
|
|
break;
|
|
|
|
case 0x82e:
|
|
m_incr[3] &= 0xff00ff;
|
|
m_incr[3] |= data<<8;
|
|
break;
|
|
|
|
case 0x82f:
|
|
m_incr[3] &= 0xffff00;
|
|
m_incr[3] |= data;
|
|
break;
|
|
}
|
|
|
|
m_regs[offset-0x800] = data;
|
|
}
|
|
}
|