mirror of
https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
202d7680a4
space by index. Update functions and methods that accepted an address space index to take an address_spacenum instead. Note that this means you can't use a raw integer in ADDRESS_SPACE macros, so instead of 0 use the enumerated AS_0. Standardized the project on the shortened constants AS_* over the older ADDRESS_SPACE_*. Removed the latter to prevent confusion. Also centralized the location of these definitions to memory.h.
614 lines
17 KiB
C
614 lines
17 KiB
C
/*
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Motorola MC68HC11 emulator
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Written by Ville Linde & Angelo Salese
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TODO:
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- Interrupts handling is really bare-bones, just to make Hit Poker happy;
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- Complete opcodes hook-up;
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- Emulate the MC68HC12 (same as HC11 with a bunch of new opcodes);
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*/
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#include "emu.h"
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#include "debugger.h"
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#include "mc68hc11.h"
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enum
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{
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HC11_PC = 1,
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HC11_SP,
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HC11_A,
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HC11_B,
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HC11_IX,
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HC11_IY
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};
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#define CC_S 0x80
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#define CC_X 0x40
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#define CC_H 0x20
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#define CC_I 0x10
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#define CC_N 0x08
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#define CC_Z 0x04
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#define CC_V 0x02
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#define CC_C 0x01
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typedef struct _hc11_state hc11_state;
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struct _hc11_state
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{
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union {
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struct {
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#ifdef LSB_FIRST
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UINT8 b;
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UINT8 a;
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#else
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UINT8 a;
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UINT8 b;
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#endif
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} d8;
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UINT16 d16;
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} d;
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UINT16 ix;
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UINT16 iy;
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UINT16 sp;
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UINT16 pc;
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UINT16 ppc;
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UINT8 ccr;
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UINT8 adctl;
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int ad_channel;
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device_irq_callback irq_callback;
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UINT8 irq_state[2];
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legacy_cpu_device *device;
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direct_read_data *direct;
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address_space *program;
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address_space *io;
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int icount;
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int ram_position;
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int reg_position;
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UINT8 *internal_ram;
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int has_extended_io; // extended I/O enable flag
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int internal_ram_size;
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UINT8 wait_state,stop_state;
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UINT8 tflg1;
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};
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INLINE hc11_state *get_safe_token(device_t *device)
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{
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assert(device != NULL);
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assert(device->type() == MC68HC11);
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return (hc11_state *)downcast<legacy_cpu_device *>(device)->token();
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}
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#define HC11OP(XX) hc11_##XX
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/*****************************************************************************/
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/* Internal registers */
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static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address)
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{
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int reg = address & 0xff;
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switch(reg)
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{
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case 0x00: /* PORTA */
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return cpustate->io->read_byte(MC68HC11_IO_PORTA);
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case 0x01: /* DDRA */
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return 0;
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case 0x02: /* PIOC */
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return 0;
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case 0x03: /* PORTC */
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return cpustate->io->read_byte(MC68HC11_IO_PORTC);
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case 0x04: /* PORTB */
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return cpustate->io->read_byte(MC68HC11_IO_PORTB);
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case 0x08: /* PORTD */
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return cpustate->io->read_byte(MC68HC11_IO_PORTD);
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case 0x09: /* DDRD */
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return 0;
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case 0x0a: /* PORTE */
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return cpustate->io->read_byte(MC68HC11_IO_PORTE);
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case 0x23:
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return cpustate->tflg1;
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case 0x28: /* SPCR1 */
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return 0;
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case 0x30: /* ADCTL */
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return 0x80;
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case 0x31: /* ADR1 */
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{
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if (cpustate->adctl & 0x10)
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD0);
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}
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else
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x32: /* ADR2 */
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{
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if (cpustate->adctl & 0x10)
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD1);
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}
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else
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x33: /* ADR3 */
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{
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if (cpustate->adctl & 0x10)
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD2);
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}
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else
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x34: /* ADR4 */
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{
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if (cpustate->adctl & 0x10)
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD3);
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}
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else
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{
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return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x38: /* OPT2 */
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return 0;
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case 0x70: /* SCBDH */
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return 0;
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case 0x71: /* SCBDL */
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return 0;
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case 0x72: /* SCCR1 */
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return 0;
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case 0x73: /* SCCR2 */
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return 0;
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case 0x74: /* SCSR1 */
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return 0x40;
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case 0x7c: /* PORTH */
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return cpustate->io->read_byte(MC68HC11_IO_PORTH);
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case 0x7e: /* PORTG */
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return cpustate->io->read_byte(MC68HC11_IO_PORTG);
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case 0x7f: /* DDRG */
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return 0;
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case 0x88: /* SPCR2 */
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return 0;
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case 0x89: /* SPSR2 */
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return 0x80;
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case 0x8a: /* SPDR2 */
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return cpustate->io->read_byte(MC68HC11_IO_SPI2_DATA);
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case 0x8b: /* OPT4 */
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return 0;
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}
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logerror("HC11: regs_r %02X\n", reg);
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return 0; // Dummy
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}
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static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
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{
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int reg = address & 0xff;
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switch(reg)
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{
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case 0x00: /* PORTA */
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cpustate->io->write_byte(MC68HC11_IO_PORTA, value);
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return;
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case 0x01: /* DDRA */
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//mame_printf_debug("HC11: ddra = %02X\n", value);
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return;
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case 0x03: /* PORTC */
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cpustate->io->write_byte(MC68HC11_IO_PORTC, value);
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return;
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case 0x04: /* PORTC */
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cpustate->io->write_byte(MC68HC11_IO_PORTB, value);
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return;
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case 0x08: /* PORTD */
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cpustate->io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f?
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return;
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case 0x09: /* DDRD */
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//mame_printf_debug("HC11: ddrd = %02X\n", value);
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return;
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case 0x0a: /* PORTE */
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cpustate->io->write_byte(MC68HC11_IO_PORTE, value);
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return;
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case 0x22: /* TMSK1 */
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return;
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case 0x23:
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cpustate->tflg1 = value;
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return;
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case 0x24: /* TMSK2 */
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return;
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case 0x28: /* SPCR1 */
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return;
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case 0x30: /* ADCTL */
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cpustate->adctl = value;
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return;
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case 0x38: /* OPT2 */
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return;
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case 0x39: /* OPTION */
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return;
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case 0x3a: /* COPRST (watchdog) */
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return;
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case 0x3d: /* INIT */
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{
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int reg_page = value & 0xf;
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int ram_page = (value >> 4) & 0xf;
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if (reg_page == ram_page) {
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cpustate->reg_position = reg_page << 12;
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cpustate->ram_position = (ram_page << 12) + 0x100;
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} else {
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cpustate->reg_position = reg_page << 12;
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cpustate->ram_position = ram_page << 12;
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}
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return;
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}
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case 0x3f: /* CONFIG */
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return;
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case 0x70: /* SCBDH */
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return;
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case 0x71: /* SCBDL */
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return;
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case 0x72: /* SCCR1 */
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return;
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case 0x73: /* SCCR2 */
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return;
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case 0x77: /* SCDRL */
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return;
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case 0x7c: /* PORTH */
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cpustate->io->write_byte(MC68HC11_IO_PORTH, value);
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return;
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case 0x7d: /* DDRH */
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//mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc);
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return;
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case 0x7e: /* PORTG */
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cpustate->io->write_byte(MC68HC11_IO_PORTG, value);
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return;
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case 0x7f: /* DDRG */
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//mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc);
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return;
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case 0x88: /* SPCR2 */
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return;
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case 0x89: /* SPSR2 */
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return;
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case 0x8a: /* SPDR2 */
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cpustate->io->write_byte(MC68HC11_IO_SPI2_DATA, value);
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return;
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case 0x8b: /* OPT4 */
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return;
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}
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logerror("HC11: regs_w %02X, %02X\n", reg, value);
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}
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/*****************************************************************************/
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INLINE UINT8 FETCH(hc11_state *cpustate)
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{
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return cpustate->direct->read_decrypted_byte(cpustate->pc++);
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}
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INLINE UINT16 FETCH16(hc11_state *cpustate)
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{
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UINT16 w;
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w = (cpustate->direct->read_decrypted_byte(cpustate->pc) << 8) | (cpustate->direct->read_decrypted_byte(cpustate->pc+1));
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cpustate->pc += 2;
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return w;
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}
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INLINE UINT8 READ8(hc11_state *cpustate, UINT32 address)
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{
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if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40))
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{
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return hc11_regs_r(cpustate, address);
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}
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else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
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{
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return cpustate->internal_ram[address-cpustate->ram_position];
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}
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return cpustate->program->read_byte(address);
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}
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INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value)
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{
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if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40))
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{
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hc11_regs_w(cpustate, address, value);
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return;
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}
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else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
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{
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cpustate->internal_ram[address-cpustate->ram_position] = value;
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return;
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}
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cpustate->program->write_byte(address, value);
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}
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INLINE UINT16 READ16(hc11_state *cpustate, UINT32 address)
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{
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return (READ8(cpustate, address) << 8) | (READ8(cpustate, address+1));
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}
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INLINE void WRITE16(hc11_state *cpustate, UINT32 address, UINT16 value)
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{
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WRITE8(cpustate, address+0, (value >> 8) & 0xff);
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WRITE8(cpustate, address+1, (value >> 0) & 0xff);
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}
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/*****************************************************************************/
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static void (*hc11_optable[256])(hc11_state *cpustate);
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static void (*hc11_optable_page2[256])(hc11_state *cpustate);
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static void (*hc11_optable_page3[256])(hc11_state *cpustate);
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static void (*hc11_optable_page4[256])(hc11_state *cpustate);
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#include "hc11ops.c"
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#include "hc11ops.h"
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static CPU_INIT( hc11 )
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{
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hc11_state *cpustate = get_safe_token(device);
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int i;
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const hc11_config *conf = (const hc11_config *)device->baseconfig().static_config();
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/* clear the opcode tables */
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for(i=0; i < 256; i++) {
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hc11_optable[i] = HC11OP(invalid);
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hc11_optable_page2[i] = HC11OP(invalid);
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hc11_optable_page3[i] = HC11OP(invalid);
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hc11_optable_page4[i] = HC11OP(invalid);
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}
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/* fill the opcode tables */
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for(i=0; i < sizeof(hc11_opcode_list)/sizeof(hc11_opcode_list_struct); i++)
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{
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switch(hc11_opcode_list[i].page)
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{
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case 0x00:
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hc11_optable[hc11_opcode_list[i].opcode] = hc11_opcode_list[i].handler;
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break;
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case 0x18:
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hc11_optable_page2[hc11_opcode_list[i].opcode] = hc11_opcode_list[i].handler;
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break;
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case 0x1A:
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hc11_optable_page3[hc11_opcode_list[i].opcode] = hc11_opcode_list[i].handler;
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break;
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case 0xCD:
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hc11_optable_page4[hc11_opcode_list[i].opcode] = hc11_opcode_list[i].handler;
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break;
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}
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}
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if(conf)
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{
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cpustate->has_extended_io = conf->has_extended_io;
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cpustate->internal_ram_size = conf->internal_ram_size;
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}
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else
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{
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/* defaults it to the HC11M0 version for now (I might strip this down on a later date) */
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cpustate->has_extended_io = 1;
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cpustate->internal_ram_size = 1280;
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}
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cpustate->internal_ram = auto_alloc_array(device->machine, UINT8, cpustate->internal_ram_size);
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cpustate->reg_position = 0;
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cpustate->ram_position = 0x100;
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cpustate->irq_callback = irqcallback;
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cpustate->device = device;
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cpustate->program = device->space(AS_PROGRAM);
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cpustate->direct = &cpustate->program->direct();
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cpustate->io = device->space(AS_IO);
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}
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static CPU_RESET( hc11 )
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{
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hc11_state *cpustate = get_safe_token(device);
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cpustate->pc = READ16(cpustate, 0xfffe);
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cpustate->wait_state = 0;
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cpustate->stop_state = 0;
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cpustate->ccr = CC_X | CC_I | CC_S;
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cpustate->reg_position = 0x1000;
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cpustate->ram_position = 0;
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}
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static CPU_EXIT( hc11 )
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{
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}
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/*
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IRQ table vectors:
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0xffd6: SCI
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0xffd8: SPI
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0xffda: Pulse Accumulator Input Edge
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0xffdc: Pulse Accumulator Overflow
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0xffde: Timer Overflow
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0xffe0: Timer Output Capture 5
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0xffe2: Timer Output Capture 4
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0xffe4: Timer Output Capture 3
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0xffe6: Timer Output Capture 2
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0xffe8: Timer Output Capture 1
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0xffea: Timer Input Capture 3
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0xffec: Timer Input Capture 2
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0xffee: Timer Input Capture 1
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0xfff0: Real Time Int
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0xfff2: IRQ
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0xfff4: XIRQ
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0xfff6: SWI (Trap IRQ)
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0xfff8: Illegal Opcode (NMI)
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0xfffa: CO-Processor Fail
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0xfffc: Clock Monitor
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0xfffe: RESET
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*/
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static void check_irq_lines(hc11_state *cpustate)
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{
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if( cpustate->irq_state[MC68HC11_IRQ_LINE]!=CLEAR_LINE && (!(cpustate->ccr & CC_I)) )
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{
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UINT16 pc_vector;
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if(cpustate->wait_state == 0)
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{
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PUSH16(cpustate, cpustate->pc);
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PUSH16(cpustate, cpustate->iy);
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PUSH16(cpustate, cpustate->ix);
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PUSH8(cpustate, REG_A);
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PUSH8(cpustate, REG_B);
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PUSH8(cpustate, cpustate->ccr);
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}
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pc_vector = READ16(cpustate, 0xfff2);
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SET_PC(cpustate, pc_vector);
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cpustate->ccr |= CC_I; //irq taken, mask the flag
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if(cpustate->wait_state == 1) { cpustate->wait_state = 2; }
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if(cpustate->stop_state == 1) { cpustate->stop_state = 2; }
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(void)(*cpustate->irq_callback)(cpustate->device, MC68HC11_IRQ_LINE);
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}
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}
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static void set_irq_line(hc11_state *cpustate, int irqline, int state)
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{
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cpustate->irq_state[irqline] = state;
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if (state == CLEAR_LINE) return;
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check_irq_lines(cpustate);
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}
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static CPU_EXECUTE( hc11 )
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{
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hc11_state *cpustate = get_safe_token(device);
|
|
|
|
while(cpustate->icount > 0)
|
|
{
|
|
UINT8 op;
|
|
|
|
check_irq_lines(cpustate);
|
|
|
|
cpustate->ppc = cpustate->pc;
|
|
debugger_instruction_hook(device, cpustate->pc);
|
|
|
|
op = FETCH(cpustate);
|
|
hc11_optable[op](cpustate);
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
|
|
static CPU_SET_INFO( mc68hc11 )
|
|
{
|
|
hc11_state *cpustate = get_safe_token(device);
|
|
|
|
switch (state)
|
|
{
|
|
case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: set_irq_line(cpustate, MC68HC11_IRQ_LINE, info->i); break;
|
|
|
|
/* --- the following bits of info are set as 64-bit signed integers --- */
|
|
case CPUINFO_INT_PC: cpustate->pc = info->i; break;
|
|
case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
|
|
case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break;
|
|
case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break;
|
|
case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break;
|
|
case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break;
|
|
case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break;
|
|
}
|
|
}
|
|
|
|
CPU_GET_INFO( mc68hc11 )
|
|
{
|
|
hc11_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
|
|
|
switch(state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break;
|
|
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
|
|
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
|
case DEVINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
|
|
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
|
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
|
|
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
|
|
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
|
|
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
|
|
case CPUINFO_INT_MAX_CYCLES: info->i = 41; break;
|
|
|
|
case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
|
|
case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
|
|
case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
|
|
case DEVINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
|
|
case DEVINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
|
|
case DEVINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
|
|
case DEVINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
|
|
case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break;
|
|
case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
|
|
|
|
case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break;
|
|
|
|
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
|
|
|
|
case CPUINFO_INT_PC: /* intentional fallthrough */
|
|
case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break;
|
|
case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break;
|
|
case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break;
|
|
case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break;
|
|
case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break;
|
|
case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break;
|
|
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hc11); break;
|
|
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hc11); break;
|
|
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(hc11); break;
|
|
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break;
|
|
case CPUINFO_FCT_BURN: info->burn = NULL; break;
|
|
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hc11); break;
|
|
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case DEVINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break;
|
|
case DEVINFO_STR_FAMILY: strcpy(info->s, "Motorola MC68HC11"); break;
|
|
case DEVINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
|
|
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
|
|
case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break;
|
|
|
|
case CPUINFO_STR_FLAGS:
|
|
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
|
(cpustate->ccr & CC_S) ? 'S' : '.',
|
|
(cpustate->ccr & CC_X) ? 'X' : '.',
|
|
(cpustate->ccr & CC_H) ? 'H' : '.',
|
|
(cpustate->ccr & CC_I) ? 'I' : '.',
|
|
(cpustate->ccr & CC_N) ? 'N' : '.',
|
|
(cpustate->ccr & CC_Z) ? 'Z' : '.',
|
|
(cpustate->ccr & CC_V) ? 'V' : '.',
|
|
(cpustate->ccr & CC_C) ? 'C' : '.');
|
|
break;
|
|
|
|
case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
|
|
case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break;
|
|
case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break;
|
|
case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break;
|
|
case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break;
|
|
case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break;
|
|
}
|
|
}
|
|
|
|
DEFINE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11);
|