mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
56 lines
1.2 KiB
C++
56 lines
1.2 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:hap
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/*
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The ChessMachine SR by Tasc
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*/
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#ifndef MAME_BUS_ISA_CHESSMSR_H
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#define MAME_BUS_ISA_CHESSMSR_H
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#pragma once
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#include "isa.h"
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#include "cpu/arm/arm.h"
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#include "machine/gen_latch.h"
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class isa8_chessmsr_device :
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public device_t,
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public device_isa8_card_interface
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{
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public:
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// construction/destruction
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isa8_chessmsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_reset_after_children() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual ioport_constructor device_input_ports() const override;
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private:
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required_device<arm_cpu_device> m_maincpu;
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required_device<generic_latch_8_device> m_mainlatch;
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required_device<generic_latch_8_device> m_sublatch;
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optional_shared_ptr<u32> m_ram;
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u8 m_ram_offset;
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bool m_suspended;
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bool m_installed;
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DECLARE_READ8_MEMBER(chessmsr_r);
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DECLARE_WRITE8_MEMBER(chessmsr_w);
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void chessmsr_mem(address_map &map);
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};
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DECLARE_DEVICE_TYPE(ISA8_CHESSMSR, isa8_chessmsr_device)
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#endif // MAME_BUS_ISA_CHESSMSR_H
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