mirror of
https://github.com/holub/mame
synced 2025-06-02 02:49:44 +03:00
132 lines
2.9 KiB
C++
132 lines
2.9 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Barry Rodewald
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/*
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* 8x300dasm.c
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* Implementation of the Scientific Micro Systems SMS300 / Signetics 8X300 Microcontroller
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*
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* Created on: 18/12/2013
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*/
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#include "emu.h"
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#include "8x300.h"
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#define SRC ((opcode & 0x1f00) >> 8)
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#define DST (opcode & 0x001f)
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#define ROTLEN ((opcode & 0x00e0) >> 5)
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#define IMM8 (opcode & 0x00ff)
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#define IMM5 (opcode & 0x001f)
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static const char *reg_names[32] =
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{
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"AUX", "R1", "R2", "R3", "R4", "R5", "R6", "IVL", "OVF", "R11",
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"Unused12", "Unused13", "Unused14", "Unused15", "Unused16", "IVR",
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"LIV0", "LIV1", "LIV2", "LIV3", "LIV4", "LIV5", "LIV6", "LIV7",
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"RIV0", "RIV1", "RIV2", "RIV3", "RIV4", "RIV5", "RIV6", "RIV7"
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};
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// determines if right rotate or I/O field length is to be used
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static inline bool is_rot(uint16_t opcode)
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{
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if((opcode & 0x1000) || (opcode & 0x0010))
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return false;
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else
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return true;
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}
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static inline bool is_src_rot(uint16_t opcode)
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{
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if((opcode & 0x1000))
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return false;
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else
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return true;
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}
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CPU_DISASSEMBLE(n8x300)
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{
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unsigned startpc = pc;
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uint16_t opcode = (oprom[pc - startpc] << 8) | oprom[pc+1 - startpc];
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uint8_t inst = opcode >> 13;
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pc+=2;
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// determine instruction
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switch (inst)
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{
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case 0x00:
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stream << "MOVE " << reg_names[SRC];
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if(is_rot(opcode))
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x01:
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stream << "ADD " << reg_names[SRC];
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if(is_rot(opcode))
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x02:
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stream << "AND " << reg_names[SRC];
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if(is_rot(opcode))
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x03:
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stream << "XOR " << reg_names[SRC];
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if(is_rot(opcode))
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x04:
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stream << "XEC " << reg_names[SRC];
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if(is_src_rot(opcode))
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{
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util::stream_format(stream, ",%02XH", IMM8);
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}
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else
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{
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util::stream_format(stream, ",%i", ROTLEN);
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util::stream_format(stream, ",%02XH", IMM5);
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}
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break;
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case 0x05:
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stream << "NZT " << reg_names[SRC];
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if(is_src_rot(opcode))
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{
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util::stream_format(stream, ",%02XH", IMM8);
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}
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else
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{
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util::stream_format(stream, ",%i", ROTLEN);
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util::stream_format(stream, ",%02XH", IMM5);
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}
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break;
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case 0x06:
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stream << "XMIT ";
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if(is_src_rot(opcode))
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{
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util::stream_format(stream, "%02XH,", IMM8);
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stream << reg_names[SRC];
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}
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else
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{
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util::stream_format(stream, "%02XH,", IMM5);
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stream << reg_names[SRC];
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util::stream_format(stream, ",%i", ROTLEN);
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}
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break;
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case 0x07:
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util::stream_format(stream, "JMP %04XH", (opcode & 0x1fff) << 1);
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break;
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}
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return (pc - startpc);
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}
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