mirror of
https://github.com/holub/mame
synced 2025-05-25 15:25:33 +03:00
2e65d4a968
- Split SATURATE_ACCUM into a signed and unsigned version to reduce stack usage. - Corrected an issue with the 0h variants of VMRG, VAND, VNAND, VOR, VNOR, VXOR and VNXOR. - Slightly optimized unaligned reads and writes - Optimized unaligned dword reads - Corrected an issue where badly-written RSP programs could jump to invalid addresses
309 lines
8.3 KiB
C
309 lines
8.3 KiB
C
/***************************************************************************
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rspfe.c
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Front-end for RSP recompiler
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Copyright the MESS team
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Released for general non-commercial use under the MAME license
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Visit http://mamedev.org for licensing and usage restrictions.
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***************************************************************************/
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#include <stddef.h>
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#include "cpuintrf.h"
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#include "rspfe.h"
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#include "rsp.h"
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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static int describe_instruction_special(rsp_state *rsp, UINT32 op, opcode_desc *desc);
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static int describe_instruction_regimm(rsp_state *rsp, UINT32 op, opcode_desc *desc);
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static int describe_instruction_cop0(rsp_state *rsp, UINT32 op, opcode_desc *desc);
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static int describe_instruction_cop2(rsp_state *rsp, UINT32 op, opcode_desc *desc);
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/***************************************************************************
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INSTRUCTION PARSERS
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***************************************************************************/
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/*-------------------------------------------------
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describe_instruction - build a description
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of a single instruction
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-------------------------------------------------*/
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int rspfe_describe(void *param, opcode_desc *desc, const opcode_desc *prev)
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{
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rsp_state *rsp = (rsp_state *)param;
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UINT32 op, opswitch;
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/* fetch the opcode */
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op = desc->opptr.l[0] = memory_decrypted_read_dword(rsp->program, desc->physpc | 0x1000);
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/* all instructions are 4 bytes and default to a single cycle each */
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desc->length = 4;
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desc->cycles = 1;
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/* parse the instruction */
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opswitch = op >> 26;
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switch (opswitch)
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{
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case 0x00: /* SPECIAL */
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return describe_instruction_special(rsp, op, desc);
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case 0x01: /* REGIMM */
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return describe_instruction_regimm(rsp, op, desc);
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case 0x10: /* COP0 */
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return describe_instruction_cop0(rsp, op, desc);
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case 0x12: /* COP2 */
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return describe_instruction_cop2(rsp, op, desc);
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case 0x02: /* J */
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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desc->targetpc = ((LIMMVAL << 2) & 0x00000fff) | 0x1000;
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desc->delayslots = 1;
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return TRUE;
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case 0x03: /* JAL */
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desc->regout[0] |= REGFLAG_R(31);
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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desc->targetpc = ((LIMMVAL << 2) & 0x00000fff) | 0x1000;
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desc->delayslots = 1;
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return TRUE;
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case 0x04: /* BEQ */
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case 0x05: /* BNE */
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if ((opswitch == 0x04 || opswitch == 0x14) && RSREG == RTREG)
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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else
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{
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desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
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desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
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}
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desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
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desc->delayslots = 1;
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desc->skipslots = (opswitch & 0x10) ? 1 : 0;
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return TRUE;
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case 0x06: /* BLEZ */
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case 0x07: /* BGTZ */
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if ((opswitch == 0x06 || opswitch == 0x16) && RSREG == 0)
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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else
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{
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
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}
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desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
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desc->delayslots = 1;
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desc->skipslots = (opswitch & 0x10) ? 1 : 0;
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return TRUE;
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case 0x08: /* ADDI */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->regout[0] |= REGFLAG_R(RTREG);
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return TRUE;
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case 0x09: /* ADDIU */
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case 0x0a: /* SLTI */
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case 0x0b: /* SLTIU */
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case 0x0c: /* ANDI */
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case 0x0d: /* ORI */
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case 0x0e: /* XORI */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->regout[0] |= REGFLAG_R(RTREG);
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return TRUE;
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case 0x0f: /* LUI */
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desc->regout[0] |= REGFLAG_R(RTREG);
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return TRUE;
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case 0x20: /* LB */
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case 0x21: /* LH */
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case 0x23: /* LW */
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case 0x24: /* LBU */
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case 0x25: /* LHU */
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case 0x27: /* LWU */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->regout[0] |= REGFLAG_R(RTREG);
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desc->flags |= OPFLAG_READS_MEMORY;
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return TRUE;
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case 0x28: /* SB */
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case 0x29: /* SH */
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case 0x2b: /* SW */
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desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
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desc->flags |= OPFLAG_WRITES_MEMORY;
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return TRUE;
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case 0x32: /* LWC2 */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->flags |= OPFLAG_READS_MEMORY;
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return TRUE;
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case 0x3a: /* SWC2 */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->flags |= OPFLAG_WRITES_MEMORY;
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return TRUE;
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}
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return FALSE;
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}
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/*-------------------------------------------------
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describe_instruction_special - build a
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description of a single instruction in the
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'special' group
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-------------------------------------------------*/
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static int describe_instruction_special(rsp_state *rsp, UINT32 op, opcode_desc *desc)
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{
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switch (op & 63)
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{
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case 0x00: /* SLL */
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case 0x02: /* SRL */
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case 0x03: /* SRA */
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desc->regin[0] |= REGFLAG_R(RTREG);
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desc->regout[0] |= REGFLAG_R(RDREG);
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return TRUE;
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case 0x04: /* SLLV */
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case 0x06: /* SRLV */
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case 0x07: /* SRAV */
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case 0x21: /* ADDU */
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case 0x23: /* SUBU */
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case 0x24: /* AND */
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case 0x25: /* OR */
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case 0x26: /* XOR */
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case 0x27: /* NOR */
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case 0x2a: /* SLT */
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case 0x2b: /* SLTU */
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desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
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desc->regout[0] |= REGFLAG_R(RDREG);
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return TRUE;
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case 0x20: /* ADD */
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case 0x22: /* SUB */
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desc->regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
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desc->regout[0] |= REGFLAG_R(RDREG);
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return TRUE;
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case 0x08: /* JR */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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desc->targetpc = BRANCH_TARGET_DYNAMIC;
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desc->delayslots = 1;
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return TRUE;
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case 0x09: /* JALR */
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->regout[0] |= REGFLAG_R(RDREG);
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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desc->targetpc = BRANCH_TARGET_DYNAMIC;
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desc->delayslots = 1;
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return TRUE;
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case 0x0d: /* BREAK */
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desc->flags |= OPFLAG_END_SEQUENCE;
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desc->targetpc = BRANCH_TARGET_DYNAMIC;
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return TRUE;
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}
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return FALSE;
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}
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/*-------------------------------------------------
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describe_instruction_regimm - build a
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description of a single instruction in the
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'regimm' group
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-------------------------------------------------*/
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static int describe_instruction_regimm(rsp_state *rsp, UINT32 op, opcode_desc *desc)
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{
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switch (RTREG)
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{
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case 0x00: /* BLTZ */
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case 0x01: /* BGEZ */
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if (RTREG == 0x01 && RSREG == 0)
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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else
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{
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
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}
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desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
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desc->delayslots = 1;
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desc->skipslots = (RTREG & 0x02) ? 1 : 0;
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return TRUE;
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case 0x10: /* BLTZAL */
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case 0x11: /* BGEZAL */
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if (RTREG == 0x11 && RSREG == 0)
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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else
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{
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desc->regin[0] |= REGFLAG_R(RSREG);
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desc->flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
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}
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desc->regout[0] |= REGFLAG_R(31);
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desc->targetpc = ((desc->pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
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desc->delayslots = 1;
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desc->skipslots = (RTREG & 0x02) ? 1 : 0;
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return TRUE;
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}
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return FALSE;
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}
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/*-------------------------------------------------
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describe_instruction_cop0 - build a
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description of a single instruction in the
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COP0 group
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-------------------------------------------------*/
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static int describe_instruction_cop0(rsp_state *rsp, UINT32 op, opcode_desc *desc)
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{
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switch (RSREG)
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{
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case 0x00: /* MFCz */
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desc->regout[0] |= REGFLAG_R(RTREG);
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return TRUE;
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case 0x04: /* MTCz */
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desc->regin[0] |= REGFLAG_R(RTREG);
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return TRUE;
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}
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return FALSE;
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}
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/*-------------------------------------------------
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describe_instruction_cop2 - build a
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description of a single instruction in the
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COP2 group
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-------------------------------------------------*/
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static int describe_instruction_cop2(rsp_state *rsp, UINT32 op, opcode_desc *desc)
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{
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switch (RSREG)
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{
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case 0x00: /* MFCz */
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case 0x02: /* CFCz */
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desc->regout[0] |= REGFLAG_R(RTREG);
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return TRUE;
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case 0x04: /* MTCz */
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case 0x06: /* CTCz */
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desc->regin[0] |= REGFLAG_R(RTREG);
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return TRUE;
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}
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return FALSE;
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}
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