yz70s a81cb8469e i386: add a simple cache to the athlon xp processor (nw) ... . A single 64K 2-way set associative cache Used for both instructions and data Enabled only for addresses in the first megabyte Works always in writeback mode . It is needed by the nforce motherboard bios that uses it to simulate a block of ram at address d0000 before ddr ram is configured		2019-03-14 21:03:12 +01:00
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build	(nw) Further layout work:	2018-08-02 23:11:17 +10:00
font	srcclean and manual cleanups (nw)	2017-12-24 15:03:04 +11:00
minimaws	minimaws: expose RAM size	2018-03-27 01:40:15 +11:00
resources	windows rc: use emulator name for description (this is the application title that shows up on task manager for example) (nw)	2017-11-05 14:58:09 +01:00
src	i386: add a simple cache to the athlon xp processor (nw)	2019-03-14 21:03:12 +01:00
target	fix build (nw)	2019-03-14 11:47:30 -04:00
xslt	Add some example XSLTs that operate on -listxml output	2019-01-03 03:38:25 +11:00
extlib.lua	Added possibility of building using system pugixml	2018-03-27 10:19:22 +11:00
genie.lua	further quieting of MS-LLVM (nw)	2019-02-25 14:48:37 -08:00
toolchain.lua	Android compile fix (#4395)	2018-12-11 19:38:27 -05:00