mirror of
https://github.com/holub/mame
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946 lines
31 KiB
C
946 lines
31 KiB
C
/***************************************************************************
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dsp32.c
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Core implementation for the portable DSP32 emulator.
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Written by Aaron Giles
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****************************************************************************
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Important note:
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At this time, the emulator is rather incomplete. However, it is
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sufficiently complete to run both Race Drivin' and Hard Drivin's
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Airborne, which is all I was after.
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Things that still need to be implemented:
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* interrupts
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* carry-reverse add operations
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* do loops
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* ieee/dsp conversions
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* input/output conversion
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* serial I/O
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In addition, there are several optimizations enabled which make
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assumptions about the code which may not be valid for other
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applications. Check dsp32ops.c for details.
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***************************************************************************/
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#include "debugger.h"
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#include "deprecat.h"
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#include "dsp32.h"
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/***************************************************************************
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DEBUGGING
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***************************************************************************/
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#define DETECT_MISALIGNED_MEMORY 0
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/***************************************************************************
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CONSTANTS
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***************************************************************************/
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/* internal register numbering for PIO registers */
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#define PIO_PAR 0
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#define PIO_PDR 1
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#define PIO_EMR 2
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#define PIO_ESR 3
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#define PIO_PCR 4
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#define PIO_PIR 5
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#define PIO_PARE 6
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#define PIO_PDR2 7
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#define PIO_RESERVED 8
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#define UPPER (0x00ff << 8)
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#define LOWER (0xff00 << 8)
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/* bits in the PCR register */
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#define PCR_RESET 0x001
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#define PCR_REGMAP 0x002
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#define PCR_ENI 0x004
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#define PCR_DMA 0x008
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#define PCR_AUTO 0x010
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#define PCR_PDFs 0x020
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#define PCR_PIFs 0x040
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#define PCR_RES 0x080
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#define PCR_DMA32 0x100
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#define PCR_PIO16 0x200
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#define PCR_FLG 0x400
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/* internal flag bits */
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#define UFLAGBIT 1
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#define VFLAGBIT 2
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/***************************************************************************
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MACROS
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***************************************************************************/
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/* register mapping */
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#define R0 r[0]
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#define R1 r[1]
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#define R2 r[2]
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#define R3 r[3]
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#define R4 r[4]
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#define R5 r[5]
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#define R6 r[6]
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#define R7 r[7]
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#define R8 r[8]
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#define R9 r[9]
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#define R10 r[10]
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#define R11 r[11]
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#define R12 r[12]
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#define R13 r[13]
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#define R14 r[14]
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#define PC r[15]
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#define R0_ALT r[16]
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#define R15 r[17]
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#define R16 r[18]
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#define R17 r[19]
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#define R18 r[20]
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#define R19 r[21]
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#define RMM r[22]
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#define RPP r[23]
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#define R20 r[24]
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#define R21 r[25]
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#define DAUC r[26]
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#define IOC r[27]
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#define R22 r[29]
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#define PCSH r[30]
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#define A0 a[0]
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#define A1 a[1]
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#define A2 a[2]
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#define A3 a[3]
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#define A_0 a[4]
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#define A_1 a[5]
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#define OP dsp32.op
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#define zFLAG ((dsp32.nzcflags & 0xffffff) == 0)
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#define nFLAG ((dsp32.nzcflags & 0x800000) != 0)
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#define cFLAG ((dsp32.nzcflags & 0x1000000) != 0)
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#define vFLAG ((dsp32.vflags & 0x800000) != 0)
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#define ZFLAG (dsp32.NZflags == 0)
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#define NFLAG (dsp32.NZflags < 0)
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#define UFLAG (dsp32.VUflags & UFLAGBIT)
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#define VFLAG (dsp32.VUflags & VFLAGBIT)
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/***************************************************************************
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STRUCTURES & TYPEDEFS
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***************************************************************************/
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/* DSP32 Registers */
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typedef struct
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{
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/* core registers */
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UINT32 r[32];
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UINT32 pin, pout;
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UINT32 ivtp;
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UINT32 nzcflags;
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UINT32 vflags;
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double a[6];
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double NZflags;
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UINT8 VUflags;
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double abuf[4];
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UINT8 abufreg[4];
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UINT8 abufVUflags[4];
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UINT8 abufNZflags[4];
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int abufcycle[4];
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int abuf_index;
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INT32 mbufaddr[4];
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UINT32 mbufdata[4];
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int mbuf_index;
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UINT16 par;
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UINT8 pare;
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UINT16 pdr;
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UINT16 pdr2;
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UINT16 pir;
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UINT16 pcr;
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UINT16 emr;
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UINT8 esr;
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UINT16 pcw;
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UINT8 piop;
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UINT32 ibuf;
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UINT32 isr;
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UINT32 obuf;
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UINT32 osr;
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/* internal stuff */
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UINT8 lastpins;
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UINT32 ppc;
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UINT32 op;
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int interrupt_cycles;
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void (*output_pins_changed)(UINT32 pins);
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const device_config *device;
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const address_space *program;
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} dsp32_regs;
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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static CPU_RESET( dsp32c );
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/***************************************************************************
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PRIVATE GLOBAL VARIABLES
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***************************************************************************/
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static dsp32_regs dsp32;
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static int dsp32_icount;
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/***************************************************************************
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MEMORY ACCESSORS
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***************************************************************************/
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#define ROPCODE(pc) memory_decrypted_read_dword(dsp32.program, pc)
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#define RBYTE(addr) memory_read_byte_32le(dsp32.program, addr)
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#define WBYTE(addr,data) memory_write_byte_32le(dsp32.program, (addr), data)
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#if (!DETECT_MISALIGNED_MEMORY)
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#define RWORD(addr) memory_read_word_32le(dsp32.program, addr)
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#define WWORD(addr,data) memory_write_word_32le(dsp32.program, (addr), data)
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#define RLONG(addr) memory_read_dword_32le(dsp32.program, addr)
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#define WLONG(addr,data) memory_write_dword_32le(dsp32.program, (addr), data)
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#else
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INLINE UINT16 RWORD(offs_t addr)
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{
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UINT16 data;
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if (addr & 1) fprintf(stderr, "Unaligned word read @ %06X, PC=%06X\n", addr, dsp32.PC);
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data = memory_read_word_32le(dsp32.program, addr);
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return data;
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}
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INLINE UINT32 RLONG(offs_t addr)
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{
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UINT32 data;
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if (addr & 3) fprintf(stderr, "Unaligned long read @ %06X, PC=%06X\n", addr, dsp32.PC);
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data = memory_write_word_32le(dsp32.program, addr);
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return data;
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}
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INLINE void WWORD(offs_t addr, UINT16 data)
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{
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if (addr & 1) fprintf(stderr, "Unaligned word write @ %06X, PC=%06X\n", addr, dsp32.PC);
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memory_read_dword_32le(dsp32.program, (addr), data);
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}
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INLINE void WLONG(offs_t addr, UINT32 data)
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{
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if (addr & 3) fprintf(stderr, "Unaligned long write @ %06X, PC=%06X\n", addr, dsp32.PC);
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memory_write_dword_32le(dsp32.program, (addr), data);
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}
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#endif
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/***************************************************************************
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EXECEPTION HANDLING
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***************************************************************************/
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#ifdef UNUSED_FUNCTION
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INLINE void generate_exception(int exception)
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{
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}
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#endif
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#ifdef UNUSED_FUNCTION
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INLINE void invalid_instruction(UINT32 op)
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{
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}
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#endif
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/***************************************************************************
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IRQ HANDLING
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***************************************************************************/
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static void check_irqs(void)
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{
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/* finish me! */
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}
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static void set_irq_line(int irqline, int state)
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{
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/* finish me! */
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}
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/***************************************************************************
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REGISTER HANDLING
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***************************************************************************/
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static void update_pcr(UINT16 newval)
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{
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UINT16 oldval = dsp32.pcr;
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dsp32.pcr = newval;
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/* reset the chip if we get a reset */
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if ((oldval & PCR_RESET) == 0 && (newval & PCR_RESET) != 0)
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CPU_RESET_NAME(dsp32c)(dsp32.device);
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/* track the state of the output pins */
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if (dsp32.output_pins_changed)
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{
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UINT16 newoutput = ((newval & (PCR_PIFs | PCR_ENI)) == (PCR_PIFs | PCR_ENI)) ? DSP32_OUTPUT_PIF : 0;
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if (newoutput != dsp32.lastpins)
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{
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dsp32.lastpins = newoutput;
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(*dsp32.output_pins_changed)(newoutput);
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}
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}
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}
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/***************************************************************************
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CONTEXT SWITCHING
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***************************************************************************/
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static CPU_GET_CONTEXT( dsp32c )
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{
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/* copy the context */
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if (dst)
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*(dsp32_regs *)dst = dsp32;
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}
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static CPU_SET_CONTEXT( dsp32c )
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{
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/* copy the context */
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if (src)
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dsp32 = *(dsp32_regs *)src;
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/* check for IRQs */
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check_irqs();
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}
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/***************************************************************************
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INITIALIZATION AND SHUTDOWN
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***************************************************************************/
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static CPU_INIT( dsp32c )
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{
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const dsp32_config *configdata = device->static_config;
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/* copy in config data */
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if (configdata)
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dsp32.output_pins_changed = configdata->output_pins_changed;
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dsp32.device = device;
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dsp32.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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}
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static CPU_RESET( dsp32c )
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{
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/* reset goes to 0 */
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dsp32.PC = 0;
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/* clear some registers */
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dsp32.pcw &= 0x03ff;
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update_pcr(dsp32.pcr & PCR_RESET);
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dsp32.esr = 0;
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dsp32.emr = 0xffff;
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/* initialize fixed registers */
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dsp32.R0 = dsp32.R0_ALT = 0;
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dsp32.RMM = -1;
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dsp32.RPP = 1;
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dsp32.A_0 = 0.0;
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dsp32.A_1 = 1.0;
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/* init internal stuff */
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dsp32.abufcycle[0] = dsp32.abufcycle[1] = dsp32.abufcycle[2] = dsp32.abufcycle[3] = 12345678;
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dsp32.mbufaddr[0] = dsp32.mbufaddr[1] = dsp32.mbufaddr[2] = dsp32.mbufaddr[3] = 1;
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}
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static CPU_EXIT( dsp32c )
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{
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}
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/***************************************************************************
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CORE INCLUDE
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***************************************************************************/
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#include "dsp32ops.c"
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/***************************************************************************
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CORE EXECUTION LOOP
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***************************************************************************/
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static CPU_EXECUTE( dsp32c )
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{
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/* skip if halted */
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if ((dsp32.pcr & PCR_RESET) == 0)
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return cycles;
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/* count cycles and interrupt cycles */
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dsp32_icount = cycles;
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dsp32_icount -= dsp32.interrupt_cycles;
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dsp32.interrupt_cycles = 0;
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/* update buffered accumulator values */
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dsp32.abufcycle[0] += dsp32_icount;
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dsp32.abufcycle[1] += dsp32_icount;
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dsp32.abufcycle[2] += dsp32_icount;
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dsp32.abufcycle[3] += dsp32_icount;
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while (dsp32_icount > 0)
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execute_one();
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dsp32_icount -= dsp32.interrupt_cycles;
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dsp32.interrupt_cycles = 0;
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/* normalize buffered accumulator values */
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dsp32.abufcycle[0] -= dsp32_icount;
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dsp32.abufcycle[1] -= dsp32_icount;
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dsp32.abufcycle[2] -= dsp32_icount;
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dsp32.abufcycle[3] -= dsp32_icount;
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return cycles - dsp32_icount;
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}
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/***************************************************************************
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DISASSEMBLY HOOK
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***************************************************************************/
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static CPU_DISASSEMBLE( dsp32c )
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{
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extern unsigned dasm_dsp32(char *, unsigned, UINT32);
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return dasm_dsp32(buffer, pc, oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24));
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}
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/***************************************************************************
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PARALLEL INTERFACE WRITES
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***************************************************************************/
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static const UINT32 regmap[4][16] =
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{
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{ /* DSP32 compatible mode */
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PIO_PAR|LOWER, PIO_PAR|UPPER, PIO_PDR|LOWER, PIO_PDR|UPPER,
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PIO_EMR|LOWER, PIO_EMR|UPPER, PIO_ESR|LOWER, PIO_PCR|LOWER,
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PIO_PIR|UPPER, PIO_PIR|UPPER, PIO_PIR|UPPER, PIO_PIR|UPPER,
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PIO_PIR|UPPER, PIO_PIR|UPPER, PIO_PIR|UPPER, PIO_PIR|UPPER
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},
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{ /* DSP32C 8-bit mode */
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PIO_PAR|LOWER, PIO_PAR|UPPER, PIO_PDR|LOWER, PIO_PDR|UPPER,
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PIO_EMR|LOWER, PIO_EMR|UPPER, PIO_ESR|LOWER, PIO_PCR|LOWER,
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PIO_PIR|LOWER, PIO_PIR|UPPER, PIO_PCR|UPPER, PIO_PARE|LOWER,
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PIO_PDR2|LOWER,PIO_PDR2|UPPER,PIO_RESERVED, PIO_RESERVED
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},
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{ /* DSP32C illegal mode */
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PIO_RESERVED, PIO_RESERVED, PIO_RESERVED, PIO_RESERVED,
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PIO_RESERVED, PIO_RESERVED, PIO_RESERVED, PIO_RESERVED,
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PIO_RESERVED, PIO_RESERVED, PIO_RESERVED, PIO_RESERVED,
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PIO_RESERVED, PIO_RESERVED, PIO_RESERVED, PIO_RESERVED
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},
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{ /* DSP32C 16-bit mode */
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PIO_PAR, PIO_RESERVED, PIO_PDR, PIO_RESERVED,
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PIO_EMR, PIO_RESERVED, PIO_ESR|LOWER, PIO_PCR,
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PIO_PIR, PIO_RESERVED, PIO_RESERVED, PIO_PARE|LOWER,
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PIO_PDR2, PIO_RESERVED, PIO_RESERVED, PIO_RESERVED
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}
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};
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/***************************************************************************
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PARALLEL INTERFACE WRITES
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***************************************************************************/
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INLINE void dma_increment(void)
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{
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if (dsp32.pcr & PCR_AUTO)
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{
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int amount = (dsp32.pcr & PCR_DMA32) ? 4 : 2;
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dsp32.par += amount;
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if (dsp32.par < amount)
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dsp32.pare++;
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}
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}
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INLINE void dma_load(void)
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{
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/* only process if DMA is enabled */
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if (dsp32.pcr & PCR_DMA)
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{
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UINT32 addr = dsp32.par | (dsp32.pare << 16);
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/* 16-bit case */
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if (!(dsp32.pcr & PCR_DMA32))
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dsp32.pdr = RWORD(addr & 0xfffffe);
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/* 32-bit case */
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else
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{
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UINT32 temp = RLONG(addr & 0xfffffc);
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dsp32.pdr = temp >> 16;
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dsp32.pdr2 = temp & 0xffff;
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}
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/* set the PDF flag to indicate we have data ready */
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update_pcr(dsp32.pcr | PCR_PDFs);
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}
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}
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INLINE void dma_store(void)
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{
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/* only process if DMA is enabled */
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if (dsp32.pcr & PCR_DMA)
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{
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UINT32 addr = dsp32.par | (dsp32.pare << 16);
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/* 16-bit case */
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if (!(dsp32.pcr & PCR_DMA32))
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WWORD(addr & 0xfffffe, dsp32.pdr);
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/* 32-bit case */
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else
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WLONG(addr & 0xfffffc, (dsp32.pdr << 16) | dsp32.pdr2);
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/* clear the PDF flag to indicate we have taken the data */
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update_pcr(dsp32.pcr & ~PCR_PDFs);
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}
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}
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void dsp32c_pio_w(int cpunum, int reg, int data)
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{
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UINT16 mask;
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UINT8 mode;
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cpu_push_context(Machine->cpu[cpunum]);
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/* look up register and mask */
|
|
mode = ((dsp32.pcr >> 8) & 2) | ((dsp32.pcr >> 1) & 1);
|
|
reg = regmap[mode][reg];
|
|
mask = reg >> 8;
|
|
if (mask == 0x00ff) data <<= 8;
|
|
data &= ~mask;
|
|
reg &= 0xff;
|
|
|
|
/* switch off the register */
|
|
switch (reg)
|
|
{
|
|
case PIO_PAR:
|
|
dsp32.par = (dsp32.par & mask) | data;
|
|
|
|
/* trigger a load on the upper half */
|
|
if (!(mask & 0xff00))
|
|
dma_load();
|
|
break;
|
|
|
|
case PIO_PARE:
|
|
dsp32.pare = (dsp32.pare & mask) | data;
|
|
break;
|
|
|
|
case PIO_PDR:
|
|
dsp32.pdr = (dsp32.pdr & mask) | data;
|
|
|
|
/* trigger a write and PDF setting on the upper half */
|
|
if (!(mask & 0xff00))
|
|
{
|
|
dma_store();
|
|
dma_increment();
|
|
}
|
|
break;
|
|
|
|
case PIO_PDR2:
|
|
dsp32.pdr2 = (dsp32.pdr2 & mask) | data;
|
|
break;
|
|
|
|
case PIO_EMR:
|
|
dsp32.emr = (dsp32.emr & mask) | data;
|
|
break;
|
|
|
|
case PIO_ESR:
|
|
dsp32.esr = (dsp32.esr & mask) | data;
|
|
break;
|
|
|
|
case PIO_PCR:
|
|
mask |= 0x0060;
|
|
data &= ~mask;
|
|
update_pcr((dsp32.pcr & mask) | data);
|
|
break;
|
|
|
|
case PIO_PIR:
|
|
dsp32.pir = (dsp32.pir & mask) | data;
|
|
|
|
/* set PIF on upper half */
|
|
if (!(mask & 0xff00))
|
|
update_pcr(dsp32.pcr | PCR_PIFs);
|
|
break;
|
|
|
|
/* error case */
|
|
default:
|
|
logerror("dsp32_pio_w called on invalid register %d\n", reg);
|
|
break;
|
|
}
|
|
|
|
cpu_pop_context();
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
PARALLEL INTERFACE READS
|
|
***************************************************************************/
|
|
|
|
int dsp32c_pio_r(int cpunum, int reg)
|
|
{
|
|
UINT16 mask, result = 0xffff;
|
|
UINT8 mode, shift = 0;
|
|
|
|
cpu_push_context(Machine->cpu[cpunum]);
|
|
|
|
/* look up register and mask */
|
|
mode = ((dsp32.pcr >> 8) & 2) | ((dsp32.pcr >> 1) & 1);
|
|
reg = regmap[mode][reg];
|
|
mask = reg >> 8;
|
|
if (mask == 0x00ff) mask = 0xff00, shift = 8;
|
|
reg &= 0xff;
|
|
|
|
/* switch off the register */
|
|
switch (reg)
|
|
{
|
|
case PIO_PAR:
|
|
result = dsp32.par | 1;
|
|
break;
|
|
|
|
case PIO_PARE:
|
|
result = dsp32.pare;
|
|
break;
|
|
|
|
case PIO_PDR:
|
|
result = dsp32.pdr;
|
|
|
|
/* trigger an increment on the lower half */
|
|
if (shift != 8)
|
|
dma_increment();
|
|
|
|
/* trigger a fetch on the upper half */
|
|
if (!(mask & 0xff00))
|
|
dma_load();
|
|
break;
|
|
|
|
case PIO_PDR2:
|
|
result = dsp32.pdr2;
|
|
break;
|
|
|
|
case PIO_EMR:
|
|
result = dsp32.emr;
|
|
break;
|
|
|
|
case PIO_ESR:
|
|
result = dsp32.esr;
|
|
break;
|
|
|
|
case PIO_PCR:
|
|
result = dsp32.pcr;
|
|
break;
|
|
|
|
case PIO_PIR:
|
|
if (!(mask & 0xff00))
|
|
update_pcr(dsp32.pcr & ~PCR_PIFs); /* clear PIFs */
|
|
result = dsp32.pir;
|
|
break;
|
|
|
|
/* error case */
|
|
default:
|
|
logerror("dsp32_pio_w called on invalid register %d\n", reg);
|
|
break;
|
|
}
|
|
|
|
cpu_pop_context();
|
|
return (result >> shift) & ~mask;
|
|
}
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
* Generic set_info
|
|
**************************************************************************/
|
|
|
|
static CPU_SET_INFO( dsp32c )
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are set as 64-bit signed integers --- */
|
|
case CPUINFO_INT_INPUT_STATE + DSP32_IRQ0: set_irq_line(DSP32_IRQ0, info->i); break;
|
|
case CPUINFO_INT_INPUT_STATE + DSP32_IRQ1: set_irq_line(DSP32_IRQ1, info->i); break;
|
|
|
|
/* CAU */
|
|
case CPUINFO_INT_PC:
|
|
case CPUINFO_INT_REGISTER + DSP32_PC: dsp32.PC = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R0: dsp32.R0 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R1: dsp32.R1 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R2: dsp32.R2 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R3: dsp32.R3 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R4: dsp32.R4 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R5: dsp32.R5 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R6: dsp32.R6 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R7: dsp32.R7 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R8: dsp32.R8 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R9: dsp32.R9 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R10: dsp32.R10 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R11: dsp32.R11 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R12: dsp32.R12 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R13: dsp32.R13 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R14: dsp32.R14 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R15: dsp32.R15 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R16: dsp32.R16 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R17: dsp32.R17 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R18: dsp32.R18 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R19: dsp32.R19 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R20: dsp32.R20 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_SP:
|
|
case CPUINFO_INT_REGISTER + DSP32_R21: dsp32.R21 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R22: dsp32.R22 = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PIN: dsp32.pin = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_POUT: dsp32.pout = info->i & 0xffffff; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_IVTP: dsp32.ivtp = info->i & 0xffffff; break;
|
|
|
|
/* DAU */
|
|
case CPUINFO_INT_REGISTER + DSP32_A0: dsp32.A0 = info->i; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_A1: dsp32.A1 = info->i; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_A2: dsp32.A2 = info->i; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_A3: dsp32.A3 = info->i; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_DAUC: dsp32.DAUC = info->i; break;
|
|
|
|
/* PIO */
|
|
case CPUINFO_INT_REGISTER + DSP32_PAR: dsp32.par = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PDR: dsp32.pdr = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PIR: dsp32.pir = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PCR: update_pcr(info->i & 0x3ff); break;
|
|
case CPUINFO_INT_REGISTER + DSP32_EMR: dsp32.emr = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_ESR: dsp32.esr = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PCW: dsp32.pcw = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PIOP: dsp32.piop = info->i; break;
|
|
|
|
/* SIO */
|
|
case CPUINFO_INT_REGISTER + DSP32_IBUF: dsp32.ibuf = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_ISR: dsp32.isr = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_OBUF: dsp32.obuf = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_OSR: dsp32.osr = info->i; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_IOC: dsp32.IOC = info->i & 0xfffff; break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
* Generic get_info
|
|
**************************************************************************/
|
|
|
|
CPU_GET_INFO( dsp32c )
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(dsp32); break;
|
|
case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
|
|
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
|
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
|
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
|
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
|
|
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
|
|
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
|
|
case CPUINFO_INT_MIN_CYCLES: info->i = 4; break;
|
|
case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
|
|
|
|
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
|
|
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 24; break;
|
|
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
|
|
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
|
|
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
|
|
|
case CPUINFO_INT_INPUT_STATE + DSP32_IRQ0: info->i = 0; break;
|
|
case CPUINFO_INT_INPUT_STATE + DSP32_IRQ1: info->i = 0; break;
|
|
|
|
case CPUINFO_INT_PREVIOUSPC: info->i = dsp32.ppc; break;
|
|
|
|
/* CAU */
|
|
case CPUINFO_INT_PC:
|
|
case CPUINFO_INT_REGISTER + DSP32_PC: info->i = dsp32.PC; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R0: info->i = dsp32.R0; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R1: info->i = dsp32.R1; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R2: info->i = dsp32.R2; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R3: info->i = dsp32.R3; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R4: info->i = dsp32.R4; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R5: info->i = dsp32.R5; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R6: info->i = dsp32.R6; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R7: info->i = dsp32.R7; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R8: info->i = dsp32.R8; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R9: info->i = dsp32.R9; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R10: info->i = dsp32.R10; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R11: info->i = dsp32.R11; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R12: info->i = dsp32.R12; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R13: info->i = dsp32.R13; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R14: info->i = dsp32.R14; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R15: info->i = dsp32.R15; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R16: info->i = dsp32.R16; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R17: info->i = dsp32.R17; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R18: info->i = dsp32.R18; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R19: info->i = dsp32.R19; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R20: info->i = dsp32.R20; break;
|
|
case CPUINFO_INT_SP:
|
|
case CPUINFO_INT_REGISTER + DSP32_R21: info->i = dsp32.R21; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_R22: info->i = dsp32.R22; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PIN: info->i = dsp32.pin; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_POUT: info->i = dsp32.pout; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_IVTP: info->i = dsp32.ivtp; break;
|
|
|
|
/* DAU */
|
|
case CPUINFO_INT_REGISTER + DSP32_A0: info->i = dsp32.A0; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_A1: info->i = dsp32.A1; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_A2: info->i = dsp32.A2; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_A3: info->i = dsp32.A3; /* fix me -- very wrong */ break;
|
|
case CPUINFO_INT_REGISTER + DSP32_DAUC: info->i = dsp32.DAUC; break;
|
|
|
|
/* PIO */
|
|
case CPUINFO_INT_REGISTER + DSP32_PAR: info->i = dsp32.par; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PDR: info->i = dsp32.pdr; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PIR: info->i = dsp32.pir; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PCR: info->i = dsp32.pcr; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_EMR: info->i = dsp32.emr; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_ESR: info->i = dsp32.esr; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PCW: info->i = dsp32.pcw; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_PIOP: info->i = dsp32.piop; break;
|
|
|
|
/* SIO */
|
|
case CPUINFO_INT_REGISTER + DSP32_IBUF: info->i = dsp32.ibuf; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_ISR: info->i = dsp32.isr; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_OBUF: info->i = dsp32.obuf; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_OSR: info->i = dsp32.osr; break;
|
|
case CPUINFO_INT_REGISTER + DSP32_IOC: info->i = dsp32.IOC; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
|
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(dsp32c); break;
|
|
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &dsp32_icount; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case CPUINFO_STR_NAME: strcpy(info->s, "DSP32C"); break;
|
|
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Lucent DSP32"); break;
|
|
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break;
|
|
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
|
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Aaron Giles"); break;
|
|
|
|
case CPUINFO_STR_FLAGS:
|
|
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
|
NFLAG ? 'N':'.',
|
|
ZFLAG ? 'Z':'.',
|
|
UFLAG ? 'U':'.',
|
|
VFLAG ? 'V':'.',
|
|
nFLAG ? 'n':'.',
|
|
zFLAG ? 'z':'.',
|
|
cFLAG ? 'c':'.',
|
|
vFLAG ? 'v':'.');
|
|
break;
|
|
|
|
/* CAU */
|
|
case CPUINFO_STR_REGISTER + DSP32_PC: sprintf(info->s, "PC: %06X", dsp32.PC); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R0: sprintf(info->s, "R0: %06X", dsp32.R0); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R1: sprintf(info->s, "R1: %06X", dsp32.R1); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R2: sprintf(info->s, "R2: %06X", dsp32.R2); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R3: sprintf(info->s, "R3: %06X", dsp32.R3); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R4: sprintf(info->s, "R4: %06X", dsp32.R4); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R5: sprintf(info->s, "R5: %06X", dsp32.R5); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R6: sprintf(info->s, "R6: %06X", dsp32.R6); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R7: sprintf(info->s, "R7: %06X", dsp32.R7); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R8: sprintf(info->s, "R8: %06X", dsp32.R8); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R9: sprintf(info->s, "R9: %06X", dsp32.R9); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R10: sprintf(info->s, "R10:%06X", dsp32.R10); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R11: sprintf(info->s, "R11:%06X", dsp32.R11); break;
|
|
case CPUINFO_STR_REGISTER + DSP32_R12: sprintf(info->s, "R12:%06X", dsp32.R12); break;
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case CPUINFO_STR_REGISTER + DSP32_R13: sprintf(info->s, "R13:%06X", dsp32.R13); break;
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case CPUINFO_STR_REGISTER + DSP32_R14: sprintf(info->s, "R14:%06X", dsp32.R14); break;
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case CPUINFO_STR_REGISTER + DSP32_R15: sprintf(info->s, "R15:%06X", dsp32.R15); break;
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case CPUINFO_STR_REGISTER + DSP32_R16: sprintf(info->s, "R16:%06X", dsp32.R16); break;
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case CPUINFO_STR_REGISTER + DSP32_R17: sprintf(info->s, "R17:%06X", dsp32.R17); break;
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case CPUINFO_STR_REGISTER + DSP32_R18: sprintf(info->s, "R18:%06X", dsp32.R18); break;
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case CPUINFO_STR_REGISTER + DSP32_R19: sprintf(info->s, "R19:%06X", dsp32.R19); break;
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case CPUINFO_STR_REGISTER + DSP32_R20: sprintf(info->s, "R20:%06X", dsp32.R20); break;
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case CPUINFO_STR_REGISTER + DSP32_R21: sprintf(info->s, "R21:%06X", dsp32.R21); break;
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case CPUINFO_STR_REGISTER + DSP32_R22: sprintf(info->s, "R22:%06X", dsp32.R22); break;
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case CPUINFO_STR_REGISTER + DSP32_PIN: sprintf(info->s, "PIN:%06X", dsp32.pin); break;
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case CPUINFO_STR_REGISTER + DSP32_POUT: sprintf(info->s, "POUT:%06X", dsp32.pout); break;
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case CPUINFO_STR_REGISTER + DSP32_IVTP: sprintf(info->s, "IVTP:%06X", dsp32.ivtp); break;
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/* DAU */
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case CPUINFO_STR_REGISTER + DSP32_A0: sprintf(info->s, "A0:%8g", dsp32.A0); break;
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case CPUINFO_STR_REGISTER + DSP32_A1: sprintf(info->s, "A1:%8g", dsp32.A1); break;
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case CPUINFO_STR_REGISTER + DSP32_A2: sprintf(info->s, "A2:%8g", dsp32.A2); break;
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case CPUINFO_STR_REGISTER + DSP32_A3: sprintf(info->s, "A3:%8g", dsp32.A3); break;
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case CPUINFO_STR_REGISTER + DSP32_DAUC: sprintf(info->s, "DAUC:%02X", dsp32.DAUC); break;
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/* PIO */
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case CPUINFO_STR_REGISTER + DSP32_PAR: sprintf(info->s, "PAR:%08X", dsp32.par); break;
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case CPUINFO_STR_REGISTER + DSP32_PDR: sprintf(info->s, "PDR:%08X", dsp32.pdr); break;
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case CPUINFO_STR_REGISTER + DSP32_PIR: sprintf(info->s, "PIR:%04X", dsp32.pir); break;
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case CPUINFO_STR_REGISTER + DSP32_PCR: sprintf(info->s, "PCR:%03X", dsp32.pcr); break;
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case CPUINFO_STR_REGISTER + DSP32_EMR: sprintf(info->s, "EMR:%04X", dsp32.emr); break;
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case CPUINFO_STR_REGISTER + DSP32_ESR: sprintf(info->s, "ESR:%02X", dsp32.esr); break;
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case CPUINFO_STR_REGISTER + DSP32_PCW: sprintf(info->s, "PCW:%04X", dsp32.pcw); break;
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case CPUINFO_STR_REGISTER + DSP32_PIOP: sprintf(info->s, "PIOP:%02X", dsp32.piop); break;
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/* SIO */
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case CPUINFO_STR_REGISTER + DSP32_IBUF: sprintf(info->s, "IBUF:%08X", dsp32.ibuf); break;
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case CPUINFO_STR_REGISTER + DSP32_ISR: sprintf(info->s, "ISR:%08X", dsp32.isr); break;
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case CPUINFO_STR_REGISTER + DSP32_OBUF: sprintf(info->s, "OBUF:%08X", dsp32.obuf); break;
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case CPUINFO_STR_REGISTER + DSP32_OSR: sprintf(info->s, "OSR:%08X", dsp32.osr); break;
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case CPUINFO_STR_REGISTER + DSP32_IOC: sprintf(info->s, "IOC:%05X", dsp32.IOC); break;
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}
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}
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