mirror of
https://github.com/holub/mame
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5a57d03cfe
* Separated Acorn IOC and MEMC into devices. * Emulated 8051-based serial keyboard. * acorn_machine/memc.cpp: Ensure only one logical page is mapped to a single physical page. * Fixed RISC OS POST IOC register test. * aa310.cpp: Added debug code to display RISC OS POST failures. -machine/archimedes_keyb.cpp: Dumped Acorn Archimedes keyboard microcontroller. [Phil Pemberton]
412 lines
9.9 KiB
C++
412 lines
9.9 KiB
C++
// license:LGPL-2.1+
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// copyright-holders:Angelo Salese, R. Belmont, Juergen Buchmueller, Sandro Ronco
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/**************************************************************************************************
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Acorn RISC Machine Input/Output Controller (IOC)
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TODO:
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- support IOEB used in the ARM250 (partially implemented in aristmk5.cpp)
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**************************************************************************************************/
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#include "emu.h"
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#include "acorn_ioc.h"
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//#define VERBOSE 1
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(ACORN_IOC, acorn_ioc_device, "ioc", "Acorn IOC")
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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acorn_ioc_device::acorn_ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, ACORN_IOC, tag, owner, clock)
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, device_serial_interface(mconfig, *this)
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, m_peripherals_r(*this)
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, m_peripherals_w(*this)
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, m_giop_r(*this)
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, m_giop_w(*this)
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, m_irq_w(*this)
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, m_fiq_w(*this)
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, m_kout_w(*this)
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, m_baud_w(*this)
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{
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}
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void acorn_ioc_device::device_resolve_objects()
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{
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m_peripherals_r.resolve_all_safe(0xffffffff);
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m_peripherals_w.resolve_all_safe();
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m_giop_r.resolve_all_safe(1);
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m_giop_w.resolve_all_safe();
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m_irq_w.resolve_safe();
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m_fiq_w.resolve_safe();
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m_kout_w.resolve_safe();
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m_baud_w.resolve();
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}
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void acorn_ioc_device::device_start()
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{
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for (int i=0; i <4; i++)
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m_timers[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(acorn_ioc_device::timer_tick), this));
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save_item(NAME(m_ir));
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save_item(NAME(m_if));
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save_item(NAME(m_baud));
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save_item(NAME(m_timercnt));
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save_item(NAME(m_timerout));
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save_item(NAME(m_regs));
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}
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void acorn_ioc_device::device_reset()
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{
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std::fill(std::begin(m_regs), std::end(m_regs), 0);
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m_regs[IRQ_STATUS_A] = 0x10 | 0x80; // set up POR (Power On Reset) and Force IRQ at start-up
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m_regs[IRQ_STATUS_B] = 0x40; // set up KART Tx empty
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m_regs[FIQ_STATUS] = 0x80; // set up Force FIQ
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m_ir = CLEAR_LINE;
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m_if = CLEAR_LINE;
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m_baud = CLEAR_LINE;
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// KART interface
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set_data_frame(1, 8, PARITY_NONE, STOP_BITS_2);
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set_rate(31250);
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for (int i = 0; i < 6; i++)
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m_giop_w[i](1);
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for (int i=0; i < 2; i++)
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{
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m_timercnt[i] = 0;
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m_timerout[i] = 0;
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set_timer(i);
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}
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transmit_register_reset();
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receive_register_reset();
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}
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void acorn_ioc_device::map(address_map &map)
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{
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// Typical configuration
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// IOA[2:6] --> A[2:6] Internal registers address
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// IOA[16:18] --> B[0:2] Peripherals select
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// IOA[19:20] --> T[0:1] Peripherals access timing
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// IOA[21] --> CS Chip select
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map(0x00200000, 0x0020007f).mirror(0x0018ff80).rw(FUNC(acorn_ioc_device::registers_r), FUNC(acorn_ioc_device::registers_w));
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map(0x00210000, 0x0021ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<1>), FUNC(acorn_ioc_device::periph_w<1>));
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map(0x00220000, 0x0022ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<2>), FUNC(acorn_ioc_device::periph_w<2>));
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map(0x00230000, 0x0023ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<3>), FUNC(acorn_ioc_device::periph_w<3>));
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map(0x00240000, 0x0024ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<4>), FUNC(acorn_ioc_device::periph_w<4>));
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map(0x00250000, 0x0025ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<5>), FUNC(acorn_ioc_device::periph_w<5>));
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map(0x00260000, 0x0026ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<6>), FUNC(acorn_ioc_device::periph_w<6>));
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map(0x00270000, 0x0027ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<7>), FUNC(acorn_ioc_device::periph_w<7>));
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}
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TIMER_CALLBACK_MEMBER(acorn_ioc_device::timer_tick)
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{
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// all timers always run
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set_timer(param);
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// but only timers 0 and 1 generate IRQs
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switch (param)
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{
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case 0:
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change_interrupt(IRQ_STATUS_A, 0x20, ASSERT_LINE);
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break;
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case 1:
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change_interrupt(IRQ_STATUS_A, 0x40, ASSERT_LINE);
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break;
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case 2:
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m_baud ^= 1;
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m_baud_w(m_baud ? ASSERT_LINE : CLEAR_LINE);
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break;
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}
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}
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void acorn_ioc_device::change_interrupt(int reg, uint8_t mask, int state)
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{
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if (state)
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m_regs[reg] |= mask;
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else
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m_regs[reg] &= ~mask;
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update_interrups();
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}
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void acorn_ioc_device::tra_complete()
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{
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change_interrupt(IRQ_STATUS_B, 0x40, ASSERT_LINE); // KART Rx empty
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}
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void acorn_ioc_device::rcv_complete()
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{
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receive_register_extract();
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m_regs[KART] = get_received_char();
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change_interrupt(IRQ_STATUS_B, 0x80, ASSERT_LINE); // KART Rx full
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}
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void acorn_ioc_device::tra_callback()
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{
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m_kout_w(transmit_register_get_data_bit());
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}
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void acorn_ioc_device::set_timer(int tmr)
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{
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double freq = 0;
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switch (tmr)
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{
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case 0: // Timers
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case 1:
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if (m_timercnt[tmr] == 0)
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m_timers[tmr]->adjust(attotime::never, tmr);
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else
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m_timers[tmr]->adjust(attotime::from_usec(m_timercnt[tmr] / 2), tmr); // TODO: ARM timings are quite off there, it should be latch and not latch/2
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break;
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case 2: // Baud generator
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freq = (double)clock() / 8 / (double)(m_timercnt[tmr] + 1);
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if (!m_baud_w.isnull())
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m_timers[tmr]->adjust(attotime::from_usec(freq), tmr);
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break;
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case 3: // KART clock
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freq = (double)clock() / 8 / (double)((m_timercnt[tmr] + 1) * 16);
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set_rate((int)freq);
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break;
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}
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}
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void acorn_ioc_device::latch_timer_cnt(int tmr)
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{
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// find out how many 2 MHz ticks have gone by
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m_timerout[tmr] = m_timercnt[tmr] - (uint32_t)m_timers[tmr]->elapsed().as_ticks(clock() / 4);
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}
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WRITE_LINE_MEMBER(acorn_ioc_device::if_w)
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{
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// set on falling edge
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if (m_if && !state)
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change_interrupt(IRQ_STATUS_A, 0x04, ASSERT_LINE);
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m_if = state;
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}
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WRITE_LINE_MEMBER(acorn_ioc_device::ir_w)
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{
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// set on rising edge
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if (!m_ir && state)
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change_interrupt(IRQ_STATUS_A, 0x08, ASSERT_LINE);
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m_ir = state;
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}
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void acorn_ioc_device::update_interrups()
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{
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if ((m_regs[IRQ_STATUS_A] & m_regs[IRQ_MASK_A]) || (m_regs[IRQ_STATUS_B] & m_regs[IRQ_MASK_B]))
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m_irq_w(ASSERT_LINE);
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else
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m_irq_w(CLEAR_LINE);
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if (m_regs[FIQ_STATUS] & m_regs[FIQ_MASK])
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m_fiq_w(ASSERT_LINE);
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else
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m_fiq_w(CLEAR_LINE);
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}
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uint32_t acorn_ioc_device::registers_r(offs_t offset, uint32_t mem_mask)
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{
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LOG("%s: IOC R %02x = %02x\n", machine().describe_context(), offset, m_regs[offset]);
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uint8_t data = 0;
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switch (offset & 0x1f)
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{
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case CONTROL:
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// x--- ---- IR line
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// -x-- ---- IF line
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// --xx xxxx GPIO (C0-C5)
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for (int i = 0; i < 6; i++)
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data |= m_giop_r[i]() << i;
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data |= m_if << 6;
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data |= m_ir << 7;
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return data;
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case KART:
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change_interrupt(IRQ_STATUS_B, 0x80, CLEAR_LINE);
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return m_regs[KART];
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case IRQ_STATUS_A:
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// x--- ---- Always 1 (force IRQ)
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// -x-- ---- Timer 1
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// --x- ---- Timer 0
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// ---x ---- POR line
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// ---- x-- IR line
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// ---- -x-- IF line
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// ---- --x- IL7 line
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// ---- ---x IL6 line
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return m_regs[IRQ_STATUS_A];
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case IRQ_REQUEST_A:
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return m_regs[IRQ_STATUS_A] & m_regs[IRQ_MASK_A];
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case IRQ_MASK_A:
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return m_regs[IRQ_MASK_A];
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case IRQ_STATUS_B:
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// x--- ---- KART Rx full
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// -x-- ---- KART Tx empty
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// --xx xxxx IL0-IL5 lines
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return m_regs[IRQ_STATUS_B];
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case IRQ_REQUEST_B:
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return m_regs[IRQ_STATUS_B] & m_regs[IRQ_MASK_B];
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case IRQ_MASK_B:
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return m_regs[IRQ_MASK_B];
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case FIQ_STATUS:
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// x--- ---- Always 1 (force FIQ)
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// -x-- ---- IL0 line
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// --xx x--- C5, C4 and C3 lines
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// ---- -x-- IF line
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// ---- --xx FH0 and FH1 lines
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return m_regs[FIQ_STATUS];
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case FIQ_REQUEST:
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return m_regs[FIQ_STATUS] & m_regs[FIQ_MASK];
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case FIQ_MASK:
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return m_regs[FIQ_MASK];
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case T0_LATCH_LO:
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return m_timerout[0] & 0xff;
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case T0_LATCH_HI:
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return (m_timerout[0] >> 8) & 0xff;
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case T1_LATCH_LO:
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return m_timerout[1] & 0xff;
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case T1_LATCH_HI:
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return (m_timerout[1] >> 8) & 0xff;
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case T2_LATCH_LO:
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return m_timerout[2] & 0xff;
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case T2_LATCH_HI:
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return (m_timerout[2] >> 8) & 0xff;
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case T3_LATCH_LO:
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return m_timerout[3] & 0xff;
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case T3_LATCH_HI:
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return (m_timerout[3] >> 8) & 0xff;
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default:
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return m_regs[offset & 0x1f];
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}
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}
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void acorn_ioc_device::registers_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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LOG("%s: IOC W %02x = %02x\n", machine().describe_context(), offset, data);
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// IOC uses the data bus lines D16-D23 as inputs, this also works with byte store (STRB)
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// because the ARM CPU repeats the byte four times across the data bus.
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if (ACCESSING_BITS_16_31)
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data >>= 16;
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switch (offset & 0x1f)
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{
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case CONTROL:
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for (int i = 0; i < 6; i++)
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m_giop_w[i](BIT(data, i));
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break;
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case KART:
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change_interrupt(IRQ_STATUS_B, 0x40, CLEAR_LINE);
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m_regs[KART] = data;
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transmit_register_setup(data);
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break;
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case IRQ_REQUEST_A:
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m_regs[IRQ_STATUS_A] &= ~(data & 0x7c);
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update_interrups(); // check pending irqs
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break;
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case IRQ_MASK_A:
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m_regs[IRQ_MASK_A] = data;
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update_interrups();
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break;
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case IRQ_MASK_B:
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m_regs[IRQ_MASK_B] = data;
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update_interrups();
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break;
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case FIQ_MASK:
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m_regs[FIQ_MASK] = data;
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update_interrups();
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break;
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case T0_LATCH_LO: case T0_LATCH_HI:
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case T1_LATCH_LO: case T1_LATCH_HI:
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case T2_LATCH_LO: case T2_LATCH_HI:
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case T3_LATCH_LO: case T3_LATCH_HI:
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m_regs[offset] = data;
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break;
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case T0_LATCH: // Timer 0 latch
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latch_timer_cnt(0);
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break;
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case T1_LATCH: // Timer 1 latch
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latch_timer_cnt(1);
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break;
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case T2_LATCH: // Timer 2 latch
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latch_timer_cnt(2);
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break;
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case T3_LATCH: // Timer 3 latch
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latch_timer_cnt(3);
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break;
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case T0_GO: // Timer 0 start
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m_timercnt[0] = m_regs[T0_LATCH_HI] << 8 | m_regs[T0_LATCH_LO];
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set_timer(0);
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break;
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case T1_GO: // Timer 1 start
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m_timercnt[1] = m_regs[T1_LATCH_HI] << 8 | m_regs[T1_LATCH_LO];
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set_timer(1);
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break;
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case T2_GO: // Timer 2 start
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m_timercnt[2] = m_regs[T2_LATCH_HI] << 8 | m_regs[T2_LATCH_LO];
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set_timer(2);
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break;
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case T3_GO: // Timer 3 start
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m_timercnt[3] = m_regs[T3_LATCH_HI] << 8 | m_regs[T3_LATCH_LO];
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set_timer(3);
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break;
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default:
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m_regs[offset & 0x1f] = data;
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break;
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}
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}
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