mirror of
https://github.com/holub/mame
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128 lines
4.7 KiB
C++
128 lines
4.7 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:David Haywood,hap
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/***************************************************************************
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Toshiba TMPZ84C011, MPUZ80/TLCS-Z80 ASSP Family
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Z80 CPU, CTC, CGC, I/O8x5
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TODO:
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- CGC (clock generator/controller)
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***************************************************************************/
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#include "emu.h"
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#include "tmpz84c011.h"
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DEFINE_DEVICE_TYPE(TMPZ84C011, tmpz84c011_device, "tmpz84c011", "Toshiba TMPZ84C011")
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void tmpz84c011_device::tmpz84c011_internal_io_map(address_map &map)
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{
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map(0x10, 0x13).mirror(0xff00).rw("tmpz84c011_ctc", FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
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map(0x50, 0x50).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_pa_r), FUNC(tmpz84c011_device::tmpz84c011_pa_w));
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map(0x51, 0x51).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_pb_r), FUNC(tmpz84c011_device::tmpz84c011_pb_w));
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map(0x52, 0x52).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_pc_r), FUNC(tmpz84c011_device::tmpz84c011_pc_w));
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map(0x30, 0x30).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_pd_r), FUNC(tmpz84c011_device::tmpz84c011_pd_w));
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map(0x40, 0x40).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_pe_r), FUNC(tmpz84c011_device::tmpz84c011_pe_w));
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map(0x54, 0x54).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_dir_pa_r), FUNC(tmpz84c011_device::tmpz84c011_dir_pa_w));
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map(0x55, 0x55).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_dir_pb_r), FUNC(tmpz84c011_device::tmpz84c011_dir_pb_w));
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map(0x56, 0x56).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_dir_pc_r), FUNC(tmpz84c011_device::tmpz84c011_dir_pc_w));
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map(0x34, 0x34).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_dir_pd_r), FUNC(tmpz84c011_device::tmpz84c011_dir_pd_w));
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map(0x44, 0x44).mirror(0xff00).rw(this, FUNC(tmpz84c011_device::tmpz84c011_dir_pe_r), FUNC(tmpz84c011_device::tmpz84c011_dir_pe_w));
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}
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tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: z80_device(mconfig, TMPZ84C011, tag, owner, clock),
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m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, address_map_constructor(FUNC(tmpz84c011_device::tmpz84c011_internal_io_map), this)),
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m_ctc(*this, "tmpz84c011_ctc"),
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m_outportsa(*this),
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m_outportsb(*this),
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m_outportsc(*this),
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m_outportsd(*this),
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m_outportse(*this),
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m_inportsa(*this),
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m_inportsb(*this),
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m_inportsc(*this),
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m_inportsd(*this),
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m_inportse(*this),
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m_zc0_cb(*this),
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m_zc1_cb(*this),
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m_zc2_cb(*this)
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{
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memset(m_pio_dir, 0, 5);
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memset(m_pio_latch, 0, 5);
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}
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device_memory_interface::space_config_vector tmpz84c011_device::memory_space_config() const
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{
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auto r = z80_device::memory_space_config();
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r.back().second = &m_io_space_config;
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return r;
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void tmpz84c011_device::device_start()
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{
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z80_device::device_start();
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// resolve callbacks
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m_outportsa.resolve_safe();
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m_outportsb.resolve_safe();
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m_outportsc.resolve_safe();
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m_outportsd.resolve_safe();
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m_outportse.resolve_safe();
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m_inportsa.resolve_safe(0);
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m_inportsb.resolve_safe(0);
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m_inportsc.resolve_safe(0);
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m_inportsd.resolve_safe(0);
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m_inportse.resolve_safe(0);
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m_zc0_cb.resolve_safe();
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m_zc1_cb.resolve_safe();
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m_zc2_cb.resolve_safe();
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// register for save states
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save_item(NAME(m_pio_dir[0]));
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save_item(NAME(m_pio_latch[0]));
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save_item(NAME(m_pio_dir[1]));
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save_item(NAME(m_pio_latch[1]));
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save_item(NAME(m_pio_dir[2]));
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save_item(NAME(m_pio_latch[2]));
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save_item(NAME(m_pio_dir[3]));
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save_item(NAME(m_pio_latch[3]));
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save_item(NAME(m_pio_dir[4]));
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save_item(NAME(m_pio_latch[4]));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void tmpz84c011_device::device_reset()
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{
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z80_device::device_reset();
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// initialize I/O
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tmpz84c011_dir_pa_w(*m_io, 0, 0); tmpz84c011_pa_w(*m_io, 0, 0);
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tmpz84c011_dir_pb_w(*m_io, 0, 0); tmpz84c011_pb_w(*m_io, 0, 0);
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tmpz84c011_dir_pc_w(*m_io, 0, 0); tmpz84c011_pc_w(*m_io, 0, 0);
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tmpz84c011_dir_pd_w(*m_io, 0, 0); tmpz84c011_pd_w(*m_io, 0, 0);
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tmpz84c011_dir_pe_w(*m_io, 0, 0); tmpz84c011_pe_w(*m_io, 0, 0);
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}
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/* CPU interface */
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MACHINE_CONFIG_START(tmpz84c011_device::device_add_mconfig)
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MCFG_DEVICE_ADD("tmpz84c011_ctc", Z80CTC, DERIVED_CLOCK(1,1) )
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MCFG_Z80CTC_INTR_CB(INPUTLINE(DEVICE_SELF, INPUT_LINE_IRQ0))
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MCFG_Z80CTC_ZC0_CB(WRITELINE(tmpz84c011_device, zc0_cb_trampoline_w))
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MCFG_Z80CTC_ZC1_CB(WRITELINE(tmpz84c011_device, zc1_cb_trampoline_w))
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MCFG_Z80CTC_ZC2_CB(WRITELINE(tmpz84c011_device, zc2_cb_trampoline_w))
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MACHINE_CONFIG_END
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