mirror of
https://github.com/holub/mame
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83 lines
2.4 KiB
C++
83 lines
2.4 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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// thanks-to: Jeff Laughton
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/*
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Diablo 1300 series Printer TTL CPU disassembler
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The work is based on the RE done by Jeff Laughton http://laughtonelectronics.com/Arcana/Diablo%20CPU/DiabloCPU.html
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*/
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#include "emu.h"
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#include "diablo1300dasm.h"
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u32 diablo1300_disassembler::opcode_alignment() const
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{
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return 1;
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}
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offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms)
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{
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uint16_t op = opcodes.r16(pc);
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switch (op & 0x0007)
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{
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case 0: // OUTPUT Dport, Sreg
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util::stream_format(stream, "OUTPUT dv%d, r%02X",
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(op & 0x0070) >> 4,
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((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0));
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break;
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case 1: // JNC Addr
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util::stream_format(stream, "JNC %03X", ((op & 0xff00) >> 8) + ((op & 0x0008) ? 0x100 : 0));
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break;
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case 2: // RST #Dport
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util::stream_format(stream, "RST dv%d", (op & 0x0700) >> 8);
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break;
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case 3: // LDBBIT Sreg, #val
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util::stream_format(stream, "LDBBIT r%02X, %02X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0),
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(op & 0xff00) >> 8);
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break;
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case 4: //
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switch (op & 0xc000)
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{
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case 0x4000: // XLAT Dreg
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util::stream_format(stream, "XLAT r%02X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0));
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break;
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case 0xc000: // MOVCPL Dreg, Sreg
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util::stream_format(stream, "MOVCPL r%02X, r%02X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0),
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((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0));
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break;
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case 0x8000: // INPUT Dreg, Sport
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util::stream_format(stream, "INPUT r%02X, dv%X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0),
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((op & 0x0f00) >> 8));
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break;
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default:
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util::stream_format(stream, "???");
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break;
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}
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break;
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case 5: // LOAD# Dreg,#val
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util::stream_format(stream, "LOAD# r%02X, %02X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0),
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(op & 0xff00) >> 8);
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break;
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case 6: // ADCCPL S/Dreg, Sreg
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util::stream_format(stream, "ADCCPL r%02X, r%02X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0),
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((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0));
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break;
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case 7: // ADC# S/Dreg, val
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util::stream_format(stream, "ADC# r%02X, %02X",
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((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0),
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(op & 0xff00) >> 8);
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break;
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default:
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util::stream_format(stream, "???");
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break;
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}
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return 1 | SUPPORTED;
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}
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